1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
5 #include <rte_malloc.h>
6 #include <ethdev_driver.h>
9 #include "ionic_logs.h"
10 #include "ionic_lif.h"
11 #include "ionic_ethdev.h"
12 #include "ionic_rx_filter.h"
13 #include "ionic_rxtx.h"
15 /* queuetype support level */
16 static const uint8_t ionic_qtype_vers[IONIC_QTYPE_MAX] = {
17 [IONIC_QTYPE_ADMINQ] = 0, /* 0 = Base version with CQ support */
18 [IONIC_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */
19 [IONIC_QTYPE_RXQ] = 2, /* 0 = Base version with CQ+SG support
23 [IONIC_QTYPE_TXQ] = 3, /* 0 = Base version with CQ+SG support
24 * 1 = ... with Tx SG version 1
30 static int ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr);
31 static int ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr);
34 ionic_qcq_enable(struct ionic_qcq *qcq)
36 struct ionic_queue *q = &qcq->q;
37 struct ionic_lif *lif = q->lif;
38 struct ionic_admin_ctx ctx = {
41 .opcode = IONIC_CMD_Q_CONTROL,
43 .index = rte_cpu_to_le_32(q->index),
44 .oper = IONIC_Q_ENABLE,
48 return ionic_adminq_post_wait(lif, &ctx);
52 ionic_qcq_disable(struct ionic_qcq *qcq)
54 struct ionic_queue *q = &qcq->q;
55 struct ionic_lif *lif = q->lif;
56 struct ionic_admin_ctx ctx = {
59 .opcode = IONIC_CMD_Q_CONTROL,
61 .index = rte_cpu_to_le_32(q->index),
62 .oper = IONIC_Q_DISABLE,
66 return ionic_adminq_post_wait(lif, &ctx);
70 ionic_lif_stop(struct ionic_lif *lif)
76 lif->state &= ~IONIC_LIF_F_UP;
78 for (i = 0; i < lif->nrxqcqs; i++) {
79 struct ionic_qcq *rxq = lif->rxqcqs[i];
80 if (rxq->flags & IONIC_QCQ_F_INITED)
81 (void)ionic_dev_rx_queue_stop(lif->eth_dev, i);
84 for (i = 0; i < lif->ntxqcqs; i++) {
85 struct ionic_qcq *txq = lif->txqcqs[i];
86 if (txq->flags & IONIC_QCQ_F_INITED)
87 (void)ionic_dev_tx_queue_stop(lif->eth_dev, i);
92 ionic_lif_reset(struct ionic_lif *lif)
94 struct ionic_dev *idev = &lif->adapter->idev;
99 ionic_dev_cmd_lif_reset(idev);
100 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
102 IONIC_PRINT(WARNING, "Failed to reset %s", lif->name);
106 ionic_lif_get_abs_stats(const struct ionic_lif *lif, struct rte_eth_stats *stats)
108 struct ionic_lif_stats *ls = &lif->info->stats;
110 uint32_t num_rx_q_counters = RTE_MIN(lif->nrxqcqs, (uint32_t)
111 RTE_ETHDEV_QUEUE_STAT_CNTRS);
112 uint32_t num_tx_q_counters = RTE_MIN(lif->ntxqcqs, (uint32_t)
113 RTE_ETHDEV_QUEUE_STAT_CNTRS);
115 memset(stats, 0, sizeof(*stats));
118 IONIC_PRINT(DEBUG, "Stats on port %u not yet initialized",
125 stats->ipackets = ls->rx_ucast_packets +
126 ls->rx_mcast_packets +
127 ls->rx_bcast_packets;
129 stats->ibytes = ls->rx_ucast_bytes +
133 for (i = 0; i < lif->nrxqcqs; i++) {
134 struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats.rx;
136 rx_stats->no_cb_arg +
137 rx_stats->bad_cq_status +
143 ls->rx_ucast_drop_packets +
144 ls->rx_mcast_drop_packets +
145 ls->rx_bcast_drop_packets;
150 ls->rx_queue_disabled +
151 ls->rx_desc_fetch_error +
152 ls->rx_desc_data_error;
154 for (i = 0; i < num_rx_q_counters; i++) {
155 struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats.rx;
156 stats->q_ipackets[i] = rx_stats->packets;
157 stats->q_ibytes[i] = rx_stats->bytes;
159 rx_stats->no_cb_arg +
160 rx_stats->bad_cq_status +
167 stats->opackets = ls->tx_ucast_packets +
168 ls->tx_mcast_packets +
169 ls->tx_bcast_packets;
171 stats->obytes = ls->tx_ucast_bytes +
175 for (i = 0; i < lif->ntxqcqs; i++) {
176 struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats.tx;
177 stats->oerrors += tx_stats->drop;
181 ls->tx_ucast_drop_packets +
182 ls->tx_mcast_drop_packets +
183 ls->tx_bcast_drop_packets;
187 ls->tx_queue_disabled +
188 ls->tx_desc_fetch_error +
189 ls->tx_desc_data_error;
191 for (i = 0; i < num_tx_q_counters; i++) {
192 struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats.tx;
193 stats->q_opackets[i] = tx_stats->packets;
194 stats->q_obytes[i] = tx_stats->bytes;
199 ionic_lif_get_stats(const struct ionic_lif *lif,
200 struct rte_eth_stats *stats)
202 ionic_lif_get_abs_stats(lif, stats);
204 stats->ipackets -= lif->stats_base.ipackets;
205 stats->opackets -= lif->stats_base.opackets;
206 stats->ibytes -= lif->stats_base.ibytes;
207 stats->obytes -= lif->stats_base.obytes;
208 stats->imissed -= lif->stats_base.imissed;
209 stats->ierrors -= lif->stats_base.ierrors;
210 stats->oerrors -= lif->stats_base.oerrors;
211 stats->rx_nombuf -= lif->stats_base.rx_nombuf;
215 ionic_lif_reset_stats(struct ionic_lif *lif)
219 for (i = 0; i < lif->nrxqcqs; i++) {
220 memset(&lif->rxqcqs[i]->stats.rx, 0,
221 sizeof(struct ionic_rx_stats));
222 memset(&lif->txqcqs[i]->stats.tx, 0,
223 sizeof(struct ionic_tx_stats));
226 ionic_lif_get_abs_stats(lif, &lif->stats_base);
230 ionic_lif_get_hw_stats(struct ionic_lif *lif, struct ionic_lif_stats *stats)
232 uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t);
233 uint64_t *stats64 = (uint64_t *)stats;
234 uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats;
235 uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base;
237 for (i = 0; i < count; i++)
238 stats64[i] = lif_stats64[i] - lif_stats64_base[i];
242 ionic_lif_reset_hw_stats(struct ionic_lif *lif)
244 uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t);
245 uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats;
246 uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base;
248 for (i = 0; i < count; i++)
249 lif_stats64_base[i] = lif_stats64[i];
253 ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr)
255 struct ionic_admin_ctx ctx = {
256 .pending_work = true,
257 .cmd.rx_filter_add = {
258 .opcode = IONIC_CMD_RX_FILTER_ADD,
259 .match = rte_cpu_to_le_16(IONIC_RX_FILTER_MATCH_MAC),
264 memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, RTE_ETHER_ADDR_LEN);
266 err = ionic_adminq_post_wait(lif, &ctx);
270 IONIC_PRINT(INFO, "rx_filter add (id %d)",
271 rte_le_to_cpu_32(ctx.comp.rx_filter_add.filter_id));
273 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);
277 ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr)
279 struct ionic_admin_ctx ctx = {
280 .pending_work = true,
281 .cmd.rx_filter_del = {
282 .opcode = IONIC_CMD_RX_FILTER_DEL,
285 struct ionic_rx_filter *f;
290 rte_spinlock_lock(&lif->rx_filters.lock);
292 f = ionic_rx_filter_by_addr(lif, addr);
294 rte_spinlock_unlock(&lif->rx_filters.lock);
298 ctx.cmd.rx_filter_del.filter_id = rte_cpu_to_le_32(f->filter_id);
299 ionic_rx_filter_free(f);
301 rte_spinlock_unlock(&lif->rx_filters.lock);
303 err = ionic_adminq_post_wait(lif, &ctx);
307 IONIC_PRINT(INFO, "rx_filter del (id %d)",
308 rte_le_to_cpu_32(ctx.cmd.rx_filter_del.filter_id));
314 ionic_dev_add_mac(struct rte_eth_dev *eth_dev,
315 struct rte_ether_addr *mac_addr,
316 uint32_t index __rte_unused, uint32_t pool __rte_unused)
318 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
322 return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr);
326 ionic_dev_remove_mac(struct rte_eth_dev *eth_dev, uint32_t index)
328 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
329 struct ionic_adapter *adapter = lif->adapter;
330 struct rte_ether_addr *mac_addr;
334 if (index >= adapter->max_mac_addrs) {
336 "Index %u is above MAC filter limit %u",
337 index, adapter->max_mac_addrs);
341 mac_addr = ð_dev->data->mac_addrs[index];
343 if (!rte_is_valid_assigned_ether_addr(mac_addr))
346 ionic_lif_addr_del(lif, (const uint8_t *)mac_addr);
350 ionic_dev_set_mac(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr)
352 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
356 if (mac_addr == NULL) {
357 IONIC_PRINT(NOTICE, "New mac is null");
361 if (!rte_is_zero_ether_addr((struct rte_ether_addr *)lif->mac_addr)) {
362 IONIC_PRINT(INFO, "Deleting mac addr %pM",
364 ionic_lif_addr_del(lif, lif->mac_addr);
365 memset(lif->mac_addr, 0, RTE_ETHER_ADDR_LEN);
368 IONIC_PRINT(INFO, "Updating mac addr");
370 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)lif->mac_addr);
372 return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr);
376 ionic_vlan_rx_add_vid(struct ionic_lif *lif, uint16_t vid)
378 struct ionic_admin_ctx ctx = {
379 .pending_work = true,
380 .cmd.rx_filter_add = {
381 .opcode = IONIC_CMD_RX_FILTER_ADD,
382 .match = rte_cpu_to_le_16(IONIC_RX_FILTER_MATCH_VLAN),
383 .vlan.vlan = rte_cpu_to_le_16(vid),
388 err = ionic_adminq_post_wait(lif, &ctx);
392 IONIC_PRINT(INFO, "rx_filter add VLAN %d (id %d)", vid,
393 rte_le_to_cpu_32(ctx.comp.rx_filter_add.filter_id));
395 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);
399 ionic_vlan_rx_kill_vid(struct ionic_lif *lif, uint16_t vid)
401 struct ionic_admin_ctx ctx = {
402 .pending_work = true,
403 .cmd.rx_filter_del = {
404 .opcode = IONIC_CMD_RX_FILTER_DEL,
407 struct ionic_rx_filter *f;
412 rte_spinlock_lock(&lif->rx_filters.lock);
414 f = ionic_rx_filter_by_vlan(lif, vid);
416 rte_spinlock_unlock(&lif->rx_filters.lock);
420 ctx.cmd.rx_filter_del.filter_id = rte_cpu_to_le_32(f->filter_id);
421 ionic_rx_filter_free(f);
422 rte_spinlock_unlock(&lif->rx_filters.lock);
424 err = ionic_adminq_post_wait(lif, &ctx);
428 IONIC_PRINT(INFO, "rx_filter del VLAN %d (id %d)", vid,
429 rte_le_to_cpu_32(ctx.cmd.rx_filter_del.filter_id));
435 ionic_dev_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id,
438 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
442 err = ionic_vlan_rx_add_vid(lif, vlan_id);
444 err = ionic_vlan_rx_kill_vid(lif, vlan_id);
450 ionic_lif_rx_mode(struct ionic_lif *lif, uint32_t rx_mode)
452 struct ionic_admin_ctx ctx = {
453 .pending_work = true,
455 .opcode = IONIC_CMD_RX_MODE_SET,
456 .rx_mode = rte_cpu_to_le_16(rx_mode),
461 if (rx_mode & IONIC_RX_MODE_F_UNICAST)
462 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_UNICAST");
463 if (rx_mode & IONIC_RX_MODE_F_MULTICAST)
464 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_MULTICAST");
465 if (rx_mode & IONIC_RX_MODE_F_BROADCAST)
466 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_BROADCAST");
467 if (rx_mode & IONIC_RX_MODE_F_PROMISC)
468 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_PROMISC");
469 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI)
470 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_ALLMULTI");
472 err = ionic_adminq_post_wait(lif, &ctx);
474 IONIC_PRINT(ERR, "Failure setting RX mode");
478 ionic_set_rx_mode(struct ionic_lif *lif, uint32_t rx_mode)
480 if (lif->rx_mode != rx_mode) {
481 lif->rx_mode = rx_mode;
482 ionic_lif_rx_mode(lif, rx_mode);
487 ionic_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
489 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
490 uint32_t rx_mode = lif->rx_mode;
494 rx_mode |= IONIC_RX_MODE_F_PROMISC;
496 ionic_set_rx_mode(lif, rx_mode);
502 ionic_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
504 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
505 uint32_t rx_mode = lif->rx_mode;
507 rx_mode &= ~IONIC_RX_MODE_F_PROMISC;
509 ionic_set_rx_mode(lif, rx_mode);
515 ionic_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
517 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
518 uint32_t rx_mode = lif->rx_mode;
520 rx_mode |= IONIC_RX_MODE_F_ALLMULTI;
522 ionic_set_rx_mode(lif, rx_mode);
528 ionic_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
530 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
531 uint32_t rx_mode = lif->rx_mode;
533 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI;
535 ionic_set_rx_mode(lif, rx_mode);
541 ionic_lif_change_mtu(struct ionic_lif *lif, int new_mtu)
543 struct ionic_admin_ctx ctx = {
544 .pending_work = true,
546 .opcode = IONIC_CMD_LIF_SETATTR,
547 .attr = IONIC_LIF_ATTR_MTU,
548 .mtu = rte_cpu_to_le_32(new_mtu),
553 err = ionic_adminq_post_wait(lif, &ctx);
561 ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr)
563 struct ionic_adapter *adapter = lif->adapter;
564 struct ionic_dev *idev = &adapter->idev;
568 * Note: interrupt handler is called for index = 0 only
569 * (we use interrupts for the notifyq only anyway,
570 * which has index = 0)
573 for (index = 0; index < adapter->nintrs; index++)
574 if (!adapter->intrs[index])
577 if (index == adapter->nintrs)
580 adapter->intrs[index] = true;
582 ionic_intr_init(idev, intr, index);
588 ionic_intr_free(struct ionic_lif *lif, struct ionic_intr_info *intr)
590 if (intr->index != IONIC_INTR_NONE)
591 lif->adapter->intrs[intr->index] = false;
595 ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type,
597 const char *base, uint32_t flags,
600 uint32_t cq_desc_size,
601 uint32_t sg_desc_size,
602 struct ionic_qcq **qcq)
604 struct ionic_dev *idev = &lif->adapter->idev;
605 struct ionic_qcq *new;
606 uint32_t q_size, cq_size, sg_size, total_size;
607 void *q_base, *cq_base, *sg_base;
608 rte_iova_t q_base_pa = 0;
609 rte_iova_t cq_base_pa = 0;
610 rte_iova_t sg_base_pa = 0;
611 uint32_t socket_id = rte_socket_id();
616 q_size = num_descs * desc_size;
617 cq_size = num_descs * cq_desc_size;
618 sg_size = num_descs * sg_desc_size;
620 total_size = RTE_ALIGN(q_size, PAGE_SIZE) +
621 RTE_ALIGN(cq_size, PAGE_SIZE);
623 * Note: aligning q_size/cq_size is not enough due to cq_base address
624 * aligning as q_base could be not aligned to the page.
627 total_size += PAGE_SIZE;
629 if (flags & IONIC_QCQ_F_SG) {
630 total_size += RTE_ALIGN(sg_size, PAGE_SIZE);
631 total_size += PAGE_SIZE;
634 new = rte_zmalloc("ionic", sizeof(*new), 0);
636 IONIC_PRINT(ERR, "Cannot allocate queue structure");
643 new->q.info = rte_zmalloc("ionic", sizeof(*new->q.info) * num_descs, 0);
645 IONIC_PRINT(ERR, "Cannot allocate queue info");
647 goto err_out_free_qcq;
652 err = ionic_q_init(lif, idev, &new->q, index, num_descs,
653 desc_size, sg_desc_size);
655 IONIC_PRINT(ERR, "Queue initialization failed");
656 goto err_out_free_info;
659 err = ionic_cq_init(&new->cq, num_descs);
661 IONIC_PRINT(ERR, "Completion queue initialization failed");
662 goto err_out_free_info;
665 new->base_z = rte_eth_dma_zone_reserve(lif->eth_dev,
666 base /* name */, index /* queue_idx */,
667 total_size, IONIC_ALIGN, socket_id);
670 IONIC_PRINT(ERR, "Cannot reserve queue DMA memory");
672 goto err_out_free_info;
675 new->base = new->base_z->addr;
676 new->base_pa = new->base_z->iova;
677 new->total_size = total_size;
680 q_base_pa = new->base_pa;
682 cq_base = (void *)RTE_ALIGN((uintptr_t)q_base + q_size, PAGE_SIZE);
683 cq_base_pa = RTE_ALIGN(q_base_pa + q_size, PAGE_SIZE);
685 if (flags & IONIC_QCQ_F_SG) {
686 sg_base = (void *)RTE_ALIGN((uintptr_t)cq_base + cq_size,
688 sg_base_pa = RTE_ALIGN(cq_base_pa + cq_size, PAGE_SIZE);
689 ionic_q_sg_map(&new->q, sg_base, sg_base_pa);
692 IONIC_PRINT(DEBUG, "Q-Base-PA = %#jx CQ-Base-PA = %#jx "
694 q_base_pa, cq_base_pa, sg_base_pa);
696 ionic_q_map(&new->q, q_base, q_base_pa);
697 ionic_cq_map(&new->cq, cq_base, cq_base_pa);
704 rte_free(new->q.info);
712 ionic_qcq_free(struct ionic_qcq *qcq)
717 rte_memzone_free(qcq->base_z);
722 rte_free(qcq->q.info);
730 ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t nrxq_descs,
731 struct ionic_qcq **qcq)
736 flags = IONIC_QCQ_F_SG;
737 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, index, "rx", flags,
739 sizeof(struct ionic_rxq_desc),
740 sizeof(struct ionic_rxq_comp),
741 sizeof(struct ionic_rxq_sg_desc),
742 &lif->rxqcqs[index]);
746 *qcq = lif->rxqcqs[index];
752 ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t ntxq_descs,
753 struct ionic_qcq **qcq)
758 flags = IONIC_QCQ_F_SG;
759 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, index, "tx", flags,
761 sizeof(struct ionic_txq_desc),
762 sizeof(struct ionic_txq_comp),
763 sizeof(struct ionic_txq_sg_desc_v1),
764 &lif->txqcqs[index]);
768 *qcq = lif->txqcqs[index];
774 ionic_admin_qcq_alloc(struct ionic_lif *lif)
780 err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags,
782 sizeof(struct ionic_admin_cmd),
783 sizeof(struct ionic_admin_comp),
793 ionic_notify_qcq_alloc(struct ionic_lif *lif)
795 struct ionic_qcq *nqcq;
796 struct ionic_dev *idev = &lif->adapter->idev;
800 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notify",
802 IONIC_NOTIFYQ_LENGTH,
803 sizeof(struct ionic_notifyq_cmd),
804 sizeof(union ionic_notifyq_comp),
810 err = ionic_intr_alloc(lif, &nqcq->intr);
812 ionic_qcq_free(nqcq);
816 ionic_intr_mask_assert(idev->intr_ctrl, nqcq->intr.index,
817 IONIC_INTR_MASK_SET);
819 lif->notifyqcq = nqcq;
825 ionic_bus_map_dbpage(struct ionic_adapter *adapter, int page_num)
827 char *vaddr = adapter->bars[IONIC_PCI_BAR_DBELL].vaddr;
829 if (adapter->num_bars <= IONIC_PCI_BAR_DBELL)
832 return (void *)&vaddr[page_num << PAGE_SHIFT];
836 ionic_lif_queue_identify(struct ionic_lif *lif)
838 struct ionic_adapter *adapter = lif->adapter;
839 struct ionic_dev *idev = &adapter->idev;
840 union ionic_q_identity *q_ident = &adapter->ident.txq;
841 uint32_t q_words = RTE_DIM(q_ident->words);
842 uint32_t cmd_words = RTE_DIM(idev->dev_cmd->data);
843 uint32_t i, nwords, qtype;
846 for (qtype = 0; qtype < RTE_DIM(ionic_qtype_vers); qtype++) {
847 struct ionic_qtype_info *qti = &lif->qtype_info[qtype];
849 /* Filter out the types this driver knows about */
851 case IONIC_QTYPE_ADMINQ:
852 case IONIC_QTYPE_NOTIFYQ:
853 case IONIC_QTYPE_RXQ:
854 case IONIC_QTYPE_TXQ:
860 memset(qti, 0, sizeof(*qti));
862 ionic_dev_cmd_queue_identify(idev, IONIC_LIF_TYPE_CLASSIC,
863 qtype, ionic_qtype_vers[qtype]);
864 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
865 if (err == -EINVAL) {
866 IONIC_PRINT(ERR, "qtype %d not supported\n", qtype);
868 } else if (err == -EIO) {
869 IONIC_PRINT(ERR, "q_ident failed, older FW\n");
872 IONIC_PRINT(ERR, "q_ident failed, qtype %d: %d\n",
877 nwords = RTE_MIN(q_words, cmd_words);
878 for (i = 0; i < nwords; i++)
879 q_ident->words[i] = ioread32(&idev->dev_cmd->data[i]);
881 qti->version = q_ident->version;
882 qti->supported = q_ident->supported;
883 qti->features = rte_le_to_cpu_64(q_ident->features);
884 qti->desc_sz = rte_le_to_cpu_16(q_ident->desc_sz);
885 qti->comp_sz = rte_le_to_cpu_16(q_ident->comp_sz);
886 qti->sg_desc_sz = rte_le_to_cpu_16(q_ident->sg_desc_sz);
887 qti->max_sg_elems = rte_le_to_cpu_16(q_ident->max_sg_elems);
888 qti->sg_desc_stride =
889 rte_le_to_cpu_16(q_ident->sg_desc_stride);
891 IONIC_PRINT(DEBUG, " qtype[%d].version = %d",
892 qtype, qti->version);
893 IONIC_PRINT(DEBUG, " qtype[%d].supported = %#x",
894 qtype, qti->supported);
895 IONIC_PRINT(DEBUG, " qtype[%d].features = %#jx",
896 qtype, qti->features);
897 IONIC_PRINT(DEBUG, " qtype[%d].desc_sz = %d",
898 qtype, qti->desc_sz);
899 IONIC_PRINT(DEBUG, " qtype[%d].comp_sz = %d",
900 qtype, qti->comp_sz);
901 IONIC_PRINT(DEBUG, " qtype[%d].sg_desc_sz = %d",
902 qtype, qti->sg_desc_sz);
903 IONIC_PRINT(DEBUG, " qtype[%d].max_sg_elems = %d",
904 qtype, qti->max_sg_elems);
905 IONIC_PRINT(DEBUG, " qtype[%d].sg_desc_stride = %d",
906 qtype, qti->sg_desc_stride);
911 ionic_lif_alloc(struct ionic_lif *lif)
913 struct ionic_adapter *adapter = lif->adapter;
914 uint32_t socket_id = rte_socket_id();
918 * lif->name was zeroed on allocation.
919 * Copy (sizeof() - 1) bytes to ensure that it is NULL terminated.
921 memcpy(lif->name, lif->eth_dev->data->name, sizeof(lif->name) - 1);
923 IONIC_PRINT(DEBUG, "LIF: %s", lif->name);
925 ionic_lif_queue_identify(lif);
927 if (lif->qtype_info[IONIC_QTYPE_TXQ].version < 1) {
928 IONIC_PRINT(ERR, "FW too old, please upgrade");
932 IONIC_PRINT(DEBUG, "Allocating Lif Info");
934 rte_spinlock_init(&lif->adminq_lock);
935 rte_spinlock_init(&lif->adminq_service_lock);
937 lif->kern_dbpage = ionic_bus_map_dbpage(adapter, 0);
938 if (!lif->kern_dbpage) {
939 IONIC_PRINT(ERR, "Cannot map dbpage, aborting");
943 lif->txqcqs = rte_zmalloc("ionic", sizeof(*lif->txqcqs) *
944 adapter->max_ntxqs_per_lif, 0);
947 IONIC_PRINT(ERR, "Cannot allocate tx queues array");
951 lif->rxqcqs = rte_zmalloc("ionic", sizeof(*lif->rxqcqs) *
952 adapter->max_nrxqs_per_lif, 0);
955 IONIC_PRINT(ERR, "Cannot allocate rx queues array");
959 IONIC_PRINT(DEBUG, "Allocating Notify Queue");
961 err = ionic_notify_qcq_alloc(lif);
963 IONIC_PRINT(ERR, "Cannot allocate notify queue");
967 IONIC_PRINT(DEBUG, "Allocating Admin Queue");
969 err = ionic_admin_qcq_alloc(lif);
971 IONIC_PRINT(ERR, "Cannot allocate admin queue");
975 IONIC_PRINT(DEBUG, "Allocating Lif Info");
977 lif->info_sz = RTE_ALIGN(sizeof(*lif->info), PAGE_SIZE);
979 lif->info_z = rte_eth_dma_zone_reserve(lif->eth_dev,
980 "lif_info", 0 /* queue_idx*/,
981 lif->info_sz, IONIC_ALIGN, socket_id);
983 IONIC_PRINT(ERR, "Cannot allocate lif info memory");
987 lif->info = lif->info_z->addr;
988 lif->info_pa = lif->info_z->iova;
994 ionic_lif_free(struct ionic_lif *lif)
996 if (lif->notifyqcq) {
997 ionic_qcq_free(lif->notifyqcq);
998 lif->notifyqcq = NULL;
1001 if (lif->adminqcq) {
1002 ionic_qcq_free(lif->adminqcq);
1003 lif->adminqcq = NULL;
1007 rte_free(lif->txqcqs);
1012 rte_free(lif->rxqcqs);
1017 rte_memzone_free(lif->info_z);
1023 ionic_lif_free_queues(struct ionic_lif *lif)
1027 for (i = 0; i < lif->ntxqcqs; i++) {
1028 ionic_dev_tx_queue_release(lif->eth_dev->data->tx_queues[i]);
1029 lif->eth_dev->data->tx_queues[i] = NULL;
1031 for (i = 0; i < lif->nrxqcqs; i++) {
1032 ionic_dev_rx_queue_release(lif->eth_dev->data->rx_queues[i]);
1033 lif->eth_dev->data->rx_queues[i] = NULL;
1038 ionic_lif_rss_config(struct ionic_lif *lif,
1039 const uint16_t types, const uint8_t *key, const uint32_t *indir)
1041 struct ionic_adapter *adapter = lif->adapter;
1042 struct ionic_admin_ctx ctx = {
1043 .pending_work = true,
1044 .cmd.lif_setattr = {
1045 .opcode = IONIC_CMD_LIF_SETATTR,
1046 .attr = IONIC_LIF_ATTR_RSS,
1047 .rss.types = rte_cpu_to_le_16(types),
1048 .rss.addr = rte_cpu_to_le_64(lif->rss_ind_tbl_pa),
1053 rte_le_to_cpu_16(adapter->ident.lif.eth.rss_ind_tbl_sz);
1057 lif->rss_types = types;
1060 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE);
1063 for (i = 0; i < tbl_sz; i++)
1064 lif->rss_ind_tbl[i] = indir[i];
1066 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key,
1067 IONIC_RSS_HASH_KEY_SIZE);
1069 return ionic_adminq_post_wait(lif, &ctx);
1073 ionic_lif_rss_setup(struct ionic_lif *lif)
1075 struct ionic_adapter *adapter = lif->adapter;
1076 static const uint8_t toeplitz_symmetric_key[] = {
1077 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
1078 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
1079 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
1080 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
1081 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
1085 rte_le_to_cpu_16(adapter->ident.lif.eth.rss_ind_tbl_sz);
1089 if (!lif->rss_ind_tbl_z) {
1090 lif->rss_ind_tbl_z = rte_eth_dma_zone_reserve(lif->eth_dev,
1091 "rss_ind_tbl", 0 /* queue_idx */,
1092 sizeof(*lif->rss_ind_tbl) * tbl_sz,
1093 IONIC_ALIGN, rte_socket_id());
1094 if (!lif->rss_ind_tbl_z) {
1095 IONIC_PRINT(ERR, "OOM");
1099 lif->rss_ind_tbl = lif->rss_ind_tbl_z->addr;
1100 lif->rss_ind_tbl_pa = lif->rss_ind_tbl_z->iova;
1103 if (lif->rss_ind_tbl_nrxqcqs != lif->nrxqcqs) {
1104 lif->rss_ind_tbl_nrxqcqs = lif->nrxqcqs;
1106 /* Fill indirection table with 'default' values */
1107 for (i = 0; i < tbl_sz; i++)
1108 lif->rss_ind_tbl[i] = i % lif->nrxqcqs;
1111 return ionic_lif_rss_config(lif, IONIC_RSS_OFFLOAD_ALL,
1112 toeplitz_symmetric_key, NULL);
1116 ionic_lif_rss_teardown(struct ionic_lif *lif)
1118 if (!lif->rss_ind_tbl)
1121 if (lif->rss_ind_tbl_z) {
1122 /* Disable RSS on the NIC */
1123 ionic_lif_rss_config(lif, 0x0, NULL, NULL);
1125 lif->rss_ind_tbl = NULL;
1126 lif->rss_ind_tbl_pa = 0;
1127 rte_memzone_free(lif->rss_ind_tbl_z);
1128 lif->rss_ind_tbl_z = NULL;
1133 ionic_lif_qcq_deinit(struct ionic_qcq *qcq)
1135 qcq->flags &= ~IONIC_QCQ_F_INITED;
1139 ionic_lif_txq_deinit(struct ionic_qcq *qcq)
1141 ionic_lif_qcq_deinit(qcq);
1145 ionic_lif_rxq_deinit(struct ionic_qcq *qcq)
1147 ionic_lif_qcq_deinit(qcq);
1151 ionic_lif_notifyq_deinit(struct ionic_lif *lif)
1153 struct ionic_qcq *nqcq = lif->notifyqcq;
1154 struct ionic_dev *idev = &lif->adapter->idev;
1156 if (!(nqcq->flags & IONIC_QCQ_F_INITED))
1159 ionic_intr_mask(idev->intr_ctrl, nqcq->intr.index,
1160 IONIC_INTR_MASK_SET);
1162 nqcq->flags &= ~IONIC_QCQ_F_INITED;
1165 /* This acts like ionic_napi */
1167 ionic_qcq_service(struct ionic_qcq *qcq, int budget, ionic_cq_cb cb,
1170 struct ionic_cq *cq = &qcq->cq;
1173 work_done = ionic_cq_service(cq, budget, cb, cb_arg);
1179 ionic_link_status_check(struct ionic_lif *lif)
1181 struct ionic_adapter *adapter = lif->adapter;
1184 lif->state &= ~IONIC_LIF_F_LINK_CHECK_NEEDED;
1189 link_up = (lif->info->status.link_status == IONIC_PORT_OPER_STATUS_UP);
1191 if ((link_up && adapter->link_up) ||
1192 (!link_up && !adapter->link_up))
1196 adapter->link_speed =
1197 rte_le_to_cpu_32(lif->info->status.link_speed);
1198 IONIC_PRINT(DEBUG, "Link up - %d Gbps",
1199 adapter->link_speed);
1201 IONIC_PRINT(DEBUG, "Link down");
1204 adapter->link_up = link_up;
1205 ionic_dev_link_update(lif->eth_dev, 0);
1209 ionic_lif_handle_fw_down(struct ionic_lif *lif)
1211 if (lif->state & IONIC_LIF_F_FW_RESET)
1214 lif->state |= IONIC_LIF_F_FW_RESET;
1216 if (lif->state & IONIC_LIF_F_UP) {
1218 "Surprise FW stop, stopping %s\n", lif->name);
1219 ionic_lif_stop(lif);
1222 IONIC_PRINT(NOTICE, "FW down, %s stopped", lif->name);
1226 ionic_notifyq_cb(struct ionic_cq *cq, uint32_t cq_desc_index, void *cb_arg)
1228 union ionic_notifyq_comp *cq_desc_base = cq->base;
1229 union ionic_notifyq_comp *cq_desc = &cq_desc_base[cq_desc_index];
1230 struct ionic_lif *lif = cb_arg;
1232 IONIC_PRINT(DEBUG, "Notifyq callback eid = %jd ecode = %d",
1233 cq_desc->event.eid, cq_desc->event.ecode);
1235 /* Have we run out of new completions to process? */
1236 if (!(cq_desc->event.eid > lif->last_eid))
1239 lif->last_eid = cq_desc->event.eid;
1241 switch (cq_desc->event.ecode) {
1242 case IONIC_EVENT_LINK_CHANGE:
1244 "Notifyq IONIC_EVENT_LINK_CHANGE %s "
1245 "eid=%jd link_status=%d link_speed=%d",
1248 cq_desc->link_change.link_status,
1249 cq_desc->link_change.link_speed);
1251 lif->state |= IONIC_LIF_F_LINK_CHECK_NEEDED;
1254 case IONIC_EVENT_RESET:
1256 "Notifyq IONIC_EVENT_RESET %s "
1257 "eid=%jd, reset_code=%d state=%d",
1260 cq_desc->reset.reset_code,
1261 cq_desc->reset.state);
1262 ionic_lif_handle_fw_down(lif);
1266 IONIC_PRINT(WARNING, "Notifyq bad event ecode=%d eid=%jd",
1267 cq_desc->event.ecode, cq_desc->event.eid);
1275 ionic_notifyq_handler(struct ionic_lif *lif, int budget)
1277 struct ionic_dev *idev = &lif->adapter->idev;
1278 struct ionic_qcq *qcq = lif->notifyqcq;
1281 if (!(qcq->flags & IONIC_QCQ_F_INITED)) {
1282 IONIC_PRINT(DEBUG, "Notifyq not yet initialized");
1286 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1287 IONIC_INTR_MASK_SET);
1289 work_done = ionic_qcq_service(qcq, budget, ionic_notifyq_cb, lif);
1291 if (lif->state & IONIC_LIF_F_LINK_CHECK_NEEDED)
1292 ionic_link_status_check(lif);
1294 ionic_intr_credits(idev->intr_ctrl, qcq->intr.index,
1295 work_done, IONIC_INTR_CRED_RESET_COALESCE);
1297 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1298 IONIC_INTR_MASK_CLEAR);
1304 ionic_lif_adminq_init(struct ionic_lif *lif)
1306 struct ionic_dev *idev = &lif->adapter->idev;
1307 struct ionic_qcq *qcq = lif->adminqcq;
1308 struct ionic_queue *q = &qcq->q;
1309 struct ionic_q_init_comp comp;
1312 ionic_dev_cmd_adminq_init(idev, qcq);
1313 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1317 ionic_dev_cmd_comp(idev, &comp);
1319 q->hw_type = comp.hw_type;
1320 q->hw_index = rte_le_to_cpu_32(comp.hw_index);
1321 q->db = ionic_db_map(lif, q);
1323 IONIC_PRINT(DEBUG, "adminq->hw_type %d", q->hw_type);
1324 IONIC_PRINT(DEBUG, "adminq->hw_index %d", q->hw_index);
1325 IONIC_PRINT(DEBUG, "adminq->db %p", q->db);
1327 qcq->flags |= IONIC_QCQ_F_INITED;
1333 ionic_lif_notifyq_init(struct ionic_lif *lif)
1335 struct ionic_dev *idev = &lif->adapter->idev;
1336 struct ionic_qcq *qcq = lif->notifyqcq;
1337 struct ionic_queue *q = &qcq->q;
1340 struct ionic_admin_ctx ctx = {
1341 .pending_work = true,
1343 .opcode = IONIC_CMD_Q_INIT,
1345 .ver = lif->qtype_info[q->type].version,
1346 .index = rte_cpu_to_le_32(q->index),
1347 .intr_index = rte_cpu_to_le_16(qcq->intr.index),
1348 .flags = rte_cpu_to_le_16(IONIC_QINIT_F_IRQ |
1350 .ring_size = rte_log2_u32(q->num_descs),
1351 .ring_base = rte_cpu_to_le_64(q->base_pa),
1355 IONIC_PRINT(DEBUG, "notifyq_init.index %d", q->index);
1356 IONIC_PRINT(DEBUG, "notifyq_init.ring_base 0x%" PRIx64 "", q->base_pa);
1357 IONIC_PRINT(DEBUG, "notifyq_init.ring_size %d",
1358 ctx.cmd.q_init.ring_size);
1359 IONIC_PRINT(DEBUG, "notifyq_init.ver %u", ctx.cmd.q_init.ver);
1361 err = ionic_adminq_post_wait(lif, &ctx);
1365 q->hw_type = ctx.comp.q_init.hw_type;
1366 q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index);
1369 IONIC_PRINT(DEBUG, "notifyq->hw_type %d", q->hw_type);
1370 IONIC_PRINT(DEBUG, "notifyq->hw_index %d", q->hw_index);
1371 IONIC_PRINT(DEBUG, "notifyq->db %p", q->db);
1373 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1374 IONIC_INTR_MASK_CLEAR);
1376 qcq->flags |= IONIC_QCQ_F_INITED;
1382 ionic_lif_set_features(struct ionic_lif *lif)
1384 struct ionic_admin_ctx ctx = {
1385 .pending_work = true,
1386 .cmd.lif_setattr = {
1387 .opcode = IONIC_CMD_LIF_SETATTR,
1388 .attr = IONIC_LIF_ATTR_FEATURES,
1389 .features = rte_cpu_to_le_64(lif->features),
1394 err = ionic_adminq_post_wait(lif, &ctx);
1398 lif->hw_features = rte_le_to_cpu_64(ctx.cmd.lif_setattr.features &
1399 ctx.comp.lif_setattr.features);
1401 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
1402 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_TX_TAG");
1403 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
1404 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_STRIP");
1405 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
1406 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_FILTER");
1407 if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
1408 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_HASH");
1409 if (lif->hw_features & IONIC_ETH_HW_TX_SG)
1410 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_SG");
1411 if (lif->hw_features & IONIC_ETH_HW_RX_SG)
1412 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_SG");
1413 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
1414 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_CSUM");
1415 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
1416 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_CSUM");
1417 if (lif->hw_features & IONIC_ETH_HW_TSO)
1418 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO");
1419 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
1420 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPV6");
1421 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
1422 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_ECN");
1423 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
1424 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE");
1425 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
1426 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE_CSUM");
1427 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
1428 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP4");
1429 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
1430 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP6");
1431 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
1432 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP");
1433 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
1434 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP_CSUM");
1440 ionic_lif_txq_init(struct ionic_qcq *qcq)
1442 struct ionic_queue *q = &qcq->q;
1443 struct ionic_lif *lif = qcq->lif;
1444 struct ionic_cq *cq = &qcq->cq;
1445 struct ionic_admin_ctx ctx = {
1446 .pending_work = true,
1448 .opcode = IONIC_CMD_Q_INIT,
1450 .ver = lif->qtype_info[q->type].version,
1451 .index = rte_cpu_to_le_32(q->index),
1452 .flags = rte_cpu_to_le_16(IONIC_QINIT_F_SG |
1454 .intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE),
1455 .ring_size = rte_log2_u32(q->num_descs),
1456 .ring_base = rte_cpu_to_le_64(q->base_pa),
1457 .cq_ring_base = rte_cpu_to_le_64(cq->base_pa),
1458 .sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa),
1463 IONIC_PRINT(DEBUG, "txq_init.index %d", q->index);
1464 IONIC_PRINT(DEBUG, "txq_init.ring_base 0x%" PRIx64 "", q->base_pa);
1465 IONIC_PRINT(DEBUG, "txq_init.ring_size %d",
1466 ctx.cmd.q_init.ring_size);
1467 IONIC_PRINT(DEBUG, "txq_init.ver %u", ctx.cmd.q_init.ver);
1469 err = ionic_adminq_post_wait(qcq->lif, &ctx);
1473 q->hw_type = ctx.comp.q_init.hw_type;
1474 q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index);
1475 q->db = ionic_db_map(lif, q);
1477 IONIC_PRINT(DEBUG, "txq->hw_type %d", q->hw_type);
1478 IONIC_PRINT(DEBUG, "txq->hw_index %d", q->hw_index);
1479 IONIC_PRINT(DEBUG, "txq->db %p", q->db);
1481 qcq->flags |= IONIC_QCQ_F_INITED;
1487 ionic_lif_rxq_init(struct ionic_qcq *qcq)
1489 struct ionic_queue *q = &qcq->q;
1490 struct ionic_lif *lif = qcq->lif;
1491 struct ionic_cq *cq = &qcq->cq;
1492 struct ionic_admin_ctx ctx = {
1493 .pending_work = true,
1495 .opcode = IONIC_CMD_Q_INIT,
1497 .ver = lif->qtype_info[q->type].version,
1498 .index = rte_cpu_to_le_32(q->index),
1499 .flags = rte_cpu_to_le_16(IONIC_QINIT_F_SG |
1501 .intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE),
1502 .ring_size = rte_log2_u32(q->num_descs),
1503 .ring_base = rte_cpu_to_le_64(q->base_pa),
1504 .cq_ring_base = rte_cpu_to_le_64(cq->base_pa),
1505 .sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa),
1510 IONIC_PRINT(DEBUG, "rxq_init.index %d", q->index);
1511 IONIC_PRINT(DEBUG, "rxq_init.ring_base 0x%" PRIx64 "", q->base_pa);
1512 IONIC_PRINT(DEBUG, "rxq_init.ring_size %d",
1513 ctx.cmd.q_init.ring_size);
1514 IONIC_PRINT(DEBUG, "rxq_init.ver %u", ctx.cmd.q_init.ver);
1516 err = ionic_adminq_post_wait(qcq->lif, &ctx);
1520 q->hw_type = ctx.comp.q_init.hw_type;
1521 q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index);
1522 q->db = ionic_db_map(lif, q);
1524 qcq->flags |= IONIC_QCQ_F_INITED;
1526 IONIC_PRINT(DEBUG, "rxq->hw_type %d", q->hw_type);
1527 IONIC_PRINT(DEBUG, "rxq->hw_index %d", q->hw_index);
1528 IONIC_PRINT(DEBUG, "rxq->db %p", q->db);
1534 ionic_station_set(struct ionic_lif *lif)
1536 struct ionic_admin_ctx ctx = {
1537 .pending_work = true,
1538 .cmd.lif_getattr = {
1539 .opcode = IONIC_CMD_LIF_GETATTR,
1540 .attr = IONIC_LIF_ATTR_MAC,
1547 err = ionic_adminq_post_wait(lif, &ctx);
1551 memcpy(lif->mac_addr, ctx.comp.lif_getattr.mac, RTE_ETHER_ADDR_LEN);
1557 ionic_lif_set_name(struct ionic_lif *lif)
1559 struct ionic_admin_ctx ctx = {
1560 .pending_work = true,
1561 .cmd.lif_setattr = {
1562 .opcode = IONIC_CMD_LIF_SETATTR,
1563 .attr = IONIC_LIF_ATTR_NAME,
1567 memcpy(ctx.cmd.lif_setattr.name, lif->name,
1568 sizeof(ctx.cmd.lif_setattr.name) - 1);
1570 ionic_adminq_post_wait(lif, &ctx);
1574 ionic_lif_init(struct ionic_lif *lif)
1576 struct ionic_dev *idev = &lif->adapter->idev;
1577 struct ionic_q_init_comp comp;
1580 memset(&lif->stats_base, 0, sizeof(lif->stats_base));
1582 ionic_dev_cmd_lif_init(idev, lif->info_pa);
1583 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1584 ionic_dev_cmd_comp(idev, &comp);
1588 lif->hw_index = rte_cpu_to_le_16(comp.hw_index);
1590 err = ionic_lif_adminq_init(lif);
1594 err = ionic_lif_notifyq_init(lif);
1596 goto err_out_adminq_deinit;
1599 * Configure initial feature set
1600 * This will be updated later by the dev_configure() step
1602 lif->features = IONIC_ETH_HW_RX_HASH | IONIC_ETH_HW_VLAN_RX_FILTER;
1604 err = ionic_lif_set_features(lif);
1606 goto err_out_notifyq_deinit;
1608 err = ionic_rx_filters_init(lif);
1610 goto err_out_notifyq_deinit;
1612 err = ionic_station_set(lif);
1614 goto err_out_rx_filter_deinit;
1616 ionic_lif_set_name(lif);
1618 lif->state |= IONIC_LIF_F_INITED;
1622 err_out_rx_filter_deinit:
1623 ionic_rx_filters_deinit(lif);
1625 err_out_notifyq_deinit:
1626 ionic_lif_notifyq_deinit(lif);
1628 err_out_adminq_deinit:
1629 ionic_lif_qcq_deinit(lif->adminqcq);
1635 ionic_lif_deinit(struct ionic_lif *lif)
1637 if (!(lif->state & IONIC_LIF_F_INITED))
1640 ionic_rx_filters_deinit(lif);
1641 ionic_lif_rss_teardown(lif);
1642 ionic_lif_notifyq_deinit(lif);
1643 ionic_lif_qcq_deinit(lif->adminqcq);
1645 lif->state &= ~IONIC_LIF_F_INITED;
1649 ionic_lif_configure_vlan_offload(struct ionic_lif *lif, int mask)
1651 struct rte_eth_dev *eth_dev = lif->eth_dev;
1652 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1655 * IONIC_ETH_HW_VLAN_RX_FILTER cannot be turned off, so
1656 * set DEV_RX_OFFLOAD_VLAN_FILTER and ignore ETH_VLAN_FILTER_MASK
1658 rxmode->offloads |= DEV_RX_OFFLOAD_VLAN_FILTER;
1660 if (mask & ETH_VLAN_STRIP_MASK) {
1661 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1662 lif->features |= IONIC_ETH_HW_VLAN_RX_STRIP;
1664 lif->features &= ~IONIC_ETH_HW_VLAN_RX_STRIP;
1669 ionic_lif_configure(struct ionic_lif *lif)
1671 struct rte_eth_rxmode *rxmode = &lif->eth_dev->data->dev_conf.rxmode;
1672 struct rte_eth_txmode *txmode = &lif->eth_dev->data->dev_conf.txmode;
1673 struct ionic_identity *ident = &lif->adapter->ident;
1674 union ionic_lif_config *cfg = &ident->lif.eth.config;
1675 uint32_t ntxqs_per_lif =
1676 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]);
1677 uint32_t nrxqs_per_lif =
1678 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]);
1679 uint32_t nrxqs = lif->eth_dev->data->nb_rx_queues;
1680 uint32_t ntxqs = lif->eth_dev->data->nb_tx_queues;
1682 lif->port_id = lif->eth_dev->data->port_id;
1684 IONIC_PRINT(DEBUG, "Configuring LIF on port %u",
1688 nrxqs_per_lif = RTE_MIN(nrxqs_per_lif, nrxqs);
1691 ntxqs_per_lif = RTE_MIN(ntxqs_per_lif, ntxqs);
1693 lif->nrxqcqs = nrxqs_per_lif;
1694 lif->ntxqcqs = ntxqs_per_lif;
1696 /* Update the LIF configuration based on the eth_dev */
1699 * NB: While it is true that RSS_HASH is always enabled on ionic,
1700 * setting this flag unconditionally causes problems in DTS.
1701 * rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1706 if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM ||
1707 rxmode->offloads & DEV_RX_OFFLOAD_UDP_CKSUM ||
1708 rxmode->offloads & DEV_RX_OFFLOAD_TCP_CKSUM)
1709 lif->features |= IONIC_ETH_HW_RX_CSUM;
1711 lif->features &= ~IONIC_ETH_HW_RX_CSUM;
1713 if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER) {
1714 lif->features |= IONIC_ETH_HW_RX_SG;
1715 lif->eth_dev->data->scattered_rx = 1;
1717 lif->features &= ~IONIC_ETH_HW_RX_SG;
1718 lif->eth_dev->data->scattered_rx = 0;
1721 /* Covers VLAN_STRIP */
1722 ionic_lif_configure_vlan_offload(lif, ETH_VLAN_STRIP_MASK);
1726 if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
1727 txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
1728 txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM ||
1729 txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
1730 txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)
1731 lif->features |= IONIC_ETH_HW_TX_CSUM;
1733 lif->features &= ~IONIC_ETH_HW_TX_CSUM;
1735 if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
1736 lif->features |= IONIC_ETH_HW_VLAN_TX_TAG;
1738 lif->features &= ~IONIC_ETH_HW_VLAN_TX_TAG;
1740 if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
1741 lif->features |= IONIC_ETH_HW_TX_SG;
1743 lif->features &= ~IONIC_ETH_HW_TX_SG;
1745 if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
1746 lif->features |= IONIC_ETH_HW_TSO;
1747 lif->features |= IONIC_ETH_HW_TSO_IPV6;
1748 lif->features |= IONIC_ETH_HW_TSO_ECN;
1750 lif->features &= ~IONIC_ETH_HW_TSO;
1751 lif->features &= ~IONIC_ETH_HW_TSO_IPV6;
1752 lif->features &= ~IONIC_ETH_HW_TSO_ECN;
1757 ionic_lif_start(struct ionic_lif *lif)
1763 err = ionic_lif_rss_setup(lif);
1767 if (!lif->rx_mode) {
1768 IONIC_PRINT(DEBUG, "Setting RX mode on %s",
1771 rx_mode = IONIC_RX_MODE_F_UNICAST;
1772 rx_mode |= IONIC_RX_MODE_F_MULTICAST;
1773 rx_mode |= IONIC_RX_MODE_F_BROADCAST;
1775 ionic_set_rx_mode(lif, rx_mode);
1778 IONIC_PRINT(DEBUG, "Starting %u RX queues and %u TX queues "
1780 lif->nrxqcqs, lif->ntxqcqs, lif->port_id);
1782 for (i = 0; i < lif->nrxqcqs; i++) {
1783 struct ionic_qcq *rxq = lif->rxqcqs[i];
1784 if (!(rxq->flags & IONIC_QCQ_F_DEFERRED)) {
1785 err = ionic_dev_rx_queue_start(lif->eth_dev, i);
1792 for (i = 0; i < lif->ntxqcqs; i++) {
1793 struct ionic_qcq *txq = lif->txqcqs[i];
1794 if (!(txq->flags & IONIC_QCQ_F_DEFERRED)) {
1795 err = ionic_dev_tx_queue_start(lif->eth_dev, i);
1802 /* Carrier ON here */
1803 lif->state |= IONIC_LIF_F_UP;
1805 ionic_link_status_check(lif);
1811 ionic_lif_identify(struct ionic_adapter *adapter)
1813 struct ionic_dev *idev = &adapter->idev;
1814 struct ionic_identity *ident = &adapter->ident;
1815 union ionic_lif_config *cfg = &ident->lif.eth.config;
1816 uint32_t lif_words = RTE_DIM(ident->lif.words);
1817 uint32_t cmd_words = RTE_DIM(idev->dev_cmd->data);
1821 ionic_dev_cmd_lif_identify(idev, IONIC_LIF_TYPE_CLASSIC,
1822 IONIC_IDENTITY_VERSION_1);
1823 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1827 nwords = RTE_MIN(lif_words, cmd_words);
1828 for (i = 0; i < nwords; i++)
1829 ident->lif.words[i] = ioread32(&idev->dev_cmd->data[i]);
1831 IONIC_PRINT(INFO, "capabilities 0x%" PRIx64 " ",
1832 rte_le_to_cpu_64(ident->lif.capabilities));
1834 IONIC_PRINT(INFO, "eth.max_ucast_filters 0x%" PRIx32 " ",
1835 rte_le_to_cpu_32(ident->lif.eth.max_ucast_filters));
1836 IONIC_PRINT(INFO, "eth.max_mcast_filters 0x%" PRIx32 " ",
1837 rte_le_to_cpu_32(ident->lif.eth.max_mcast_filters));
1839 IONIC_PRINT(INFO, "eth.features 0x%" PRIx64 " ",
1840 rte_le_to_cpu_64(cfg->features));
1841 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_ADMINQ] 0x%" PRIx32 " ",
1842 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_ADMINQ]));
1843 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] 0x%" PRIx32 " ",
1844 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_NOTIFYQ]));
1845 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_RXQ] 0x%" PRIx32 " ",
1846 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]));
1847 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_TXQ] 0x%" PRIx32 " ",
1848 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]));
1854 ionic_lifs_size(struct ionic_adapter *adapter)
1856 struct ionic_identity *ident = &adapter->ident;
1857 union ionic_lif_config *cfg = &ident->lif.eth.config;
1858 uint32_t nintrs, dev_nintrs = rte_le_to_cpu_32(ident->dev.nintrs);
1860 adapter->max_ntxqs_per_lif =
1861 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]);
1862 adapter->max_nrxqs_per_lif =
1863 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]);
1865 nintrs = 1 /* notifyq */;
1867 if (nintrs > dev_nintrs) {
1869 "At most %d intr supported, minimum req'd is %u",
1870 dev_nintrs, nintrs);
1874 adapter->nintrs = nintrs;