drivers/net/ionic/ionic_lif.c

   1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
   2  * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
   3  */
   4
   5 #include <rte_malloc.h>
   6 #include <ethdev_driver.h>
   7
   8 #include "ionic.h"
   9 #include "ionic_logs.h"
  10 #include "ionic_lif.h"
  11 #include "ionic_ethdev.h"
  12 #include "ionic_rx_filter.h"
  13 #include "ionic_rxtx.h"
  14
  15 /* queuetype support level */
  16 static const uint8_t ionic_qtype_vers[IONIC_QTYPE_MAX] = {
  17         [IONIC_QTYPE_ADMINQ]  = 0,   /* 0 = Base version with CQ support */
  18         [IONIC_QTYPE_NOTIFYQ] = 0,   /* 0 = Base version */
  19         [IONIC_QTYPE_RXQ]     = 2,   /* 0 = Base version with CQ+SG support
  20                                       * 1 =       ... with EQ
  21                                       * 2 =       ... with CMB
  22                                       */
  23         [IONIC_QTYPE_TXQ]     = 3,   /* 0 = Base version with CQ+SG support
  24                                       * 1 =   ... with Tx SG version 1
  25                                       * 2 =       ... with EQ
  26                                       * 3 =       ... with CMB
  27                                       */
  28 };
  29
  30 static int ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr);
  31 static int ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr);
  32
  33 int
  34 ionic_qcq_enable(struct ionic_qcq *qcq)
  35 {
  36         struct ionic_queue *q = &qcq->q;
  37         struct ionic_lif *lif = q->lif;
  38         struct ionic_admin_ctx ctx = {
  39                 .pending_work = true,
  40                 .cmd.q_control = {
  41                         .opcode = IONIC_CMD_Q_CONTROL,
  42                         .type = q->type,
  43                         .index = rte_cpu_to_le_32(q->index),
  44                         .oper = IONIC_Q_ENABLE,
  45                 },
  46         };
  47
  48         return ionic_adminq_post_wait(lif, &ctx);
  49 }
  50
  51 int
  52 ionic_qcq_disable(struct ionic_qcq *qcq)
  53 {
  54         struct ionic_queue *q = &qcq->q;
  55         struct ionic_lif *lif = q->lif;
  56         struct ionic_admin_ctx ctx = {
  57                 .pending_work = true,
  58                 .cmd.q_control = {
  59                         .opcode = IONIC_CMD_Q_CONTROL,
  60                         .type = q->type,
  61                         .index = rte_cpu_to_le_32(q->index),
  62                         .oper = IONIC_Q_DISABLE,
  63                 },
  64         };
  65
  66         return ionic_adminq_post_wait(lif, &ctx);
  67 }
  68
  69 void
  70 ionic_lif_stop(struct ionic_lif *lif)
  71 {
  72         uint32_t i;
  73
  74         IONIC_PRINT_CALL();
  75
  76         lif->state &= ~IONIC_LIF_F_UP;
  77
  78         for (i = 0; i < lif->nrxqcqs; i++) {
  79                 struct ionic_qcq *rxq = lif->rxqcqs[i];
  80                 if (rxq->flags & IONIC_QCQ_F_INITED)
  81                         (void)ionic_dev_rx_queue_stop(lif->eth_dev, i);
  82         }
  83
  84         for (i = 0; i < lif->ntxqcqs; i++) {
  85                 struct ionic_qcq *txq = lif->txqcqs[i];
  86                 if (txq->flags & IONIC_QCQ_F_INITED)
  87                         (void)ionic_dev_tx_queue_stop(lif->eth_dev, i);
  88         }
  89 }
  90
  91 void
  92 ionic_lif_reset(struct ionic_lif *lif)
  93 {
  94         struct ionic_dev *idev = &lif->adapter->idev;
  95         int err;
  96
  97         IONIC_PRINT_CALL();
  98
  99         ionic_dev_cmd_lif_reset(idev);
 100         err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
 101         if (err)
 102                 IONIC_PRINT(WARNING, "Failed to reset %s", lif->name);
 103 }
 104
 105 static void
 106 ionic_lif_get_abs_stats(const struct ionic_lif *lif, struct rte_eth_stats *stats)
 107 {
 108         struct ionic_lif_stats *ls = &lif->info->stats;
 109         uint32_t i;
 110         uint32_t num_rx_q_counters = RTE_MIN(lif->nrxqcqs, (uint32_t)
 111                         RTE_ETHDEV_QUEUE_STAT_CNTRS);
 112         uint32_t num_tx_q_counters = RTE_MIN(lif->ntxqcqs, (uint32_t)
 113                         RTE_ETHDEV_QUEUE_STAT_CNTRS);
 114
 115         memset(stats, 0, sizeof(*stats));
 116
 117         if (ls == NULL) {
 118                 IONIC_PRINT(DEBUG, "Stats on port %u not yet initialized",
 119                         lif->port_id);
 120                 return;
 121         }
 122
 123         /* RX */
 124
 125         stats->ipackets = ls->rx_ucast_packets +
 126                 ls->rx_mcast_packets +
 127                 ls->rx_bcast_packets;
 128
 129         stats->ibytes = ls->rx_ucast_bytes +
 130                 ls->rx_mcast_bytes +
 131                 ls->rx_bcast_bytes;
 132
 133         for (i = 0; i < lif->nrxqcqs; i++) {
 134                 struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats.rx;
 135                 stats->imissed +=
 136                         rx_stats->no_cb_arg +
 137                         rx_stats->bad_cq_status +
 138                         rx_stats->no_room +
 139                         rx_stats->bad_len;
 140         }
 141
 142         stats->imissed +=
 143                 ls->rx_ucast_drop_packets +
 144                 ls->rx_mcast_drop_packets +
 145                 ls->rx_bcast_drop_packets;
 146
 147         stats->imissed +=
 148                 ls->rx_queue_empty +
 149                 ls->rx_dma_error +
 150                 ls->rx_queue_disabled +
 151                 ls->rx_desc_fetch_error +
 152                 ls->rx_desc_data_error;
 153
 154         for (i = 0; i < num_rx_q_counters; i++) {
 155                 struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats.rx;
 156                 stats->q_ipackets[i] = rx_stats->packets;
 157                 stats->q_ibytes[i] = rx_stats->bytes;
 158                 stats->q_errors[i] =
 159                         rx_stats->no_cb_arg +
 160                         rx_stats->bad_cq_status +
 161                         rx_stats->no_room +
 162                         rx_stats->bad_len;
 163         }
 164
 165         /* TX */
 166
 167         stats->opackets = ls->tx_ucast_packets +
 168                 ls->tx_mcast_packets +
 169                 ls->tx_bcast_packets;
 170
 171         stats->obytes = ls->tx_ucast_bytes +
 172                 ls->tx_mcast_bytes +
 173                 ls->tx_bcast_bytes;
 174
 175         for (i = 0; i < lif->ntxqcqs; i++) {
 176                 struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats.tx;
 177                 stats->oerrors += tx_stats->drop;
 178         }
 179
 180         stats->oerrors +=
 181                 ls->tx_ucast_drop_packets +
 182                 ls->tx_mcast_drop_packets +
 183                 ls->tx_bcast_drop_packets;
 184
 185         stats->oerrors +=
 186                 ls->tx_dma_error +
 187                 ls->tx_queue_disabled +
 188                 ls->tx_desc_fetch_error +
 189                 ls->tx_desc_data_error;
 190
 191         for (i = 0; i < num_tx_q_counters; i++) {
 192                 struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats.tx;
 193                 stats->q_opackets[i] = tx_stats->packets;
 194                 stats->q_obytes[i] = tx_stats->bytes;
 195         }
 196 }
 197
 198 void
 199 ionic_lif_get_stats(const struct ionic_lif *lif,
 200                 struct rte_eth_stats *stats)
 201 {
 202         ionic_lif_get_abs_stats(lif, stats);
 203
 204         stats->ipackets  -= lif->stats_base.ipackets;
 205         stats->opackets  -= lif->stats_base.opackets;
 206         stats->ibytes    -= lif->stats_base.ibytes;
 207         stats->obytes    -= lif->stats_base.obytes;
 208         stats->imissed   -= lif->stats_base.imissed;
 209         stats->ierrors   -= lif->stats_base.ierrors;
 210         stats->oerrors   -= lif->stats_base.oerrors;
 211         stats->rx_nombuf -= lif->stats_base.rx_nombuf;
 212 }
 213
 214 void
 215 ionic_lif_reset_stats(struct ionic_lif *lif)
 216 {
 217         uint32_t i;
 218
 219         for (i = 0; i < lif->nrxqcqs; i++) {
 220                 memset(&lif->rxqcqs[i]->stats.rx, 0,
 221                         sizeof(struct ionic_rx_stats));
 222                 memset(&lif->txqcqs[i]->stats.tx, 0,
 223                         sizeof(struct ionic_tx_stats));
 224         }
 225
 226         ionic_lif_get_abs_stats(lif, &lif->stats_base);
 227 }
 228
 229 void
 230 ionic_lif_get_hw_stats(struct ionic_lif *lif, struct ionic_lif_stats *stats)
 231 {
 232         uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t);
 233         uint64_t *stats64 = (uint64_t *)stats;
 234         uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats;
 235         uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base;
 236
 237         for (i = 0; i < count; i++)
 238                 stats64[i] = lif_stats64[i] - lif_stats64_base[i];
 239 }
 240
 241 void
 242 ionic_lif_reset_hw_stats(struct ionic_lif *lif)
 243 {
 244         uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t);
 245         uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats;
 246         uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base;
 247
 248         for (i = 0; i < count; i++)
 249                 lif_stats64_base[i] = lif_stats64[i];
 250 }
 251
 252 static int
 253 ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr)
 254 {
 255         struct ionic_admin_ctx ctx = {
 256                 .pending_work = true,
 257                 .cmd.rx_filter_add = {
 258                         .opcode = IONIC_CMD_RX_FILTER_ADD,
 259                         .match = rte_cpu_to_le_16(IONIC_RX_FILTER_MATCH_MAC),
 260                 },
 261         };
 262         int err;
 263
 264         memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, RTE_ETHER_ADDR_LEN);
 265
 266         err = ionic_adminq_post_wait(lif, &ctx);
 267         if (err)
 268                 return err;
 269
 270         IONIC_PRINT(INFO, "rx_filter add (id %d)",
 271                 rte_le_to_cpu_32(ctx.comp.rx_filter_add.filter_id));
 272
 273         return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);
 274 }
 275
 276 static int
 277 ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr)
 278 {
 279         struct ionic_admin_ctx ctx = {
 280                 .pending_work = true,
 281                 .cmd.rx_filter_del = {
 282                         .opcode = IONIC_CMD_RX_FILTER_DEL,
 283                 },
 284         };
 285         struct ionic_rx_filter *f;
 286         int err;
 287
 288         IONIC_PRINT_CALL();
 289
 290         rte_spinlock_lock(&lif->rx_filters.lock);
 291
 292         f = ionic_rx_filter_by_addr(lif, addr);
 293         if (!f) {
 294                 rte_spinlock_unlock(&lif->rx_filters.lock);
 295                 return -ENOENT;
 296         }
 297
 298         ctx.cmd.rx_filter_del.filter_id = rte_cpu_to_le_32(f->filter_id);
 299         ionic_rx_filter_free(f);
 300
 301         rte_spinlock_unlock(&lif->rx_filters.lock);
 302
 303         err = ionic_adminq_post_wait(lif, &ctx);
 304         if (err)
 305                 return err;
 306
 307         IONIC_PRINT(INFO, "rx_filter del (id %d)",
 308                 rte_le_to_cpu_32(ctx.cmd.rx_filter_del.filter_id));
 309
 310         return 0;
 311 }
 312
 313 int
 314 ionic_dev_add_mac(struct rte_eth_dev *eth_dev,
 315                 struct rte_ether_addr *mac_addr,
 316                 uint32_t index __rte_unused, uint32_t pool __rte_unused)
 317 {
 318         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 319
 320         IONIC_PRINT_CALL();
 321
 322         return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr);
 323 }
 324
 325 void
 326 ionic_dev_remove_mac(struct rte_eth_dev *eth_dev, uint32_t index)
 327 {
 328         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 329         struct ionic_adapter *adapter = lif->adapter;
 330         struct rte_ether_addr *mac_addr;
 331
 332         IONIC_PRINT_CALL();
 333
 334         if (index >= adapter->max_mac_addrs) {
 335                 IONIC_PRINT(WARNING,
 336                         "Index %u is above MAC filter limit %u",
 337                         index, adapter->max_mac_addrs);
 338                 return;
 339         }
 340
 341         mac_addr = &eth_dev->data->mac_addrs[index];
 342
 343         if (!rte_is_valid_assigned_ether_addr(mac_addr))
 344                 return;
 345
 346         ionic_lif_addr_del(lif, (const uint8_t *)mac_addr);
 347 }
 348
 349 int
 350 ionic_dev_set_mac(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr)
 351 {
 352         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 353
 354         IONIC_PRINT_CALL();
 355
 356         if (mac_addr == NULL) {
 357                 IONIC_PRINT(NOTICE, "New mac is null");
 358                 return -1;
 359         }
 360
 361         if (!rte_is_zero_ether_addr((struct rte_ether_addr *)lif->mac_addr)) {
 362                 IONIC_PRINT(INFO, "Deleting mac addr %pM",
 363                         lif->mac_addr);
 364                 ionic_lif_addr_del(lif, lif->mac_addr);
 365                 memset(lif->mac_addr, 0, RTE_ETHER_ADDR_LEN);
 366         }
 367
 368         IONIC_PRINT(INFO, "Updating mac addr");
 369
 370         rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)lif->mac_addr);
 371
 372         return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr);
 373 }
 374
 375 static int
 376 ionic_vlan_rx_add_vid(struct ionic_lif *lif, uint16_t vid)
 377 {
 378         struct ionic_admin_ctx ctx = {
 379                 .pending_work = true,
 380                 .cmd.rx_filter_add = {
 381                         .opcode = IONIC_CMD_RX_FILTER_ADD,
 382                         .match = rte_cpu_to_le_16(IONIC_RX_FILTER_MATCH_VLAN),
 383                         .vlan.vlan = rte_cpu_to_le_16(vid),
 384                 },
 385         };
 386         int err;
 387
 388         err = ionic_adminq_post_wait(lif, &ctx);
 389         if (err)
 390                 return err;
 391
 392         IONIC_PRINT(INFO, "rx_filter add VLAN %d (id %d)", vid,
 393                 rte_le_to_cpu_32(ctx.comp.rx_filter_add.filter_id));
 394
 395         return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);
 396 }
 397
 398 static int
 399 ionic_vlan_rx_kill_vid(struct ionic_lif *lif, uint16_t vid)
 400 {
 401         struct ionic_admin_ctx ctx = {
 402                 .pending_work = true,
 403                 .cmd.rx_filter_del = {
 404                         .opcode = IONIC_CMD_RX_FILTER_DEL,
 405                 },
 406         };
 407         struct ionic_rx_filter *f;
 408         int err;
 409
 410         IONIC_PRINT_CALL();
 411
 412         rte_spinlock_lock(&lif->rx_filters.lock);
 413
 414         f = ionic_rx_filter_by_vlan(lif, vid);
 415         if (!f) {
 416                 rte_spinlock_unlock(&lif->rx_filters.lock);
 417                 return -ENOENT;
 418         }
 419
 420         ctx.cmd.rx_filter_del.filter_id = rte_cpu_to_le_32(f->filter_id);
 421         ionic_rx_filter_free(f);
 422         rte_spinlock_unlock(&lif->rx_filters.lock);
 423
 424         err = ionic_adminq_post_wait(lif, &ctx);
 425         if (err)
 426                 return err;
 427
 428         IONIC_PRINT(INFO, "rx_filter del VLAN %d (id %d)", vid,
 429                 rte_le_to_cpu_32(ctx.cmd.rx_filter_del.filter_id));
 430
 431         return 0;
 432 }
 433
 434 int
 435 ionic_dev_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id,
 436                 int on)
 437 {
 438         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 439         int err;
 440
 441         if (on)
 442                 err = ionic_vlan_rx_add_vid(lif, vlan_id);
 443         else
 444                 err = ionic_vlan_rx_kill_vid(lif, vlan_id);
 445
 446         return err;
 447 }
 448
 449 static void
 450 ionic_lif_rx_mode(struct ionic_lif *lif, uint32_t rx_mode)
 451 {
 452         struct ionic_admin_ctx ctx = {
 453                 .pending_work = true,
 454                 .cmd.rx_mode_set = {
 455                         .opcode = IONIC_CMD_RX_MODE_SET,
 456                         .rx_mode = rte_cpu_to_le_16(rx_mode),
 457                 },
 458         };
 459         int err;
 460
 461         if (rx_mode & IONIC_RX_MODE_F_UNICAST)
 462                 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_UNICAST");
 463         if (rx_mode & IONIC_RX_MODE_F_MULTICAST)
 464                 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_MULTICAST");
 465         if (rx_mode & IONIC_RX_MODE_F_BROADCAST)
 466                 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_BROADCAST");
 467         if (rx_mode & IONIC_RX_MODE_F_PROMISC)
 468                 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_PROMISC");
 469         if (rx_mode & IONIC_RX_MODE_F_ALLMULTI)
 470                 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_ALLMULTI");
 471
 472         err = ionic_adminq_post_wait(lif, &ctx);
 473         if (err)
 474                 IONIC_PRINT(ERR, "Failure setting RX mode");
 475 }
 476
 477 static void
 478 ionic_set_rx_mode(struct ionic_lif *lif, uint32_t rx_mode)
 479 {
 480         if (lif->rx_mode != rx_mode) {
 481                 lif->rx_mode = rx_mode;
 482                 ionic_lif_rx_mode(lif, rx_mode);
 483         }
 484 }
 485
 486 int
 487 ionic_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
 488 {
 489         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 490         uint32_t rx_mode = lif->rx_mode;
 491
 492         IONIC_PRINT_CALL();
 493
 494         rx_mode |= IONIC_RX_MODE_F_PROMISC;
 495
 496         ionic_set_rx_mode(lif, rx_mode);
 497
 498         return 0;
 499 }
 500
 501 int
 502 ionic_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
 503 {
 504         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 505         uint32_t rx_mode = lif->rx_mode;
 506
 507         rx_mode &= ~IONIC_RX_MODE_F_PROMISC;
 508
 509         ionic_set_rx_mode(lif, rx_mode);
 510
 511         return 0;
 512 }
 513
 514 int
 515 ionic_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
 516 {
 517         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 518         uint32_t rx_mode = lif->rx_mode;
 519
 520         rx_mode |= IONIC_RX_MODE_F_ALLMULTI;
 521
 522         ionic_set_rx_mode(lif, rx_mode);
 523
 524         return 0;
 525 }
 526
 527 int
 528 ionic_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
 529 {
 530         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 531         uint32_t rx_mode = lif->rx_mode;
 532
 533         rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI;
 534
 535         ionic_set_rx_mode(lif, rx_mode);
 536
 537         return 0;
 538 }
 539
 540 int
 541 ionic_lif_change_mtu(struct ionic_lif *lif, int new_mtu)
 542 {
 543         struct ionic_admin_ctx ctx = {
 544                 .pending_work = true,
 545                 .cmd.lif_setattr = {
 546                         .opcode = IONIC_CMD_LIF_SETATTR,
 547                         .attr = IONIC_LIF_ATTR_MTU,
 548                         .mtu = rte_cpu_to_le_32(new_mtu),
 549                 },
 550         };
 551         int err;
 552
 553         err = ionic_adminq_post_wait(lif, &ctx);
 554         if (err)
 555                 return err;
 556
 557         return 0;
 558 }
 559
 560 int
 561 ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr)
 562 {
 563         struct ionic_adapter *adapter = lif->adapter;
 564         struct ionic_dev *idev = &adapter->idev;
 565         unsigned long index;
 566
 567         /*
 568          * Note: interrupt handler is called for index = 0 only
 569          * (we use interrupts for the notifyq only anyway,
 570          * which has index = 0)
 571          */
 572
 573         for (index = 0; index < adapter->nintrs; index++)
 574                 if (!adapter->intrs[index])
 575                         break;
 576
 577         if (index == adapter->nintrs)
 578                 return -ENOSPC;
 579
 580         adapter->intrs[index] = true;
 581
 582         ionic_intr_init(idev, intr, index);
 583
 584         return 0;
 585 }
 586
 587 void
 588 ionic_intr_free(struct ionic_lif *lif, struct ionic_intr_info *intr)
 589 {
 590         if (intr->index != IONIC_INTR_NONE)
 591                 lif->adapter->intrs[intr->index] = false;
 592 }
 593
 594 static int
 595 ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type,
 596                 uint32_t index,
 597                 const char *base, uint32_t flags,
 598                 uint32_t num_descs,
 599                 uint32_t desc_size,
 600                 uint32_t cq_desc_size,
 601                 uint32_t sg_desc_size,
 602                 struct ionic_qcq **qcq)
 603 {
 604         struct ionic_dev *idev = &lif->adapter->idev;
 605         struct ionic_qcq *new;
 606         uint32_t q_size, cq_size, sg_size, total_size;
 607         void *q_base, *cq_base, *sg_base;
 608         rte_iova_t q_base_pa = 0;
 609         rte_iova_t cq_base_pa = 0;
 610         rte_iova_t sg_base_pa = 0;
 611         uint32_t socket_id = rte_socket_id();
 612         int err;
 613
 614         *qcq = NULL;
 615
 616         q_size  = num_descs * desc_size;
 617         cq_size = num_descs * cq_desc_size;
 618         sg_size = num_descs * sg_desc_size;
 619
 620         total_size = RTE_ALIGN(q_size, PAGE_SIZE) +
 621                 RTE_ALIGN(cq_size, PAGE_SIZE);
 622         /*
 623          * Note: aligning q_size/cq_size is not enough due to cq_base address
 624          * aligning as q_base could be not aligned to the page.
 625          * Adding PAGE_SIZE.
 626          */
 627         total_size += PAGE_SIZE;
 628
 629         if (flags & IONIC_QCQ_F_SG) {
 630                 total_size += RTE_ALIGN(sg_size, PAGE_SIZE);
 631                 total_size += PAGE_SIZE;
 632         }
 633
 634         new = rte_zmalloc("ionic", sizeof(*new), 0);
 635         if (!new) {
 636                 IONIC_PRINT(ERR, "Cannot allocate queue structure");
 637                 return -ENOMEM;
 638         }
 639
 640         new->lif = lif;
 641         new->flags = flags;
 642
 643         new->q.info = rte_zmalloc("ionic", sizeof(*new->q.info) * num_descs, 0);
 644         if (!new->q.info) {
 645                 IONIC_PRINT(ERR, "Cannot allocate queue info");
 646                 err = -ENOMEM;
 647                 goto err_out_free_qcq;
 648         }
 649
 650         new->q.type = type;
 651
 652         err = ionic_q_init(lif, idev, &new->q, index, num_descs,
 653                 desc_size, sg_desc_size);
 654         if (err) {
 655                 IONIC_PRINT(ERR, "Queue initialization failed");
 656                 goto err_out_free_info;
 657         }
 658
 659         err = ionic_cq_init(&new->cq, num_descs);
 660         if (err) {
 661                 IONIC_PRINT(ERR, "Completion queue initialization failed");
 662                 goto err_out_free_info;
 663         }
 664
 665         new->base_z = rte_eth_dma_zone_reserve(lif->eth_dev,
 666                 base /* name */, index /* queue_idx */,
 667                 total_size, IONIC_ALIGN, socket_id);
 668
 669         if (!new->base_z) {
 670                 IONIC_PRINT(ERR, "Cannot reserve queue DMA memory");
 671                 err = -ENOMEM;
 672                 goto err_out_free_info;
 673         }
 674
 675         new->base = new->base_z->addr;
 676         new->base_pa = new->base_z->iova;
 677         new->total_size = total_size;
 678
 679         q_base = new->base;
 680         q_base_pa = new->base_pa;
 681
 682         cq_base = (void *)RTE_ALIGN((uintptr_t)q_base + q_size, PAGE_SIZE);
 683         cq_base_pa = RTE_ALIGN(q_base_pa + q_size, PAGE_SIZE);
 684
 685         if (flags & IONIC_QCQ_F_SG) {
 686                 sg_base = (void *)RTE_ALIGN((uintptr_t)cq_base + cq_size,
 687                         PAGE_SIZE);
 688                 sg_base_pa = RTE_ALIGN(cq_base_pa + cq_size, PAGE_SIZE);
 689                 ionic_q_sg_map(&new->q, sg_base, sg_base_pa);
 690         }
 691
 692         IONIC_PRINT(DEBUG, "Q-Base-PA = %#jx CQ-Base-PA = %#jx "
 693                 "SG-base-PA = %#jx",
 694                 q_base_pa, cq_base_pa, sg_base_pa);
 695
 696         ionic_q_map(&new->q, q_base, q_base_pa);
 697         ionic_cq_map(&new->cq, cq_base, cq_base_pa);
 698
 699         *qcq = new;
 700
 701         return 0;
 702
 703 err_out_free_info:
 704         rte_free(new->q.info);
 705 err_out_free_qcq:
 706         rte_free(new);
 707
 708         return err;
 709 }
 710
 711 void
 712 ionic_qcq_free(struct ionic_qcq *qcq)
 713 {
 714         if (qcq->base_z) {
 715                 qcq->base = NULL;
 716                 qcq->base_pa = 0;
 717                 rte_memzone_free(qcq->base_z);
 718                 qcq->base_z = NULL;
 719         }
 720
 721         if (qcq->q.info) {
 722                 rte_free(qcq->q.info);
 723                 qcq->q.info = NULL;
 724         }
 725
 726         rte_free(qcq);
 727 }
 728
 729 int
 730 ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t nrxq_descs,
 731                 struct ionic_qcq **qcq)
 732 {
 733         uint32_t flags;
 734         int err = -ENOMEM;
 735
 736         flags = IONIC_QCQ_F_SG;
 737         err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, index, "rx", flags,
 738                 nrxq_descs,
 739                 sizeof(struct ionic_rxq_desc),
 740                 sizeof(struct ionic_rxq_comp),
 741                 sizeof(struct ionic_rxq_sg_desc),
 742                 &lif->rxqcqs[index]);
 743         if (err)
 744                 return err;
 745
 746         *qcq = lif->rxqcqs[index];
 747
 748         return 0;
 749 }
 750
 751 int
 752 ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t ntxq_descs,
 753                 struct ionic_qcq **qcq)
 754 {
 755         uint32_t flags;
 756         int err = -ENOMEM;
 757
 758         flags = IONIC_QCQ_F_SG;
 759         err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, index, "tx", flags,
 760                 ntxq_descs,
 761                 sizeof(struct ionic_txq_desc),
 762                 sizeof(struct ionic_txq_comp),
 763                 sizeof(struct ionic_txq_sg_desc_v1),
 764                 &lif->txqcqs[index]);
 765         if (err)
 766                 return err;
 767
 768         *qcq = lif->txqcqs[index];
 769
 770         return 0;
 771 }
 772
 773 static int
 774 ionic_admin_qcq_alloc(struct ionic_lif *lif)
 775 {
 776         uint32_t flags;
 777         int err = -ENOMEM;
 778
 779         flags = 0;
 780         err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags,
 781                 IONIC_ADMINQ_LENGTH,
 782                 sizeof(struct ionic_admin_cmd),
 783                 sizeof(struct ionic_admin_comp),
 784                 0,
 785                 &lif->adminqcq);
 786         if (err)
 787                 return err;
 788
 789         return 0;
 790 }
 791
 792 static int
 793 ionic_notify_qcq_alloc(struct ionic_lif *lif)
 794 {
 795         struct ionic_qcq *nqcq;
 796         struct ionic_dev *idev = &lif->adapter->idev;
 797         uint32_t flags = 0;
 798         int err = -ENOMEM;
 799
 800         err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notify",
 801                 flags,
 802                 IONIC_NOTIFYQ_LENGTH,
 803                 sizeof(struct ionic_notifyq_cmd),
 804                 sizeof(union ionic_notifyq_comp),
 805                 0,
 806                 &nqcq);
 807         if (err)
 808                 return err;
 809
 810         err = ionic_intr_alloc(lif, &nqcq->intr);
 811         if (err) {
 812                 ionic_qcq_free(nqcq);
 813                 return err;
 814         }
 815
 816         ionic_intr_mask_assert(idev->intr_ctrl, nqcq->intr.index,
 817                 IONIC_INTR_MASK_SET);
 818
 819         lif->notifyqcq = nqcq;
 820
 821         return 0;
 822 }
 823
 824 static void *
 825 ionic_bus_map_dbpage(struct ionic_adapter *adapter, int page_num)
 826 {
 827         char *vaddr = adapter->bars[IONIC_PCI_BAR_DBELL].vaddr;
 828
 829         if (adapter->num_bars <= IONIC_PCI_BAR_DBELL)
 830                 return NULL;
 831
 832         return (void *)&vaddr[page_num << PAGE_SHIFT];
 833 }
 834
 835 static void
 836 ionic_lif_queue_identify(struct ionic_lif *lif)
 837 {
 838         struct ionic_adapter *adapter = lif->adapter;
 839         struct ionic_dev *idev = &adapter->idev;
 840         union ionic_q_identity *q_ident = &adapter->ident.txq;
 841         uint32_t q_words = RTE_DIM(q_ident->words);
 842         uint32_t cmd_words = RTE_DIM(idev->dev_cmd->data);
 843         uint32_t i, nwords, qtype;
 844         int err;
 845
 846         for (qtype = 0; qtype < RTE_DIM(ionic_qtype_vers); qtype++) {
 847                 struct ionic_qtype_info *qti = &lif->qtype_info[qtype];
 848
 849                 /* Filter out the types this driver knows about */
 850                 switch (qtype) {
 851                 case IONIC_QTYPE_ADMINQ:
 852                 case IONIC_QTYPE_NOTIFYQ:
 853                 case IONIC_QTYPE_RXQ:
 854                 case IONIC_QTYPE_TXQ:
 855                         break;
 856                 default:
 857                         continue;
 858                 }
 859
 860                 memset(qti, 0, sizeof(*qti));
 861
 862                 ionic_dev_cmd_queue_identify(idev, IONIC_LIF_TYPE_CLASSIC,
 863                         qtype, ionic_qtype_vers[qtype]);
 864                 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
 865                 if (err == -EINVAL) {
 866                         IONIC_PRINT(ERR, "qtype %d not supported\n", qtype);
 867                         continue;
 868                 } else if (err == -EIO) {
 869                         IONIC_PRINT(ERR, "q_ident failed, older FW\n");
 870                         return;
 871                 } else if (err) {
 872                         IONIC_PRINT(ERR, "q_ident failed, qtype %d: %d\n",
 873                                 qtype, err);
 874                         return;
 875                 }
 876
 877                 nwords = RTE_MIN(q_words, cmd_words);
 878                 for (i = 0; i < nwords; i++)
 879                         q_ident->words[i] = ioread32(&idev->dev_cmd->data[i]);
 880
 881                 qti->version   = q_ident->version;
 882                 qti->supported = q_ident->supported;
 883                 qti->features  = rte_le_to_cpu_64(q_ident->features);
 884                 qti->desc_sz   = rte_le_to_cpu_16(q_ident->desc_sz);
 885                 qti->comp_sz   = rte_le_to_cpu_16(q_ident->comp_sz);
 886                 qti->sg_desc_sz   = rte_le_to_cpu_16(q_ident->sg_desc_sz);
 887                 qti->max_sg_elems = rte_le_to_cpu_16(q_ident->max_sg_elems);
 888                 qti->sg_desc_stride =
 889                         rte_le_to_cpu_16(q_ident->sg_desc_stride);
 890
 891                 IONIC_PRINT(DEBUG, " qtype[%d].version = %d",
 892                         qtype, qti->version);
 893                 IONIC_PRINT(DEBUG, " qtype[%d].supported = %#x",
 894                         qtype, qti->supported);
 895                 IONIC_PRINT(DEBUG, " qtype[%d].features = %#jx",
 896                         qtype, qti->features);
 897                 IONIC_PRINT(DEBUG, " qtype[%d].desc_sz = %d",
 898                         qtype, qti->desc_sz);
 899                 IONIC_PRINT(DEBUG, " qtype[%d].comp_sz = %d",
 900                         qtype, qti->comp_sz);
 901                 IONIC_PRINT(DEBUG, " qtype[%d].sg_desc_sz = %d",
 902                         qtype, qti->sg_desc_sz);
 903                 IONIC_PRINT(DEBUG, " qtype[%d].max_sg_elems = %d",
 904                         qtype, qti->max_sg_elems);
 905                 IONIC_PRINT(DEBUG, " qtype[%d].sg_desc_stride = %d",
 906                         qtype, qti->sg_desc_stride);
 907         }
 908 }
 909
 910 int
 911 ionic_lif_alloc(struct ionic_lif *lif)
 912 {
 913         struct ionic_adapter *adapter = lif->adapter;
 914         uint32_t socket_id = rte_socket_id();
 915         int err;
 916
 917         /*
 918          * lif->name was zeroed on allocation.
 919          * Copy (sizeof() - 1) bytes to ensure that it is NULL terminated.
 920          */
 921         memcpy(lif->name, lif->eth_dev->data->name, sizeof(lif->name) - 1);
 922
 923         IONIC_PRINT(DEBUG, "LIF: %s", lif->name);
 924
 925         ionic_lif_queue_identify(lif);
 926
 927         if (lif->qtype_info[IONIC_QTYPE_TXQ].version < 1) {
 928                 IONIC_PRINT(ERR, "FW too old, please upgrade");
 929                 return -ENXIO;
 930         }
 931
 932         IONIC_PRINT(DEBUG, "Allocating Lif Info");
 933
 934         rte_spinlock_init(&lif->adminq_lock);
 935         rte_spinlock_init(&lif->adminq_service_lock);
 936
 937         lif->kern_dbpage = ionic_bus_map_dbpage(adapter, 0);
 938         if (!lif->kern_dbpage) {
 939                 IONIC_PRINT(ERR, "Cannot map dbpage, aborting");
 940                 return -ENOMEM;
 941         }
 942
 943         lif->txqcqs = rte_zmalloc("ionic", sizeof(*lif->txqcqs) *
 944                 adapter->max_ntxqs_per_lif, 0);
 945
 946         if (!lif->txqcqs) {
 947                 IONIC_PRINT(ERR, "Cannot allocate tx queues array");
 948                 return -ENOMEM;
 949         }
 950
 951         lif->rxqcqs = rte_zmalloc("ionic", sizeof(*lif->rxqcqs) *
 952                 adapter->max_nrxqs_per_lif, 0);
 953
 954         if (!lif->rxqcqs) {
 955                 IONIC_PRINT(ERR, "Cannot allocate rx queues array");
 956                 return -ENOMEM;
 957         }
 958
 959         IONIC_PRINT(DEBUG, "Allocating Notify Queue");
 960
 961         err = ionic_notify_qcq_alloc(lif);
 962         if (err) {
 963                 IONIC_PRINT(ERR, "Cannot allocate notify queue");
 964                 return err;
 965         }
 966
 967         IONIC_PRINT(DEBUG, "Allocating Admin Queue");
 968
 969         err = ionic_admin_qcq_alloc(lif);
 970         if (err) {
 971                 IONIC_PRINT(ERR, "Cannot allocate admin queue");
 972                 return err;
 973         }
 974
 975         IONIC_PRINT(DEBUG, "Allocating Lif Info");
 976
 977         lif->info_sz = RTE_ALIGN(sizeof(*lif->info), PAGE_SIZE);
 978
 979         lif->info_z = rte_eth_dma_zone_reserve(lif->eth_dev,
 980                 "lif_info", 0 /* queue_idx*/,
 981                 lif->info_sz, IONIC_ALIGN, socket_id);
 982         if (!lif->info_z) {
 983                 IONIC_PRINT(ERR, "Cannot allocate lif info memory");
 984                 return -ENOMEM;
 985         }
 986
 987         lif->info = lif->info_z->addr;
 988         lif->info_pa = lif->info_z->iova;
 989
 990         return 0;
 991 }
 992
 993 void
 994 ionic_lif_free(struct ionic_lif *lif)
 995 {
 996         if (lif->notifyqcq) {
 997                 ionic_qcq_free(lif->notifyqcq);
 998                 lif->notifyqcq = NULL;
 999         }
1000
1001         if (lif->adminqcq) {
1002                 ionic_qcq_free(lif->adminqcq);
1003                 lif->adminqcq = NULL;
1004         }
1005
1006         if (lif->txqcqs) {
1007                 rte_free(lif->txqcqs);
1008                 lif->txqcqs = NULL;
1009         }
1010
1011         if (lif->rxqcqs) {
1012                 rte_free(lif->rxqcqs);
1013                 lif->rxqcqs = NULL;
1014         }
1015
1016         if (lif->info) {
1017                 rte_memzone_free(lif->info_z);
1018                 lif->info = NULL;
1019         }
1020 }
1021
1022 void
1023 ionic_lif_free_queues(struct ionic_lif *lif)
1024 {
1025         uint32_t i;
1026
1027         for (i = 0; i < lif->ntxqcqs; i++) {
1028                 ionic_dev_tx_queue_release(lif->eth_dev->data->tx_queues[i]);
1029                 lif->eth_dev->data->tx_queues[i] = NULL;
1030         }
1031         for (i = 0; i < lif->nrxqcqs; i++) {
1032                 ionic_dev_rx_queue_release(lif->eth_dev->data->rx_queues[i]);
1033                 lif->eth_dev->data->rx_queues[i] = NULL;
1034         }
1035 }
1036
1037 int
1038 ionic_lif_rss_config(struct ionic_lif *lif,
1039                 const uint16_t types, const uint8_t *key, const uint32_t *indir)
1040 {
1041         struct ionic_adapter *adapter = lif->adapter;
1042         struct ionic_admin_ctx ctx = {
1043                 .pending_work = true,
1044                 .cmd.lif_setattr = {
1045                         .opcode = IONIC_CMD_LIF_SETATTR,
1046                         .attr = IONIC_LIF_ATTR_RSS,
1047                         .rss.types = rte_cpu_to_le_16(types),
1048                         .rss.addr = rte_cpu_to_le_64(lif->rss_ind_tbl_pa),
1049                 },
1050         };
1051         unsigned int i;
1052         uint16_t tbl_sz =
1053                 rte_le_to_cpu_16(adapter->ident.lif.eth.rss_ind_tbl_sz);
1054
1055         IONIC_PRINT_CALL();
1056
1057         lif->rss_types = types;
1058
1059         if (key)
1060                 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE);
1061
1062         if (indir)
1063                 for (i = 0; i < tbl_sz; i++)
1064                         lif->rss_ind_tbl[i] = indir[i];
1065
1066         memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key,
1067                IONIC_RSS_HASH_KEY_SIZE);
1068
1069         return ionic_adminq_post_wait(lif, &ctx);
1070 }
1071
1072 static int
1073 ionic_lif_rss_setup(struct ionic_lif *lif)
1074 {
1075         struct ionic_adapter *adapter = lif->adapter;
1076         static const uint8_t toeplitz_symmetric_key[] = {
1077                 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
1078                 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
1079                 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
1080                 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
1081                 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
1082         };
1083         uint32_t i;
1084         uint16_t tbl_sz =
1085                 rte_le_to_cpu_16(adapter->ident.lif.eth.rss_ind_tbl_sz);
1086
1087         IONIC_PRINT_CALL();
1088
1089         if (!lif->rss_ind_tbl_z) {
1090                 lif->rss_ind_tbl_z = rte_eth_dma_zone_reserve(lif->eth_dev,
1091                                         "rss_ind_tbl", 0 /* queue_idx */,
1092                                         sizeof(*lif->rss_ind_tbl) * tbl_sz,
1093                                         IONIC_ALIGN, rte_socket_id());
1094                 if (!lif->rss_ind_tbl_z) {
1095                         IONIC_PRINT(ERR, "OOM");
1096                         return -ENOMEM;
1097                 }
1098
1099                 lif->rss_ind_tbl = lif->rss_ind_tbl_z->addr;
1100                 lif->rss_ind_tbl_pa = lif->rss_ind_tbl_z->iova;
1101         }
1102
1103         if (lif->rss_ind_tbl_nrxqcqs != lif->nrxqcqs) {
1104                 lif->rss_ind_tbl_nrxqcqs = lif->nrxqcqs;
1105
1106                 /* Fill indirection table with 'default' values */
1107                 for (i = 0; i < tbl_sz; i++)
1108                         lif->rss_ind_tbl[i] = i % lif->nrxqcqs;
1109         }
1110
1111         return ionic_lif_rss_config(lif, IONIC_RSS_OFFLOAD_ALL,
1112                         toeplitz_symmetric_key, NULL);
1113 }
1114
1115 static void
1116 ionic_lif_rss_teardown(struct ionic_lif *lif)
1117 {
1118         if (!lif->rss_ind_tbl)
1119                 return;
1120
1121         if (lif->rss_ind_tbl_z) {
1122                 /* Disable RSS on the NIC */
1123                 ionic_lif_rss_config(lif, 0x0, NULL, NULL);
1124
1125                 lif->rss_ind_tbl = NULL;
1126                 lif->rss_ind_tbl_pa = 0;
1127                 rte_memzone_free(lif->rss_ind_tbl_z);
1128                 lif->rss_ind_tbl_z = NULL;
1129         }
1130 }
1131
1132 static void
1133 ionic_lif_qcq_deinit(struct ionic_qcq *qcq)
1134 {
1135         qcq->flags &= ~IONIC_QCQ_F_INITED;
1136 }
1137
1138 void
1139 ionic_lif_txq_deinit(struct ionic_qcq *qcq)
1140 {
1141         ionic_lif_qcq_deinit(qcq);
1142 }
1143
1144 void
1145 ionic_lif_rxq_deinit(struct ionic_qcq *qcq)
1146 {
1147         ionic_lif_qcq_deinit(qcq);
1148 }
1149
1150 static void
1151 ionic_lif_notifyq_deinit(struct ionic_lif *lif)
1152 {
1153         struct ionic_qcq *nqcq = lif->notifyqcq;
1154         struct ionic_dev *idev = &lif->adapter->idev;
1155
1156         if (!(nqcq->flags & IONIC_QCQ_F_INITED))
1157                 return;
1158
1159         ionic_intr_mask(idev->intr_ctrl, nqcq->intr.index,
1160                 IONIC_INTR_MASK_SET);
1161
1162         nqcq->flags &= ~IONIC_QCQ_F_INITED;
1163 }
1164
1165 /* This acts like ionic_napi */
1166 int
1167 ionic_qcq_service(struct ionic_qcq *qcq, int budget, ionic_cq_cb cb,
1168                 void *cb_arg)
1169 {
1170         struct ionic_cq *cq = &qcq->cq;
1171         uint32_t work_done;
1172
1173         work_done = ionic_cq_service(cq, budget, cb, cb_arg);
1174
1175         return work_done;
1176 }
1177
1178 static void
1179 ionic_link_status_check(struct ionic_lif *lif)
1180 {
1181         struct ionic_adapter *adapter = lif->adapter;
1182         bool link_up;
1183
1184         lif->state &= ~IONIC_LIF_F_LINK_CHECK_NEEDED;
1185
1186         if (!lif->info)
1187                 return;
1188
1189         link_up = (lif->info->status.link_status == IONIC_PORT_OPER_STATUS_UP);
1190
1191         if ((link_up  && adapter->link_up) ||
1192             (!link_up && !adapter->link_up))
1193                 return;
1194
1195         if (link_up) {
1196                 adapter->link_speed =
1197                         rte_le_to_cpu_32(lif->info->status.link_speed);
1198                 IONIC_PRINT(DEBUG, "Link up - %d Gbps",
1199                         adapter->link_speed);
1200         } else {
1201                 IONIC_PRINT(DEBUG, "Link down");
1202         }
1203
1204         adapter->link_up = link_up;
1205         ionic_dev_link_update(lif->eth_dev, 0);
1206 }
1207
1208 static void
1209 ionic_lif_handle_fw_down(struct ionic_lif *lif)
1210 {
1211         if (lif->state & IONIC_LIF_F_FW_RESET)
1212                 return;
1213
1214         lif->state |= IONIC_LIF_F_FW_RESET;
1215
1216         if (lif->state & IONIC_LIF_F_UP) {
1217                 IONIC_PRINT(NOTICE,
1218                         "Surprise FW stop, stopping %s\n", lif->name);
1219                 ionic_lif_stop(lif);
1220         }
1221
1222         IONIC_PRINT(NOTICE, "FW down, %s stopped", lif->name);
1223 }
1224
1225 static bool
1226 ionic_notifyq_cb(struct ionic_cq *cq, uint32_t cq_desc_index, void *cb_arg)
1227 {
1228         union ionic_notifyq_comp *cq_desc_base = cq->base;
1229         union ionic_notifyq_comp *cq_desc = &cq_desc_base[cq_desc_index];
1230         struct ionic_lif *lif = cb_arg;
1231
1232         IONIC_PRINT(DEBUG, "Notifyq callback eid = %jd ecode = %d",
1233                 cq_desc->event.eid, cq_desc->event.ecode);
1234
1235         /* Have we run out of new completions to process? */
1236         if (!(cq_desc->event.eid > lif->last_eid))
1237                 return false;
1238
1239         lif->last_eid = cq_desc->event.eid;
1240
1241         switch (cq_desc->event.ecode) {
1242         case IONIC_EVENT_LINK_CHANGE:
1243                 IONIC_PRINT(DEBUG,
1244                         "Notifyq IONIC_EVENT_LINK_CHANGE %s "
1245                         "eid=%jd link_status=%d link_speed=%d",
1246                         lif->name,
1247                         cq_desc->event.eid,
1248                         cq_desc->link_change.link_status,
1249                         cq_desc->link_change.link_speed);
1250
1251                 lif->state |= IONIC_LIF_F_LINK_CHECK_NEEDED;
1252                 break;
1253
1254         case IONIC_EVENT_RESET:
1255                 IONIC_PRINT(NOTICE,
1256                         "Notifyq IONIC_EVENT_RESET %s "
1257                         "eid=%jd, reset_code=%d state=%d",
1258                         lif->name,
1259                         cq_desc->event.eid,
1260                         cq_desc->reset.reset_code,
1261                         cq_desc->reset.state);
1262                 ionic_lif_handle_fw_down(lif);
1263                 break;
1264
1265         default:
1266                 IONIC_PRINT(WARNING, "Notifyq bad event ecode=%d eid=%jd",
1267                         cq_desc->event.ecode, cq_desc->event.eid);
1268                 break;
1269         }
1270
1271         return true;
1272 }
1273
1274 int
1275 ionic_notifyq_handler(struct ionic_lif *lif, int budget)
1276 {
1277         struct ionic_dev *idev = &lif->adapter->idev;
1278         struct ionic_qcq *qcq = lif->notifyqcq;
1279         uint32_t work_done;
1280
1281         if (!(qcq->flags & IONIC_QCQ_F_INITED)) {
1282                 IONIC_PRINT(DEBUG, "Notifyq not yet initialized");
1283                 return -1;
1284         }
1285
1286         ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1287                 IONIC_INTR_MASK_SET);
1288
1289         work_done = ionic_qcq_service(qcq, budget, ionic_notifyq_cb, lif);
1290
1291         if (lif->state & IONIC_LIF_F_LINK_CHECK_NEEDED)
1292                 ionic_link_status_check(lif);
1293
1294         ionic_intr_credits(idev->intr_ctrl, qcq->intr.index,
1295                 work_done, IONIC_INTR_CRED_RESET_COALESCE);
1296
1297         ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1298                 IONIC_INTR_MASK_CLEAR);
1299
1300         return 0;
1301 }
1302
1303 static int
1304 ionic_lif_adminq_init(struct ionic_lif *lif)
1305 {
1306         struct ionic_dev *idev = &lif->adapter->idev;
1307         struct ionic_qcq *qcq = lif->adminqcq;
1308         struct ionic_queue *q = &qcq->q;
1309         struct ionic_q_init_comp comp;
1310         int err;
1311
1312         ionic_dev_cmd_adminq_init(idev, qcq);
1313         err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1314         if (err)
1315                 return err;
1316
1317         ionic_dev_cmd_comp(idev, &comp);
1318
1319         q->hw_type = comp.hw_type;
1320         q->hw_index = rte_le_to_cpu_32(comp.hw_index);
1321         q->db = ionic_db_map(lif, q);
1322
1323         IONIC_PRINT(DEBUG, "adminq->hw_type %d", q->hw_type);
1324         IONIC_PRINT(DEBUG, "adminq->hw_index %d", q->hw_index);
1325         IONIC_PRINT(DEBUG, "adminq->db %p", q->db);
1326
1327         qcq->flags |= IONIC_QCQ_F_INITED;
1328
1329         return 0;
1330 }
1331
1332 static int
1333 ionic_lif_notifyq_init(struct ionic_lif *lif)
1334 {
1335         struct ionic_dev *idev = &lif->adapter->idev;
1336         struct ionic_qcq *qcq = lif->notifyqcq;
1337         struct ionic_queue *q = &qcq->q;
1338         int err;
1339
1340         struct ionic_admin_ctx ctx = {
1341                 .pending_work = true,
1342                 .cmd.q_init = {
1343                         .opcode = IONIC_CMD_Q_INIT,
1344                         .type = q->type,
1345                         .ver = lif->qtype_info[q->type].version,
1346                         .index = rte_cpu_to_le_32(q->index),
1347                         .intr_index = rte_cpu_to_le_16(qcq->intr.index),
1348                         .flags = rte_cpu_to_le_16(IONIC_QINIT_F_IRQ |
1349                                                 IONIC_QINIT_F_ENA),
1350                         .ring_size = rte_log2_u32(q->num_descs),
1351                         .ring_base = rte_cpu_to_le_64(q->base_pa),
1352                 }
1353         };
1354
1355         IONIC_PRINT(DEBUG, "notifyq_init.index %d", q->index);
1356         IONIC_PRINT(DEBUG, "notifyq_init.ring_base 0x%" PRIx64 "", q->base_pa);
1357         IONIC_PRINT(DEBUG, "notifyq_init.ring_size %d",
1358                 ctx.cmd.q_init.ring_size);
1359         IONIC_PRINT(DEBUG, "notifyq_init.ver %u", ctx.cmd.q_init.ver);
1360
1361         err = ionic_adminq_post_wait(lif, &ctx);
1362         if (err)
1363                 return err;
1364
1365         q->hw_type = ctx.comp.q_init.hw_type;
1366         q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index);
1367         q->db = NULL;
1368
1369         IONIC_PRINT(DEBUG, "notifyq->hw_type %d", q->hw_type);
1370         IONIC_PRINT(DEBUG, "notifyq->hw_index %d", q->hw_index);
1371         IONIC_PRINT(DEBUG, "notifyq->db %p", q->db);
1372
1373         ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1374                 IONIC_INTR_MASK_CLEAR);
1375
1376         qcq->flags |= IONIC_QCQ_F_INITED;
1377
1378         return 0;
1379 }
1380
1381 int
1382 ionic_lif_set_features(struct ionic_lif *lif)
1383 {
1384         struct ionic_admin_ctx ctx = {
1385                 .pending_work = true,
1386                 .cmd.lif_setattr = {
1387                         .opcode = IONIC_CMD_LIF_SETATTR,
1388                         .attr = IONIC_LIF_ATTR_FEATURES,
1389                         .features = rte_cpu_to_le_64(lif->features),
1390                 },
1391         };
1392         int err;
1393
1394         err = ionic_adminq_post_wait(lif, &ctx);
1395         if (err)
1396                 return err;
1397
1398         lif->hw_features = rte_le_to_cpu_64(ctx.cmd.lif_setattr.features &
1399                                                 ctx.comp.lif_setattr.features);
1400
1401         if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
1402                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_TX_TAG");
1403         if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
1404                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_STRIP");
1405         if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
1406                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_FILTER");
1407         if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
1408                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_HASH");
1409         if (lif->hw_features & IONIC_ETH_HW_TX_SG)
1410                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_SG");
1411         if (lif->hw_features & IONIC_ETH_HW_RX_SG)
1412                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_SG");
1413         if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
1414                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_CSUM");
1415         if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
1416                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_CSUM");
1417         if (lif->hw_features & IONIC_ETH_HW_TSO)
1418                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO");
1419         if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
1420                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPV6");
1421         if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
1422                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_ECN");
1423         if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
1424                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE");
1425         if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
1426                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE_CSUM");
1427         if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
1428                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP4");
1429         if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
1430                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP6");
1431         if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
1432                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP");
1433         if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
1434                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP_CSUM");
1435
1436         return 0;
1437 }
1438
1439 int
1440 ionic_lif_txq_init(struct ionic_qcq *qcq)
1441 {
1442         struct ionic_queue *q = &qcq->q;
1443         struct ionic_lif *lif = qcq->lif;
1444         struct ionic_cq *cq = &qcq->cq;
1445         struct ionic_admin_ctx ctx = {
1446                 .pending_work = true,
1447                 .cmd.q_init = {
1448                         .opcode = IONIC_CMD_Q_INIT,
1449                         .type = q->type,
1450                         .ver = lif->qtype_info[q->type].version,
1451                         .index = rte_cpu_to_le_32(q->index),
1452                         .flags = rte_cpu_to_le_16(IONIC_QINIT_F_SG |
1453                                                 IONIC_QINIT_F_ENA),
1454                         .intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE),
1455                         .ring_size = rte_log2_u32(q->num_descs),
1456                         .ring_base = rte_cpu_to_le_64(q->base_pa),
1457                         .cq_ring_base = rte_cpu_to_le_64(cq->base_pa),
1458                         .sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa),
1459                 },
1460         };
1461         int err;
1462
1463         IONIC_PRINT(DEBUG, "txq_init.index %d", q->index);
1464         IONIC_PRINT(DEBUG, "txq_init.ring_base 0x%" PRIx64 "", q->base_pa);
1465         IONIC_PRINT(DEBUG, "txq_init.ring_size %d",
1466                 ctx.cmd.q_init.ring_size);
1467         IONIC_PRINT(DEBUG, "txq_init.ver %u", ctx.cmd.q_init.ver);
1468
1469         err = ionic_adminq_post_wait(qcq->lif, &ctx);
1470         if (err)
1471                 return err;
1472
1473         q->hw_type = ctx.comp.q_init.hw_type;
1474         q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index);
1475         q->db = ionic_db_map(lif, q);
1476
1477         IONIC_PRINT(DEBUG, "txq->hw_type %d", q->hw_type);
1478         IONIC_PRINT(DEBUG, "txq->hw_index %d", q->hw_index);
1479         IONIC_PRINT(DEBUG, "txq->db %p", q->db);
1480
1481         qcq->flags |= IONIC_QCQ_F_INITED;
1482
1483         return 0;
1484 }
1485
1486 int
1487 ionic_lif_rxq_init(struct ionic_qcq *qcq)
1488 {
1489         struct ionic_queue *q = &qcq->q;
1490         struct ionic_lif *lif = qcq->lif;
1491         struct ionic_cq *cq = &qcq->cq;
1492         struct ionic_admin_ctx ctx = {
1493                 .pending_work = true,
1494                 .cmd.q_init = {
1495                         .opcode = IONIC_CMD_Q_INIT,
1496                         .type = q->type,
1497                         .ver = lif->qtype_info[q->type].version,
1498                         .index = rte_cpu_to_le_32(q->index),
1499                         .flags = rte_cpu_to_le_16(IONIC_QINIT_F_SG |
1500                                                 IONIC_QINIT_F_ENA),
1501                         .intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE),
1502                         .ring_size = rte_log2_u32(q->num_descs),
1503                         .ring_base = rte_cpu_to_le_64(q->base_pa),
1504                         .cq_ring_base = rte_cpu_to_le_64(cq->base_pa),
1505                         .sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa),
1506                 },
1507         };
1508         int err;
1509
1510         IONIC_PRINT(DEBUG, "rxq_init.index %d", q->index);
1511         IONIC_PRINT(DEBUG, "rxq_init.ring_base 0x%" PRIx64 "", q->base_pa);
1512         IONIC_PRINT(DEBUG, "rxq_init.ring_size %d",
1513                 ctx.cmd.q_init.ring_size);
1514         IONIC_PRINT(DEBUG, "rxq_init.ver %u", ctx.cmd.q_init.ver);
1515
1516         err = ionic_adminq_post_wait(qcq->lif, &ctx);
1517         if (err)
1518                 return err;
1519
1520         q->hw_type = ctx.comp.q_init.hw_type;
1521         q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index);
1522         q->db = ionic_db_map(lif, q);
1523
1524         qcq->flags |= IONIC_QCQ_F_INITED;
1525
1526         IONIC_PRINT(DEBUG, "rxq->hw_type %d", q->hw_type);
1527         IONIC_PRINT(DEBUG, "rxq->hw_index %d", q->hw_index);
1528         IONIC_PRINT(DEBUG, "rxq->db %p", q->db);
1529
1530         return 0;
1531 }
1532
1533 static int
1534 ionic_station_set(struct ionic_lif *lif)
1535 {
1536         struct ionic_admin_ctx ctx = {
1537                 .pending_work = true,
1538                 .cmd.lif_getattr = {
1539                         .opcode = IONIC_CMD_LIF_GETATTR,
1540                         .attr = IONIC_LIF_ATTR_MAC,
1541                 },
1542         };
1543         int err;
1544
1545         IONIC_PRINT_CALL();
1546
1547         err = ionic_adminq_post_wait(lif, &ctx);
1548         if (err)
1549                 return err;
1550
1551         memcpy(lif->mac_addr, ctx.comp.lif_getattr.mac, RTE_ETHER_ADDR_LEN);
1552
1553         return 0;
1554 }
1555
1556 static void
1557 ionic_lif_set_name(struct ionic_lif *lif)
1558 {
1559         struct ionic_admin_ctx ctx = {
1560                 .pending_work = true,
1561                 .cmd.lif_setattr = {
1562                         .opcode = IONIC_CMD_LIF_SETATTR,
1563                         .attr = IONIC_LIF_ATTR_NAME,
1564                 },
1565         };
1566
1567         memcpy(ctx.cmd.lif_setattr.name, lif->name,
1568                 sizeof(ctx.cmd.lif_setattr.name) - 1);
1569
1570         ionic_adminq_post_wait(lif, &ctx);
1571 }
1572
1573 int
1574 ionic_lif_init(struct ionic_lif *lif)
1575 {
1576         struct ionic_dev *idev = &lif->adapter->idev;
1577         struct ionic_q_init_comp comp;
1578         int err;
1579
1580         memset(&lif->stats_base, 0, sizeof(lif->stats_base));
1581
1582         ionic_dev_cmd_lif_init(idev, lif->info_pa);
1583         err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1584         ionic_dev_cmd_comp(idev, &comp);
1585         if (err)
1586                 return err;
1587
1588         lif->hw_index = rte_cpu_to_le_16(comp.hw_index);
1589
1590         err = ionic_lif_adminq_init(lif);
1591         if (err)
1592                 return err;
1593
1594         err = ionic_lif_notifyq_init(lif);
1595         if (err)
1596                 goto err_out_adminq_deinit;
1597
1598         /*
1599          * Configure initial feature set
1600          * This will be updated later by the dev_configure() step
1601          */
1602         lif->features = IONIC_ETH_HW_RX_HASH | IONIC_ETH_HW_VLAN_RX_FILTER;
1603
1604         err = ionic_lif_set_features(lif);
1605         if (err)
1606                 goto err_out_notifyq_deinit;
1607
1608         err = ionic_rx_filters_init(lif);
1609         if (err)
1610                 goto err_out_notifyq_deinit;
1611
1612         err = ionic_station_set(lif);
1613         if (err)
1614                 goto err_out_rx_filter_deinit;
1615
1616         ionic_lif_set_name(lif);
1617
1618         lif->state |= IONIC_LIF_F_INITED;
1619
1620         return 0;
1621
1622 err_out_rx_filter_deinit:
1623         ionic_rx_filters_deinit(lif);
1624
1625 err_out_notifyq_deinit:
1626         ionic_lif_notifyq_deinit(lif);
1627
1628 err_out_adminq_deinit:
1629         ionic_lif_qcq_deinit(lif->adminqcq);
1630
1631         return err;
1632 }
1633
1634 void
1635 ionic_lif_deinit(struct ionic_lif *lif)
1636 {
1637         if (!(lif->state & IONIC_LIF_F_INITED))
1638                 return;
1639
1640         ionic_rx_filters_deinit(lif);
1641         ionic_lif_rss_teardown(lif);
1642         ionic_lif_notifyq_deinit(lif);
1643         ionic_lif_qcq_deinit(lif->adminqcq);
1644
1645         lif->state &= ~IONIC_LIF_F_INITED;
1646 }
1647
1648 void
1649 ionic_lif_configure_vlan_offload(struct ionic_lif *lif, int mask)
1650 {
1651         struct rte_eth_dev *eth_dev = lif->eth_dev;
1652         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1653
1654         /*
1655          * IONIC_ETH_HW_VLAN_RX_FILTER cannot be turned off, so
1656          * set DEV_RX_OFFLOAD_VLAN_FILTER and ignore ETH_VLAN_FILTER_MASK
1657          */
1658         rxmode->offloads |= DEV_RX_OFFLOAD_VLAN_FILTER;
1659
1660         if (mask & ETH_VLAN_STRIP_MASK) {
1661                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1662                         lif->features |= IONIC_ETH_HW_VLAN_RX_STRIP;
1663                 else
1664                         lif->features &= ~IONIC_ETH_HW_VLAN_RX_STRIP;
1665         }
1666 }
1667
1668 void
1669 ionic_lif_configure(struct ionic_lif *lif)
1670 {
1671         struct rte_eth_rxmode *rxmode = &lif->eth_dev->data->dev_conf.rxmode;
1672         struct rte_eth_txmode *txmode = &lif->eth_dev->data->dev_conf.txmode;
1673         struct ionic_identity *ident = &lif->adapter->ident;
1674         union ionic_lif_config *cfg = &ident->lif.eth.config;
1675         uint32_t ntxqs_per_lif =
1676                 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]);
1677         uint32_t nrxqs_per_lif =
1678                 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]);
1679         uint32_t nrxqs = lif->eth_dev->data->nb_rx_queues;
1680         uint32_t ntxqs = lif->eth_dev->data->nb_tx_queues;
1681
1682         lif->port_id = lif->eth_dev->data->port_id;
1683
1684         IONIC_PRINT(DEBUG, "Configuring LIF on port %u",
1685                 lif->port_id);
1686
1687         if (nrxqs > 0)
1688                 nrxqs_per_lif = RTE_MIN(nrxqs_per_lif, nrxqs);
1689
1690         if (ntxqs > 0)
1691                 ntxqs_per_lif = RTE_MIN(ntxqs_per_lif, ntxqs);
1692
1693         lif->nrxqcqs = nrxqs_per_lif;
1694         lif->ntxqcqs = ntxqs_per_lif;
1695
1696         /* Update the LIF configuration based on the eth_dev */
1697
1698         /*
1699          * NB: While it is true that RSS_HASH is always enabled on ionic,
1700          *     setting this flag unconditionally causes problems in DTS.
1701          * rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1702          */
1703
1704         /* RX per-port */
1705
1706         if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM ||
1707             rxmode->offloads & DEV_RX_OFFLOAD_UDP_CKSUM ||
1708             rxmode->offloads & DEV_RX_OFFLOAD_TCP_CKSUM)
1709                 lif->features |= IONIC_ETH_HW_RX_CSUM;
1710         else
1711                 lif->features &= ~IONIC_ETH_HW_RX_CSUM;
1712
1713         if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER) {
1714                 lif->features |= IONIC_ETH_HW_RX_SG;
1715                 lif->eth_dev->data->scattered_rx = 1;
1716         } else {
1717                 lif->features &= ~IONIC_ETH_HW_RX_SG;
1718                 lif->eth_dev->data->scattered_rx = 0;
1719         }
1720
1721         /* Covers VLAN_STRIP */
1722         ionic_lif_configure_vlan_offload(lif, ETH_VLAN_STRIP_MASK);
1723
1724         /* TX per-port */
1725
1726         if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
1727             txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
1728             txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM ||
1729             txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
1730             txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)
1731                 lif->features |= IONIC_ETH_HW_TX_CSUM;
1732         else
1733                 lif->features &= ~IONIC_ETH_HW_TX_CSUM;
1734
1735         if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
1736                 lif->features |= IONIC_ETH_HW_VLAN_TX_TAG;
1737         else
1738                 lif->features &= ~IONIC_ETH_HW_VLAN_TX_TAG;
1739
1740         if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
1741                 lif->features |= IONIC_ETH_HW_TX_SG;
1742         else
1743                 lif->features &= ~IONIC_ETH_HW_TX_SG;
1744
1745         if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
1746                 lif->features |= IONIC_ETH_HW_TSO;
1747                 lif->features |= IONIC_ETH_HW_TSO_IPV6;
1748                 lif->features |= IONIC_ETH_HW_TSO_ECN;
1749         } else {
1750                 lif->features &= ~IONIC_ETH_HW_TSO;
1751                 lif->features &= ~IONIC_ETH_HW_TSO_IPV6;
1752                 lif->features &= ~IONIC_ETH_HW_TSO_ECN;
1753         }
1754 }
1755
1756 int
1757 ionic_lif_start(struct ionic_lif *lif)
1758 {
1759         uint32_t rx_mode;
1760         uint32_t i;
1761         int err;
1762
1763         err = ionic_lif_rss_setup(lif);
1764         if (err)
1765                 return err;
1766
1767         if (!lif->rx_mode) {
1768                 IONIC_PRINT(DEBUG, "Setting RX mode on %s",
1769                         lif->name);
1770
1771                 rx_mode  = IONIC_RX_MODE_F_UNICAST;
1772                 rx_mode |= IONIC_RX_MODE_F_MULTICAST;
1773                 rx_mode |= IONIC_RX_MODE_F_BROADCAST;
1774
1775                 ionic_set_rx_mode(lif, rx_mode);
1776         }
1777
1778         IONIC_PRINT(DEBUG, "Starting %u RX queues and %u TX queues "
1779                 "on port %u",
1780                 lif->nrxqcqs, lif->ntxqcqs, lif->port_id);
1781
1782         for (i = 0; i < lif->nrxqcqs; i++) {
1783                 struct ionic_qcq *rxq = lif->rxqcqs[i];
1784                 if (!(rxq->flags & IONIC_QCQ_F_DEFERRED)) {
1785                         err = ionic_dev_rx_queue_start(lif->eth_dev, i);
1786
1787                         if (err)
1788                                 return err;
1789                 }
1790         }
1791
1792         for (i = 0; i < lif->ntxqcqs; i++) {
1793                 struct ionic_qcq *txq = lif->txqcqs[i];
1794                 if (!(txq->flags & IONIC_QCQ_F_DEFERRED)) {
1795                         err = ionic_dev_tx_queue_start(lif->eth_dev, i);
1796
1797                         if (err)
1798                                 return err;
1799                 }
1800         }
1801
1802         /* Carrier ON here */
1803         lif->state |= IONIC_LIF_F_UP;
1804
1805         ionic_link_status_check(lif);
1806
1807         return 0;
1808 }
1809
1810 int
1811 ionic_lif_identify(struct ionic_adapter *adapter)
1812 {
1813         struct ionic_dev *idev = &adapter->idev;
1814         struct ionic_identity *ident = &adapter->ident;
1815         union ionic_lif_config *cfg = &ident->lif.eth.config;
1816         uint32_t lif_words = RTE_DIM(ident->lif.words);
1817         uint32_t cmd_words = RTE_DIM(idev->dev_cmd->data);
1818         uint32_t i, nwords;
1819         int err;
1820
1821         ionic_dev_cmd_lif_identify(idev, IONIC_LIF_TYPE_CLASSIC,
1822                 IONIC_IDENTITY_VERSION_1);
1823         err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1824         if (err)
1825                 return (err);
1826
1827         nwords = RTE_MIN(lif_words, cmd_words);
1828         for (i = 0; i < nwords; i++)
1829                 ident->lif.words[i] = ioread32(&idev->dev_cmd->data[i]);
1830
1831         IONIC_PRINT(INFO, "capabilities 0x%" PRIx64 " ",
1832                 rte_le_to_cpu_64(ident->lif.capabilities));
1833
1834         IONIC_PRINT(INFO, "eth.max_ucast_filters 0x%" PRIx32 " ",
1835                 rte_le_to_cpu_32(ident->lif.eth.max_ucast_filters));
1836         IONIC_PRINT(INFO, "eth.max_mcast_filters 0x%" PRIx32 " ",
1837                 rte_le_to_cpu_32(ident->lif.eth.max_mcast_filters));
1838
1839         IONIC_PRINT(INFO, "eth.features 0x%" PRIx64 " ",
1840                 rte_le_to_cpu_64(cfg->features));
1841         IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_ADMINQ] 0x%" PRIx32 " ",
1842                 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_ADMINQ]));
1843         IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] 0x%" PRIx32 " ",
1844                 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_NOTIFYQ]));
1845         IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_RXQ] 0x%" PRIx32 " ",
1846                 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]));
1847         IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_TXQ] 0x%" PRIx32 " ",
1848                 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]));
1849
1850         return 0;
1851 }
1852
1853 int
1854 ionic_lifs_size(struct ionic_adapter *adapter)
1855 {
1856         struct ionic_identity *ident = &adapter->ident;
1857         union ionic_lif_config *cfg = &ident->lif.eth.config;
1858         uint32_t nintrs, dev_nintrs = rte_le_to_cpu_32(ident->dev.nintrs);
1859
1860         adapter->max_ntxqs_per_lif =
1861                 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]);
1862         adapter->max_nrxqs_per_lif =
1863                 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]);
1864
1865         nintrs = 1 /* notifyq */;
1866
1867         if (nintrs > dev_nintrs) {
1868                 IONIC_PRINT(ERR,
1869                         "At most %d intr supported, minimum req'd is %u",
1870                         dev_nintrs, nintrs);
1871                 return -ENOSPC;
1872         }
1873
1874         adapter->nintrs = nintrs;
1875
1876         return 0;
1877 }