1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
5 #include <rte_malloc.h>
6 #include <rte_ethdev_driver.h>
9 #include "ionic_logs.h"
10 #include "ionic_lif.h"
11 #include "ionic_ethdev.h"
12 #include "ionic_rx_filter.h"
13 #include "ionic_rxtx.h"
15 static int ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr);
16 static int ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr);
19 ionic_qcq_enable(struct ionic_qcq *qcq)
21 struct ionic_queue *q = &qcq->q;
22 struct ionic_lif *lif = q->lif;
23 struct ionic_dev *idev = &lif->adapter->idev;
24 struct ionic_admin_ctx ctx = {
27 .opcode = IONIC_CMD_Q_CONTROL,
28 .lif_index = lif->index,
31 .oper = IONIC_Q_ENABLE,
35 if (qcq->flags & IONIC_QCQ_F_INTR) {
36 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
37 IONIC_INTR_MASK_CLEAR);
40 return ionic_adminq_post_wait(lif, &ctx);
44 ionic_qcq_disable(struct ionic_qcq *qcq)
46 struct ionic_queue *q = &qcq->q;
47 struct ionic_lif *lif = q->lif;
48 struct ionic_dev *idev = &lif->adapter->idev;
49 struct ionic_admin_ctx ctx = {
52 .opcode = IONIC_CMD_Q_CONTROL,
53 .lif_index = lif->index,
56 .oper = IONIC_Q_DISABLE,
60 if (qcq->flags & IONIC_QCQ_F_INTR) {
61 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
65 return ionic_adminq_post_wait(lif, &ctx);
69 ionic_lif_stop(struct ionic_lif *lif __rte_unused)
71 /* Carrier OFF here */
77 ionic_lif_reset(struct ionic_lif *lif)
79 struct ionic_dev *idev = &lif->adapter->idev;
84 ionic_dev_cmd_lif_reset(idev, lif->index);
85 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
87 IONIC_PRINT(WARNING, "Failed to reset %s", lif->name);
91 ionic_lif_get_abs_stats(const struct ionic_lif *lif, struct rte_eth_stats *stats)
93 struct ionic_lif_stats *ls = &lif->info->stats;
95 uint32_t num_rx_q_counters = RTE_MIN(lif->nrxqcqs, (uint32_t)
96 RTE_ETHDEV_QUEUE_STAT_CNTRS);
97 uint32_t num_tx_q_counters = RTE_MIN(lif->ntxqcqs, (uint32_t)
98 RTE_ETHDEV_QUEUE_STAT_CNTRS);
100 memset(stats, 0, sizeof(*stats));
103 IONIC_PRINT(DEBUG, "Stats on port %u not yet initialized",
110 stats->ipackets = ls->rx_ucast_packets +
111 ls->rx_mcast_packets +
112 ls->rx_bcast_packets;
114 stats->ibytes = ls->rx_ucast_bytes +
118 for (i = 0; i < lif->nrxqcqs; i++) {
119 struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats.rx;
121 rx_stats->no_cb_arg +
122 rx_stats->bad_cq_status +
128 ls->rx_ucast_drop_packets +
129 ls->rx_mcast_drop_packets +
130 ls->rx_bcast_drop_packets;
135 ls->rx_queue_disabled +
136 ls->rx_desc_fetch_error +
137 ls->rx_desc_data_error;
139 for (i = 0; i < num_rx_q_counters; i++) {
140 struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats.rx;
141 stats->q_ipackets[i] = rx_stats->packets;
142 stats->q_ibytes[i] = rx_stats->bytes;
144 rx_stats->no_cb_arg +
145 rx_stats->bad_cq_status +
152 stats->opackets = ls->tx_ucast_packets +
153 ls->tx_mcast_packets +
154 ls->tx_bcast_packets;
156 stats->obytes = ls->tx_ucast_bytes +
160 for (i = 0; i < lif->ntxqcqs; i++) {
161 struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats.tx;
162 stats->oerrors += tx_stats->drop;
166 ls->tx_ucast_drop_packets +
167 ls->tx_mcast_drop_packets +
168 ls->tx_bcast_drop_packets;
172 ls->tx_queue_disabled +
173 ls->tx_desc_fetch_error +
174 ls->tx_desc_data_error;
176 for (i = 0; i < num_tx_q_counters; i++) {
177 struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats.tx;
178 stats->q_opackets[i] = tx_stats->packets;
179 stats->q_obytes[i] = tx_stats->bytes;
184 ionic_lif_get_stats(const struct ionic_lif *lif,
185 struct rte_eth_stats *stats)
187 ionic_lif_get_abs_stats(lif, stats);
189 stats->ipackets -= lif->stats_base.ipackets;
190 stats->opackets -= lif->stats_base.opackets;
191 stats->ibytes -= lif->stats_base.ibytes;
192 stats->obytes -= lif->stats_base.obytes;
193 stats->imissed -= lif->stats_base.imissed;
194 stats->ierrors -= lif->stats_base.ierrors;
195 stats->oerrors -= lif->stats_base.oerrors;
196 stats->rx_nombuf -= lif->stats_base.rx_nombuf;
200 ionic_lif_reset_stats(struct ionic_lif *lif)
204 for (i = 0; i < lif->nrxqcqs; i++) {
205 memset(&lif->rxqcqs[i]->stats.rx, 0,
206 sizeof(struct ionic_rx_stats));
207 memset(&lif->txqcqs[i]->stats.tx, 0,
208 sizeof(struct ionic_tx_stats));
211 ionic_lif_get_abs_stats(lif, &lif->stats_base);
215 ionic_lif_get_hw_stats(struct ionic_lif *lif, struct ionic_lif_stats *stats)
217 uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t);
218 uint64_t *stats64 = (uint64_t *)stats;
219 uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats;
220 uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base;
222 for (i = 0; i < count; i++)
223 stats64[i] = lif_stats64[i] - lif_stats64_base[i];
227 ionic_lif_reset_hw_stats(struct ionic_lif *lif)
229 uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t);
230 uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats;
231 uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base;
233 for (i = 0; i < count; i++)
234 lif_stats64_base[i] = lif_stats64[i];
238 ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr)
240 struct ionic_admin_ctx ctx = {
241 .pending_work = true,
242 .cmd.rx_filter_add = {
243 .opcode = IONIC_CMD_RX_FILTER_ADD,
244 .match = IONIC_RX_FILTER_MATCH_MAC,
249 memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, RTE_ETHER_ADDR_LEN);
251 err = ionic_adminq_post_wait(lif, &ctx);
255 IONIC_PRINT(INFO, "rx_filter add (id %d)",
256 ctx.comp.rx_filter_add.filter_id);
258 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);
262 ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr)
264 struct ionic_admin_ctx ctx = {
265 .pending_work = true,
266 .cmd.rx_filter_del = {
267 .opcode = IONIC_CMD_RX_FILTER_DEL,
270 struct ionic_rx_filter *f;
275 rte_spinlock_lock(&lif->rx_filters.lock);
277 f = ionic_rx_filter_by_addr(lif, addr);
279 rte_spinlock_unlock(&lif->rx_filters.lock);
283 ctx.cmd.rx_filter_del.filter_id = f->filter_id;
284 ionic_rx_filter_free(f);
286 rte_spinlock_unlock(&lif->rx_filters.lock);
288 err = ionic_adminq_post_wait(lif, &ctx);
292 IONIC_PRINT(INFO, "rx_filter del (id %d)",
293 ctx.cmd.rx_filter_del.filter_id);
299 ionic_dev_add_mac(struct rte_eth_dev *eth_dev,
300 struct rte_ether_addr *mac_addr,
301 uint32_t index __rte_unused, uint32_t pool __rte_unused)
303 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
307 return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr);
311 ionic_dev_remove_mac(struct rte_eth_dev *eth_dev, uint32_t index)
313 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
314 struct ionic_adapter *adapter = lif->adapter;
315 struct rte_ether_addr *mac_addr;
319 if (index >= adapter->max_mac_addrs) {
321 "Index %u is above MAC filter limit %u",
322 index, adapter->max_mac_addrs);
326 mac_addr = ð_dev->data->mac_addrs[index];
328 if (!rte_is_valid_assigned_ether_addr(mac_addr))
331 ionic_lif_addr_del(lif, (const uint8_t *)mac_addr);
335 ionic_dev_set_mac(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr)
337 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
341 if (mac_addr == NULL) {
342 IONIC_PRINT(NOTICE, "New mac is null");
346 if (!rte_is_zero_ether_addr((struct rte_ether_addr *)lif->mac_addr)) {
347 IONIC_PRINT(INFO, "Deleting mac addr %pM",
349 ionic_lif_addr_del(lif, lif->mac_addr);
350 memset(lif->mac_addr, 0, RTE_ETHER_ADDR_LEN);
353 IONIC_PRINT(INFO, "Updating mac addr");
355 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)lif->mac_addr);
357 return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr);
361 ionic_vlan_rx_add_vid(struct ionic_lif *lif, uint16_t vid)
363 struct ionic_admin_ctx ctx = {
364 .pending_work = true,
365 .cmd.rx_filter_add = {
366 .opcode = IONIC_CMD_RX_FILTER_ADD,
367 .match = IONIC_RX_FILTER_MATCH_VLAN,
373 err = ionic_adminq_post_wait(lif, &ctx);
377 IONIC_PRINT(INFO, "rx_filter add VLAN %d (id %d)", vid,
378 ctx.comp.rx_filter_add.filter_id);
380 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);
384 ionic_vlan_rx_kill_vid(struct ionic_lif *lif, uint16_t vid)
386 struct ionic_admin_ctx ctx = {
387 .pending_work = true,
388 .cmd.rx_filter_del = {
389 .opcode = IONIC_CMD_RX_FILTER_DEL,
392 struct ionic_rx_filter *f;
397 rte_spinlock_lock(&lif->rx_filters.lock);
399 f = ionic_rx_filter_by_vlan(lif, vid);
401 rte_spinlock_unlock(&lif->rx_filters.lock);
405 ctx.cmd.rx_filter_del.filter_id = f->filter_id;
406 ionic_rx_filter_free(f);
407 rte_spinlock_unlock(&lif->rx_filters.lock);
409 err = ionic_adminq_post_wait(lif, &ctx);
413 IONIC_PRINT(INFO, "rx_filter del VLAN %d (id %d)", vid,
414 ctx.cmd.rx_filter_del.filter_id);
420 ionic_dev_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id,
423 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
427 err = ionic_vlan_rx_add_vid(lif, vlan_id);
429 err = ionic_vlan_rx_kill_vid(lif, vlan_id);
435 ionic_lif_rx_mode(struct ionic_lif *lif, uint32_t rx_mode)
437 struct ionic_admin_ctx ctx = {
438 .pending_work = true,
440 .opcode = IONIC_CMD_RX_MODE_SET,
441 .lif_index = lif->index,
447 if (rx_mode & IONIC_RX_MODE_F_UNICAST)
448 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_UNICAST");
449 if (rx_mode & IONIC_RX_MODE_F_MULTICAST)
450 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_MULTICAST");
451 if (rx_mode & IONIC_RX_MODE_F_BROADCAST)
452 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_BROADCAST");
453 if (rx_mode & IONIC_RX_MODE_F_PROMISC)
454 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_PROMISC");
455 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI)
456 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_ALLMULTI");
458 err = ionic_adminq_post_wait(lif, &ctx);
460 IONIC_PRINT(ERR, "Failure setting RX mode");
464 ionic_set_rx_mode(struct ionic_lif *lif, uint32_t rx_mode)
466 if (lif->rx_mode != rx_mode) {
467 lif->rx_mode = rx_mode;
468 ionic_lif_rx_mode(lif, rx_mode);
473 ionic_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
475 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
476 uint32_t rx_mode = lif->rx_mode;
480 rx_mode |= IONIC_RX_MODE_F_PROMISC;
482 ionic_set_rx_mode(lif, rx_mode);
488 ionic_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
490 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
491 uint32_t rx_mode = lif->rx_mode;
493 rx_mode &= ~IONIC_RX_MODE_F_PROMISC;
495 ionic_set_rx_mode(lif, rx_mode);
501 ionic_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
503 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
504 uint32_t rx_mode = lif->rx_mode;
506 rx_mode |= IONIC_RX_MODE_F_ALLMULTI;
508 ionic_set_rx_mode(lif, rx_mode);
514 ionic_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
516 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
517 uint32_t rx_mode = lif->rx_mode;
519 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI;
521 ionic_set_rx_mode(lif, rx_mode);
527 ionic_lif_change_mtu(struct ionic_lif *lif, int new_mtu)
529 struct ionic_admin_ctx ctx = {
530 .pending_work = true,
532 .opcode = IONIC_CMD_LIF_SETATTR,
534 .attr = IONIC_LIF_ATTR_MTU,
540 err = ionic_adminq_post_wait(lif, &ctx);
548 ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr)
550 struct ionic_adapter *adapter = lif->adapter;
551 struct ionic_dev *idev = &adapter->idev;
555 * Note: interrupt handler is called for index = 0 only
556 * (we use interrupts for the notifyq only anyway,
557 * which has index = 0)
560 for (index = 0; index < adapter->nintrs; index++)
561 if (!adapter->intrs[index])
564 if (index == adapter->nintrs)
567 adapter->intrs[index] = true;
569 ionic_intr_init(idev, intr, index);
575 ionic_intr_free(struct ionic_lif *lif, struct ionic_intr_info *intr)
577 if (intr->index != IONIC_INTR_INDEX_NOT_ASSIGNED)
578 lif->adapter->intrs[intr->index] = false;
582 ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type,
584 const char *base, uint32_t flags,
587 uint32_t cq_desc_size,
588 uint32_t sg_desc_size,
589 struct ionic_qcq **qcq)
591 struct ionic_dev *idev = &lif->adapter->idev;
592 struct ionic_qcq *new;
593 uint32_t q_size, cq_size, sg_size, total_size;
594 void *q_base, *cq_base, *sg_base;
595 rte_iova_t q_base_pa = 0;
596 rte_iova_t cq_base_pa = 0;
597 rte_iova_t sg_base_pa = 0;
598 uint32_t socket_id = rte_socket_id();
603 q_size = num_descs * desc_size;
604 cq_size = num_descs * cq_desc_size;
605 sg_size = num_descs * sg_desc_size;
607 total_size = RTE_ALIGN(q_size, PAGE_SIZE) +
608 RTE_ALIGN(cq_size, PAGE_SIZE);
610 * Note: aligning q_size/cq_size is not enough due to cq_base address
611 * aligning as q_base could be not aligned to the page.
614 total_size += PAGE_SIZE;
616 if (flags & IONIC_QCQ_F_SG) {
617 total_size += RTE_ALIGN(sg_size, PAGE_SIZE);
618 total_size += PAGE_SIZE;
621 new = rte_zmalloc("ionic", sizeof(*new), 0);
623 IONIC_PRINT(ERR, "Cannot allocate queue structure");
630 new->q.info = rte_zmalloc("ionic", sizeof(*new->q.info) * num_descs, 0);
632 IONIC_PRINT(ERR, "Cannot allocate queue info");
638 err = ionic_q_init(lif, idev, &new->q, index, num_descs,
639 desc_size, sg_desc_size);
641 IONIC_PRINT(ERR, "Queue initialization failed");
645 if (flags & IONIC_QCQ_F_INTR) {
646 err = ionic_intr_alloc(lif, &new->intr);
650 ionic_intr_mask_assert(idev->intr_ctrl, new->intr.index,
651 IONIC_INTR_MASK_SET);
653 new->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED;
656 err = ionic_cq_init(lif, &new->cq, &new->intr,
657 num_descs, cq_desc_size);
659 IONIC_PRINT(ERR, "Completion queue initialization failed");
660 goto err_out_free_intr;
663 new->base_z = rte_eth_dma_zone_reserve(lif->eth_dev,
664 base /* name */, index /* queue_idx */,
665 total_size, IONIC_ALIGN, socket_id);
668 IONIC_PRINT(ERR, "Cannot reserve queue DMA memory");
670 goto err_out_free_intr;
673 new->base = new->base_z->addr;
674 new->base_pa = new->base_z->iova;
675 new->total_size = total_size;
678 q_base_pa = new->base_pa;
680 cq_base = (void *)RTE_ALIGN((uintptr_t)q_base + q_size, PAGE_SIZE);
681 cq_base_pa = RTE_ALIGN(q_base_pa + q_size, PAGE_SIZE);
683 if (flags & IONIC_QCQ_F_SG) {
684 sg_base = (void *)RTE_ALIGN((uintptr_t)cq_base + cq_size,
686 sg_base_pa = RTE_ALIGN(cq_base_pa + cq_size, PAGE_SIZE);
687 ionic_q_sg_map(&new->q, sg_base, sg_base_pa);
690 IONIC_PRINT(DEBUG, "Q-Base-PA = %#jx CQ-Base-PA = %#jx "
692 q_base_pa, cq_base_pa, sg_base_pa);
694 ionic_q_map(&new->q, q_base, q_base_pa);
695 ionic_cq_map(&new->cq, cq_base, cq_base_pa);
696 ionic_cq_bind(&new->cq, &new->q);
703 if (flags & IONIC_QCQ_F_INTR)
704 ionic_intr_free(lif, &new->intr);
710 ionic_qcq_free(struct ionic_qcq *qcq)
715 rte_memzone_free(qcq->base_z);
720 rte_free(qcq->q.info);
728 ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t nrxq_descs,
729 struct ionic_qcq **qcq)
734 flags = IONIC_QCQ_F_SG;
735 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, index, "rx", flags,
737 sizeof(struct ionic_rxq_desc),
738 sizeof(struct ionic_rxq_comp),
739 sizeof(struct ionic_rxq_sg_desc),
740 &lif->rxqcqs[index]);
744 *qcq = lif->rxqcqs[index];
750 ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t ntxq_descs,
751 struct ionic_qcq **qcq)
756 flags = IONIC_QCQ_F_SG;
757 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, index, "tx", flags,
759 sizeof(struct ionic_txq_desc),
760 sizeof(struct ionic_txq_comp),
761 sizeof(struct ionic_txq_sg_desc),
762 &lif->txqcqs[index]);
766 *qcq = lif->txqcqs[index];
772 ionic_admin_qcq_alloc(struct ionic_lif *lif)
778 err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags,
780 sizeof(struct ionic_admin_cmd),
781 sizeof(struct ionic_admin_comp),
791 ionic_notify_qcq_alloc(struct ionic_lif *lif)
796 flags = IONIC_QCQ_F_NOTIFYQ | IONIC_QCQ_F_INTR;
798 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notify",
800 IONIC_NOTIFYQ_LENGTH,
801 sizeof(struct ionic_notifyq_cmd),
802 sizeof(union ionic_notifyq_comp),
812 ionic_bus_map_dbpage(struct ionic_adapter *adapter, int page_num)
814 char *vaddr = adapter->bars[IONIC_PCI_BAR_DBELL].vaddr;
816 if (adapter->num_bars <= IONIC_PCI_BAR_DBELL)
819 return (void *)&vaddr[page_num << PAGE_SHIFT];
823 ionic_lif_alloc(struct ionic_lif *lif)
825 struct ionic_adapter *adapter = lif->adapter;
826 uint32_t socket_id = rte_socket_id();
831 * lif->name was zeroed on allocation.
832 * Copy (sizeof() - 1) bytes to ensure that it is NULL terminated.
834 memcpy(lif->name, lif->eth_dev->data->name, sizeof(lif->name) - 1);
836 IONIC_PRINT(DEBUG, "LIF: %s", lif->name);
838 IONIC_PRINT(DEBUG, "Allocating Lif Info");
840 rte_spinlock_init(&lif->adminq_lock);
841 rte_spinlock_init(&lif->adminq_service_lock);
843 dbpage_num = ionic_db_page_num(lif, 0);
845 lif->kern_dbpage = ionic_bus_map_dbpage(adapter, dbpage_num);
846 if (!lif->kern_dbpage) {
847 IONIC_PRINT(ERR, "Cannot map dbpage, aborting");
851 lif->txqcqs = rte_zmalloc("ionic", sizeof(*lif->txqcqs) *
852 adapter->max_ntxqs_per_lif, 0);
855 IONIC_PRINT(ERR, "Cannot allocate tx queues array");
859 lif->rxqcqs = rte_zmalloc("ionic", sizeof(*lif->rxqcqs) *
860 adapter->max_nrxqs_per_lif, 0);
863 IONIC_PRINT(ERR, "Cannot allocate rx queues array");
867 IONIC_PRINT(DEBUG, "Allocating Notify Queue");
869 err = ionic_notify_qcq_alloc(lif);
871 IONIC_PRINT(ERR, "Cannot allocate notify queue");
875 IONIC_PRINT(DEBUG, "Allocating Admin Queue");
877 err = ionic_admin_qcq_alloc(lif);
879 IONIC_PRINT(ERR, "Cannot allocate admin queue");
883 IONIC_PRINT(DEBUG, "Allocating Lif Info");
885 lif->info_sz = RTE_ALIGN(sizeof(*lif->info), PAGE_SIZE);
887 lif->info_z = rte_eth_dma_zone_reserve(lif->eth_dev,
888 "lif_info", 0 /* queue_idx*/,
889 lif->info_sz, IONIC_ALIGN, socket_id);
891 IONIC_PRINT(ERR, "Cannot allocate lif info memory");
895 lif->info = lif->info_z->addr;
896 lif->info_pa = lif->info_z->iova;
902 ionic_lif_free(struct ionic_lif *lif)
904 if (lif->notifyqcq) {
905 ionic_qcq_free(lif->notifyqcq);
906 lif->notifyqcq = NULL;
910 ionic_qcq_free(lif->adminqcq);
911 lif->adminqcq = NULL;
915 rte_free(lif->txqcqs);
920 rte_free(lif->rxqcqs);
925 rte_memzone_free(lif->info_z);
931 ionic_lif_rss_config(struct ionic_lif *lif,
932 const uint16_t types, const uint8_t *key, const uint32_t *indir)
934 struct ionic_admin_ctx ctx = {
935 .pending_work = true,
937 .opcode = IONIC_CMD_LIF_SETATTR,
938 .attr = IONIC_LIF_ATTR_RSS,
940 .rss.addr = lif->rss_ind_tbl_pa,
947 lif->rss_types = types;
950 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE);
953 for (i = 0; i < lif->adapter->ident.lif.eth.rss_ind_tbl_sz; i++)
954 lif->rss_ind_tbl[i] = indir[i];
956 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key,
957 IONIC_RSS_HASH_KEY_SIZE);
959 return ionic_adminq_post_wait(lif, &ctx);
963 ionic_lif_rss_setup(struct ionic_lif *lif)
965 size_t tbl_size = sizeof(*lif->rss_ind_tbl) *
966 lif->adapter->ident.lif.eth.rss_ind_tbl_sz;
967 static const uint8_t toeplitz_symmetric_key[] = {
968 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
969 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
970 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
971 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
972 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
974 uint32_t socket_id = rte_socket_id();
980 lif->rss_ind_tbl_z = rte_eth_dma_zone_reserve(lif->eth_dev,
982 0 /* queue_idx*/, tbl_size, IONIC_ALIGN, socket_id);
984 if (!lif->rss_ind_tbl_z) {
985 IONIC_PRINT(ERR, "OOM");
989 lif->rss_ind_tbl = lif->rss_ind_tbl_z->addr;
990 lif->rss_ind_tbl_pa = lif->rss_ind_tbl_z->iova;
992 /* Fill indirection table with 'default' values */
993 for (i = 0; i < lif->adapter->ident.lif.eth.rss_ind_tbl_sz; i++)
994 lif->rss_ind_tbl[i] = i % lif->nrxqcqs;
996 err = ionic_lif_rss_config(lif, IONIC_RSS_OFFLOAD_ALL,
997 toeplitz_symmetric_key, NULL);
1005 ionic_lif_rss_teardown(struct ionic_lif *lif)
1007 if (!lif->rss_ind_tbl)
1010 if (lif->rss_ind_tbl_z) {
1011 /* Disable RSS on the NIC */
1012 ionic_lif_rss_config(lif, 0x0, NULL, NULL);
1014 lif->rss_ind_tbl = NULL;
1015 lif->rss_ind_tbl_pa = 0;
1016 rte_memzone_free(lif->rss_ind_tbl_z);
1017 lif->rss_ind_tbl_z = NULL;
1022 ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq)
1024 struct ionic_dev *idev = &lif->adapter->idev;
1026 if (!(qcq->flags & IONIC_QCQ_F_INITED))
1029 if (qcq->flags & IONIC_QCQ_F_INTR)
1030 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1031 IONIC_INTR_MASK_SET);
1033 qcq->flags &= ~IONIC_QCQ_F_INITED;
1037 ionic_lif_txq_deinit(struct ionic_qcq *qcq)
1039 ionic_lif_qcq_deinit(qcq->lif, qcq);
1043 ionic_lif_rxq_deinit(struct ionic_qcq *qcq)
1045 ionic_lif_qcq_deinit(qcq->lif, qcq);
1049 ionic_adminq_service(struct ionic_cq *cq, uint32_t cq_desc_index,
1050 void *cb_arg __rte_unused)
1052 struct ionic_admin_comp *cq_desc_base = cq->base;
1053 struct ionic_admin_comp *cq_desc = &cq_desc_base[cq_desc_index];
1055 if (!color_match(cq_desc->color, cq->done_color))
1058 ionic_q_service(cq->bound_q, cq_desc_index, cq_desc->comp_index, NULL);
1063 /* This acts like ionic_napi */
1065 ionic_qcq_service(struct ionic_qcq *qcq, int budget, ionic_cq_cb cb,
1068 struct ionic_cq *cq = &qcq->cq;
1071 work_done = ionic_cq_service(cq, budget, cb, cb_arg);
1077 ionic_link_status_check(struct ionic_lif *lif)
1079 struct ionic_adapter *adapter = lif->adapter;
1082 lif->state &= ~IONIC_LIF_F_LINK_CHECK_NEEDED;
1087 link_up = (lif->info->status.link_status == IONIC_PORT_OPER_STATUS_UP);
1089 if ((link_up && adapter->link_up) ||
1090 (!link_up && !adapter->link_up))
1094 IONIC_PRINT(DEBUG, "Link up - %d Gbps",
1095 lif->info->status.link_speed);
1096 adapter->link_speed = lif->info->status.link_speed;
1098 IONIC_PRINT(DEBUG, "Link down");
1101 adapter->link_up = link_up;
1105 ionic_notifyq_cb(struct ionic_cq *cq, uint32_t cq_desc_index, void *cb_arg)
1107 union ionic_notifyq_comp *cq_desc_base = cq->base;
1108 union ionic_notifyq_comp *cq_desc = &cq_desc_base[cq_desc_index];
1109 struct ionic_lif *lif = cb_arg;
1111 IONIC_PRINT(DEBUG, "Notifyq callback eid = %jd ecode = %d",
1112 cq_desc->event.eid, cq_desc->event.ecode);
1114 /* Have we run out of new completions to process? */
1115 if (!(cq_desc->event.eid > lif->last_eid))
1118 lif->last_eid = cq_desc->event.eid;
1120 switch (cq_desc->event.ecode) {
1121 case IONIC_EVENT_LINK_CHANGE:
1123 "Notifyq IONIC_EVENT_LINK_CHANGE eid=%jd link_status=%d link_speed=%d",
1125 cq_desc->link_change.link_status,
1126 cq_desc->link_change.link_speed);
1128 lif->state |= IONIC_LIF_F_LINK_CHECK_NEEDED;
1132 IONIC_PRINT(WARNING, "Notifyq bad event ecode=%d eid=%jd",
1133 cq_desc->event.ecode, cq_desc->event.eid);
1141 ionic_notifyq_handler(struct ionic_lif *lif, int budget)
1143 struct ionic_dev *idev = &lif->adapter->idev;
1144 struct ionic_qcq *qcq = lif->notifyqcq;
1147 if (!(qcq->flags & IONIC_QCQ_F_INITED)) {
1148 IONIC_PRINT(DEBUG, "Notifyq not yet initialized");
1152 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1153 IONIC_INTR_MASK_SET);
1155 work_done = ionic_qcq_service(qcq, budget, ionic_notifyq_cb, lif);
1157 if (lif->state & IONIC_LIF_F_LINK_CHECK_NEEDED)
1158 ionic_link_status_check(lif);
1160 ionic_intr_credits(idev->intr_ctrl, qcq->intr.index,
1161 work_done, IONIC_INTR_CRED_RESET_COALESCE);
1163 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1164 IONIC_INTR_MASK_CLEAR);
1170 ionic_lif_adminq_init(struct ionic_lif *lif)
1172 struct ionic_dev *idev = &lif->adapter->idev;
1173 struct ionic_qcq *qcq = lif->adminqcq;
1174 struct ionic_queue *q = &qcq->q;
1175 struct ionic_q_init_comp comp;
1178 ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index);
1179 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1183 ionic_dev_cmd_comp(idev, &comp);
1185 q->hw_type = comp.hw_type;
1186 q->hw_index = comp.hw_index;
1187 q->db = ionic_db_map(lif, q);
1189 IONIC_PRINT(DEBUG, "adminq->hw_type %d", q->hw_type);
1190 IONIC_PRINT(DEBUG, "adminq->hw_index %d", q->hw_index);
1191 IONIC_PRINT(DEBUG, "adminq->db %p", q->db);
1193 if (qcq->flags & IONIC_QCQ_F_INTR)
1194 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1195 IONIC_INTR_MASK_CLEAR);
1197 qcq->flags |= IONIC_QCQ_F_INITED;
1203 ionic_lif_notifyq_init(struct ionic_lif *lif)
1205 struct ionic_dev *idev = &lif->adapter->idev;
1206 struct ionic_qcq *qcq = lif->notifyqcq;
1207 struct ionic_queue *q = &qcq->q;
1210 struct ionic_admin_ctx ctx = {
1211 .pending_work = true,
1213 .opcode = IONIC_CMD_Q_INIT,
1214 .lif_index = lif->index,
1217 .flags = (IONIC_QINIT_F_IRQ | IONIC_QINIT_F_ENA),
1218 .intr_index = qcq->intr.index,
1219 .ring_size = rte_log2_u32(q->num_descs),
1220 .ring_base = q->base_pa,
1224 IONIC_PRINT(DEBUG, "notifyq_init.index %d",
1225 ctx.cmd.q_init.index);
1226 IONIC_PRINT(DEBUG, "notifyq_init.ring_base 0x%" PRIx64 "",
1227 ctx.cmd.q_init.ring_base);
1228 IONIC_PRINT(DEBUG, "notifyq_init.ring_size %d",
1229 ctx.cmd.q_init.ring_size);
1230 IONIC_PRINT(DEBUG, "notifyq_init.ver %u", ctx.cmd.q_init.ver);
1232 err = ionic_adminq_post_wait(lif, &ctx);
1236 q->hw_type = ctx.comp.q_init.hw_type;
1237 q->hw_index = ctx.comp.q_init.hw_index;
1240 IONIC_PRINT(DEBUG, "notifyq->hw_type %d", q->hw_type);
1241 IONIC_PRINT(DEBUG, "notifyq->hw_index %d", q->hw_index);
1242 IONIC_PRINT(DEBUG, "notifyq->db %p", q->db);
1244 if (qcq->flags & IONIC_QCQ_F_INTR)
1245 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1246 IONIC_INTR_MASK_CLEAR);
1248 qcq->flags |= IONIC_QCQ_F_INITED;
1254 ionic_lif_set_features(struct ionic_lif *lif)
1256 struct ionic_admin_ctx ctx = {
1257 .pending_work = true,
1258 .cmd.lif_setattr = {
1259 .opcode = IONIC_CMD_LIF_SETATTR,
1260 .index = lif->index,
1261 .attr = IONIC_LIF_ATTR_FEATURES,
1262 .features = lif->features,
1267 err = ionic_adminq_post_wait(lif, &ctx);
1271 lif->hw_features = (ctx.cmd.lif_setattr.features &
1272 ctx.comp.lif_setattr.features);
1274 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
1275 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_TX_TAG");
1276 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
1277 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_STRIP");
1278 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
1279 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_FILTER");
1280 if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
1281 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_HASH");
1282 if (lif->hw_features & IONIC_ETH_HW_TX_SG)
1283 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_SG");
1284 if (lif->hw_features & IONIC_ETH_HW_RX_SG)
1285 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_SG");
1286 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
1287 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_CSUM");
1288 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
1289 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_CSUM");
1290 if (lif->hw_features & IONIC_ETH_HW_TSO)
1291 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO");
1292 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
1293 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPV6");
1294 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
1295 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_ECN");
1296 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
1297 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE");
1298 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
1299 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE_CSUM");
1300 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
1301 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP4");
1302 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
1303 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP6");
1304 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
1305 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP");
1306 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
1307 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP_CSUM");
1313 ionic_lif_txq_init(struct ionic_qcq *qcq)
1315 struct ionic_queue *q = &qcq->q;
1316 struct ionic_lif *lif = qcq->lif;
1317 struct ionic_cq *cq = &qcq->cq;
1318 struct ionic_admin_ctx ctx = {
1319 .pending_work = true,
1321 .opcode = IONIC_CMD_Q_INIT,
1322 .lif_index = lif->index,
1325 .flags = IONIC_QINIT_F_SG,
1326 .intr_index = cq->bound_intr->index,
1327 .ring_size = rte_log2_u32(q->num_descs),
1328 .ring_base = q->base_pa,
1329 .cq_ring_base = cq->base_pa,
1330 .sg_ring_base = q->sg_base_pa,
1335 IONIC_PRINT(DEBUG, "txq_init.index %d", ctx.cmd.q_init.index);
1336 IONIC_PRINT(DEBUG, "txq_init.ring_base 0x%" PRIx64 "",
1337 ctx.cmd.q_init.ring_base);
1338 IONIC_PRINT(DEBUG, "txq_init.ring_size %d",
1339 ctx.cmd.q_init.ring_size);
1340 IONIC_PRINT(DEBUG, "txq_init.ver %u", ctx.cmd.q_init.ver);
1342 err = ionic_adminq_post_wait(qcq->lif, &ctx);
1346 q->hw_type = ctx.comp.q_init.hw_type;
1347 q->hw_index = ctx.comp.q_init.hw_index;
1348 q->db = ionic_db_map(lif, q);
1350 IONIC_PRINT(DEBUG, "txq->hw_type %d", q->hw_type);
1351 IONIC_PRINT(DEBUG, "txq->hw_index %d", q->hw_index);
1352 IONIC_PRINT(DEBUG, "txq->db %p", q->db);
1354 qcq->flags |= IONIC_QCQ_F_INITED;
1360 ionic_lif_rxq_init(struct ionic_qcq *qcq)
1362 struct ionic_queue *q = &qcq->q;
1363 struct ionic_lif *lif = qcq->lif;
1364 struct ionic_cq *cq = &qcq->cq;
1365 struct ionic_admin_ctx ctx = {
1366 .pending_work = true,
1368 .opcode = IONIC_CMD_Q_INIT,
1369 .lif_index = lif->index,
1372 .flags = IONIC_QINIT_F_SG,
1373 .intr_index = cq->bound_intr->index,
1374 .ring_size = rte_log2_u32(q->num_descs),
1375 .ring_base = q->base_pa,
1376 .cq_ring_base = cq->base_pa,
1377 .sg_ring_base = q->sg_base_pa,
1382 IONIC_PRINT(DEBUG, "rxq_init.index %d", ctx.cmd.q_init.index);
1383 IONIC_PRINT(DEBUG, "rxq_init.ring_base 0x%" PRIx64 "",
1384 ctx.cmd.q_init.ring_base);
1385 IONIC_PRINT(DEBUG, "rxq_init.ring_size %d",
1386 ctx.cmd.q_init.ring_size);
1387 IONIC_PRINT(DEBUG, "rxq_init.ver %u", ctx.cmd.q_init.ver);
1389 err = ionic_adminq_post_wait(qcq->lif, &ctx);
1393 q->hw_type = ctx.comp.q_init.hw_type;
1394 q->hw_index = ctx.comp.q_init.hw_index;
1395 q->db = ionic_db_map(lif, q);
1397 qcq->flags |= IONIC_QCQ_F_INITED;
1399 IONIC_PRINT(DEBUG, "rxq->hw_type %d", q->hw_type);
1400 IONIC_PRINT(DEBUG, "rxq->hw_index %d", q->hw_index);
1401 IONIC_PRINT(DEBUG, "rxq->db %p", q->db);
1407 ionic_station_set(struct ionic_lif *lif)
1409 struct ionic_admin_ctx ctx = {
1410 .pending_work = true,
1411 .cmd.lif_getattr = {
1412 .opcode = IONIC_CMD_LIF_GETATTR,
1413 .index = lif->index,
1414 .attr = IONIC_LIF_ATTR_MAC,
1421 err = ionic_adminq_post_wait(lif, &ctx);
1425 if (!rte_is_zero_ether_addr((struct rte_ether_addr *)
1427 IONIC_PRINT(INFO, "deleting station MAC addr");
1429 ionic_lif_addr_del(lif, lif->mac_addr);
1432 memcpy(lif->mac_addr, ctx.comp.lif_getattr.mac, RTE_ETHER_ADDR_LEN);
1434 if (rte_is_zero_ether_addr((struct rte_ether_addr *)lif->mac_addr)) {
1435 IONIC_PRINT(NOTICE, "empty MAC addr (VF?)");
1439 IONIC_PRINT(DEBUG, "adding station MAC addr");
1441 ionic_lif_addr_add(lif, lif->mac_addr);
1447 ionic_lif_set_name(struct ionic_lif *lif)
1449 struct ionic_admin_ctx ctx = {
1450 .pending_work = true,
1451 .cmd.lif_setattr = {
1452 .opcode = IONIC_CMD_LIF_SETATTR,
1453 .index = lif->index,
1454 .attr = IONIC_LIF_ATTR_NAME,
1458 memcpy(ctx.cmd.lif_setattr.name, lif->name,
1459 sizeof(ctx.cmd.lif_setattr.name) - 1);
1461 ionic_adminq_post_wait(lif, &ctx);
1465 ionic_lif_init(struct ionic_lif *lif)
1467 struct ionic_dev *idev = &lif->adapter->idev;
1468 struct ionic_q_init_comp comp;
1471 memset(&lif->stats_base, 0, sizeof(lif->stats_base));
1473 ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa);
1474 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1475 ionic_dev_cmd_comp(idev, &comp);
1479 lif->hw_index = comp.hw_index;
1481 err = ionic_lif_adminq_init(lif);
1485 err = ionic_lif_notifyq_init(lif);
1487 goto err_out_adminq_deinit;
1490 IONIC_ETH_HW_VLAN_TX_TAG
1491 | IONIC_ETH_HW_VLAN_RX_STRIP
1492 | IONIC_ETH_HW_VLAN_RX_FILTER
1493 | IONIC_ETH_HW_RX_HASH
1494 | IONIC_ETH_HW_TX_SG
1495 | IONIC_ETH_HW_RX_SG
1496 | IONIC_ETH_HW_TX_CSUM
1497 | IONIC_ETH_HW_RX_CSUM
1499 | IONIC_ETH_HW_TSO_IPV6
1500 | IONIC_ETH_HW_TSO_ECN;
1502 err = ionic_lif_set_features(lif);
1504 goto err_out_notifyq_deinit;
1506 err = ionic_rx_filters_init(lif);
1508 goto err_out_notifyq_deinit;
1510 err = ionic_station_set(lif);
1512 goto err_out_rx_filter_deinit;
1514 ionic_lif_set_name(lif);
1516 lif->state |= IONIC_LIF_F_INITED;
1520 err_out_rx_filter_deinit:
1521 ionic_rx_filters_deinit(lif);
1523 err_out_notifyq_deinit:
1524 ionic_lif_qcq_deinit(lif, lif->notifyqcq);
1526 err_out_adminq_deinit:
1527 ionic_lif_qcq_deinit(lif, lif->adminqcq);
1533 ionic_lif_deinit(struct ionic_lif *lif)
1535 if (!(lif->state & IONIC_LIF_F_INITED))
1538 ionic_rx_filters_deinit(lif);
1539 ionic_lif_rss_teardown(lif);
1540 ionic_lif_qcq_deinit(lif, lif->notifyqcq);
1541 ionic_lif_qcq_deinit(lif, lif->adminqcq);
1543 lif->state &= ~IONIC_LIF_F_INITED;
1547 ionic_lif_configure(struct ionic_lif *lif)
1549 struct ionic_identity *ident = &lif->adapter->ident;
1550 uint32_t ntxqs_per_lif =
1551 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ];
1552 uint32_t nrxqs_per_lif =
1553 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ];
1554 uint32_t nrxqs = lif->eth_dev->data->nb_rx_queues;
1555 uint32_t ntxqs = lif->eth_dev->data->nb_tx_queues;
1557 lif->port_id = lif->eth_dev->data->port_id;
1559 IONIC_PRINT(DEBUG, "Configuring LIF on port %u",
1563 nrxqs_per_lif = RTE_MIN(nrxqs_per_lif, nrxqs);
1566 ntxqs_per_lif = RTE_MIN(ntxqs_per_lif, ntxqs);
1568 lif->nrxqcqs = nrxqs_per_lif;
1569 lif->ntxqcqs = ntxqs_per_lif;
1575 ionic_lif_start(struct ionic_lif *lif)
1577 uint32_t rx_mode = 0;
1581 IONIC_PRINT(DEBUG, "Setting RSS configuration on port %u",
1584 err = ionic_lif_rss_setup(lif);
1588 IONIC_PRINT(DEBUG, "Setting RX mode on port %u",
1591 rx_mode |= IONIC_RX_MODE_F_UNICAST;
1592 rx_mode |= IONIC_RX_MODE_F_MULTICAST;
1593 rx_mode |= IONIC_RX_MODE_F_BROADCAST;
1595 lif->rx_mode = 0; /* set by ionic_set_rx_mode */
1597 ionic_set_rx_mode(lif, rx_mode);
1599 IONIC_PRINT(DEBUG, "Starting %u RX queues and %u TX queues "
1601 lif->nrxqcqs, lif->ntxqcqs, lif->port_id);
1603 for (i = 0; i < lif->nrxqcqs; i++) {
1604 struct ionic_qcq *rxq = lif->rxqcqs[i];
1605 if (!(rxq->flags & IONIC_QCQ_F_DEFERRED)) {
1606 err = ionic_dev_rx_queue_start(lif->eth_dev, i);
1613 for (i = 0; i < lif->ntxqcqs; i++) {
1614 struct ionic_qcq *txq = lif->txqcqs[i];
1615 if (!(txq->flags & IONIC_QCQ_F_DEFERRED)) {
1616 err = ionic_dev_tx_queue_start(lif->eth_dev, i);
1623 ionic_link_status_check(lif);
1625 /* Carrier ON here */
1631 ionic_lif_identify(struct ionic_adapter *adapter)
1633 struct ionic_dev *idev = &adapter->idev;
1634 struct ionic_identity *ident = &adapter->ident;
1637 unsigned int lif_words = sizeof(ident->lif.words) /
1638 sizeof(ident->lif.words[0]);
1639 unsigned int cmd_words = sizeof(idev->dev_cmd->data) /
1640 sizeof(idev->dev_cmd->data[0]);
1641 unsigned int nwords;
1643 ionic_dev_cmd_lif_identify(idev, IONIC_LIF_TYPE_CLASSIC,
1644 IONIC_IDENTITY_VERSION_1);
1645 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1649 nwords = RTE_MIN(lif_words, cmd_words);
1650 for (i = 0; i < nwords; i++)
1651 ident->lif.words[i] = ioread32(&idev->dev_cmd->data[i]);
1653 IONIC_PRINT(INFO, "capabilities 0x%" PRIx64 " ",
1654 ident->lif.capabilities);
1656 IONIC_PRINT(INFO, "eth.max_ucast_filters 0x%" PRIx32 " ",
1657 ident->lif.eth.max_ucast_filters);
1658 IONIC_PRINT(INFO, "eth.max_mcast_filters 0x%" PRIx32 " ",
1659 ident->lif.eth.max_mcast_filters);
1661 IONIC_PRINT(INFO, "eth.features 0x%" PRIx64 " ",
1662 ident->lif.eth.config.features);
1663 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_ADMINQ] 0x%" PRIx32 " ",
1664 ident->lif.eth.config.queue_count[IONIC_QTYPE_ADMINQ]);
1665 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] 0x%" PRIx32 " ",
1666 ident->lif.eth.config.queue_count[IONIC_QTYPE_NOTIFYQ]);
1667 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_RXQ] 0x%" PRIx32 " ",
1668 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ]);
1669 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_TXQ] 0x%" PRIx32 " ",
1670 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ]);
1676 ionic_lifs_size(struct ionic_adapter *adapter)
1678 struct ionic_identity *ident = &adapter->ident;
1679 uint32_t nlifs = ident->dev.nlifs;
1680 uint32_t nintrs, dev_nintrs = ident->dev.nintrs;
1682 adapter->max_ntxqs_per_lif =
1683 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ];
1684 adapter->max_nrxqs_per_lif =
1685 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ];
1687 nintrs = nlifs * 1 /* notifyq */;
1689 if (nintrs > dev_nintrs) {
1691 "At most %d intr supported, minimum req'd is %u",
1692 dev_nintrs, nintrs);
1696 adapter->nintrs = nintrs;