1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
5 #include <rte_malloc.h>
6 #include <rte_ethdev_driver.h>
9 #include "ionic_logs.h"
10 #include "ionic_lif.h"
11 #include "ionic_ethdev.h"
12 #include "ionic_rx_filter.h"
13 #include "ionic_rxtx.h"
15 static int ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr);
16 static int ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr);
19 ionic_qcq_enable(struct ionic_qcq *qcq)
21 struct ionic_queue *q = &qcq->q;
22 struct ionic_lif *lif = q->lif;
23 struct ionic_dev *idev = &lif->adapter->idev;
24 struct ionic_admin_ctx ctx = {
27 .opcode = IONIC_CMD_Q_CONTROL,
28 .lif_index = lif->index,
31 .oper = IONIC_Q_ENABLE,
35 if (qcq->flags & IONIC_QCQ_F_INTR) {
36 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
37 IONIC_INTR_MASK_CLEAR);
40 return ionic_adminq_post_wait(lif, &ctx);
44 ionic_qcq_disable(struct ionic_qcq *qcq)
46 struct ionic_queue *q = &qcq->q;
47 struct ionic_lif *lif = q->lif;
48 struct ionic_dev *idev = &lif->adapter->idev;
49 struct ionic_admin_ctx ctx = {
52 .opcode = IONIC_CMD_Q_CONTROL,
53 .lif_index = lif->index,
56 .oper = IONIC_Q_DISABLE,
60 if (qcq->flags & IONIC_QCQ_F_INTR) {
61 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
65 return ionic_adminq_post_wait(lif, &ctx);
69 ionic_lif_stop(struct ionic_lif *lif __rte_unused)
71 /* Carrier OFF here */
77 ionic_lif_reset(struct ionic_lif *lif)
79 struct ionic_dev *idev = &lif->adapter->idev;
84 ionic_dev_cmd_lif_reset(idev, lif->index);
85 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
87 IONIC_PRINT(WARNING, "Failed to reset lif");
91 ionic_lif_get_abs_stats(const struct ionic_lif *lif, struct rte_eth_stats *stats)
93 struct ionic_lif_stats *ls = &lif->info->stats;
95 uint32_t num_rx_q_counters = RTE_MIN(lif->nrxqcqs, (uint32_t)
96 RTE_ETHDEV_QUEUE_STAT_CNTRS);
97 uint32_t num_tx_q_counters = RTE_MIN(lif->ntxqcqs, (uint32_t)
98 RTE_ETHDEV_QUEUE_STAT_CNTRS);
100 memset(stats, 0, sizeof(*stats));
103 IONIC_PRINT(DEBUG, "Stats on port %u not yet initialized",
110 stats->ipackets = ls->rx_ucast_packets +
111 ls->rx_mcast_packets +
112 ls->rx_bcast_packets;
114 stats->ibytes = ls->rx_ucast_bytes +
118 for (i = 0; i < lif->nrxqcqs; i++) {
119 struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats.rx;
121 rx_stats->no_cb_arg +
122 rx_stats->bad_cq_status +
128 ls->rx_ucast_drop_packets +
129 ls->rx_mcast_drop_packets +
130 ls->rx_bcast_drop_packets;
135 ls->rx_queue_disabled +
136 ls->rx_desc_fetch_error +
137 ls->rx_desc_data_error;
139 for (i = 0; i < num_rx_q_counters; i++) {
140 struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats.rx;
141 stats->q_ipackets[i] = rx_stats->packets;
142 stats->q_ibytes[i] = rx_stats->bytes;
144 rx_stats->no_cb_arg +
145 rx_stats->bad_cq_status +
152 stats->opackets = ls->tx_ucast_packets +
153 ls->tx_mcast_packets +
154 ls->tx_bcast_packets;
156 stats->obytes = ls->tx_ucast_bytes +
160 for (i = 0; i < lif->ntxqcqs; i++) {
161 struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats.tx;
162 stats->oerrors += tx_stats->drop;
166 ls->tx_ucast_drop_packets +
167 ls->tx_mcast_drop_packets +
168 ls->tx_bcast_drop_packets;
172 ls->tx_queue_disabled +
173 ls->tx_desc_fetch_error +
174 ls->tx_desc_data_error;
176 for (i = 0; i < num_tx_q_counters; i++) {
177 struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats.tx;
178 stats->q_opackets[i] = tx_stats->packets;
179 stats->q_obytes[i] = tx_stats->bytes;
184 ionic_lif_get_stats(const struct ionic_lif *lif,
185 struct rte_eth_stats *stats)
187 ionic_lif_get_abs_stats(lif, stats);
189 stats->ipackets -= lif->stats_base.ipackets;
190 stats->opackets -= lif->stats_base.opackets;
191 stats->ibytes -= lif->stats_base.ibytes;
192 stats->obytes -= lif->stats_base.obytes;
193 stats->imissed -= lif->stats_base.imissed;
194 stats->ierrors -= lif->stats_base.ierrors;
195 stats->oerrors -= lif->stats_base.oerrors;
196 stats->rx_nombuf -= lif->stats_base.rx_nombuf;
200 ionic_lif_reset_stats(struct ionic_lif *lif)
204 for (i = 0; i < lif->nrxqcqs; i++) {
205 memset(&lif->rxqcqs[i]->stats.rx, 0,
206 sizeof(struct ionic_rx_stats));
207 memset(&lif->txqcqs[i]->stats.tx, 0,
208 sizeof(struct ionic_tx_stats));
211 ionic_lif_get_abs_stats(lif, &lif->stats_base);
215 ionic_lif_get_hw_stats(struct ionic_lif *lif, struct ionic_lif_stats *stats)
217 uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t);
218 uint64_t *stats64 = (uint64_t *)stats;
219 uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats;
220 uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base;
222 for (i = 0; i < count; i++)
223 stats64[i] = lif_stats64[i] - lif_stats64_base[i];
227 ionic_lif_reset_hw_stats(struct ionic_lif *lif)
229 uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t);
230 uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats;
231 uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base;
233 for (i = 0; i < count; i++)
234 lif_stats64_base[i] = lif_stats64[i];
238 ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr)
240 struct ionic_admin_ctx ctx = {
241 .pending_work = true,
242 .cmd.rx_filter_add = {
243 .opcode = IONIC_CMD_RX_FILTER_ADD,
244 .match = IONIC_RX_FILTER_MATCH_MAC,
249 memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, RTE_ETHER_ADDR_LEN);
251 err = ionic_adminq_post_wait(lif, &ctx);
255 IONIC_PRINT(INFO, "rx_filter add (id %d)",
256 ctx.comp.rx_filter_add.filter_id);
258 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);
262 ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr)
264 struct ionic_admin_ctx ctx = {
265 .pending_work = true,
266 .cmd.rx_filter_del = {
267 .opcode = IONIC_CMD_RX_FILTER_DEL,
270 struct ionic_rx_filter *f;
275 rte_spinlock_lock(&lif->rx_filters.lock);
277 f = ionic_rx_filter_by_addr(lif, addr);
279 rte_spinlock_unlock(&lif->rx_filters.lock);
283 ctx.cmd.rx_filter_del.filter_id = f->filter_id;
284 ionic_rx_filter_free(f);
286 rte_spinlock_unlock(&lif->rx_filters.lock);
288 err = ionic_adminq_post_wait(lif, &ctx);
292 IONIC_PRINT(INFO, "rx_filter del (id %d)",
293 ctx.cmd.rx_filter_del.filter_id);
299 ionic_dev_add_mac(struct rte_eth_dev *eth_dev,
300 struct rte_ether_addr *mac_addr,
301 uint32_t index __rte_unused, uint32_t pool __rte_unused)
303 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
307 return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr);
311 ionic_dev_remove_mac(struct rte_eth_dev *eth_dev, uint32_t index)
313 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
314 struct ionic_adapter *adapter = lif->adapter;
315 struct rte_ether_addr *mac_addr;
319 if (index >= adapter->max_mac_addrs) {
321 "Index %u is above MAC filter limit %u",
322 index, adapter->max_mac_addrs);
326 mac_addr = ð_dev->data->mac_addrs[index];
328 if (!rte_is_valid_assigned_ether_addr(mac_addr))
331 ionic_lif_addr_del(lif, (const uint8_t *)mac_addr);
335 ionic_dev_set_mac(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr)
337 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
341 if (mac_addr == NULL) {
342 IONIC_PRINT(NOTICE, "New mac is null");
346 if (!rte_is_zero_ether_addr((struct rte_ether_addr *)lif->mac_addr)) {
347 IONIC_PRINT(INFO, "Deleting mac addr %pM",
349 ionic_lif_addr_del(lif, lif->mac_addr);
350 memset(lif->mac_addr, 0, RTE_ETHER_ADDR_LEN);
353 IONIC_PRINT(INFO, "Updating mac addr");
355 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)lif->mac_addr);
357 return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr);
361 ionic_vlan_rx_add_vid(struct ionic_lif *lif, uint16_t vid)
363 struct ionic_admin_ctx ctx = {
364 .pending_work = true,
365 .cmd.rx_filter_add = {
366 .opcode = IONIC_CMD_RX_FILTER_ADD,
367 .match = IONIC_RX_FILTER_MATCH_VLAN,
373 err = ionic_adminq_post_wait(lif, &ctx);
377 IONIC_PRINT(INFO, "rx_filter add VLAN %d (id %d)", vid,
378 ctx.comp.rx_filter_add.filter_id);
380 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);
384 ionic_vlan_rx_kill_vid(struct ionic_lif *lif, uint16_t vid)
386 struct ionic_admin_ctx ctx = {
387 .pending_work = true,
388 .cmd.rx_filter_del = {
389 .opcode = IONIC_CMD_RX_FILTER_DEL,
392 struct ionic_rx_filter *f;
397 rte_spinlock_lock(&lif->rx_filters.lock);
399 f = ionic_rx_filter_by_vlan(lif, vid);
401 rte_spinlock_unlock(&lif->rx_filters.lock);
405 ctx.cmd.rx_filter_del.filter_id = f->filter_id;
406 ionic_rx_filter_free(f);
407 rte_spinlock_unlock(&lif->rx_filters.lock);
409 err = ionic_adminq_post_wait(lif, &ctx);
413 IONIC_PRINT(INFO, "rx_filter del VLAN %d (id %d)", vid,
414 ctx.cmd.rx_filter_del.filter_id);
420 ionic_dev_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id,
423 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
427 err = ionic_vlan_rx_add_vid(lif, vlan_id);
429 err = ionic_vlan_rx_kill_vid(lif, vlan_id);
435 ionic_lif_rx_mode(struct ionic_lif *lif, uint32_t rx_mode)
437 struct ionic_admin_ctx ctx = {
438 .pending_work = true,
440 .opcode = IONIC_CMD_RX_MODE_SET,
441 .lif_index = lif->index,
447 if (rx_mode & IONIC_RX_MODE_F_UNICAST)
448 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_UNICAST");
449 if (rx_mode & IONIC_RX_MODE_F_MULTICAST)
450 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_MULTICAST");
451 if (rx_mode & IONIC_RX_MODE_F_BROADCAST)
452 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_BROADCAST");
453 if (rx_mode & IONIC_RX_MODE_F_PROMISC)
454 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_PROMISC");
455 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI)
456 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_ALLMULTI");
458 err = ionic_adminq_post_wait(lif, &ctx);
460 IONIC_PRINT(ERR, "Failure setting RX mode");
464 ionic_set_rx_mode(struct ionic_lif *lif, uint32_t rx_mode)
466 if (lif->rx_mode != rx_mode) {
467 lif->rx_mode = rx_mode;
468 ionic_lif_rx_mode(lif, rx_mode);
473 ionic_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
475 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
476 uint32_t rx_mode = lif->rx_mode;
480 rx_mode |= IONIC_RX_MODE_F_PROMISC;
482 ionic_set_rx_mode(lif, rx_mode);
488 ionic_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
490 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
491 uint32_t rx_mode = lif->rx_mode;
493 rx_mode &= ~IONIC_RX_MODE_F_PROMISC;
495 ionic_set_rx_mode(lif, rx_mode);
501 ionic_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
503 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
504 uint32_t rx_mode = lif->rx_mode;
506 rx_mode |= IONIC_RX_MODE_F_ALLMULTI;
508 ionic_set_rx_mode(lif, rx_mode);
514 ionic_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
516 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
517 uint32_t rx_mode = lif->rx_mode;
519 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI;
521 ionic_set_rx_mode(lif, rx_mode);
527 ionic_lif_change_mtu(struct ionic_lif *lif, int new_mtu)
529 struct ionic_admin_ctx ctx = {
530 .pending_work = true,
532 .opcode = IONIC_CMD_LIF_SETATTR,
534 .attr = IONIC_LIF_ATTR_MTU,
540 err = ionic_adminq_post_wait(lif, &ctx);
548 ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr)
550 struct ionic_adapter *adapter = lif->adapter;
551 struct ionic_dev *idev = &adapter->idev;
555 * Note: interrupt handler is called for index = 0 only
556 * (we use interrupts for the notifyq only anyway,
557 * which hash index = 0)
560 for (index = 0; index < adapter->nintrs; index++)
561 if (!adapter->intrs[index])
564 if (index == adapter->nintrs)
567 adapter->intrs[index] = true;
569 ionic_intr_init(idev, intr, index);
575 ionic_intr_free(struct ionic_lif *lif, struct ionic_intr_info *intr)
577 if (intr->index != IONIC_INTR_INDEX_NOT_ASSIGNED)
578 lif->adapter->intrs[intr->index] = false;
582 ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type,
584 const char *base, uint32_t flags,
587 uint32_t cq_desc_size,
588 uint32_t sg_desc_size,
589 struct ionic_qcq **qcq)
591 struct ionic_dev *idev = &lif->adapter->idev;
592 struct ionic_qcq *new;
593 uint32_t q_size, cq_size, sg_size, total_size;
594 void *q_base, *cq_base, *sg_base;
595 rte_iova_t q_base_pa = 0;
596 rte_iova_t cq_base_pa = 0;
597 rte_iova_t sg_base_pa = 0;
598 uint32_t socket_id = rte_socket_id();
603 q_size = num_descs * desc_size;
604 cq_size = num_descs * cq_desc_size;
605 sg_size = num_descs * sg_desc_size;
607 total_size = RTE_ALIGN(q_size, PAGE_SIZE) +
608 RTE_ALIGN(cq_size, PAGE_SIZE);
610 * Note: aligning q_size/cq_size is not enough due to cq_base address
611 * aligning as q_base could be not aligned to the page.
614 total_size += PAGE_SIZE;
616 if (flags & IONIC_QCQ_F_SG) {
617 total_size += RTE_ALIGN(sg_size, PAGE_SIZE);
618 total_size += PAGE_SIZE;
621 new = rte_zmalloc("ionic", sizeof(*new), 0);
623 IONIC_PRINT(ERR, "Cannot allocate queue structure");
630 new->q.info = rte_zmalloc("ionic", sizeof(*new->q.info) * num_descs, 0);
632 IONIC_PRINT(ERR, "Cannot allocate queue info");
638 err = ionic_q_init(lif, idev, &new->q, index, num_descs,
639 desc_size, sg_desc_size);
641 IONIC_PRINT(ERR, "Queue initialization failed");
645 if (flags & IONIC_QCQ_F_INTR) {
646 err = ionic_intr_alloc(lif, &new->intr);
650 ionic_intr_mask_assert(idev->intr_ctrl, new->intr.index,
651 IONIC_INTR_MASK_SET);
653 new->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED;
656 err = ionic_cq_init(lif, &new->cq, &new->intr,
657 num_descs, cq_desc_size);
659 IONIC_PRINT(ERR, "Completion queue initialization failed");
660 goto err_out_free_intr;
663 new->base_z = rte_eth_dma_zone_reserve(lif->eth_dev,
664 base /* name */, index /* queue_idx */,
665 total_size, IONIC_ALIGN, socket_id);
668 IONIC_PRINT(ERR, "Cannot reserve queue DMA memory");
670 goto err_out_free_intr;
673 new->base = new->base_z->addr;
674 new->base_pa = new->base_z->iova;
675 new->total_size = total_size;
678 q_base_pa = new->base_pa;
680 cq_base = (void *)RTE_ALIGN((uintptr_t)q_base + q_size, PAGE_SIZE);
681 cq_base_pa = RTE_ALIGN(q_base_pa + q_size, PAGE_SIZE);
683 if (flags & IONIC_QCQ_F_SG) {
684 sg_base = (void *)RTE_ALIGN((uintptr_t)cq_base + cq_size,
686 sg_base_pa = RTE_ALIGN(cq_base_pa + cq_size, PAGE_SIZE);
687 ionic_q_sg_map(&new->q, sg_base, sg_base_pa);
690 IONIC_PRINT(DEBUG, "Q-Base-PA = %ju CQ-Base-PA = %ju "
692 q_base_pa, cq_base_pa, sg_base_pa);
694 ionic_q_map(&new->q, q_base, q_base_pa);
695 ionic_cq_map(&new->cq, cq_base, cq_base_pa);
696 ionic_cq_bind(&new->cq, &new->q);
703 if (flags & IONIC_QCQ_F_INTR)
704 ionic_intr_free(lif, &new->intr);
710 ionic_qcq_free(struct ionic_qcq *qcq)
715 rte_memzone_free(qcq->base_z);
720 rte_free(qcq->q.info);
728 ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t nrxq_descs,
729 struct ionic_qcq **qcq)
734 flags = IONIC_QCQ_F_SG;
735 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, index, "rx", flags,
737 sizeof(struct ionic_rxq_desc),
738 sizeof(struct ionic_rxq_comp),
739 sizeof(struct ionic_rxq_sg_desc),
740 &lif->rxqcqs[index]);
744 *qcq = lif->rxqcqs[index];
750 ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t ntxq_descs,
751 struct ionic_qcq **qcq)
756 flags = IONIC_QCQ_F_SG;
757 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, index, "tx", flags,
759 sizeof(struct ionic_txq_desc),
760 sizeof(struct ionic_txq_comp),
761 sizeof(struct ionic_txq_sg_desc),
762 &lif->txqcqs[index]);
766 *qcq = lif->txqcqs[index];
772 ionic_admin_qcq_alloc(struct ionic_lif *lif)
778 err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags,
780 sizeof(struct ionic_admin_cmd),
781 sizeof(struct ionic_admin_comp),
791 ionic_notify_qcq_alloc(struct ionic_lif *lif)
796 flags = IONIC_QCQ_F_NOTIFYQ | IONIC_QCQ_F_INTR;
798 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notify",
800 IONIC_NOTIFYQ_LENGTH,
801 sizeof(struct ionic_notifyq_cmd),
802 sizeof(union ionic_notifyq_comp),
812 ionic_bus_map_dbpage(struct ionic_adapter *adapter, int page_num)
814 char *vaddr = adapter->bars[IONIC_PCI_BAR_DBELL].vaddr;
816 if (adapter->num_bars <= IONIC_PCI_BAR_DBELL)
819 return (void *)&vaddr[page_num << PAGE_SHIFT];
823 ionic_lif_alloc(struct ionic_lif *lif)
825 struct ionic_adapter *adapter = lif->adapter;
826 uint32_t socket_id = rte_socket_id();
830 snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index);
832 IONIC_PRINT(DEBUG, "Allocating Lif Info");
834 rte_spinlock_init(&lif->adminq_lock);
835 rte_spinlock_init(&lif->adminq_service_lock);
837 dbpage_num = ionic_db_page_num(lif, 0);
839 lif->kern_dbpage = ionic_bus_map_dbpage(adapter, dbpage_num);
840 if (!lif->kern_dbpage) {
841 IONIC_PRINT(ERR, "Cannot map dbpage, aborting");
845 lif->txqcqs = rte_zmalloc("ionic", sizeof(*lif->txqcqs) *
846 adapter->max_ntxqs_per_lif, 0);
849 IONIC_PRINT(ERR, "Cannot allocate tx queues array");
853 lif->rxqcqs = rte_zmalloc("ionic", sizeof(*lif->rxqcqs) *
854 adapter->max_nrxqs_per_lif, 0);
857 IONIC_PRINT(ERR, "Cannot allocate rx queues array");
861 IONIC_PRINT(DEBUG, "Allocating Notify Queue");
863 err = ionic_notify_qcq_alloc(lif);
865 IONIC_PRINT(ERR, "Cannot allocate notify queue");
869 IONIC_PRINT(DEBUG, "Allocating Admin Queue");
871 IONIC_PRINT(DEBUG, "Allocating Admin Queue");
873 err = ionic_admin_qcq_alloc(lif);
875 IONIC_PRINT(ERR, "Cannot allocate admin queue");
879 IONIC_PRINT(DEBUG, "Allocating Lif Info");
881 lif->info_sz = RTE_ALIGN(sizeof(*lif->info), PAGE_SIZE);
883 lif->info_z = rte_eth_dma_zone_reserve(lif->eth_dev,
884 "lif_info", 0 /* queue_idx*/,
885 lif->info_sz, IONIC_ALIGN, socket_id);
887 IONIC_PRINT(ERR, "Cannot allocate lif info memory");
891 lif->info = lif->info_z->addr;
892 lif->info_pa = lif->info_z->iova;
898 ionic_lif_free(struct ionic_lif *lif)
900 if (lif->notifyqcq) {
901 ionic_qcq_free(lif->notifyqcq);
902 lif->notifyqcq = NULL;
906 ionic_qcq_free(lif->adminqcq);
907 lif->adminqcq = NULL;
911 rte_free(lif->txqcqs);
916 rte_free(lif->rxqcqs);
921 rte_memzone_free(lif->info_z);
927 ionic_lif_rss_config(struct ionic_lif *lif,
928 const uint16_t types, const uint8_t *key, const uint32_t *indir)
930 struct ionic_admin_ctx ctx = {
931 .pending_work = true,
933 .opcode = IONIC_CMD_LIF_SETATTR,
934 .attr = IONIC_LIF_ATTR_RSS,
936 .rss.addr = lif->rss_ind_tbl_pa,
943 lif->rss_types = types;
946 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE);
949 for (i = 0; i < lif->adapter->ident.lif.eth.rss_ind_tbl_sz; i++)
950 lif->rss_ind_tbl[i] = indir[i];
952 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key,
953 IONIC_RSS_HASH_KEY_SIZE);
955 return ionic_adminq_post_wait(lif, &ctx);
959 ionic_lif_rss_setup(struct ionic_lif *lif)
961 size_t tbl_size = sizeof(*lif->rss_ind_tbl) *
962 lif->adapter->ident.lif.eth.rss_ind_tbl_sz;
963 static const uint8_t toeplitz_symmetric_key[] = {
964 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
965 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
966 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
967 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
968 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
970 uint32_t socket_id = rte_socket_id();
976 lif->rss_ind_tbl_z = rte_eth_dma_zone_reserve(lif->eth_dev,
978 0 /* queue_idx*/, tbl_size, IONIC_ALIGN, socket_id);
980 if (!lif->rss_ind_tbl_z) {
981 IONIC_PRINT(ERR, "OOM");
985 lif->rss_ind_tbl = lif->rss_ind_tbl_z->addr;
986 lif->rss_ind_tbl_pa = lif->rss_ind_tbl_z->iova;
988 /* Fill indirection table with 'default' values */
989 for (i = 0; i < lif->adapter->ident.lif.eth.rss_ind_tbl_sz; i++)
990 lif->rss_ind_tbl[i] = i % lif->nrxqcqs;
992 err = ionic_lif_rss_config(lif, IONIC_RSS_OFFLOAD_ALL,
993 toeplitz_symmetric_key, NULL);
1001 ionic_lif_rss_teardown(struct ionic_lif *lif)
1003 if (!lif->rss_ind_tbl)
1006 if (lif->rss_ind_tbl_z) {
1007 /* Disable RSS on the NIC */
1008 ionic_lif_rss_config(lif, 0x0, NULL, NULL);
1010 lif->rss_ind_tbl = NULL;
1011 lif->rss_ind_tbl_pa = 0;
1012 rte_memzone_free(lif->rss_ind_tbl_z);
1013 lif->rss_ind_tbl_z = NULL;
1018 ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq)
1020 struct ionic_dev *idev = &lif->adapter->idev;
1022 if (!(qcq->flags & IONIC_QCQ_F_INITED))
1025 if (qcq->flags & IONIC_QCQ_F_INTR)
1026 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1027 IONIC_INTR_MASK_SET);
1029 qcq->flags &= ~IONIC_QCQ_F_INITED;
1033 ionic_lif_txq_deinit(struct ionic_qcq *qcq)
1035 ionic_lif_qcq_deinit(qcq->lif, qcq);
1039 ionic_lif_rxq_deinit(struct ionic_qcq *qcq)
1041 ionic_lif_qcq_deinit(qcq->lif, qcq);
1045 ionic_adminq_service(struct ionic_cq *cq, uint32_t cq_desc_index,
1046 void *cb_arg __rte_unused)
1048 struct ionic_admin_comp *cq_desc_base = cq->base;
1049 struct ionic_admin_comp *cq_desc = &cq_desc_base[cq_desc_index];
1051 if (!color_match(cq_desc->color, cq->done_color))
1054 ionic_q_service(cq->bound_q, cq_desc_index, cq_desc->comp_index, NULL);
1059 /* This acts like ionic_napi */
1061 ionic_qcq_service(struct ionic_qcq *qcq, int budget, ionic_cq_cb cb,
1064 struct ionic_cq *cq = &qcq->cq;
1067 work_done = ionic_cq_service(cq, budget, cb, cb_arg);
1073 ionic_link_status_check(struct ionic_lif *lif)
1075 struct ionic_adapter *adapter = lif->adapter;
1078 lif->state &= ~IONIC_LIF_F_LINK_CHECK_NEEDED;
1083 link_up = (lif->info->status.link_status == IONIC_PORT_OPER_STATUS_UP);
1085 if ((link_up && adapter->link_up) ||
1086 (!link_up && !adapter->link_up))
1090 IONIC_PRINT(DEBUG, "Link up - %d Gbps",
1091 lif->info->status.link_speed);
1092 adapter->link_speed = lif->info->status.link_speed;
1094 IONIC_PRINT(DEBUG, "Link down");
1097 adapter->link_up = link_up;
1101 ionic_notifyq_cb(struct ionic_cq *cq, uint32_t cq_desc_index, void *cb_arg)
1103 union ionic_notifyq_comp *cq_desc_base = cq->base;
1104 union ionic_notifyq_comp *cq_desc = &cq_desc_base[cq_desc_index];
1105 struct ionic_lif *lif = cb_arg;
1107 IONIC_PRINT(DEBUG, "Notifyq callback eid = %jd ecode = %d",
1108 cq_desc->event.eid, cq_desc->event.ecode);
1110 /* Have we run out of new completions to process? */
1111 if (!(cq_desc->event.eid > lif->last_eid))
1114 lif->last_eid = cq_desc->event.eid;
1116 switch (cq_desc->event.ecode) {
1117 case IONIC_EVENT_LINK_CHANGE:
1119 "Notifyq IONIC_EVENT_LINK_CHANGE eid=%jd link_status=%d link_speed=%d",
1121 cq_desc->link_change.link_status,
1122 cq_desc->link_change.link_speed);
1124 lif->state |= IONIC_LIF_F_LINK_CHECK_NEEDED;
1128 IONIC_PRINT(WARNING, "Notifyq bad event ecode=%d eid=%jd",
1129 cq_desc->event.ecode, cq_desc->event.eid);
1137 ionic_notifyq_handler(struct ionic_lif *lif, int budget)
1139 struct ionic_dev *idev = &lif->adapter->idev;
1140 struct ionic_qcq *qcq = lif->notifyqcq;
1143 if (!(qcq->flags & IONIC_QCQ_F_INITED)) {
1144 IONIC_PRINT(DEBUG, "Notifyq not yet initialized");
1148 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1149 IONIC_INTR_MASK_SET);
1151 work_done = ionic_qcq_service(qcq, budget, ionic_notifyq_cb, lif);
1153 if (lif->state & IONIC_LIF_F_LINK_CHECK_NEEDED)
1154 ionic_link_status_check(lif);
1156 ionic_intr_credits(idev->intr_ctrl, qcq->intr.index,
1157 work_done, IONIC_INTR_CRED_RESET_COALESCE);
1159 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1160 IONIC_INTR_MASK_CLEAR);
1166 ionic_lif_adminq_init(struct ionic_lif *lif)
1168 struct ionic_dev *idev = &lif->adapter->idev;
1169 struct ionic_qcq *qcq = lif->adminqcq;
1170 struct ionic_queue *q = &qcq->q;
1171 struct ionic_q_init_comp comp;
1174 ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index);
1175 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1179 ionic_dev_cmd_comp(idev, &comp);
1181 q->hw_type = comp.hw_type;
1182 q->hw_index = comp.hw_index;
1183 q->db = ionic_db_map(lif, q);
1185 IONIC_PRINT(DEBUG, "adminq->hw_type %d", q->hw_type);
1186 IONIC_PRINT(DEBUG, "adminq->hw_index %d", q->hw_index);
1187 IONIC_PRINT(DEBUG, "adminq->db %p", q->db);
1189 if (qcq->flags & IONIC_QCQ_F_INTR)
1190 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1191 IONIC_INTR_MASK_CLEAR);
1193 qcq->flags |= IONIC_QCQ_F_INITED;
1199 ionic_lif_notifyq_init(struct ionic_lif *lif)
1201 struct ionic_dev *idev = &lif->adapter->idev;
1202 struct ionic_qcq *qcq = lif->notifyqcq;
1203 struct ionic_queue *q = &qcq->q;
1206 struct ionic_admin_ctx ctx = {
1207 .pending_work = true,
1209 .opcode = IONIC_CMD_Q_INIT,
1210 .lif_index = lif->index,
1213 .flags = (IONIC_QINIT_F_IRQ | IONIC_QINIT_F_ENA),
1214 .intr_index = qcq->intr.index,
1215 .ring_size = rte_log2_u32(q->num_descs),
1216 .ring_base = q->base_pa,
1220 IONIC_PRINT(DEBUG, "notifyq_init.index %d",
1221 ctx.cmd.q_init.index);
1222 IONIC_PRINT(DEBUG, "notifyq_init.ring_base 0x%" PRIx64 "",
1223 ctx.cmd.q_init.ring_base);
1224 IONIC_PRINT(DEBUG, "notifyq_init.ring_size %d",
1225 ctx.cmd.q_init.ring_size);
1227 err = ionic_adminq_post_wait(lif, &ctx);
1231 q->hw_type = ctx.comp.q_init.hw_type;
1232 q->hw_index = ctx.comp.q_init.hw_index;
1235 IONIC_PRINT(DEBUG, "notifyq->hw_type %d", q->hw_type);
1236 IONIC_PRINT(DEBUG, "notifyq->hw_index %d", q->hw_index);
1237 IONIC_PRINT(DEBUG, "notifyq->db %p", q->db);
1239 if (qcq->flags & IONIC_QCQ_F_INTR)
1240 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1241 IONIC_INTR_MASK_CLEAR);
1243 qcq->flags |= IONIC_QCQ_F_INITED;
1249 ionic_lif_set_features(struct ionic_lif *lif)
1251 struct ionic_admin_ctx ctx = {
1252 .pending_work = true,
1253 .cmd.lif_setattr = {
1254 .opcode = IONIC_CMD_LIF_SETATTR,
1255 .index = lif->index,
1256 .attr = IONIC_LIF_ATTR_FEATURES,
1257 .features = lif->features,
1262 err = ionic_adminq_post_wait(lif, &ctx);
1266 lif->hw_features = (ctx.cmd.lif_setattr.features &
1267 ctx.comp.lif_setattr.features);
1269 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
1270 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_TX_TAG");
1271 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
1272 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_STRIP");
1273 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
1274 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_FILTER");
1275 if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
1276 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_HASH");
1277 if (lif->hw_features & IONIC_ETH_HW_TX_SG)
1278 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_SG");
1279 if (lif->hw_features & IONIC_ETH_HW_RX_SG)
1280 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_SG");
1281 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
1282 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_CSUM");
1283 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
1284 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_CSUM");
1285 if (lif->hw_features & IONIC_ETH_HW_TSO)
1286 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO");
1287 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
1288 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPV6");
1289 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
1290 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_ECN");
1291 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
1292 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE");
1293 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
1294 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE_CSUM");
1295 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
1296 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP4");
1297 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
1298 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP6");
1299 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
1300 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP");
1301 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
1302 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP_CSUM");
1308 ionic_lif_txq_init(struct ionic_qcq *qcq)
1310 struct ionic_queue *q = &qcq->q;
1311 struct ionic_lif *lif = qcq->lif;
1312 struct ionic_cq *cq = &qcq->cq;
1313 struct ionic_admin_ctx ctx = {
1314 .pending_work = true,
1316 .opcode = IONIC_CMD_Q_INIT,
1317 .lif_index = lif->index,
1320 .flags = IONIC_QINIT_F_SG,
1321 .intr_index = cq->bound_intr->index,
1322 .ring_size = rte_log2_u32(q->num_descs),
1323 .ring_base = q->base_pa,
1324 .cq_ring_base = cq->base_pa,
1325 .sg_ring_base = q->sg_base_pa,
1330 IONIC_PRINT(DEBUG, "txq_init.index %d", ctx.cmd.q_init.index);
1331 IONIC_PRINT(DEBUG, "txq_init.ring_base 0x%" PRIx64 "",
1332 ctx.cmd.q_init.ring_base);
1333 IONIC_PRINT(DEBUG, "txq_init.ring_size %d",
1334 ctx.cmd.q_init.ring_size);
1336 err = ionic_adminq_post_wait(qcq->lif, &ctx);
1340 q->hw_type = ctx.comp.q_init.hw_type;
1341 q->hw_index = ctx.comp.q_init.hw_index;
1342 q->db = ionic_db_map(lif, q);
1344 IONIC_PRINT(DEBUG, "txq->hw_type %d", q->hw_type);
1345 IONIC_PRINT(DEBUG, "txq->hw_index %d", q->hw_index);
1346 IONIC_PRINT(DEBUG, "txq->db %p", q->db);
1348 qcq->flags |= IONIC_QCQ_F_INITED;
1354 ionic_lif_rxq_init(struct ionic_qcq *qcq)
1356 struct ionic_queue *q = &qcq->q;
1357 struct ionic_lif *lif = qcq->lif;
1358 struct ionic_cq *cq = &qcq->cq;
1359 struct ionic_admin_ctx ctx = {
1360 .pending_work = true,
1362 .opcode = IONIC_CMD_Q_INIT,
1363 .lif_index = lif->index,
1366 .flags = IONIC_QINIT_F_SG,
1367 .intr_index = cq->bound_intr->index,
1368 .ring_size = rte_log2_u32(q->num_descs),
1369 .ring_base = q->base_pa,
1370 .cq_ring_base = cq->base_pa,
1371 .sg_ring_base = q->sg_base_pa,
1376 IONIC_PRINT(DEBUG, "rxq_init.index %d", ctx.cmd.q_init.index);
1377 IONIC_PRINT(DEBUG, "rxq_init.ring_base 0x%" PRIx64 "",
1378 ctx.cmd.q_init.ring_base);
1379 IONIC_PRINT(DEBUG, "rxq_init.ring_size %d",
1380 ctx.cmd.q_init.ring_size);
1382 err = ionic_adminq_post_wait(qcq->lif, &ctx);
1386 q->hw_type = ctx.comp.q_init.hw_type;
1387 q->hw_index = ctx.comp.q_init.hw_index;
1388 q->db = ionic_db_map(lif, q);
1390 qcq->flags |= IONIC_QCQ_F_INITED;
1392 IONIC_PRINT(DEBUG, "rxq->hw_type %d", q->hw_type);
1393 IONIC_PRINT(DEBUG, "rxq->hw_index %d", q->hw_index);
1394 IONIC_PRINT(DEBUG, "rxq->db %p", q->db);
1400 ionic_station_set(struct ionic_lif *lif)
1402 struct ionic_admin_ctx ctx = {
1403 .pending_work = true,
1404 .cmd.lif_getattr = {
1405 .opcode = IONIC_CMD_LIF_GETATTR,
1406 .index = lif->index,
1407 .attr = IONIC_LIF_ATTR_MAC,
1414 err = ionic_adminq_post_wait(lif, &ctx);
1418 if (!rte_is_zero_ether_addr((struct rte_ether_addr *)
1420 IONIC_PRINT(INFO, "deleting station MAC addr");
1422 ionic_lif_addr_del(lif, lif->mac_addr);
1425 memcpy(lif->mac_addr, ctx.comp.lif_getattr.mac, RTE_ETHER_ADDR_LEN);
1427 if (rte_is_zero_ether_addr((struct rte_ether_addr *)lif->mac_addr)) {
1428 IONIC_PRINT(NOTICE, "empty MAC addr (VF?)");
1432 IONIC_PRINT(DEBUG, "adding station MAC addr");
1434 ionic_lif_addr_add(lif, lif->mac_addr);
1440 ionic_lif_set_name(struct ionic_lif *lif)
1442 struct ionic_admin_ctx ctx = {
1443 .pending_work = true,
1444 .cmd.lif_setattr = {
1445 .opcode = IONIC_CMD_LIF_SETATTR,
1446 .index = lif->index,
1447 .attr = IONIC_LIF_ATTR_NAME,
1451 snprintf(ctx.cmd.lif_setattr.name, sizeof(ctx.cmd.lif_setattr.name),
1452 "%d", lif->port_id);
1454 ionic_adminq_post_wait(lif, &ctx);
1458 ionic_lif_init(struct ionic_lif *lif)
1460 struct ionic_dev *idev = &lif->adapter->idev;
1461 struct ionic_q_init_comp comp;
1464 memset(&lif->stats_base, 0, sizeof(lif->stats_base));
1466 ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa);
1467 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1468 ionic_dev_cmd_comp(idev, &comp);
1472 lif->hw_index = comp.hw_index;
1474 err = ionic_lif_adminq_init(lif);
1478 err = ionic_lif_notifyq_init(lif);
1480 goto err_out_adminq_deinit;
1483 IONIC_ETH_HW_VLAN_TX_TAG
1484 | IONIC_ETH_HW_VLAN_RX_STRIP
1485 | IONIC_ETH_HW_VLAN_RX_FILTER
1486 | IONIC_ETH_HW_RX_HASH
1487 | IONIC_ETH_HW_TX_SG
1488 | IONIC_ETH_HW_RX_SG
1489 | IONIC_ETH_HW_TX_CSUM
1490 | IONIC_ETH_HW_RX_CSUM
1492 | IONIC_ETH_HW_TSO_IPV6
1493 | IONIC_ETH_HW_TSO_ECN;
1495 err = ionic_lif_set_features(lif);
1497 goto err_out_notifyq_deinit;
1499 err = ionic_rx_filters_init(lif);
1501 goto err_out_notifyq_deinit;
1503 err = ionic_station_set(lif);
1505 goto err_out_rx_filter_deinit;
1507 ionic_lif_set_name(lif);
1509 lif->state |= IONIC_LIF_F_INITED;
1513 err_out_rx_filter_deinit:
1514 ionic_rx_filters_deinit(lif);
1516 err_out_notifyq_deinit:
1517 ionic_lif_qcq_deinit(lif, lif->notifyqcq);
1519 err_out_adminq_deinit:
1520 ionic_lif_qcq_deinit(lif, lif->adminqcq);
1526 ionic_lif_deinit(struct ionic_lif *lif)
1528 if (!(lif->state & IONIC_LIF_F_INITED))
1531 ionic_rx_filters_deinit(lif);
1532 ionic_lif_rss_teardown(lif);
1533 ionic_lif_qcq_deinit(lif, lif->notifyqcq);
1534 ionic_lif_qcq_deinit(lif, lif->adminqcq);
1536 lif->state &= ~IONIC_LIF_F_INITED;
1540 ionic_lif_configure(struct ionic_lif *lif)
1542 struct ionic_identity *ident = &lif->adapter->ident;
1543 uint32_t ntxqs_per_lif =
1544 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ];
1545 uint32_t nrxqs_per_lif =
1546 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ];
1547 uint32_t nrxqs = lif->eth_dev->data->nb_rx_queues;
1548 uint32_t ntxqs = lif->eth_dev->data->nb_tx_queues;
1550 lif->port_id = lif->eth_dev->data->port_id;
1552 IONIC_PRINT(DEBUG, "Configuring LIF on port %u",
1556 nrxqs_per_lif = RTE_MIN(nrxqs_per_lif, nrxqs);
1559 ntxqs_per_lif = RTE_MIN(ntxqs_per_lif, ntxqs);
1561 lif->nrxqcqs = nrxqs_per_lif;
1562 lif->ntxqcqs = ntxqs_per_lif;
1568 ionic_lif_start(struct ionic_lif *lif)
1570 uint32_t rx_mode = 0;
1574 IONIC_PRINT(DEBUG, "Setting RSS configuration on port %u",
1577 err = ionic_lif_rss_setup(lif);
1581 IONIC_PRINT(DEBUG, "Setting RX mode on port %u",
1584 rx_mode |= IONIC_RX_MODE_F_UNICAST;
1585 rx_mode |= IONIC_RX_MODE_F_MULTICAST;
1586 rx_mode |= IONIC_RX_MODE_F_BROADCAST;
1588 lif->rx_mode = 0; /* set by ionic_set_rx_mode */
1590 ionic_set_rx_mode(lif, rx_mode);
1592 IONIC_PRINT(DEBUG, "Starting %u RX queues and %u TX queues "
1594 lif->nrxqcqs, lif->ntxqcqs, lif->port_id);
1596 for (i = 0; i < lif->nrxqcqs; i++) {
1597 struct ionic_qcq *rxq = lif->rxqcqs[i];
1598 if (!(rxq->flags & IONIC_QCQ_F_DEFERRED)) {
1599 err = ionic_dev_rx_queue_start(lif->eth_dev, i);
1606 for (i = 0; i < lif->ntxqcqs; i++) {
1607 struct ionic_qcq *txq = lif->txqcqs[i];
1608 if (!(txq->flags & IONIC_QCQ_F_DEFERRED)) {
1609 err = ionic_dev_tx_queue_start(lif->eth_dev, i);
1616 ionic_link_status_check(lif);
1618 /* Carrier ON here */
1624 ionic_lif_identify(struct ionic_adapter *adapter)
1626 struct ionic_dev *idev = &adapter->idev;
1627 struct ionic_identity *ident = &adapter->ident;
1630 unsigned int lif_words = sizeof(ident->lif.words) /
1631 sizeof(ident->lif.words[0]);
1632 unsigned int cmd_words = sizeof(idev->dev_cmd->data) /
1633 sizeof(idev->dev_cmd->data[0]);
1634 unsigned int nwords;
1636 ionic_dev_cmd_lif_identify(idev, IONIC_LIF_TYPE_CLASSIC,
1637 IONIC_IDENTITY_VERSION_1);
1638 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1642 nwords = RTE_MIN(lif_words, cmd_words);
1643 for (i = 0; i < nwords; i++)
1644 ident->lif.words[i] = ioread32(&idev->dev_cmd->data[i]);
1646 IONIC_PRINT(INFO, "capabilities 0x%" PRIx64 " ",
1647 ident->lif.capabilities);
1649 IONIC_PRINT(INFO, "eth.max_ucast_filters 0x%" PRIx32 " ",
1650 ident->lif.eth.max_ucast_filters);
1651 IONIC_PRINT(INFO, "eth.max_mcast_filters 0x%" PRIx32 " ",
1652 ident->lif.eth.max_mcast_filters);
1654 IONIC_PRINT(INFO, "eth.features 0x%" PRIx64 " ",
1655 ident->lif.eth.config.features);
1656 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_ADMINQ] 0x%" PRIx32 " ",
1657 ident->lif.eth.config.queue_count[IONIC_QTYPE_ADMINQ]);
1658 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] 0x%" PRIx32 " ",
1659 ident->lif.eth.config.queue_count[IONIC_QTYPE_NOTIFYQ]);
1660 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_RXQ] 0x%" PRIx32 " ",
1661 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ]);
1662 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_TXQ] 0x%" PRIx32 " ",
1663 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ]);
1669 ionic_lifs_size(struct ionic_adapter *adapter)
1671 struct ionic_identity *ident = &adapter->ident;
1672 uint32_t nlifs = ident->dev.nlifs;
1673 uint32_t nintrs, dev_nintrs = ident->dev.nintrs;
1675 adapter->max_ntxqs_per_lif =
1676 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ];
1677 adapter->max_nrxqs_per_lif =
1678 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ];
1680 nintrs = nlifs * 1 /* notifyq */;
1682 if (nintrs > dev_nintrs) {
1683 IONIC_PRINT(ERR, "At most %d intr queues supported, minimum required is %u",
1684 dev_nintrs, nintrs);
1688 adapter->nintrs = nintrs;