1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
5 #include <rte_malloc.h>
6 #include <rte_ethdev_driver.h>
9 #include "ionic_logs.h"
10 #include "ionic_lif.h"
11 #include "ionic_ethdev.h"
12 #include "ionic_rx_filter.h"
13 #include "ionic_rxtx.h"
15 static int ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr);
16 static int ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr);
19 ionic_qcq_enable(struct ionic_qcq *qcq)
21 struct ionic_queue *q = &qcq->q;
22 struct ionic_lif *lif = q->lif;
23 struct ionic_dev *idev = &lif->adapter->idev;
24 struct ionic_admin_ctx ctx = {
27 .opcode = IONIC_CMD_Q_CONTROL,
30 .oper = IONIC_Q_ENABLE,
34 if (qcq->flags & IONIC_QCQ_F_INTR) {
35 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
36 IONIC_INTR_MASK_CLEAR);
39 return ionic_adminq_post_wait(lif, &ctx);
43 ionic_qcq_disable(struct ionic_qcq *qcq)
45 struct ionic_queue *q = &qcq->q;
46 struct ionic_lif *lif = q->lif;
47 struct ionic_dev *idev = &lif->adapter->idev;
48 struct ionic_admin_ctx ctx = {
51 .opcode = IONIC_CMD_Q_CONTROL,
54 .oper = IONIC_Q_DISABLE,
58 if (qcq->flags & IONIC_QCQ_F_INTR) {
59 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
63 return ionic_adminq_post_wait(lif, &ctx);
67 ionic_lif_stop(struct ionic_lif *lif __rte_unused)
69 /* Carrier OFF here */
75 ionic_lif_reset(struct ionic_lif *lif)
77 struct ionic_dev *idev = &lif->adapter->idev;
82 ionic_dev_cmd_lif_reset(idev);
83 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
85 IONIC_PRINT(WARNING, "Failed to reset %s", lif->name);
89 ionic_lif_get_abs_stats(const struct ionic_lif *lif, struct rte_eth_stats *stats)
91 struct ionic_lif_stats *ls = &lif->info->stats;
93 uint32_t num_rx_q_counters = RTE_MIN(lif->nrxqcqs, (uint32_t)
94 RTE_ETHDEV_QUEUE_STAT_CNTRS);
95 uint32_t num_tx_q_counters = RTE_MIN(lif->ntxqcqs, (uint32_t)
96 RTE_ETHDEV_QUEUE_STAT_CNTRS);
98 memset(stats, 0, sizeof(*stats));
101 IONIC_PRINT(DEBUG, "Stats on port %u not yet initialized",
108 stats->ipackets = ls->rx_ucast_packets +
109 ls->rx_mcast_packets +
110 ls->rx_bcast_packets;
112 stats->ibytes = ls->rx_ucast_bytes +
116 for (i = 0; i < lif->nrxqcqs; i++) {
117 struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats.rx;
119 rx_stats->no_cb_arg +
120 rx_stats->bad_cq_status +
126 ls->rx_ucast_drop_packets +
127 ls->rx_mcast_drop_packets +
128 ls->rx_bcast_drop_packets;
133 ls->rx_queue_disabled +
134 ls->rx_desc_fetch_error +
135 ls->rx_desc_data_error;
137 for (i = 0; i < num_rx_q_counters; i++) {
138 struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats.rx;
139 stats->q_ipackets[i] = rx_stats->packets;
140 stats->q_ibytes[i] = rx_stats->bytes;
142 rx_stats->no_cb_arg +
143 rx_stats->bad_cq_status +
150 stats->opackets = ls->tx_ucast_packets +
151 ls->tx_mcast_packets +
152 ls->tx_bcast_packets;
154 stats->obytes = ls->tx_ucast_bytes +
158 for (i = 0; i < lif->ntxqcqs; i++) {
159 struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats.tx;
160 stats->oerrors += tx_stats->drop;
164 ls->tx_ucast_drop_packets +
165 ls->tx_mcast_drop_packets +
166 ls->tx_bcast_drop_packets;
170 ls->tx_queue_disabled +
171 ls->tx_desc_fetch_error +
172 ls->tx_desc_data_error;
174 for (i = 0; i < num_tx_q_counters; i++) {
175 struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats.tx;
176 stats->q_opackets[i] = tx_stats->packets;
177 stats->q_obytes[i] = tx_stats->bytes;
182 ionic_lif_get_stats(const struct ionic_lif *lif,
183 struct rte_eth_stats *stats)
185 ionic_lif_get_abs_stats(lif, stats);
187 stats->ipackets -= lif->stats_base.ipackets;
188 stats->opackets -= lif->stats_base.opackets;
189 stats->ibytes -= lif->stats_base.ibytes;
190 stats->obytes -= lif->stats_base.obytes;
191 stats->imissed -= lif->stats_base.imissed;
192 stats->ierrors -= lif->stats_base.ierrors;
193 stats->oerrors -= lif->stats_base.oerrors;
194 stats->rx_nombuf -= lif->stats_base.rx_nombuf;
198 ionic_lif_reset_stats(struct ionic_lif *lif)
202 for (i = 0; i < lif->nrxqcqs; i++) {
203 memset(&lif->rxqcqs[i]->stats.rx, 0,
204 sizeof(struct ionic_rx_stats));
205 memset(&lif->txqcqs[i]->stats.tx, 0,
206 sizeof(struct ionic_tx_stats));
209 ionic_lif_get_abs_stats(lif, &lif->stats_base);
213 ionic_lif_get_hw_stats(struct ionic_lif *lif, struct ionic_lif_stats *stats)
215 uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t);
216 uint64_t *stats64 = (uint64_t *)stats;
217 uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats;
218 uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base;
220 for (i = 0; i < count; i++)
221 stats64[i] = lif_stats64[i] - lif_stats64_base[i];
225 ionic_lif_reset_hw_stats(struct ionic_lif *lif)
227 uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t);
228 uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats;
229 uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base;
231 for (i = 0; i < count; i++)
232 lif_stats64_base[i] = lif_stats64[i];
236 ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr)
238 struct ionic_admin_ctx ctx = {
239 .pending_work = true,
240 .cmd.rx_filter_add = {
241 .opcode = IONIC_CMD_RX_FILTER_ADD,
242 .match = IONIC_RX_FILTER_MATCH_MAC,
247 memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, RTE_ETHER_ADDR_LEN);
249 err = ionic_adminq_post_wait(lif, &ctx);
253 IONIC_PRINT(INFO, "rx_filter add (id %d)",
254 ctx.comp.rx_filter_add.filter_id);
256 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);
260 ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr)
262 struct ionic_admin_ctx ctx = {
263 .pending_work = true,
264 .cmd.rx_filter_del = {
265 .opcode = IONIC_CMD_RX_FILTER_DEL,
268 struct ionic_rx_filter *f;
273 rte_spinlock_lock(&lif->rx_filters.lock);
275 f = ionic_rx_filter_by_addr(lif, addr);
277 rte_spinlock_unlock(&lif->rx_filters.lock);
281 ctx.cmd.rx_filter_del.filter_id = f->filter_id;
282 ionic_rx_filter_free(f);
284 rte_spinlock_unlock(&lif->rx_filters.lock);
286 err = ionic_adminq_post_wait(lif, &ctx);
290 IONIC_PRINT(INFO, "rx_filter del (id %d)",
291 ctx.cmd.rx_filter_del.filter_id);
297 ionic_dev_add_mac(struct rte_eth_dev *eth_dev,
298 struct rte_ether_addr *mac_addr,
299 uint32_t index __rte_unused, uint32_t pool __rte_unused)
301 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
305 return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr);
309 ionic_dev_remove_mac(struct rte_eth_dev *eth_dev, uint32_t index)
311 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
312 struct ionic_adapter *adapter = lif->adapter;
313 struct rte_ether_addr *mac_addr;
317 if (index >= adapter->max_mac_addrs) {
319 "Index %u is above MAC filter limit %u",
320 index, adapter->max_mac_addrs);
324 mac_addr = ð_dev->data->mac_addrs[index];
326 if (!rte_is_valid_assigned_ether_addr(mac_addr))
329 ionic_lif_addr_del(lif, (const uint8_t *)mac_addr);
333 ionic_dev_set_mac(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr)
335 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
339 if (mac_addr == NULL) {
340 IONIC_PRINT(NOTICE, "New mac is null");
344 if (!rte_is_zero_ether_addr((struct rte_ether_addr *)lif->mac_addr)) {
345 IONIC_PRINT(INFO, "Deleting mac addr %pM",
347 ionic_lif_addr_del(lif, lif->mac_addr);
348 memset(lif->mac_addr, 0, RTE_ETHER_ADDR_LEN);
351 IONIC_PRINT(INFO, "Updating mac addr");
353 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)lif->mac_addr);
355 return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr);
359 ionic_vlan_rx_add_vid(struct ionic_lif *lif, uint16_t vid)
361 struct ionic_admin_ctx ctx = {
362 .pending_work = true,
363 .cmd.rx_filter_add = {
364 .opcode = IONIC_CMD_RX_FILTER_ADD,
365 .match = IONIC_RX_FILTER_MATCH_VLAN,
371 err = ionic_adminq_post_wait(lif, &ctx);
375 IONIC_PRINT(INFO, "rx_filter add VLAN %d (id %d)", vid,
376 ctx.comp.rx_filter_add.filter_id);
378 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);
382 ionic_vlan_rx_kill_vid(struct ionic_lif *lif, uint16_t vid)
384 struct ionic_admin_ctx ctx = {
385 .pending_work = true,
386 .cmd.rx_filter_del = {
387 .opcode = IONIC_CMD_RX_FILTER_DEL,
390 struct ionic_rx_filter *f;
395 rte_spinlock_lock(&lif->rx_filters.lock);
397 f = ionic_rx_filter_by_vlan(lif, vid);
399 rte_spinlock_unlock(&lif->rx_filters.lock);
403 ctx.cmd.rx_filter_del.filter_id = f->filter_id;
404 ionic_rx_filter_free(f);
405 rte_spinlock_unlock(&lif->rx_filters.lock);
407 err = ionic_adminq_post_wait(lif, &ctx);
411 IONIC_PRINT(INFO, "rx_filter del VLAN %d (id %d)", vid,
412 ctx.cmd.rx_filter_del.filter_id);
418 ionic_dev_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id,
421 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
425 err = ionic_vlan_rx_add_vid(lif, vlan_id);
427 err = ionic_vlan_rx_kill_vid(lif, vlan_id);
433 ionic_lif_rx_mode(struct ionic_lif *lif, uint32_t rx_mode)
435 struct ionic_admin_ctx ctx = {
436 .pending_work = true,
438 .opcode = IONIC_CMD_RX_MODE_SET,
444 if (rx_mode & IONIC_RX_MODE_F_UNICAST)
445 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_UNICAST");
446 if (rx_mode & IONIC_RX_MODE_F_MULTICAST)
447 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_MULTICAST");
448 if (rx_mode & IONIC_RX_MODE_F_BROADCAST)
449 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_BROADCAST");
450 if (rx_mode & IONIC_RX_MODE_F_PROMISC)
451 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_PROMISC");
452 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI)
453 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_ALLMULTI");
455 err = ionic_adminq_post_wait(lif, &ctx);
457 IONIC_PRINT(ERR, "Failure setting RX mode");
461 ionic_set_rx_mode(struct ionic_lif *lif, uint32_t rx_mode)
463 if (lif->rx_mode != rx_mode) {
464 lif->rx_mode = rx_mode;
465 ionic_lif_rx_mode(lif, rx_mode);
470 ionic_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
472 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
473 uint32_t rx_mode = lif->rx_mode;
477 rx_mode |= IONIC_RX_MODE_F_PROMISC;
479 ionic_set_rx_mode(lif, rx_mode);
485 ionic_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
487 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
488 uint32_t rx_mode = lif->rx_mode;
490 rx_mode &= ~IONIC_RX_MODE_F_PROMISC;
492 ionic_set_rx_mode(lif, rx_mode);
498 ionic_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
500 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
501 uint32_t rx_mode = lif->rx_mode;
503 rx_mode |= IONIC_RX_MODE_F_ALLMULTI;
505 ionic_set_rx_mode(lif, rx_mode);
511 ionic_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
513 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
514 uint32_t rx_mode = lif->rx_mode;
516 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI;
518 ionic_set_rx_mode(lif, rx_mode);
524 ionic_lif_change_mtu(struct ionic_lif *lif, int new_mtu)
526 struct ionic_admin_ctx ctx = {
527 .pending_work = true,
529 .opcode = IONIC_CMD_LIF_SETATTR,
530 .attr = IONIC_LIF_ATTR_MTU,
536 err = ionic_adminq_post_wait(lif, &ctx);
544 ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr)
546 struct ionic_adapter *adapter = lif->adapter;
547 struct ionic_dev *idev = &adapter->idev;
551 * Note: interrupt handler is called for index = 0 only
552 * (we use interrupts for the notifyq only anyway,
553 * which has index = 0)
556 for (index = 0; index < adapter->nintrs; index++)
557 if (!adapter->intrs[index])
560 if (index == adapter->nintrs)
563 adapter->intrs[index] = true;
565 ionic_intr_init(idev, intr, index);
571 ionic_intr_free(struct ionic_lif *lif, struct ionic_intr_info *intr)
573 if (intr->index != IONIC_INTR_INDEX_NOT_ASSIGNED)
574 lif->adapter->intrs[intr->index] = false;
578 ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type,
580 const char *base, uint32_t flags,
583 uint32_t cq_desc_size,
584 uint32_t sg_desc_size,
585 struct ionic_qcq **qcq)
587 struct ionic_dev *idev = &lif->adapter->idev;
588 struct ionic_qcq *new;
589 uint32_t q_size, cq_size, sg_size, total_size;
590 void *q_base, *cq_base, *sg_base;
591 rte_iova_t q_base_pa = 0;
592 rte_iova_t cq_base_pa = 0;
593 rte_iova_t sg_base_pa = 0;
594 uint32_t socket_id = rte_socket_id();
599 q_size = num_descs * desc_size;
600 cq_size = num_descs * cq_desc_size;
601 sg_size = num_descs * sg_desc_size;
603 total_size = RTE_ALIGN(q_size, PAGE_SIZE) +
604 RTE_ALIGN(cq_size, PAGE_SIZE);
606 * Note: aligning q_size/cq_size is not enough due to cq_base address
607 * aligning as q_base could be not aligned to the page.
610 total_size += PAGE_SIZE;
612 if (flags & IONIC_QCQ_F_SG) {
613 total_size += RTE_ALIGN(sg_size, PAGE_SIZE);
614 total_size += PAGE_SIZE;
617 new = rte_zmalloc("ionic", sizeof(*new), 0);
619 IONIC_PRINT(ERR, "Cannot allocate queue structure");
626 new->q.info = rte_zmalloc("ionic", sizeof(*new->q.info) * num_descs, 0);
628 IONIC_PRINT(ERR, "Cannot allocate queue info");
634 err = ionic_q_init(lif, idev, &new->q, index, num_descs,
635 desc_size, sg_desc_size);
637 IONIC_PRINT(ERR, "Queue initialization failed");
641 if (flags & IONIC_QCQ_F_INTR) {
642 err = ionic_intr_alloc(lif, &new->intr);
646 ionic_intr_mask_assert(idev->intr_ctrl, new->intr.index,
647 IONIC_INTR_MASK_SET);
649 new->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED;
652 err = ionic_cq_init(lif, &new->cq, &new->intr,
653 num_descs, cq_desc_size);
655 IONIC_PRINT(ERR, "Completion queue initialization failed");
656 goto err_out_free_intr;
659 new->base_z = rte_eth_dma_zone_reserve(lif->eth_dev,
660 base /* name */, index /* queue_idx */,
661 total_size, IONIC_ALIGN, socket_id);
664 IONIC_PRINT(ERR, "Cannot reserve queue DMA memory");
666 goto err_out_free_intr;
669 new->base = new->base_z->addr;
670 new->base_pa = new->base_z->iova;
671 new->total_size = total_size;
674 q_base_pa = new->base_pa;
676 cq_base = (void *)RTE_ALIGN((uintptr_t)q_base + q_size, PAGE_SIZE);
677 cq_base_pa = RTE_ALIGN(q_base_pa + q_size, PAGE_SIZE);
679 if (flags & IONIC_QCQ_F_SG) {
680 sg_base = (void *)RTE_ALIGN((uintptr_t)cq_base + cq_size,
682 sg_base_pa = RTE_ALIGN(cq_base_pa + cq_size, PAGE_SIZE);
683 ionic_q_sg_map(&new->q, sg_base, sg_base_pa);
686 IONIC_PRINT(DEBUG, "Q-Base-PA = %#jx CQ-Base-PA = %#jx "
688 q_base_pa, cq_base_pa, sg_base_pa);
690 ionic_q_map(&new->q, q_base, q_base_pa);
691 ionic_cq_map(&new->cq, cq_base, cq_base_pa);
692 ionic_cq_bind(&new->cq, &new->q);
699 if (flags & IONIC_QCQ_F_INTR)
700 ionic_intr_free(lif, &new->intr);
706 ionic_qcq_free(struct ionic_qcq *qcq)
711 rte_memzone_free(qcq->base_z);
716 rte_free(qcq->q.info);
724 ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t nrxq_descs,
725 struct ionic_qcq **qcq)
730 flags = IONIC_QCQ_F_SG;
731 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, index, "rx", flags,
733 sizeof(struct ionic_rxq_desc),
734 sizeof(struct ionic_rxq_comp),
735 sizeof(struct ionic_rxq_sg_desc),
736 &lif->rxqcqs[index]);
740 *qcq = lif->rxqcqs[index];
746 ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t ntxq_descs,
747 struct ionic_qcq **qcq)
752 flags = IONIC_QCQ_F_SG;
753 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, index, "tx", flags,
755 sizeof(struct ionic_txq_desc),
756 sizeof(struct ionic_txq_comp),
757 sizeof(struct ionic_txq_sg_desc),
758 &lif->txqcqs[index]);
762 *qcq = lif->txqcqs[index];
768 ionic_admin_qcq_alloc(struct ionic_lif *lif)
774 err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags,
776 sizeof(struct ionic_admin_cmd),
777 sizeof(struct ionic_admin_comp),
787 ionic_notify_qcq_alloc(struct ionic_lif *lif)
792 flags = IONIC_QCQ_F_NOTIFYQ | IONIC_QCQ_F_INTR;
794 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notify",
796 IONIC_NOTIFYQ_LENGTH,
797 sizeof(struct ionic_notifyq_cmd),
798 sizeof(union ionic_notifyq_comp),
808 ionic_bus_map_dbpage(struct ionic_adapter *adapter, int page_num)
810 char *vaddr = adapter->bars[IONIC_PCI_BAR_DBELL].vaddr;
812 if (adapter->num_bars <= IONIC_PCI_BAR_DBELL)
815 return (void *)&vaddr[page_num << PAGE_SHIFT];
819 ionic_lif_alloc(struct ionic_lif *lif)
821 struct ionic_adapter *adapter = lif->adapter;
822 uint32_t socket_id = rte_socket_id();
826 * lif->name was zeroed on allocation.
827 * Copy (sizeof() - 1) bytes to ensure that it is NULL terminated.
829 memcpy(lif->name, lif->eth_dev->data->name, sizeof(lif->name) - 1);
831 IONIC_PRINT(DEBUG, "LIF: %s", lif->name);
833 IONIC_PRINT(DEBUG, "Allocating Lif Info");
835 rte_spinlock_init(&lif->adminq_lock);
836 rte_spinlock_init(&lif->adminq_service_lock);
838 lif->kern_dbpage = ionic_bus_map_dbpage(adapter, 0);
839 if (!lif->kern_dbpage) {
840 IONIC_PRINT(ERR, "Cannot map dbpage, aborting");
844 lif->txqcqs = rte_zmalloc("ionic", sizeof(*lif->txqcqs) *
845 adapter->max_ntxqs_per_lif, 0);
848 IONIC_PRINT(ERR, "Cannot allocate tx queues array");
852 lif->rxqcqs = rte_zmalloc("ionic", sizeof(*lif->rxqcqs) *
853 adapter->max_nrxqs_per_lif, 0);
856 IONIC_PRINT(ERR, "Cannot allocate rx queues array");
860 IONIC_PRINT(DEBUG, "Allocating Notify Queue");
862 err = ionic_notify_qcq_alloc(lif);
864 IONIC_PRINT(ERR, "Cannot allocate notify queue");
868 IONIC_PRINT(DEBUG, "Allocating Admin Queue");
870 err = ionic_admin_qcq_alloc(lif);
872 IONIC_PRINT(ERR, "Cannot allocate admin queue");
876 IONIC_PRINT(DEBUG, "Allocating Lif Info");
878 lif->info_sz = RTE_ALIGN(sizeof(*lif->info), PAGE_SIZE);
880 lif->info_z = rte_eth_dma_zone_reserve(lif->eth_dev,
881 "lif_info", 0 /* queue_idx*/,
882 lif->info_sz, IONIC_ALIGN, socket_id);
884 IONIC_PRINT(ERR, "Cannot allocate lif info memory");
888 lif->info = lif->info_z->addr;
889 lif->info_pa = lif->info_z->iova;
895 ionic_lif_free(struct ionic_lif *lif)
897 if (lif->notifyqcq) {
898 ionic_qcq_free(lif->notifyqcq);
899 lif->notifyqcq = NULL;
903 ionic_qcq_free(lif->adminqcq);
904 lif->adminqcq = NULL;
908 rte_free(lif->txqcqs);
913 rte_free(lif->rxqcqs);
918 rte_memzone_free(lif->info_z);
924 ionic_lif_free_queues(struct ionic_lif *lif)
928 for (i = 0; i < lif->ntxqcqs; i++) {
929 ionic_dev_tx_queue_release(lif->eth_dev->data->tx_queues[i]);
930 lif->eth_dev->data->tx_queues[i] = NULL;
932 for (i = 0; i < lif->nrxqcqs; i++) {
933 ionic_dev_rx_queue_release(lif->eth_dev->data->rx_queues[i]);
934 lif->eth_dev->data->rx_queues[i] = NULL;
939 ionic_lif_rss_config(struct ionic_lif *lif,
940 const uint16_t types, const uint8_t *key, const uint32_t *indir)
942 struct ionic_admin_ctx ctx = {
943 .pending_work = true,
945 .opcode = IONIC_CMD_LIF_SETATTR,
946 .attr = IONIC_LIF_ATTR_RSS,
948 .rss.addr = lif->rss_ind_tbl_pa,
955 lif->rss_types = types;
958 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE);
961 for (i = 0; i < lif->adapter->ident.lif.eth.rss_ind_tbl_sz; i++)
962 lif->rss_ind_tbl[i] = indir[i];
964 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key,
965 IONIC_RSS_HASH_KEY_SIZE);
967 return ionic_adminq_post_wait(lif, &ctx);
971 ionic_lif_rss_setup(struct ionic_lif *lif)
973 static const uint8_t toeplitz_symmetric_key[] = {
974 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
975 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
976 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
977 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
978 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
981 uint16_t tbl_sz = lif->adapter->ident.lif.eth.rss_ind_tbl_sz;
985 if (!lif->rss_ind_tbl_z) {
986 lif->rss_ind_tbl_z = rte_eth_dma_zone_reserve(lif->eth_dev,
987 "rss_ind_tbl", 0 /* queue_idx */,
988 sizeof(*lif->rss_ind_tbl) * tbl_sz,
989 IONIC_ALIGN, rte_socket_id());
990 if (!lif->rss_ind_tbl_z) {
991 IONIC_PRINT(ERR, "OOM");
995 lif->rss_ind_tbl = lif->rss_ind_tbl_z->addr;
996 lif->rss_ind_tbl_pa = lif->rss_ind_tbl_z->iova;
999 if (lif->rss_ind_tbl_nrxqcqs != lif->nrxqcqs) {
1000 lif->rss_ind_tbl_nrxqcqs = lif->nrxqcqs;
1002 /* Fill indirection table with 'default' values */
1003 for (i = 0; i < tbl_sz; i++)
1004 lif->rss_ind_tbl[i] = i % lif->nrxqcqs;
1007 return ionic_lif_rss_config(lif, IONIC_RSS_OFFLOAD_ALL,
1008 toeplitz_symmetric_key, NULL);
1012 ionic_lif_rss_teardown(struct ionic_lif *lif)
1014 if (!lif->rss_ind_tbl)
1017 if (lif->rss_ind_tbl_z) {
1018 /* Disable RSS on the NIC */
1019 ionic_lif_rss_config(lif, 0x0, NULL, NULL);
1021 lif->rss_ind_tbl = NULL;
1022 lif->rss_ind_tbl_pa = 0;
1023 rte_memzone_free(lif->rss_ind_tbl_z);
1024 lif->rss_ind_tbl_z = NULL;
1029 ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq)
1031 struct ionic_dev *idev = &lif->adapter->idev;
1033 if (!(qcq->flags & IONIC_QCQ_F_INITED))
1036 if (qcq->flags & IONIC_QCQ_F_INTR)
1037 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1038 IONIC_INTR_MASK_SET);
1040 qcq->flags &= ~IONIC_QCQ_F_INITED;
1044 ionic_lif_txq_deinit(struct ionic_qcq *qcq)
1046 ionic_lif_qcq_deinit(qcq->lif, qcq);
1050 ionic_lif_rxq_deinit(struct ionic_qcq *qcq)
1052 ionic_lif_qcq_deinit(qcq->lif, qcq);
1056 ionic_adminq_service(struct ionic_cq *cq, uint32_t cq_desc_index,
1057 void *cb_arg __rte_unused)
1059 struct ionic_admin_comp *cq_desc_base = cq->base;
1060 struct ionic_admin_comp *cq_desc = &cq_desc_base[cq_desc_index];
1062 if (!color_match(cq_desc->color, cq->done_color))
1065 ionic_q_service(cq->bound_q, cq_desc_index, cq_desc->comp_index, NULL);
1070 /* This acts like ionic_napi */
1072 ionic_qcq_service(struct ionic_qcq *qcq, int budget, ionic_cq_cb cb,
1075 struct ionic_cq *cq = &qcq->cq;
1078 work_done = ionic_cq_service(cq, budget, cb, cb_arg);
1084 ionic_link_status_check(struct ionic_lif *lif)
1086 struct ionic_adapter *adapter = lif->adapter;
1089 lif->state &= ~IONIC_LIF_F_LINK_CHECK_NEEDED;
1094 link_up = (lif->info->status.link_status == IONIC_PORT_OPER_STATUS_UP);
1096 if ((link_up && adapter->link_up) ||
1097 (!link_up && !adapter->link_up))
1101 IONIC_PRINT(DEBUG, "Link up - %d Gbps",
1102 lif->info->status.link_speed);
1103 adapter->link_speed = lif->info->status.link_speed;
1105 IONIC_PRINT(DEBUG, "Link down");
1108 adapter->link_up = link_up;
1112 ionic_notifyq_cb(struct ionic_cq *cq, uint32_t cq_desc_index, void *cb_arg)
1114 union ionic_notifyq_comp *cq_desc_base = cq->base;
1115 union ionic_notifyq_comp *cq_desc = &cq_desc_base[cq_desc_index];
1116 struct ionic_lif *lif = cb_arg;
1118 IONIC_PRINT(DEBUG, "Notifyq callback eid = %jd ecode = %d",
1119 cq_desc->event.eid, cq_desc->event.ecode);
1121 /* Have we run out of new completions to process? */
1122 if (!(cq_desc->event.eid > lif->last_eid))
1125 lif->last_eid = cq_desc->event.eid;
1127 switch (cq_desc->event.ecode) {
1128 case IONIC_EVENT_LINK_CHANGE:
1130 "Notifyq IONIC_EVENT_LINK_CHANGE eid=%jd link_status=%d link_speed=%d",
1132 cq_desc->link_change.link_status,
1133 cq_desc->link_change.link_speed);
1135 lif->state |= IONIC_LIF_F_LINK_CHECK_NEEDED;
1139 IONIC_PRINT(WARNING, "Notifyq bad event ecode=%d eid=%jd",
1140 cq_desc->event.ecode, cq_desc->event.eid);
1148 ionic_notifyq_handler(struct ionic_lif *lif, int budget)
1150 struct ionic_dev *idev = &lif->adapter->idev;
1151 struct ionic_qcq *qcq = lif->notifyqcq;
1154 if (!(qcq->flags & IONIC_QCQ_F_INITED)) {
1155 IONIC_PRINT(DEBUG, "Notifyq not yet initialized");
1159 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1160 IONIC_INTR_MASK_SET);
1162 work_done = ionic_qcq_service(qcq, budget, ionic_notifyq_cb, lif);
1164 if (lif->state & IONIC_LIF_F_LINK_CHECK_NEEDED)
1165 ionic_link_status_check(lif);
1167 ionic_intr_credits(idev->intr_ctrl, qcq->intr.index,
1168 work_done, IONIC_INTR_CRED_RESET_COALESCE);
1170 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1171 IONIC_INTR_MASK_CLEAR);
1177 ionic_lif_adminq_init(struct ionic_lif *lif)
1179 struct ionic_dev *idev = &lif->adapter->idev;
1180 struct ionic_qcq *qcq = lif->adminqcq;
1181 struct ionic_queue *q = &qcq->q;
1182 struct ionic_q_init_comp comp;
1185 ionic_dev_cmd_adminq_init(idev, qcq, qcq->intr.index);
1186 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1190 ionic_dev_cmd_comp(idev, &comp);
1192 q->hw_type = comp.hw_type;
1193 q->hw_index = comp.hw_index;
1194 q->db = ionic_db_map(lif, q);
1196 IONIC_PRINT(DEBUG, "adminq->hw_type %d", q->hw_type);
1197 IONIC_PRINT(DEBUG, "adminq->hw_index %d", q->hw_index);
1198 IONIC_PRINT(DEBUG, "adminq->db %p", q->db);
1200 if (qcq->flags & IONIC_QCQ_F_INTR)
1201 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1202 IONIC_INTR_MASK_CLEAR);
1204 qcq->flags |= IONIC_QCQ_F_INITED;
1210 ionic_lif_notifyq_init(struct ionic_lif *lif)
1212 struct ionic_dev *idev = &lif->adapter->idev;
1213 struct ionic_qcq *qcq = lif->notifyqcq;
1214 struct ionic_queue *q = &qcq->q;
1217 struct ionic_admin_ctx ctx = {
1218 .pending_work = true,
1220 .opcode = IONIC_CMD_Q_INIT,
1223 .flags = (IONIC_QINIT_F_IRQ | IONIC_QINIT_F_ENA),
1224 .intr_index = qcq->intr.index,
1225 .ring_size = rte_log2_u32(q->num_descs),
1226 .ring_base = q->base_pa,
1230 IONIC_PRINT(DEBUG, "notifyq_init.index %d",
1231 ctx.cmd.q_init.index);
1232 IONIC_PRINT(DEBUG, "notifyq_init.ring_base 0x%" PRIx64 "",
1233 ctx.cmd.q_init.ring_base);
1234 IONIC_PRINT(DEBUG, "notifyq_init.ring_size %d",
1235 ctx.cmd.q_init.ring_size);
1236 IONIC_PRINT(DEBUG, "notifyq_init.ver %u", ctx.cmd.q_init.ver);
1238 err = ionic_adminq_post_wait(lif, &ctx);
1242 q->hw_type = ctx.comp.q_init.hw_type;
1243 q->hw_index = ctx.comp.q_init.hw_index;
1246 IONIC_PRINT(DEBUG, "notifyq->hw_type %d", q->hw_type);
1247 IONIC_PRINT(DEBUG, "notifyq->hw_index %d", q->hw_index);
1248 IONIC_PRINT(DEBUG, "notifyq->db %p", q->db);
1250 if (qcq->flags & IONIC_QCQ_F_INTR)
1251 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1252 IONIC_INTR_MASK_CLEAR);
1254 qcq->flags |= IONIC_QCQ_F_INITED;
1260 ionic_lif_set_features(struct ionic_lif *lif)
1262 struct ionic_admin_ctx ctx = {
1263 .pending_work = true,
1264 .cmd.lif_setattr = {
1265 .opcode = IONIC_CMD_LIF_SETATTR,
1266 .attr = IONIC_LIF_ATTR_FEATURES,
1267 .features = lif->features,
1272 err = ionic_adminq_post_wait(lif, &ctx);
1276 lif->hw_features = (ctx.cmd.lif_setattr.features &
1277 ctx.comp.lif_setattr.features);
1279 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
1280 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_TX_TAG");
1281 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
1282 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_STRIP");
1283 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
1284 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_FILTER");
1285 if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
1286 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_HASH");
1287 if (lif->hw_features & IONIC_ETH_HW_TX_SG)
1288 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_SG");
1289 if (lif->hw_features & IONIC_ETH_HW_RX_SG)
1290 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_SG");
1291 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
1292 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_CSUM");
1293 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
1294 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_CSUM");
1295 if (lif->hw_features & IONIC_ETH_HW_TSO)
1296 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO");
1297 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
1298 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPV6");
1299 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
1300 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_ECN");
1301 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
1302 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE");
1303 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
1304 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE_CSUM");
1305 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
1306 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP4");
1307 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
1308 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP6");
1309 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
1310 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP");
1311 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
1312 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP_CSUM");
1318 ionic_lif_txq_init(struct ionic_qcq *qcq)
1320 struct ionic_queue *q = &qcq->q;
1321 struct ionic_lif *lif = qcq->lif;
1322 struct ionic_cq *cq = &qcq->cq;
1323 struct ionic_admin_ctx ctx = {
1324 .pending_work = true,
1326 .opcode = IONIC_CMD_Q_INIT,
1329 .flags = IONIC_QINIT_F_SG,
1330 .intr_index = cq->bound_intr->index,
1331 .ring_size = rte_log2_u32(q->num_descs),
1332 .ring_base = q->base_pa,
1333 .cq_ring_base = cq->base_pa,
1334 .sg_ring_base = q->sg_base_pa,
1339 IONIC_PRINT(DEBUG, "txq_init.index %d", ctx.cmd.q_init.index);
1340 IONIC_PRINT(DEBUG, "txq_init.ring_base 0x%" PRIx64 "",
1341 ctx.cmd.q_init.ring_base);
1342 IONIC_PRINT(DEBUG, "txq_init.ring_size %d",
1343 ctx.cmd.q_init.ring_size);
1344 IONIC_PRINT(DEBUG, "txq_init.ver %u", ctx.cmd.q_init.ver);
1346 err = ionic_adminq_post_wait(qcq->lif, &ctx);
1350 q->hw_type = ctx.comp.q_init.hw_type;
1351 q->hw_index = ctx.comp.q_init.hw_index;
1352 q->db = ionic_db_map(lif, q);
1354 IONIC_PRINT(DEBUG, "txq->hw_type %d", q->hw_type);
1355 IONIC_PRINT(DEBUG, "txq->hw_index %d", q->hw_index);
1356 IONIC_PRINT(DEBUG, "txq->db %p", q->db);
1358 qcq->flags |= IONIC_QCQ_F_INITED;
1364 ionic_lif_rxq_init(struct ionic_qcq *qcq)
1366 struct ionic_queue *q = &qcq->q;
1367 struct ionic_lif *lif = qcq->lif;
1368 struct ionic_cq *cq = &qcq->cq;
1369 struct ionic_admin_ctx ctx = {
1370 .pending_work = true,
1372 .opcode = IONIC_CMD_Q_INIT,
1375 .flags = IONIC_QINIT_F_SG,
1376 .intr_index = cq->bound_intr->index,
1377 .ring_size = rte_log2_u32(q->num_descs),
1378 .ring_base = q->base_pa,
1379 .cq_ring_base = cq->base_pa,
1380 .sg_ring_base = q->sg_base_pa,
1385 IONIC_PRINT(DEBUG, "rxq_init.index %d", ctx.cmd.q_init.index);
1386 IONIC_PRINT(DEBUG, "rxq_init.ring_base 0x%" PRIx64 "",
1387 ctx.cmd.q_init.ring_base);
1388 IONIC_PRINT(DEBUG, "rxq_init.ring_size %d",
1389 ctx.cmd.q_init.ring_size);
1390 IONIC_PRINT(DEBUG, "rxq_init.ver %u", ctx.cmd.q_init.ver);
1392 err = ionic_adminq_post_wait(qcq->lif, &ctx);
1396 q->hw_type = ctx.comp.q_init.hw_type;
1397 q->hw_index = ctx.comp.q_init.hw_index;
1398 q->db = ionic_db_map(lif, q);
1400 qcq->flags |= IONIC_QCQ_F_INITED;
1402 IONIC_PRINT(DEBUG, "rxq->hw_type %d", q->hw_type);
1403 IONIC_PRINT(DEBUG, "rxq->hw_index %d", q->hw_index);
1404 IONIC_PRINT(DEBUG, "rxq->db %p", q->db);
1410 ionic_station_set(struct ionic_lif *lif)
1412 struct ionic_admin_ctx ctx = {
1413 .pending_work = true,
1414 .cmd.lif_getattr = {
1415 .opcode = IONIC_CMD_LIF_GETATTR,
1416 .attr = IONIC_LIF_ATTR_MAC,
1423 err = ionic_adminq_post_wait(lif, &ctx);
1427 if (!rte_is_zero_ether_addr((struct rte_ether_addr *)
1429 IONIC_PRINT(INFO, "deleting station MAC addr");
1431 ionic_lif_addr_del(lif, lif->mac_addr);
1434 memcpy(lif->mac_addr, ctx.comp.lif_getattr.mac, RTE_ETHER_ADDR_LEN);
1436 if (rte_is_zero_ether_addr((struct rte_ether_addr *)lif->mac_addr)) {
1437 IONIC_PRINT(NOTICE, "empty MAC addr (VF?)");
1441 IONIC_PRINT(DEBUG, "adding station MAC addr");
1443 ionic_lif_addr_add(lif, lif->mac_addr);
1449 ionic_lif_set_name(struct ionic_lif *lif)
1451 struct ionic_admin_ctx ctx = {
1452 .pending_work = true,
1453 .cmd.lif_setattr = {
1454 .opcode = IONIC_CMD_LIF_SETATTR,
1455 .attr = IONIC_LIF_ATTR_NAME,
1459 memcpy(ctx.cmd.lif_setattr.name, lif->name,
1460 sizeof(ctx.cmd.lif_setattr.name) - 1);
1462 ionic_adminq_post_wait(lif, &ctx);
1466 ionic_lif_init(struct ionic_lif *lif)
1468 struct ionic_dev *idev = &lif->adapter->idev;
1469 struct ionic_q_init_comp comp;
1472 memset(&lif->stats_base, 0, sizeof(lif->stats_base));
1474 ionic_dev_cmd_lif_init(idev, lif->info_pa);
1475 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1476 ionic_dev_cmd_comp(idev, &comp);
1480 lif->hw_index = comp.hw_index;
1482 err = ionic_lif_adminq_init(lif);
1486 err = ionic_lif_notifyq_init(lif);
1488 goto err_out_adminq_deinit;
1491 IONIC_ETH_HW_VLAN_TX_TAG
1492 | IONIC_ETH_HW_VLAN_RX_STRIP
1493 | IONIC_ETH_HW_VLAN_RX_FILTER
1494 | IONIC_ETH_HW_RX_HASH
1495 | IONIC_ETH_HW_TX_SG
1496 | IONIC_ETH_HW_RX_SG
1497 | IONIC_ETH_HW_TX_CSUM
1498 | IONIC_ETH_HW_RX_CSUM
1500 | IONIC_ETH_HW_TSO_IPV6
1501 | IONIC_ETH_HW_TSO_ECN;
1503 err = ionic_lif_set_features(lif);
1505 goto err_out_notifyq_deinit;
1507 err = ionic_rx_filters_init(lif);
1509 goto err_out_notifyq_deinit;
1511 err = ionic_station_set(lif);
1513 goto err_out_rx_filter_deinit;
1515 ionic_lif_set_name(lif);
1517 lif->state |= IONIC_LIF_F_INITED;
1521 err_out_rx_filter_deinit:
1522 ionic_rx_filters_deinit(lif);
1524 err_out_notifyq_deinit:
1525 ionic_lif_qcq_deinit(lif, lif->notifyqcq);
1527 err_out_adminq_deinit:
1528 ionic_lif_qcq_deinit(lif, lif->adminqcq);
1534 ionic_lif_deinit(struct ionic_lif *lif)
1536 if (!(lif->state & IONIC_LIF_F_INITED))
1539 ionic_rx_filters_deinit(lif);
1540 ionic_lif_rss_teardown(lif);
1541 ionic_lif_qcq_deinit(lif, lif->notifyqcq);
1542 ionic_lif_qcq_deinit(lif, lif->adminqcq);
1544 lif->state &= ~IONIC_LIF_F_INITED;
1548 ionic_lif_configure(struct ionic_lif *lif)
1550 struct ionic_identity *ident = &lif->adapter->ident;
1551 uint32_t ntxqs_per_lif =
1552 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ];
1553 uint32_t nrxqs_per_lif =
1554 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ];
1555 uint32_t nrxqs = lif->eth_dev->data->nb_rx_queues;
1556 uint32_t ntxqs = lif->eth_dev->data->nb_tx_queues;
1558 lif->port_id = lif->eth_dev->data->port_id;
1560 IONIC_PRINT(DEBUG, "Configuring LIF on port %u",
1564 nrxqs_per_lif = RTE_MIN(nrxqs_per_lif, nrxqs);
1567 ntxqs_per_lif = RTE_MIN(ntxqs_per_lif, ntxqs);
1569 lif->nrxqcqs = nrxqs_per_lif;
1570 lif->ntxqcqs = ntxqs_per_lif;
1576 ionic_lif_start(struct ionic_lif *lif)
1582 err = ionic_lif_rss_setup(lif);
1586 if (!lif->rx_mode) {
1587 IONIC_PRINT(DEBUG, "Setting RX mode on %s",
1590 rx_mode = IONIC_RX_MODE_F_UNICAST;
1591 rx_mode |= IONIC_RX_MODE_F_MULTICAST;
1592 rx_mode |= IONIC_RX_MODE_F_BROADCAST;
1594 ionic_set_rx_mode(lif, rx_mode);
1597 IONIC_PRINT(DEBUG, "Starting %u RX queues and %u TX queues "
1599 lif->nrxqcqs, lif->ntxqcqs, lif->port_id);
1601 for (i = 0; i < lif->nrxqcqs; i++) {
1602 struct ionic_qcq *rxq = lif->rxqcqs[i];
1603 if (!(rxq->flags & IONIC_QCQ_F_DEFERRED)) {
1604 err = ionic_dev_rx_queue_start(lif->eth_dev, i);
1611 for (i = 0; i < lif->ntxqcqs; i++) {
1612 struct ionic_qcq *txq = lif->txqcqs[i];
1613 if (!(txq->flags & IONIC_QCQ_F_DEFERRED)) {
1614 err = ionic_dev_tx_queue_start(lif->eth_dev, i);
1621 ionic_link_status_check(lif);
1623 /* Carrier ON here */
1629 ionic_lif_identify(struct ionic_adapter *adapter)
1631 struct ionic_dev *idev = &adapter->idev;
1632 struct ionic_identity *ident = &adapter->ident;
1635 unsigned int lif_words = sizeof(ident->lif.words) /
1636 sizeof(ident->lif.words[0]);
1637 unsigned int cmd_words = sizeof(idev->dev_cmd->data) /
1638 sizeof(idev->dev_cmd->data[0]);
1639 unsigned int nwords;
1641 ionic_dev_cmd_lif_identify(idev, IONIC_LIF_TYPE_CLASSIC,
1642 IONIC_IDENTITY_VERSION_1);
1643 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1647 nwords = RTE_MIN(lif_words, cmd_words);
1648 for (i = 0; i < nwords; i++)
1649 ident->lif.words[i] = ioread32(&idev->dev_cmd->data[i]);
1651 IONIC_PRINT(INFO, "capabilities 0x%" PRIx64 " ",
1652 ident->lif.capabilities);
1654 IONIC_PRINT(INFO, "eth.max_ucast_filters 0x%" PRIx32 " ",
1655 ident->lif.eth.max_ucast_filters);
1656 IONIC_PRINT(INFO, "eth.max_mcast_filters 0x%" PRIx32 " ",
1657 ident->lif.eth.max_mcast_filters);
1659 IONIC_PRINT(INFO, "eth.features 0x%" PRIx64 " ",
1660 ident->lif.eth.config.features);
1661 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_ADMINQ] 0x%" PRIx32 " ",
1662 ident->lif.eth.config.queue_count[IONIC_QTYPE_ADMINQ]);
1663 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] 0x%" PRIx32 " ",
1664 ident->lif.eth.config.queue_count[IONIC_QTYPE_NOTIFYQ]);
1665 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_RXQ] 0x%" PRIx32 " ",
1666 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ]);
1667 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_TXQ] 0x%" PRIx32 " ",
1668 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ]);
1674 ionic_lifs_size(struct ionic_adapter *adapter)
1676 struct ionic_identity *ident = &adapter->ident;
1677 uint32_t nintrs, dev_nintrs = ident->dev.nintrs;
1679 adapter->max_ntxqs_per_lif =
1680 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ];
1681 adapter->max_nrxqs_per_lif =
1682 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ];
1684 nintrs = 1 /* notifyq */;
1686 if (nintrs > dev_nintrs) {
1688 "At most %d intr supported, minimum req'd is %u",
1689 dev_nintrs, nintrs);
1693 adapter->nintrs = nintrs;