drivers/net/ionic/ionic_lif.c

   1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
   2  * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
   3  */
   4
   5 #include <rte_malloc.h>
   6 #include <rte_ethdev_driver.h>
   7
   8 #include "ionic.h"
   9 #include "ionic_logs.h"
  10 #include "ionic_lif.h"
  11 #include "ionic_ethdev.h"
  12 #include "ionic_rx_filter.h"
  13 #include "ionic_rxtx.h"
  14
  15 static int ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr);
  16 static int ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr);
  17
  18 int
  19 ionic_qcq_enable(struct ionic_qcq *qcq)
  20 {
  21         struct ionic_queue *q = &qcq->q;
  22         struct ionic_lif *lif = q->lif;
  23         struct ionic_dev *idev = &lif->adapter->idev;
  24         struct ionic_admin_ctx ctx = {
  25                 .pending_work = true,
  26                 .cmd.q_control = {
  27                         .opcode = IONIC_CMD_Q_CONTROL,
  28                         .lif_index = lif->index,
  29                         .type = q->type,
  30                         .index = q->index,
  31                         .oper = IONIC_Q_ENABLE,
  32                 },
  33         };
  34
  35         if (qcq->flags & IONIC_QCQ_F_INTR) {
  36                 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
  37                         IONIC_INTR_MASK_CLEAR);
  38         }
  39
  40         return ionic_adminq_post_wait(lif, &ctx);
  41 }
  42
  43 int
  44 ionic_qcq_disable(struct ionic_qcq *qcq)
  45 {
  46         struct ionic_queue *q = &qcq->q;
  47         struct ionic_lif *lif = q->lif;
  48         struct ionic_dev *idev = &lif->adapter->idev;
  49         struct ionic_admin_ctx ctx = {
  50                 .pending_work = true,
  51                 .cmd.q_control = {
  52                         .opcode = IONIC_CMD_Q_CONTROL,
  53                         .lif_index = lif->index,
  54                         .type = q->type,
  55                         .index = q->index,
  56                         .oper = IONIC_Q_DISABLE,
  57                 },
  58         };
  59
  60         if (qcq->flags & IONIC_QCQ_F_INTR) {
  61                 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
  62                         IONIC_INTR_MASK_SET);
  63         }
  64
  65         return ionic_adminq_post_wait(lif, &ctx);
  66 }
  67
  68 int
  69 ionic_lif_stop(struct ionic_lif *lif __rte_unused)
  70 {
  71         /* Carrier OFF here */
  72
  73         return 0;
  74 }
  75
  76 void
  77 ionic_lif_reset(struct ionic_lif *lif)
  78 {
  79         struct ionic_dev *idev = &lif->adapter->idev;
  80
  81         IONIC_PRINT_CALL();
  82
  83         ionic_dev_cmd_lif_reset(idev, lif->index);
  84         ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
  85 }
  86
  87 static int
  88 ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr)
  89 {
  90         struct ionic_admin_ctx ctx = {
  91                 .pending_work = true,
  92                 .cmd.rx_filter_add = {
  93                         .opcode = IONIC_CMD_RX_FILTER_ADD,
  94                         .match = IONIC_RX_FILTER_MATCH_MAC,
  95                 },
  96         };
  97         int err;
  98
  99         memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, RTE_ETHER_ADDR_LEN);
 100
 101         err = ionic_adminq_post_wait(lif, &ctx);
 102         if (err)
 103                 return err;
 104
 105         IONIC_PRINT(INFO, "rx_filter add (id %d)",
 106                 ctx.comp.rx_filter_add.filter_id);
 107
 108         return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);
 109 }
 110
 111 static int
 112 ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr)
 113 {
 114         struct ionic_admin_ctx ctx = {
 115                 .pending_work = true,
 116                 .cmd.rx_filter_del = {
 117                         .opcode = IONIC_CMD_RX_FILTER_DEL,
 118                 },
 119         };
 120         struct ionic_rx_filter *f;
 121         int err;
 122
 123         IONIC_PRINT_CALL();
 124
 125         rte_spinlock_lock(&lif->rx_filters.lock);
 126
 127         f = ionic_rx_filter_by_addr(lif, addr);
 128         if (!f) {
 129                 rte_spinlock_unlock(&lif->rx_filters.lock);
 130                 return -ENOENT;
 131         }
 132
 133         ctx.cmd.rx_filter_del.filter_id = f->filter_id;
 134         ionic_rx_filter_free(f);
 135
 136         rte_spinlock_unlock(&lif->rx_filters.lock);
 137
 138         err = ionic_adminq_post_wait(lif, &ctx);
 139         if (err)
 140                 return err;
 141
 142         IONIC_PRINT(INFO, "rx_filter del (id %d)",
 143                 ctx.cmd.rx_filter_del.filter_id);
 144
 145         return 0;
 146 }
 147
 148 int
 149 ionic_dev_add_mac(struct rte_eth_dev *eth_dev,
 150                 struct rte_ether_addr *mac_addr,
 151                 uint32_t index __rte_unused, uint32_t pool __rte_unused)
 152 {
 153         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 154
 155         IONIC_PRINT_CALL();
 156
 157         return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr);
 158 }
 159
 160 void
 161 ionic_dev_remove_mac(struct rte_eth_dev *eth_dev, uint32_t index __rte_unused)
 162 {
 163         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 164         struct ionic_adapter *adapter = lif->adapter;
 165
 166         IONIC_PRINT_CALL();
 167
 168         if (index >= adapter->max_mac_addrs) {
 169                 IONIC_PRINT(WARNING,
 170                         "Index %u is above MAC filter limit %u",
 171                         index, adapter->max_mac_addrs);
 172                 return;
 173         }
 174
 175         if (!rte_is_valid_assigned_ether_addr(&eth_dev->data->mac_addrs[index]))
 176                 return;
 177
 178         ionic_lif_addr_del(lif, (const uint8_t *)
 179                 &eth_dev->data->mac_addrs[index]);
 180 }
 181
 182 int
 183 ionic_dev_set_mac(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr)
 184 {
 185         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 186
 187         IONIC_PRINT_CALL();
 188
 189         if (mac_addr == NULL) {
 190                 IONIC_PRINT(NOTICE, "New mac is null");
 191                 return -1;
 192         }
 193
 194         if (!rte_is_zero_ether_addr((struct rte_ether_addr *)lif->mac_addr)) {
 195                 IONIC_PRINT(INFO, "Deleting mac addr %pM",
 196                         lif->mac_addr);
 197                 ionic_lif_addr_del(lif, lif->mac_addr);
 198                 memset(lif->mac_addr, 0, RTE_ETHER_ADDR_LEN);
 199         }
 200
 201         IONIC_PRINT(INFO, "Updating mac addr");
 202
 203         rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)lif->mac_addr);
 204
 205         return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr);
 206 }
 207
 208 static int
 209 ionic_vlan_rx_add_vid(struct ionic_lif *lif, uint16_t vid)
 210 {
 211         struct ionic_admin_ctx ctx = {
 212                 .pending_work = true,
 213                 .cmd.rx_filter_add = {
 214                         .opcode = IONIC_CMD_RX_FILTER_ADD,
 215                         .match = IONIC_RX_FILTER_MATCH_VLAN,
 216                         .vlan.vlan = vid,
 217                 },
 218         };
 219         int err;
 220
 221         err = ionic_adminq_post_wait(lif, &ctx);
 222         if (err)
 223                 return err;
 224
 225         IONIC_PRINT(INFO, "rx_filter add VLAN %d (id %d)", vid,
 226                 ctx.comp.rx_filter_add.filter_id);
 227
 228         return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);
 229 }
 230
 231 static int
 232 ionic_vlan_rx_kill_vid(struct ionic_lif *lif, uint16_t vid)
 233 {
 234         struct ionic_admin_ctx ctx = {
 235                 .pending_work = true,
 236                 .cmd.rx_filter_del = {
 237                         .opcode = IONIC_CMD_RX_FILTER_DEL,
 238                 },
 239         };
 240         struct ionic_rx_filter *f;
 241         int err;
 242
 243         IONIC_PRINT_CALL();
 244
 245         rte_spinlock_lock(&lif->rx_filters.lock);
 246
 247         f = ionic_rx_filter_by_vlan(lif, vid);
 248         if (!f) {
 249                 rte_spinlock_unlock(&lif->rx_filters.lock);
 250                 return -ENOENT;
 251         }
 252
 253         ctx.cmd.rx_filter_del.filter_id = f->filter_id;
 254         ionic_rx_filter_free(f);
 255         rte_spinlock_unlock(&lif->rx_filters.lock);
 256
 257         err = ionic_adminq_post_wait(lif, &ctx);
 258         if (err)
 259                 return err;
 260
 261         IONIC_PRINT(INFO, "rx_filter del VLAN %d (id %d)", vid,
 262                 ctx.cmd.rx_filter_del.filter_id);
 263
 264         return 0;
 265 }
 266
 267 int
 268 ionic_dev_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id,
 269                 int on)
 270 {
 271         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 272         int err;
 273
 274         if (on)
 275                 err = ionic_vlan_rx_add_vid(lif, vlan_id);
 276         else
 277                 err = ionic_vlan_rx_kill_vid(lif, vlan_id);
 278
 279         return err;
 280 }
 281
 282 static void
 283 ionic_lif_rx_mode(struct ionic_lif *lif, uint32_t rx_mode)
 284 {
 285         struct ionic_admin_ctx ctx = {
 286                 .pending_work = true,
 287                 .cmd.rx_mode_set = {
 288                         .opcode = IONIC_CMD_RX_MODE_SET,
 289                         .lif_index = lif->index,
 290                         .rx_mode = rx_mode,
 291                 },
 292         };
 293         int err;
 294
 295         if (rx_mode & IONIC_RX_MODE_F_UNICAST)
 296                 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_UNICAST");
 297         if (rx_mode & IONIC_RX_MODE_F_MULTICAST)
 298                 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_MULTICAST");
 299         if (rx_mode & IONIC_RX_MODE_F_BROADCAST)
 300                 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_BROADCAST");
 301         if (rx_mode & IONIC_RX_MODE_F_PROMISC)
 302                 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_PROMISC");
 303         if (rx_mode & IONIC_RX_MODE_F_ALLMULTI)
 304                 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_ALLMULTI");
 305
 306         err = ionic_adminq_post_wait(lif, &ctx);
 307         if (err)
 308                 IONIC_PRINT(ERR, "Failure setting RX mode");
 309 }
 310
 311 static void
 312 ionic_set_rx_mode(struct ionic_lif *lif, uint32_t rx_mode)
 313 {
 314         if (lif->rx_mode != rx_mode) {
 315                 lif->rx_mode = rx_mode;
 316                 ionic_lif_rx_mode(lif, rx_mode);
 317         }
 318 }
 319
 320 int
 321 ionic_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
 322 {
 323         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 324         uint32_t rx_mode = lif->rx_mode;
 325
 326         IONIC_PRINT_CALL();
 327
 328         rx_mode |= IONIC_RX_MODE_F_PROMISC;
 329
 330         ionic_set_rx_mode(lif, rx_mode);
 331
 332         return 0;
 333 }
 334
 335 int
 336 ionic_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
 337 {
 338         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 339         uint32_t rx_mode = lif->rx_mode;
 340
 341         rx_mode &= ~IONIC_RX_MODE_F_PROMISC;
 342
 343         ionic_set_rx_mode(lif, rx_mode);
 344
 345         return 0;
 346 }
 347
 348 int
 349 ionic_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
 350 {
 351         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 352         uint32_t rx_mode = lif->rx_mode;
 353
 354         rx_mode |= IONIC_RX_MODE_F_ALLMULTI;
 355
 356         ionic_set_rx_mode(lif, rx_mode);
 357
 358         return 0;
 359 }
 360
 361 int
 362 ionic_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
 363 {
 364         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 365         uint32_t rx_mode = lif->rx_mode;
 366
 367         rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI;
 368
 369         ionic_set_rx_mode(lif, rx_mode);
 370
 371         return 0;
 372 }
 373
 374 int
 375 ionic_lif_change_mtu(struct ionic_lif *lif, int new_mtu)
 376 {
 377         struct ionic_admin_ctx ctx = {
 378                 .pending_work = true,
 379                 .cmd.lif_setattr = {
 380                         .opcode = IONIC_CMD_LIF_SETATTR,
 381                         .index = lif->index,
 382                         .attr = IONIC_LIF_ATTR_MTU,
 383                         .mtu = new_mtu,
 384                 },
 385         };
 386         int err;
 387
 388         err = ionic_adminq_post_wait(lif, &ctx);
 389         if (err)
 390                 return err;
 391
 392         lif->mtu = new_mtu;
 393
 394         return 0;
 395 }
 396
 397 int
 398 ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr)
 399 {
 400         struct ionic_adapter *adapter = lif->adapter;
 401         struct ionic_dev *idev = &adapter->idev;
 402         unsigned long index;
 403
 404         /*
 405          * Note: interrupt handler is called for index = 0 only
 406          * (we use interrupts for the notifyq only anyway,
 407          * which hash index = 0)
 408          */
 409
 410         for (index = 0; index < adapter->nintrs; index++)
 411                 if (!adapter->intrs[index])
 412                         break;
 413
 414         if (index == adapter->nintrs)
 415                 return -ENOSPC;
 416
 417         adapter->intrs[index] = true;
 418
 419         ionic_intr_init(idev, intr, index);
 420
 421         return 0;
 422 }
 423
 424 void
 425 ionic_intr_free(struct ionic_lif *lif, struct ionic_intr_info *intr)
 426 {
 427         if (intr->index != IONIC_INTR_INDEX_NOT_ASSIGNED)
 428                 lif->adapter->intrs[intr->index] = false;
 429 }
 430
 431 static int
 432 ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type,
 433                 uint32_t index,
 434                 const char *base, uint32_t flags,
 435                 uint32_t num_descs,
 436                 uint32_t desc_size,
 437                 uint32_t cq_desc_size,
 438                 uint32_t sg_desc_size,
 439                 uint32_t pid, struct ionic_qcq **qcq)
 440 {
 441         struct ionic_dev *idev = &lif->adapter->idev;
 442         struct ionic_qcq *new;
 443         uint32_t q_size, cq_size, sg_size, total_size;
 444         void *q_base, *cq_base, *sg_base;
 445         rte_iova_t q_base_pa = 0;
 446         rte_iova_t cq_base_pa = 0;
 447         rte_iova_t sg_base_pa = 0;
 448         uint32_t socket_id = rte_socket_id();
 449         int err;
 450
 451         *qcq = NULL;
 452
 453         q_size  = num_descs * desc_size;
 454         cq_size = num_descs * cq_desc_size;
 455         sg_size = num_descs * sg_desc_size;
 456
 457         total_size = RTE_ALIGN(q_size, PAGE_SIZE) +
 458                 RTE_ALIGN(cq_size, PAGE_SIZE);
 459         /*
 460          * Note: aligning q_size/cq_size is not enough due to cq_base address
 461          * aligning as q_base could be not aligned to the page.
 462          * Adding PAGE_SIZE.
 463          */
 464         total_size += PAGE_SIZE;
 465
 466         if (flags & IONIC_QCQ_F_SG) {
 467                 total_size += RTE_ALIGN(sg_size, PAGE_SIZE);
 468                 total_size += PAGE_SIZE;
 469         }
 470
 471         new = rte_zmalloc("ionic", sizeof(*new), 0);
 472         if (!new) {
 473                 IONIC_PRINT(ERR, "Cannot allocate queue structure");
 474                 return -ENOMEM;
 475         }
 476
 477         new->lif = lif;
 478         new->flags = flags;
 479
 480         new->q.info = rte_zmalloc("ionic", sizeof(*new->q.info) * num_descs, 0);
 481         if (!new->q.info) {
 482                 IONIC_PRINT(ERR, "Cannot allocate queue info");
 483                 return -ENOMEM;
 484         }
 485
 486         new->q.type = type;
 487
 488         err = ionic_q_init(lif, idev, &new->q, index, num_descs,
 489                 desc_size, sg_desc_size, pid);
 490         if (err) {
 491                 IONIC_PRINT(ERR, "Queue initialization failed");
 492                 return err;
 493         }
 494
 495         if (flags & IONIC_QCQ_F_INTR) {
 496                 err = ionic_intr_alloc(lif, &new->intr);
 497                 if (err)
 498                         return err;
 499
 500                 ionic_intr_mask_assert(idev->intr_ctrl, new->intr.index,
 501                         IONIC_INTR_MASK_SET);
 502         } else {
 503                 new->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED;
 504         }
 505
 506         err = ionic_cq_init(lif, &new->cq, &new->intr,
 507                 num_descs, cq_desc_size);
 508         if (err) {
 509                 IONIC_PRINT(ERR, "Completion queue initialization failed");
 510                 goto err_out_free_intr;
 511         }
 512
 513         new->base_z = rte_eth_dma_zone_reserve(lif->eth_dev,
 514                 base /* name */, index /* queue_idx */,
 515                 total_size, IONIC_ALIGN, socket_id);
 516
 517         if (!new->base_z) {
 518                 IONIC_PRINT(ERR, "Cannot reserve queue DMA memory");
 519                 err = -ENOMEM;
 520                 goto err_out_free_intr;
 521         }
 522
 523         new->base = new->base_z->addr;
 524         new->base_pa = new->base_z->iova;
 525         new->total_size = total_size;
 526
 527         q_base = new->base;
 528         q_base_pa = new->base_pa;
 529
 530         cq_base = (void *)RTE_ALIGN((uintptr_t)q_base + q_size, PAGE_SIZE);
 531         cq_base_pa = RTE_ALIGN(q_base_pa + q_size, PAGE_SIZE);
 532
 533         if (flags & IONIC_QCQ_F_SG) {
 534                 sg_base = (void *)RTE_ALIGN((uintptr_t)cq_base + cq_size,
 535                         PAGE_SIZE);
 536                 sg_base_pa = RTE_ALIGN(cq_base_pa + cq_size, PAGE_SIZE);
 537                 ionic_q_sg_map(&new->q, sg_base, sg_base_pa);
 538         }
 539
 540         IONIC_PRINT(DEBUG, "Q-Base-PA = %ju CQ-Base-PA = %ju "
 541                 "SG-base-PA = %ju",
 542                 q_base_pa, cq_base_pa, sg_base_pa);
 543
 544         ionic_q_map(&new->q, q_base, q_base_pa);
 545         ionic_cq_map(&new->cq, cq_base, cq_base_pa);
 546         ionic_cq_bind(&new->cq, &new->q);
 547
 548         *qcq = new;
 549
 550         return 0;
 551
 552 err_out_free_intr:
 553         if (flags & IONIC_QCQ_F_INTR)
 554                 ionic_intr_free(lif, &new->intr);
 555
 556         return err;
 557 }
 558
 559 void
 560 ionic_qcq_free(struct ionic_qcq *qcq)
 561 {
 562         if (qcq->base_z) {
 563                 qcq->base = NULL;
 564                 qcq->base_pa = 0;
 565                 rte_memzone_free(qcq->base_z);
 566                 qcq->base_z = NULL;
 567         }
 568
 569         if (qcq->q.info) {
 570                 rte_free(qcq->q.info);
 571                 qcq->q.info = NULL;
 572         }
 573
 574         rte_free(qcq);
 575 }
 576
 577 int
 578 ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t nrxq_descs,
 579                 struct ionic_qcq **qcq)
 580 {
 581         uint32_t flags;
 582         int err = -ENOMEM;
 583
 584         flags = IONIC_QCQ_F_SG;
 585         err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, index, "rx", flags,
 586                 nrxq_descs,
 587                 sizeof(struct ionic_rxq_desc),
 588                 sizeof(struct ionic_rxq_comp),
 589                 sizeof(struct ionic_rxq_sg_desc),
 590                 lif->kern_pid, &lif->rxqcqs[index]);
 591         if (err)
 592                 return err;
 593
 594         *qcq = lif->rxqcqs[index];
 595
 596         return 0;
 597 }
 598
 599 int
 600 ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t ntxq_descs,
 601                 struct ionic_qcq **qcq)
 602 {
 603         uint32_t flags;
 604         int err = -ENOMEM;
 605
 606         flags = IONIC_QCQ_F_SG;
 607         err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, index, "tx", flags,
 608                 ntxq_descs,
 609                 sizeof(struct ionic_txq_desc),
 610                 sizeof(struct ionic_txq_comp),
 611                 sizeof(struct ionic_txq_sg_desc),
 612                 lif->kern_pid, &lif->txqcqs[index]);
 613         if (err)
 614                 return err;
 615
 616         *qcq = lif->txqcqs[index];
 617
 618         return 0;
 619 }
 620
 621 static int
 622 ionic_admin_qcq_alloc(struct ionic_lif *lif)
 623 {
 624         uint32_t flags;
 625         int err = -ENOMEM;
 626
 627         flags = 0;
 628         err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags,
 629                 IONIC_ADMINQ_LENGTH,
 630                 sizeof(struct ionic_admin_cmd),
 631                 sizeof(struct ionic_admin_comp),
 632                 0,
 633                 lif->kern_pid, &lif->adminqcq);
 634         if (err)
 635                 return err;
 636
 637         return 0;
 638 }
 639
 640 static int
 641 ionic_notify_qcq_alloc(struct ionic_lif *lif)
 642 {
 643         uint32_t flags;
 644         int err = -ENOMEM;
 645
 646         flags = IONIC_QCQ_F_NOTIFYQ | IONIC_QCQ_F_INTR;
 647
 648         err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notify",
 649                 flags,
 650                 IONIC_NOTIFYQ_LENGTH,
 651                 sizeof(struct ionic_notifyq_cmd),
 652                 sizeof(union ionic_notifyq_comp),
 653                 0,
 654                 lif->kern_pid, &lif->notifyqcq);
 655         if (err)
 656                 return err;
 657
 658         return 0;
 659 }
 660
 661 static void *
 662 ionic_bus_map_dbpage(struct ionic_adapter *adapter, int page_num)
 663 {
 664         char *vaddr = adapter->bars[IONIC_PCI_BAR_DBELL].vaddr;
 665
 666         if (adapter->num_bars <= IONIC_PCI_BAR_DBELL)
 667                 return NULL;
 668
 669         return (void *)&vaddr[page_num << PAGE_SHIFT];
 670 }
 671
 672 int
 673 ionic_lif_alloc(struct ionic_lif *lif)
 674 {
 675         struct ionic_adapter *adapter = lif->adapter;
 676         uint32_t socket_id = rte_socket_id();
 677         int dbpage_num;
 678         int err;
 679
 680         snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index);
 681
 682         IONIC_PRINT(DEBUG, "Allocating Lif Info");
 683
 684         rte_spinlock_init(&lif->adminq_lock);
 685         rte_spinlock_init(&lif->adminq_service_lock);
 686
 687         lif->kern_pid = 0;
 688
 689         dbpage_num = ionic_db_page_num(lif, 0);
 690
 691         lif->kern_dbpage = ionic_bus_map_dbpage(adapter, dbpage_num);
 692         if (!lif->kern_dbpage) {
 693                 IONIC_PRINT(ERR, "Cannot map dbpage, aborting");
 694                 return -ENOMEM;
 695         }
 696
 697         lif->txqcqs = rte_zmalloc("ionic", sizeof(*lif->txqcqs) *
 698                 adapter->max_ntxqs_per_lif, 0);
 699
 700         if (!lif->txqcqs) {
 701                 IONIC_PRINT(ERR, "Cannot allocate tx queues array");
 702                 return -ENOMEM;
 703         }
 704
 705         lif->rxqcqs = rte_zmalloc("ionic", sizeof(*lif->rxqcqs) *
 706                 adapter->max_nrxqs_per_lif, 0);
 707
 708         if (!lif->rxqcqs) {
 709                 IONIC_PRINT(ERR, "Cannot allocate rx queues array");
 710                 return -ENOMEM;
 711         }
 712
 713         IONIC_PRINT(DEBUG, "Allocating Notify Queue");
 714
 715         err = ionic_notify_qcq_alloc(lif);
 716         if (err) {
 717                 IONIC_PRINT(ERR, "Cannot allocate notify queue");
 718                 return err;
 719         }
 720
 721         IONIC_PRINT(DEBUG, "Allocating Admin Queue");
 722
 723         IONIC_PRINT(DEBUG, "Allocating Admin Queue");
 724
 725         err = ionic_admin_qcq_alloc(lif);
 726         if (err) {
 727                 IONIC_PRINT(ERR, "Cannot allocate admin queue");
 728                 return err;
 729         }
 730
 731         IONIC_PRINT(DEBUG, "Allocating Lif Info");
 732
 733         lif->info_sz = RTE_ALIGN(sizeof(*lif->info), PAGE_SIZE);
 734
 735         lif->info_z = rte_eth_dma_zone_reserve(lif->eth_dev,
 736                 "lif_info", 0 /* queue_idx*/,
 737                 lif->info_sz, IONIC_ALIGN, socket_id);
 738         if (!lif->info_z) {
 739                 IONIC_PRINT(ERR, "Cannot allocate lif info memory");
 740                 return -ENOMEM;
 741         }
 742
 743         lif->info = lif->info_z->addr;
 744         lif->info_pa = lif->info_z->iova;
 745
 746         return 0;
 747 }
 748
 749 void
 750 ionic_lif_free(struct ionic_lif *lif)
 751 {
 752         if (lif->notifyqcq) {
 753                 ionic_qcq_free(lif->notifyqcq);
 754                 lif->notifyqcq = NULL;
 755         }
 756
 757         if (lif->adminqcq) {
 758                 ionic_qcq_free(lif->adminqcq);
 759                 lif->adminqcq = NULL;
 760         }
 761
 762         if (lif->txqcqs) {
 763                 rte_free(lif->txqcqs);
 764                 lif->txqcqs = NULL;
 765         }
 766
 767         if (lif->rxqcqs) {
 768                 rte_free(lif->rxqcqs);
 769                 lif->rxqcqs = NULL;
 770         }
 771
 772         if (lif->info) {
 773                 rte_memzone_free(lif->info_z);
 774                 lif->info = NULL;
 775         }
 776 }
 777
 778 int
 779 ionic_lif_rss_config(struct ionic_lif *lif,
 780                 const uint16_t types, const uint8_t *key, const uint32_t *indir)
 781 {
 782         struct ionic_admin_ctx ctx = {
 783                 .pending_work = true,
 784                 .cmd.lif_setattr = {
 785                         .opcode = IONIC_CMD_LIF_SETATTR,
 786                         .attr = IONIC_LIF_ATTR_RSS,
 787                         .rss.types = types,
 788                         .rss.addr = lif->rss_ind_tbl_pa,
 789                 },
 790         };
 791         unsigned int i;
 792
 793         IONIC_PRINT_CALL();
 794
 795         lif->rss_types = types;
 796
 797         if (key)
 798                 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE);
 799
 800         if (indir)
 801                 for (i = 0; i < lif->adapter->ident.lif.eth.rss_ind_tbl_sz; i++)
 802                         lif->rss_ind_tbl[i] = indir[i];
 803
 804         memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key,
 805                IONIC_RSS_HASH_KEY_SIZE);
 806
 807         return ionic_adminq_post_wait(lif, &ctx);
 808 }
 809
 810 static int
 811 ionic_lif_rss_setup(struct ionic_lif *lif)
 812 {
 813         size_t tbl_size = sizeof(*lif->rss_ind_tbl) *
 814                 lif->adapter->ident.lif.eth.rss_ind_tbl_sz;
 815         static const uint8_t toeplitz_symmetric_key[] = {
 816                 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
 817                 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
 818                 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
 819                 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
 820                 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
 821         };
 822         uint32_t socket_id = rte_socket_id();
 823         uint32_t i;
 824         int err;
 825
 826         IONIC_PRINT_CALL();
 827
 828         lif->rss_ind_tbl_z = rte_eth_dma_zone_reserve(lif->eth_dev,
 829                 "rss_ind_tbl",
 830                 0 /* queue_idx*/, tbl_size, IONIC_ALIGN, socket_id);
 831
 832         if (!lif->rss_ind_tbl_z) {
 833                 IONIC_PRINT(ERR, "OOM");
 834                 return -ENOMEM;
 835         }
 836
 837         lif->rss_ind_tbl = lif->rss_ind_tbl_z->addr;
 838         lif->rss_ind_tbl_pa = lif->rss_ind_tbl_z->iova;
 839
 840         /* Fill indirection table with 'default' values */
 841         for (i = 0; i < lif->adapter->ident.lif.eth.rss_ind_tbl_sz; i++)
 842                 lif->rss_ind_tbl[i] = i % lif->nrxqcqs;
 843
 844         err = ionic_lif_rss_config(lif, IONIC_RSS_OFFLOAD_ALL,
 845                 toeplitz_symmetric_key, NULL);
 846         if (err)
 847                 return err;
 848
 849         return 0;
 850 }
 851
 852 static void
 853 ionic_lif_rss_teardown(struct ionic_lif *lif)
 854 {
 855         if (!lif->rss_ind_tbl)
 856                 return;
 857
 858         if (lif->rss_ind_tbl_z) {
 859                 /* Disable RSS on the NIC */
 860                 ionic_lif_rss_config(lif, 0x0, NULL, NULL);
 861
 862                 lif->rss_ind_tbl = NULL;
 863                 lif->rss_ind_tbl_pa = 0;
 864                 rte_memzone_free(lif->rss_ind_tbl_z);
 865                 lif->rss_ind_tbl_z = NULL;
 866         }
 867 }
 868
 869 static void
 870 ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq)
 871 {
 872         struct ionic_dev *idev = &lif->adapter->idev;
 873
 874         if (!(qcq->flags & IONIC_QCQ_F_INITED))
 875                 return;
 876
 877         if (qcq->flags & IONIC_QCQ_F_INTR)
 878                 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
 879                         IONIC_INTR_MASK_SET);
 880
 881         qcq->flags &= ~IONIC_QCQ_F_INITED;
 882 }
 883
 884 void
 885 ionic_lif_txq_deinit(struct ionic_qcq *qcq)
 886 {
 887         ionic_lif_qcq_deinit(qcq->lif, qcq);
 888 }
 889
 890 void
 891 ionic_lif_rxq_deinit(struct ionic_qcq *qcq)
 892 {
 893         ionic_lif_qcq_deinit(qcq->lif, qcq);
 894 }
 895
 896 bool
 897 ionic_adminq_service(struct ionic_cq *cq, uint32_t cq_desc_index,
 898                 void *cb_arg __rte_unused)
 899 {
 900         struct ionic_admin_comp *cq_desc_base = cq->base;
 901         struct ionic_admin_comp *cq_desc = &cq_desc_base[cq_desc_index];
 902
 903         if (!color_match(cq_desc->color, cq->done_color))
 904                 return false;
 905
 906         ionic_q_service(cq->bound_q, cq_desc_index, cq_desc->comp_index, NULL);
 907
 908         return true;
 909 }
 910
 911 /* This acts like ionic_napi */
 912 int
 913 ionic_qcq_service(struct ionic_qcq *qcq, int budget, ionic_cq_cb cb,
 914                 void *cb_arg)
 915 {
 916         struct ionic_cq *cq = &qcq->cq;
 917         uint32_t work_done;
 918
 919         work_done = ionic_cq_service(cq, budget, cb, cb_arg);
 920
 921         return work_done;
 922 }
 923
 924 static void
 925 ionic_link_status_check(struct ionic_lif *lif)
 926 {
 927         struct ionic_adapter *adapter = lif->adapter;
 928         bool link_up;
 929
 930         lif->state &= ~IONIC_LIF_F_LINK_CHECK_NEEDED;
 931
 932         if (!lif->info)
 933                 return;
 934
 935         link_up = (lif->info->status.link_status == IONIC_PORT_OPER_STATUS_UP);
 936
 937         if ((link_up  && adapter->link_up) ||
 938             (!link_up && !adapter->link_up))
 939                 return;
 940
 941         if (link_up) {
 942                 IONIC_PRINT(DEBUG, "Link up - %d Gbps",
 943                         lif->info->status.link_speed);
 944                 adapter->link_speed = lif->info->status.link_speed;
 945         } else {
 946                 IONIC_PRINT(DEBUG, "Link down");
 947         }
 948
 949         adapter->link_up = link_up;
 950 }
 951
 952 static bool
 953 ionic_notifyq_cb(struct ionic_cq *cq, uint32_t cq_desc_index, void *cb_arg)
 954 {
 955         union ionic_notifyq_comp *cq_desc_base = cq->base;
 956         union ionic_notifyq_comp *cq_desc = &cq_desc_base[cq_desc_index];
 957         struct ionic_lif *lif = cb_arg;
 958
 959         IONIC_PRINT(DEBUG, "Notifyq callback eid = %jd ecode = %d",
 960                 cq_desc->event.eid, cq_desc->event.ecode);
 961
 962         /* Have we run out of new completions to process? */
 963         if (!(cq_desc->event.eid > lif->last_eid))
 964                 return false;
 965
 966         lif->last_eid = cq_desc->event.eid;
 967
 968         switch (cq_desc->event.ecode) {
 969         case IONIC_EVENT_LINK_CHANGE:
 970                 IONIC_PRINT(DEBUG,
 971                         "Notifyq IONIC_EVENT_LINK_CHANGE eid=%jd link_status=%d link_speed=%d",
 972                         cq_desc->event.eid,
 973                         cq_desc->link_change.link_status,
 974                         cq_desc->link_change.link_speed);
 975
 976                 lif->state |= IONIC_LIF_F_LINK_CHECK_NEEDED;
 977
 978                 break;
 979         default:
 980                 IONIC_PRINT(WARNING, "Notifyq bad event ecode=%d eid=%jd",
 981                         cq_desc->event.ecode, cq_desc->event.eid);
 982                 break;
 983         }
 984
 985         return true;
 986 }
 987
 988 int
 989 ionic_notifyq_handler(struct ionic_lif *lif, int budget)
 990 {
 991         struct ionic_dev *idev = &lif->adapter->idev;
 992         struct ionic_qcq *qcq = lif->notifyqcq;
 993         uint32_t work_done;
 994
 995         if (!(qcq->flags & IONIC_QCQ_F_INITED)) {
 996                 IONIC_PRINT(DEBUG, "Notifyq not yet initialized");
 997                 return -1;
 998         }
 999
1000         ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1001                 IONIC_INTR_MASK_SET);
1002
1003         work_done = ionic_qcq_service(qcq, budget, ionic_notifyq_cb, lif);
1004
1005         if (lif->state & IONIC_LIF_F_LINK_CHECK_NEEDED)
1006                 ionic_link_status_check(lif);
1007
1008         ionic_intr_credits(idev->intr_ctrl, qcq->intr.index,
1009                 work_done, IONIC_INTR_CRED_RESET_COALESCE);
1010
1011         ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1012                 IONIC_INTR_MASK_CLEAR);
1013
1014         return 0;
1015 }
1016
1017 static int
1018 ionic_lif_adminq_init(struct ionic_lif *lif)
1019 {
1020         struct ionic_dev *idev = &lif->adapter->idev;
1021         struct ionic_qcq *qcq = lif->adminqcq;
1022         struct ionic_queue *q = &qcq->q;
1023         struct ionic_q_init_comp comp;
1024         int err;
1025
1026         ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index);
1027         err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1028         if (err)
1029                 return err;
1030
1031         ionic_dev_cmd_comp(idev, &comp);
1032
1033         q->hw_type = comp.hw_type;
1034         q->hw_index = comp.hw_index;
1035         q->db = ionic_db_map(lif, q);
1036
1037         IONIC_PRINT(DEBUG, "adminq->hw_type %d", q->hw_type);
1038         IONIC_PRINT(DEBUG, "adminq->hw_index %d", q->hw_index);
1039         IONIC_PRINT(DEBUG, "adminq->db %p", q->db);
1040
1041         if (qcq->flags & IONIC_QCQ_F_INTR)
1042                 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1043                         IONIC_INTR_MASK_CLEAR);
1044
1045         qcq->flags |= IONIC_QCQ_F_INITED;
1046
1047         return 0;
1048 }
1049
1050 static int
1051 ionic_lif_notifyq_init(struct ionic_lif *lif)
1052 {
1053         struct ionic_dev *idev = &lif->adapter->idev;
1054         struct ionic_qcq *qcq = lif->notifyqcq;
1055         struct ionic_queue *q = &qcq->q;
1056         int err;
1057
1058         struct ionic_admin_ctx ctx = {
1059                 .pending_work = true,
1060                 .cmd.q_init = {
1061                         .opcode = IONIC_CMD_Q_INIT,
1062                         .lif_index = lif->index,
1063                         .type = q->type,
1064                         .index = q->index,
1065                         .flags = (IONIC_QINIT_F_IRQ | IONIC_QINIT_F_ENA),
1066                         .intr_index = qcq->intr.index,
1067                         .pid = q->pid,
1068                         .ring_size = rte_log2_u32(q->num_descs),
1069                         .ring_base = q->base_pa,
1070                 }
1071         };
1072
1073         IONIC_PRINT(DEBUG, "notifyq_init.pid %d", ctx.cmd.q_init.pid);
1074         IONIC_PRINT(DEBUG, "notifyq_init.index %d",
1075                 ctx.cmd.q_init.index);
1076         IONIC_PRINT(DEBUG, "notifyq_init.ring_base 0x%" PRIx64 "",
1077                 ctx.cmd.q_init.ring_base);
1078         IONIC_PRINT(DEBUG, "notifyq_init.ring_size %d",
1079                 ctx.cmd.q_init.ring_size);
1080
1081         err = ionic_adminq_post_wait(lif, &ctx);
1082         if (err)
1083                 return err;
1084
1085         q->hw_type = ctx.comp.q_init.hw_type;
1086         q->hw_index = ctx.comp.q_init.hw_index;
1087         q->db = NULL;
1088
1089         IONIC_PRINT(DEBUG, "notifyq->hw_type %d", q->hw_type);
1090         IONIC_PRINT(DEBUG, "notifyq->hw_index %d", q->hw_index);
1091         IONIC_PRINT(DEBUG, "notifyq->db %p", q->db);
1092
1093         if (qcq->flags & IONIC_QCQ_F_INTR)
1094                 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1095                         IONIC_INTR_MASK_CLEAR);
1096
1097         qcq->flags |= IONIC_QCQ_F_INITED;
1098
1099         return 0;
1100 }
1101
1102 int
1103 ionic_lif_set_features(struct ionic_lif *lif)
1104 {
1105         struct ionic_admin_ctx ctx = {
1106                 .pending_work = true,
1107                 .cmd.lif_setattr = {
1108                         .opcode = IONIC_CMD_LIF_SETATTR,
1109                         .index = lif->index,
1110                         .attr = IONIC_LIF_ATTR_FEATURES,
1111                         .features = lif->features,
1112                 },
1113         };
1114         int err;
1115
1116         err = ionic_adminq_post_wait(lif, &ctx);
1117         if (err)
1118                 return err;
1119
1120         lif->hw_features = (ctx.cmd.lif_setattr.features &
1121                 ctx.comp.lif_setattr.features);
1122
1123         if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
1124                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_TX_TAG");
1125         if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
1126                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_STRIP");
1127         if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
1128                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_FILTER");
1129         if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
1130                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_HASH");
1131         if (lif->hw_features & IONIC_ETH_HW_TX_SG)
1132                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_SG");
1133         if (lif->hw_features & IONIC_ETH_HW_RX_SG)
1134                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_SG");
1135         if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
1136                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_CSUM");
1137         if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
1138                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_CSUM");
1139         if (lif->hw_features & IONIC_ETH_HW_TSO)
1140                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO");
1141         if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
1142                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPV6");
1143         if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
1144                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_ECN");
1145         if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
1146                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE");
1147         if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
1148                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE_CSUM");
1149         if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
1150                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP4");
1151         if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
1152                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP6");
1153         if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
1154                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP");
1155         if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
1156                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP_CSUM");
1157
1158         return 0;
1159 }
1160
1161 int
1162 ionic_lif_txq_init(struct ionic_qcq *qcq)
1163 {
1164         struct ionic_queue *q = &qcq->q;
1165         struct ionic_lif *lif = qcq->lif;
1166         struct ionic_cq *cq = &qcq->cq;
1167         struct ionic_admin_ctx ctx = {
1168                 .pending_work = true,
1169                 .cmd.q_init = {
1170                         .opcode = IONIC_CMD_Q_INIT,
1171                         .lif_index = lif->index,
1172                         .type = q->type,
1173                         .index = q->index,
1174                         .flags = IONIC_QINIT_F_SG,
1175                         .intr_index = cq->bound_intr->index,
1176                         .pid = q->pid,
1177                         .ring_size = rte_log2_u32(q->num_descs),
1178                         .ring_base = q->base_pa,
1179                         .cq_ring_base = cq->base_pa,
1180                         .sg_ring_base = q->sg_base_pa,
1181                 },
1182         };
1183         int err;
1184
1185         IONIC_PRINT(DEBUG, "txq_init.pid %d", ctx.cmd.q_init.pid);
1186         IONIC_PRINT(DEBUG, "txq_init.index %d", ctx.cmd.q_init.index);
1187         IONIC_PRINT(DEBUG, "txq_init.ring_base 0x%" PRIx64 "",
1188                 ctx.cmd.q_init.ring_base);
1189         IONIC_PRINT(DEBUG, "txq_init.ring_size %d",
1190                 ctx.cmd.q_init.ring_size);
1191
1192         err = ionic_adminq_post_wait(qcq->lif, &ctx);
1193         if (err)
1194                 return err;
1195
1196         q->hw_type = ctx.comp.q_init.hw_type;
1197         q->hw_index = ctx.comp.q_init.hw_index;
1198         q->db = ionic_db_map(lif, q);
1199
1200         IONIC_PRINT(DEBUG, "txq->hw_type %d", q->hw_type);
1201         IONIC_PRINT(DEBUG, "txq->hw_index %d", q->hw_index);
1202         IONIC_PRINT(DEBUG, "txq->db %p", q->db);
1203
1204         qcq->flags |= IONIC_QCQ_F_INITED;
1205
1206         return 0;
1207 }
1208
1209 int
1210 ionic_lif_rxq_init(struct ionic_qcq *qcq)
1211 {
1212         struct ionic_queue *q = &qcq->q;
1213         struct ionic_lif *lif = qcq->lif;
1214         struct ionic_cq *cq = &qcq->cq;
1215         struct ionic_admin_ctx ctx = {
1216                 .pending_work = true,
1217                 .cmd.q_init = {
1218                         .opcode = IONIC_CMD_Q_INIT,
1219                         .lif_index = lif->index,
1220                         .type = q->type,
1221                         .index = q->index,
1222                         .flags = IONIC_QINIT_F_SG,
1223                         .intr_index = cq->bound_intr->index,
1224                         .pid = q->pid,
1225                         .ring_size = rte_log2_u32(q->num_descs),
1226                         .ring_base = q->base_pa,
1227                         .cq_ring_base = cq->base_pa,
1228                         .sg_ring_base = q->sg_base_pa,
1229                 },
1230         };
1231         int err;
1232
1233         IONIC_PRINT(DEBUG, "rxq_init.pid %d", ctx.cmd.q_init.pid);
1234         IONIC_PRINT(DEBUG, "rxq_init.index %d", ctx.cmd.q_init.index);
1235         IONIC_PRINT(DEBUG, "rxq_init.ring_base 0x%" PRIx64 "",
1236                 ctx.cmd.q_init.ring_base);
1237         IONIC_PRINT(DEBUG, "rxq_init.ring_size %d",
1238                 ctx.cmd.q_init.ring_size);
1239
1240         err = ionic_adminq_post_wait(qcq->lif, &ctx);
1241         if (err)
1242                 return err;
1243
1244         q->hw_type = ctx.comp.q_init.hw_type;
1245         q->hw_index = ctx.comp.q_init.hw_index;
1246         q->db = ionic_db_map(lif, q);
1247
1248         qcq->flags |= IONIC_QCQ_F_INITED;
1249
1250         IONIC_PRINT(DEBUG, "rxq->hw_type %d", q->hw_type);
1251         IONIC_PRINT(DEBUG, "rxq->hw_index %d", q->hw_index);
1252         IONIC_PRINT(DEBUG, "rxq->db %p", q->db);
1253
1254         return 0;
1255 }
1256
1257 static int
1258 ionic_station_set(struct ionic_lif *lif)
1259 {
1260         struct ionic_admin_ctx ctx = {
1261                 .pending_work = true,
1262                 .cmd.lif_getattr = {
1263                         .opcode = IONIC_CMD_LIF_GETATTR,
1264                         .index = lif->index,
1265                         .attr = IONIC_LIF_ATTR_MAC,
1266                 },
1267         };
1268         int err;
1269
1270         IONIC_PRINT_CALL();
1271
1272         err = ionic_adminq_post_wait(lif, &ctx);
1273         if (err)
1274                 return err;
1275
1276         if (!rte_is_zero_ether_addr((struct rte_ether_addr *)
1277                         lif->mac_addr)) {
1278                 IONIC_PRINT(INFO, "deleting station MAC addr");
1279
1280                 ionic_lif_addr_del(lif, lif->mac_addr);
1281         }
1282
1283         memcpy(lif->mac_addr, ctx.comp.lif_getattr.mac, RTE_ETHER_ADDR_LEN);
1284
1285         if (rte_is_zero_ether_addr((struct rte_ether_addr *)lif->mac_addr)) {
1286                 IONIC_PRINT(NOTICE, "empty MAC addr (VF?)");
1287                 return 0;
1288         }
1289
1290         IONIC_PRINT(DEBUG, "adding station MAC addr");
1291
1292         ionic_lif_addr_add(lif, lif->mac_addr);
1293
1294         return 0;
1295 }
1296
1297 static void
1298 ionic_lif_set_name(struct ionic_lif *lif)
1299 {
1300         struct ionic_admin_ctx ctx = {
1301                 .pending_work = true,
1302                 .cmd.lif_setattr = {
1303                         .opcode = IONIC_CMD_LIF_SETATTR,
1304                         .index = lif->index,
1305                         .attr = IONIC_LIF_ATTR_NAME,
1306                 },
1307         };
1308
1309         snprintf(ctx.cmd.lif_setattr.name, sizeof(ctx.cmd.lif_setattr.name),
1310                 "%d", lif->port_id);
1311
1312         ionic_adminq_post_wait(lif, &ctx);
1313 }
1314
1315 int
1316 ionic_lif_init(struct ionic_lif *lif)
1317 {
1318         struct ionic_dev *idev = &lif->adapter->idev;
1319         struct ionic_q_init_comp comp;
1320         int err;
1321
1322         ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa);
1323         err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1324         ionic_dev_cmd_comp(idev, &comp);
1325         if (err)
1326                 return err;
1327
1328         lif->hw_index = comp.hw_index;
1329
1330         err = ionic_lif_adminq_init(lif);
1331         if (err)
1332                 return err;
1333
1334         err = ionic_lif_notifyq_init(lif);
1335         if (err)
1336                 goto err_out_adminq_deinit;
1337
1338         lif->features =
1339                   IONIC_ETH_HW_VLAN_TX_TAG
1340                 | IONIC_ETH_HW_VLAN_RX_STRIP
1341                 | IONIC_ETH_HW_VLAN_RX_FILTER
1342                 | IONIC_ETH_HW_RX_HASH
1343                 | IONIC_ETH_HW_TX_SG
1344                 | IONIC_ETH_HW_RX_SG
1345                 | IONIC_ETH_HW_RX_CSUM
1346                 | IONIC_ETH_HW_TSO
1347                 | IONIC_ETH_HW_TSO_IPV6
1348                 | IONIC_ETH_HW_TSO_ECN;
1349
1350         err = ionic_lif_set_features(lif);
1351         if (err)
1352                 goto err_out_notifyq_deinit;
1353
1354         err = ionic_rx_filters_init(lif);
1355         if (err)
1356                 goto err_out_notifyq_deinit;
1357
1358         err = ionic_station_set(lif);
1359         if (err)
1360                 goto err_out_rx_filter_deinit;
1361
1362         ionic_lif_set_name(lif);
1363
1364         lif->state |= IONIC_LIF_F_INITED;
1365
1366         return 0;
1367
1368 err_out_rx_filter_deinit:
1369         ionic_rx_filters_deinit(lif);
1370
1371 err_out_notifyq_deinit:
1372         ionic_lif_qcq_deinit(lif, lif->notifyqcq);
1373
1374 err_out_adminq_deinit:
1375         ionic_lif_qcq_deinit(lif, lif->adminqcq);
1376
1377         return err;
1378 }
1379
1380 void
1381 ionic_lif_deinit(struct ionic_lif *lif)
1382 {
1383         if (!(lif->state & IONIC_LIF_F_INITED))
1384                 return;
1385
1386         ionic_rx_filters_deinit(lif);
1387         ionic_lif_rss_teardown(lif);
1388         ionic_lif_qcq_deinit(lif, lif->notifyqcq);
1389         ionic_lif_qcq_deinit(lif, lif->adminqcq);
1390
1391         lif->state &= ~IONIC_LIF_F_INITED;
1392 }
1393
1394 int
1395 ionic_lif_configure(struct ionic_lif *lif)
1396 {
1397         struct ionic_identity *ident = &lif->adapter->ident;
1398         uint32_t ntxqs_per_lif =
1399                 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ];
1400         uint32_t nrxqs_per_lif =
1401                 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ];
1402         uint32_t nrxqs = lif->eth_dev->data->nb_rx_queues;
1403         uint32_t ntxqs = lif->eth_dev->data->nb_tx_queues;
1404
1405         lif->port_id = lif->eth_dev->data->port_id;
1406
1407         IONIC_PRINT(DEBUG, "Configuring LIF on port %u",
1408                 lif->port_id);
1409
1410         if (nrxqs > 0)
1411                 nrxqs_per_lif = RTE_MIN(nrxqs_per_lif, nrxqs);
1412
1413         if (ntxqs > 0)
1414                 ntxqs_per_lif = RTE_MIN(ntxqs_per_lif, ntxqs);
1415
1416         lif->nrxqcqs = nrxqs_per_lif;
1417         lif->ntxqcqs = ntxqs_per_lif;
1418
1419         return 0;
1420 }
1421
1422 int
1423 ionic_lif_start(struct ionic_lif *lif)
1424 {
1425         uint32_t rx_mode = 0;
1426         uint32_t i;
1427         int err;
1428
1429         IONIC_PRINT(DEBUG, "Setting RSS configuration on port %u",
1430                 lif->port_id);
1431
1432         err = ionic_lif_rss_setup(lif);
1433         if (err)
1434                 return err;
1435
1436         IONIC_PRINT(DEBUG, "Setting RX mode on port %u",
1437                 lif->port_id);
1438
1439         rx_mode |= IONIC_RX_MODE_F_UNICAST;
1440         rx_mode |= IONIC_RX_MODE_F_MULTICAST;
1441         rx_mode |= IONIC_RX_MODE_F_BROADCAST;
1442
1443         lif->rx_mode = 0; /* set by ionic_set_rx_mode */
1444
1445         ionic_set_rx_mode(lif, rx_mode);
1446
1447         IONIC_PRINT(DEBUG, "Starting %u RX queues and %u TX queues "
1448                 "on port %u",
1449                 lif->nrxqcqs, lif->ntxqcqs, lif->port_id);
1450
1451         for (i = 0; i < lif->nrxqcqs; i++) {
1452                 struct ionic_qcq *rxq = lif->rxqcqs[i];
1453                 if (!rxq->deferred_start) {
1454                         err = ionic_dev_rx_queue_start(lif->eth_dev, i);
1455
1456                         if (err)
1457                                 return err;
1458                 }
1459         }
1460
1461         for (i = 0; i < lif->ntxqcqs; i++) {
1462                 struct ionic_qcq *txq = lif->txqcqs[i];
1463                 if (!txq->deferred_start) {
1464                         err = ionic_dev_tx_queue_start(lif->eth_dev, i);
1465
1466                         if (err)
1467                                 return err;
1468                 }
1469         }
1470
1471         ionic_link_status_check(lif);
1472
1473         /* Carrier ON here */
1474
1475         return 0;
1476 }
1477
1478 int
1479 ionic_lif_identify(struct ionic_adapter *adapter)
1480 {
1481         struct ionic_dev *idev = &adapter->idev;
1482         struct ionic_identity *ident = &adapter->ident;
1483         int err;
1484         unsigned int i;
1485         unsigned int lif_words = sizeof(ident->lif.words) /
1486                 sizeof(ident->lif.words[0]);
1487         unsigned int cmd_words = sizeof(idev->dev_cmd->data) /
1488                 sizeof(idev->dev_cmd->data[0]);
1489         unsigned int nwords;
1490
1491         ionic_dev_cmd_lif_identify(idev, IONIC_LIF_TYPE_CLASSIC,
1492                 IONIC_IDENTITY_VERSION_1);
1493         err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1494         if (err)
1495                 return (err);
1496
1497         nwords = RTE_MIN(lif_words, cmd_words);
1498         for (i = 0; i < nwords; i++)
1499                 ident->lif.words[i] = ioread32(&idev->dev_cmd->data[i]);
1500
1501         IONIC_PRINT(INFO, "capabilities 0x%" PRIx64 " ",
1502                 ident->lif.capabilities);
1503
1504         IONIC_PRINT(INFO, "eth.max_ucast_filters 0x%" PRIx32 " ",
1505                 ident->lif.eth.max_ucast_filters);
1506         IONIC_PRINT(INFO, "eth.max_mcast_filters 0x%" PRIx32 " ",
1507                 ident->lif.eth.max_mcast_filters);
1508
1509         IONIC_PRINT(INFO, "eth.features 0x%" PRIx64 " ",
1510                 ident->lif.eth.config.features);
1511         IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_ADMINQ] 0x%" PRIx32 " ",
1512                 ident->lif.eth.config.queue_count[IONIC_QTYPE_ADMINQ]);
1513         IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] 0x%" PRIx32 " ",
1514                 ident->lif.eth.config.queue_count[IONIC_QTYPE_NOTIFYQ]);
1515         IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_RXQ] 0x%" PRIx32 " ",
1516                 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ]);
1517         IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_TXQ] 0x%" PRIx32 " ",
1518                 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ]);
1519
1520         return 0;
1521 }
1522
1523 int
1524 ionic_lifs_size(struct ionic_adapter *adapter)
1525 {
1526         struct ionic_identity *ident = &adapter->ident;
1527         uint32_t nlifs = ident->dev.nlifs;
1528         uint32_t nintrs, dev_nintrs = ident->dev.nintrs;
1529
1530         adapter->max_ntxqs_per_lif =
1531                 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ];
1532         adapter->max_nrxqs_per_lif =
1533                 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ];
1534
1535         nintrs = nlifs * 1 /* notifyq */;
1536
1537         if (nintrs > dev_nintrs) {
1538                 IONIC_PRINT(ERR, "At most %d intr queues supported, minimum required is %u",
1539                         dev_nintrs, nintrs);
1540                 return -ENOSPC;
1541         }
1542
1543         adapter->nintrs = nintrs;
1544
1545         return 0;
1546 }