1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
5 #include <rte_malloc.h>
6 #include <ethdev_driver.h>
9 #include "ionic_logs.h"
10 #include "ionic_lif.h"
11 #include "ionic_ethdev.h"
12 #include "ionic_rx_filter.h"
13 #include "ionic_rxtx.h"
15 /* queuetype support level */
16 static const uint8_t ionic_qtype_vers[IONIC_QTYPE_MAX] = {
17 [IONIC_QTYPE_ADMINQ] = 0, /* 0 = Base version with CQ support */
18 [IONIC_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */
19 [IONIC_QTYPE_RXQ] = 2, /* 0 = Base version with CQ+SG support
23 [IONIC_QTYPE_TXQ] = 3, /* 0 = Base version with CQ+SG support
24 * 1 = ... with Tx SG version 1
30 static int ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr);
31 static int ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr);
34 ionic_qcq_enable(struct ionic_qcq *qcq)
36 struct ionic_queue *q = &qcq->q;
37 struct ionic_lif *lif = qcq->lif;
38 struct ionic_admin_ctx ctx = {
41 .opcode = IONIC_CMD_Q_CONTROL,
43 .index = rte_cpu_to_le_32(q->index),
44 .oper = IONIC_Q_ENABLE,
48 return ionic_adminq_post_wait(lif, &ctx);
52 ionic_qcq_disable(struct ionic_qcq *qcq)
54 struct ionic_queue *q = &qcq->q;
55 struct ionic_lif *lif = qcq->lif;
56 struct ionic_admin_ctx ctx = {
59 .opcode = IONIC_CMD_Q_CONTROL,
61 .index = rte_cpu_to_le_32(q->index),
62 .oper = IONIC_Q_DISABLE,
66 return ionic_adminq_post_wait(lif, &ctx);
70 ionic_lif_stop(struct ionic_lif *lif)
76 lif->state &= ~IONIC_LIF_F_UP;
78 for (i = 0; i < lif->nrxqcqs; i++) {
79 struct ionic_rx_qcq *rxq = lif->rxqcqs[i];
80 if (rxq->flags & IONIC_QCQ_F_INITED)
81 (void)ionic_dev_rx_queue_stop(lif->eth_dev, i);
84 for (i = 0; i < lif->ntxqcqs; i++) {
85 struct ionic_tx_qcq *txq = lif->txqcqs[i];
86 if (txq->flags & IONIC_QCQ_F_INITED)
87 (void)ionic_dev_tx_queue_stop(lif->eth_dev, i);
92 ionic_lif_reset(struct ionic_lif *lif)
94 struct ionic_dev *idev = &lif->adapter->idev;
99 ionic_dev_cmd_lif_reset(idev);
100 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
102 IONIC_PRINT(WARNING, "Failed to reset %s", lif->name);
106 ionic_lif_get_abs_stats(const struct ionic_lif *lif, struct rte_eth_stats *stats)
108 struct ionic_lif_stats *ls = &lif->info->stats;
110 uint32_t num_rx_q_counters = RTE_MIN(lif->nrxqcqs, (uint32_t)
111 RTE_ETHDEV_QUEUE_STAT_CNTRS);
112 uint32_t num_tx_q_counters = RTE_MIN(lif->ntxqcqs, (uint32_t)
113 RTE_ETHDEV_QUEUE_STAT_CNTRS);
115 memset(stats, 0, sizeof(*stats));
118 IONIC_PRINT(DEBUG, "Stats on port %u not yet initialized",
125 stats->ipackets = ls->rx_ucast_packets +
126 ls->rx_mcast_packets +
127 ls->rx_bcast_packets;
129 stats->ibytes = ls->rx_ucast_bytes +
133 for (i = 0; i < lif->nrxqcqs; i++) {
134 struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats;
136 rx_stats->no_cb_arg +
137 rx_stats->bad_cq_status +
143 ls->rx_ucast_drop_packets +
144 ls->rx_mcast_drop_packets +
145 ls->rx_bcast_drop_packets;
150 ls->rx_queue_disabled +
151 ls->rx_desc_fetch_error +
152 ls->rx_desc_data_error;
154 for (i = 0; i < num_rx_q_counters; i++) {
155 struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats;
156 stats->q_ipackets[i] = rx_stats->packets;
157 stats->q_ibytes[i] = rx_stats->bytes;
159 rx_stats->no_cb_arg +
160 rx_stats->bad_cq_status +
167 stats->opackets = ls->tx_ucast_packets +
168 ls->tx_mcast_packets +
169 ls->tx_bcast_packets;
171 stats->obytes = ls->tx_ucast_bytes +
175 for (i = 0; i < lif->ntxqcqs; i++) {
176 struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats;
177 stats->oerrors += tx_stats->drop;
181 ls->tx_ucast_drop_packets +
182 ls->tx_mcast_drop_packets +
183 ls->tx_bcast_drop_packets;
187 ls->tx_queue_disabled +
188 ls->tx_desc_fetch_error +
189 ls->tx_desc_data_error;
191 for (i = 0; i < num_tx_q_counters; i++) {
192 struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats;
193 stats->q_opackets[i] = tx_stats->packets;
194 stats->q_obytes[i] = tx_stats->bytes;
199 ionic_lif_get_stats(const struct ionic_lif *lif,
200 struct rte_eth_stats *stats)
202 ionic_lif_get_abs_stats(lif, stats);
204 stats->ipackets -= lif->stats_base.ipackets;
205 stats->opackets -= lif->stats_base.opackets;
206 stats->ibytes -= lif->stats_base.ibytes;
207 stats->obytes -= lif->stats_base.obytes;
208 stats->imissed -= lif->stats_base.imissed;
209 stats->ierrors -= lif->stats_base.ierrors;
210 stats->oerrors -= lif->stats_base.oerrors;
211 stats->rx_nombuf -= lif->stats_base.rx_nombuf;
215 ionic_lif_reset_stats(struct ionic_lif *lif)
219 for (i = 0; i < lif->nrxqcqs; i++) {
220 memset(&lif->rxqcqs[i]->stats, 0,
221 sizeof(struct ionic_rx_stats));
222 memset(&lif->txqcqs[i]->stats, 0,
223 sizeof(struct ionic_tx_stats));
226 ionic_lif_get_abs_stats(lif, &lif->stats_base);
230 ionic_lif_get_hw_stats(struct ionic_lif *lif, struct ionic_lif_stats *stats)
232 uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t);
233 uint64_t *stats64 = (uint64_t *)stats;
234 uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats;
235 uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base;
237 for (i = 0; i < count; i++)
238 stats64[i] = lif_stats64[i] - lif_stats64_base[i];
242 ionic_lif_reset_hw_stats(struct ionic_lif *lif)
244 uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t);
245 uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats;
246 uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base;
248 for (i = 0; i < count; i++)
249 lif_stats64_base[i] = lif_stats64[i];
253 ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr)
255 struct ionic_admin_ctx ctx = {
256 .pending_work = true,
257 .cmd.rx_filter_add = {
258 .opcode = IONIC_CMD_RX_FILTER_ADD,
259 .match = rte_cpu_to_le_16(IONIC_RX_FILTER_MATCH_MAC),
264 memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, RTE_ETHER_ADDR_LEN);
266 err = ionic_adminq_post_wait(lif, &ctx);
270 IONIC_PRINT(INFO, "rx_filter add (id %d)",
271 rte_le_to_cpu_32(ctx.comp.rx_filter_add.filter_id));
273 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);
277 ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr)
279 struct ionic_admin_ctx ctx = {
280 .pending_work = true,
281 .cmd.rx_filter_del = {
282 .opcode = IONIC_CMD_RX_FILTER_DEL,
285 struct ionic_rx_filter *f;
290 rte_spinlock_lock(&lif->rx_filters.lock);
292 f = ionic_rx_filter_by_addr(lif, addr);
294 rte_spinlock_unlock(&lif->rx_filters.lock);
298 ctx.cmd.rx_filter_del.filter_id = rte_cpu_to_le_32(f->filter_id);
299 ionic_rx_filter_free(f);
301 rte_spinlock_unlock(&lif->rx_filters.lock);
303 err = ionic_adminq_post_wait(lif, &ctx);
307 IONIC_PRINT(INFO, "rx_filter del (id %d)",
308 rte_le_to_cpu_32(ctx.cmd.rx_filter_del.filter_id));
314 ionic_dev_add_mac(struct rte_eth_dev *eth_dev,
315 struct rte_ether_addr *mac_addr,
316 uint32_t index __rte_unused, uint32_t pool __rte_unused)
318 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
322 return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr);
326 ionic_dev_remove_mac(struct rte_eth_dev *eth_dev, uint32_t index)
328 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
329 struct ionic_adapter *adapter = lif->adapter;
330 struct rte_ether_addr *mac_addr;
334 if (index >= adapter->max_mac_addrs) {
336 "Index %u is above MAC filter limit %u",
337 index, adapter->max_mac_addrs);
341 mac_addr = ð_dev->data->mac_addrs[index];
343 if (!rte_is_valid_assigned_ether_addr(mac_addr))
346 ionic_lif_addr_del(lif, (const uint8_t *)mac_addr);
350 ionic_dev_set_mac(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr)
352 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
356 if (mac_addr == NULL) {
357 IONIC_PRINT(NOTICE, "New mac is null");
361 if (!rte_is_zero_ether_addr((struct rte_ether_addr *)lif->mac_addr)) {
362 IONIC_PRINT(INFO, "Deleting mac addr %pM",
364 ionic_lif_addr_del(lif, lif->mac_addr);
365 memset(lif->mac_addr, 0, RTE_ETHER_ADDR_LEN);
368 IONIC_PRINT(INFO, "Updating mac addr");
370 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)lif->mac_addr);
372 return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr);
376 ionic_vlan_rx_add_vid(struct ionic_lif *lif, uint16_t vid)
378 struct ionic_admin_ctx ctx = {
379 .pending_work = true,
380 .cmd.rx_filter_add = {
381 .opcode = IONIC_CMD_RX_FILTER_ADD,
382 .match = rte_cpu_to_le_16(IONIC_RX_FILTER_MATCH_VLAN),
383 .vlan.vlan = rte_cpu_to_le_16(vid),
388 err = ionic_adminq_post_wait(lif, &ctx);
392 IONIC_PRINT(INFO, "rx_filter add VLAN %d (id %d)", vid,
393 rte_le_to_cpu_32(ctx.comp.rx_filter_add.filter_id));
395 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);
399 ionic_vlan_rx_kill_vid(struct ionic_lif *lif, uint16_t vid)
401 struct ionic_admin_ctx ctx = {
402 .pending_work = true,
403 .cmd.rx_filter_del = {
404 .opcode = IONIC_CMD_RX_FILTER_DEL,
407 struct ionic_rx_filter *f;
412 rte_spinlock_lock(&lif->rx_filters.lock);
414 f = ionic_rx_filter_by_vlan(lif, vid);
416 rte_spinlock_unlock(&lif->rx_filters.lock);
420 ctx.cmd.rx_filter_del.filter_id = rte_cpu_to_le_32(f->filter_id);
421 ionic_rx_filter_free(f);
422 rte_spinlock_unlock(&lif->rx_filters.lock);
424 err = ionic_adminq_post_wait(lif, &ctx);
428 IONIC_PRINT(INFO, "rx_filter del VLAN %d (id %d)", vid,
429 rte_le_to_cpu_32(ctx.cmd.rx_filter_del.filter_id));
435 ionic_dev_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id,
438 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
442 err = ionic_vlan_rx_add_vid(lif, vlan_id);
444 err = ionic_vlan_rx_kill_vid(lif, vlan_id);
450 ionic_lif_rx_mode(struct ionic_lif *lif, uint32_t rx_mode)
452 struct ionic_admin_ctx ctx = {
453 .pending_work = true,
455 .opcode = IONIC_CMD_RX_MODE_SET,
456 .rx_mode = rte_cpu_to_le_16(rx_mode),
461 if (rx_mode & IONIC_RX_MODE_F_UNICAST)
462 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_UNICAST");
463 if (rx_mode & IONIC_RX_MODE_F_MULTICAST)
464 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_MULTICAST");
465 if (rx_mode & IONIC_RX_MODE_F_BROADCAST)
466 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_BROADCAST");
467 if (rx_mode & IONIC_RX_MODE_F_PROMISC)
468 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_PROMISC");
469 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI)
470 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_ALLMULTI");
472 err = ionic_adminq_post_wait(lif, &ctx);
474 IONIC_PRINT(ERR, "Failure setting RX mode");
478 ionic_set_rx_mode(struct ionic_lif *lif, uint32_t rx_mode)
480 if (lif->rx_mode != rx_mode) {
481 lif->rx_mode = rx_mode;
482 ionic_lif_rx_mode(lif, rx_mode);
487 ionic_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
489 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
490 uint32_t rx_mode = lif->rx_mode;
494 rx_mode |= IONIC_RX_MODE_F_PROMISC;
496 ionic_set_rx_mode(lif, rx_mode);
502 ionic_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
504 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
505 uint32_t rx_mode = lif->rx_mode;
507 rx_mode &= ~IONIC_RX_MODE_F_PROMISC;
509 ionic_set_rx_mode(lif, rx_mode);
515 ionic_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
517 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
518 uint32_t rx_mode = lif->rx_mode;
520 rx_mode |= IONIC_RX_MODE_F_ALLMULTI;
522 ionic_set_rx_mode(lif, rx_mode);
528 ionic_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
530 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
531 uint32_t rx_mode = lif->rx_mode;
533 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI;
535 ionic_set_rx_mode(lif, rx_mode);
541 ionic_lif_change_mtu(struct ionic_lif *lif, int new_mtu)
543 struct ionic_admin_ctx ctx = {
544 .pending_work = true,
546 .opcode = IONIC_CMD_LIF_SETATTR,
547 .attr = IONIC_LIF_ATTR_MTU,
548 .mtu = rte_cpu_to_le_32(new_mtu),
553 err = ionic_adminq_post_wait(lif, &ctx);
561 ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr)
563 struct ionic_adapter *adapter = lif->adapter;
564 struct ionic_dev *idev = &adapter->idev;
568 * Note: interrupt handler is called for index = 0 only
569 * (we use interrupts for the notifyq only anyway,
570 * which has index = 0)
573 for (index = 0; index < adapter->nintrs; index++)
574 if (!adapter->intrs[index])
577 if (index == adapter->nintrs)
580 adapter->intrs[index] = true;
582 ionic_intr_init(idev, intr, index);
588 ionic_qcq_alloc(struct ionic_lif *lif,
593 const char *type_name,
597 uint16_t cq_desc_size,
598 uint16_t sg_desc_size,
599 struct ionic_qcq **qcq)
601 struct ionic_qcq *new;
602 uint32_t q_size, cq_size, sg_size, total_size;
603 void *q_base, *cq_base, *sg_base;
604 rte_iova_t q_base_pa = 0;
605 rte_iova_t cq_base_pa = 0;
606 rte_iova_t sg_base_pa = 0;
611 q_size = num_descs * desc_size;
612 cq_size = num_descs * cq_desc_size;
613 sg_size = num_descs * sg_desc_size;
615 total_size = RTE_ALIGN(q_size, PAGE_SIZE) +
616 RTE_ALIGN(cq_size, PAGE_SIZE);
618 * Note: aligning q_size/cq_size is not enough due to cq_base address
619 * aligning as q_base could be not aligned to the page.
622 total_size += PAGE_SIZE;
624 if (flags & IONIC_QCQ_F_SG) {
625 total_size += RTE_ALIGN(sg_size, PAGE_SIZE);
626 total_size += PAGE_SIZE;
629 new = rte_zmalloc("ionic", struct_size, 0);
631 IONIC_PRINT(ERR, "Cannot allocate queue structure");
637 new->q.info = rte_calloc_socket("ionic",
638 num_descs, sizeof(void *),
639 PAGE_SIZE, socket_id);
641 IONIC_PRINT(ERR, "Cannot allocate queue info");
643 goto err_out_free_qcq;
648 err = ionic_q_init(&new->q, index, num_descs);
650 IONIC_PRINT(ERR, "Queue initialization failed");
651 goto err_out_free_info;
654 err = ionic_cq_init(&new->cq, num_descs);
656 IONIC_PRINT(ERR, "Completion queue initialization failed");
657 goto err_out_free_info;
660 new->base_z = rte_eth_dma_zone_reserve(lif->eth_dev,
661 type_name, index /* queue_idx */,
662 total_size, IONIC_ALIGN, socket_id);
665 IONIC_PRINT(ERR, "Cannot reserve queue DMA memory");
667 goto err_out_free_info;
670 new->base = new->base_z->addr;
671 new->base_pa = new->base_z->iova;
674 q_base_pa = new->base_pa;
676 cq_base = (void *)RTE_ALIGN((uintptr_t)q_base + q_size, PAGE_SIZE);
677 cq_base_pa = RTE_ALIGN(q_base_pa + q_size, PAGE_SIZE);
679 if (flags & IONIC_QCQ_F_SG) {
680 sg_base = (void *)RTE_ALIGN((uintptr_t)cq_base + cq_size,
682 sg_base_pa = RTE_ALIGN(cq_base_pa + cq_size, PAGE_SIZE);
683 ionic_q_sg_map(&new->q, sg_base, sg_base_pa);
686 IONIC_PRINT(DEBUG, "Q-Base-PA = %#jx CQ-Base-PA = %#jx "
688 q_base_pa, cq_base_pa, sg_base_pa);
690 ionic_q_map(&new->q, q_base, q_base_pa);
691 ionic_cq_map(&new->cq, cq_base, cq_base_pa);
698 rte_free(new->q.info);
706 ionic_qcq_free(struct ionic_qcq *qcq)
711 rte_memzone_free(qcq->base_z);
716 rte_free(qcq->q.info);
724 ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t socket_id, uint32_t index,
725 uint16_t nrxq_descs, struct ionic_rx_qcq **rxq_out)
727 struct ionic_rx_qcq *rxq;
731 flags = IONIC_QCQ_F_SG;
732 err = ionic_qcq_alloc(lif,
734 sizeof(struct ionic_rx_qcq),
740 sizeof(struct ionic_rxq_desc),
741 sizeof(struct ionic_rxq_comp),
742 sizeof(struct ionic_rxq_sg_desc),
743 (struct ionic_qcq **)&rxq);
749 lif->rxqcqs[index] = rxq;
756 ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t socket_id, uint32_t index,
757 uint16_t ntxq_descs, struct ionic_tx_qcq **txq_out)
759 struct ionic_tx_qcq *txq;
760 uint16_t flags, num_segs_fw;
763 flags = IONIC_QCQ_F_SG;
765 num_segs_fw = IONIC_TX_MAX_SG_ELEMS_V1 + 1;
767 err = ionic_qcq_alloc(lif,
769 sizeof(struct ionic_tx_qcq),
775 sizeof(struct ionic_txq_desc),
776 sizeof(struct ionic_txq_comp),
777 sizeof(struct ionic_txq_sg_desc_v1),
778 (struct ionic_qcq **)&txq);
783 txq->num_segs_fw = num_segs_fw;
785 lif->txqcqs[index] = txq;
792 ionic_admin_qcq_alloc(struct ionic_lif *lif)
797 err = ionic_qcq_alloc(lif,
799 sizeof(struct ionic_admin_qcq),
805 sizeof(struct ionic_admin_cmd),
806 sizeof(struct ionic_admin_comp),
808 (struct ionic_qcq **)&lif->adminqcq);
816 ionic_notify_qcq_alloc(struct ionic_lif *lif)
818 struct ionic_notify_qcq *nqcq;
819 struct ionic_dev *idev = &lif->adapter->idev;
823 err = ionic_qcq_alloc(lif,
825 sizeof(struct ionic_notify_qcq),
830 IONIC_NOTIFYQ_LENGTH,
831 sizeof(struct ionic_notifyq_cmd),
832 sizeof(union ionic_notifyq_comp),
834 (struct ionic_qcq **)&nqcq);
838 err = ionic_intr_alloc(lif, &nqcq->intr);
840 ionic_qcq_free(&nqcq->qcq);
844 ionic_intr_mask_assert(idev->intr_ctrl, nqcq->intr.index,
845 IONIC_INTR_MASK_SET);
847 lif->notifyqcq = nqcq;
853 ionic_bus_map_dbpage(struct ionic_adapter *adapter, int page_num)
855 char *vaddr = adapter->bars[IONIC_PCI_BAR_DBELL].vaddr;
857 if (adapter->num_bars <= IONIC_PCI_BAR_DBELL)
860 return (void *)&vaddr[page_num << PAGE_SHIFT];
864 ionic_lif_queue_identify(struct ionic_lif *lif)
866 struct ionic_adapter *adapter = lif->adapter;
867 struct ionic_dev *idev = &adapter->idev;
868 union ionic_q_identity *q_ident = &adapter->ident.txq;
869 uint32_t q_words = RTE_DIM(q_ident->words);
870 uint32_t cmd_words = RTE_DIM(idev->dev_cmd->data);
871 uint32_t i, nwords, qtype;
874 for (qtype = 0; qtype < RTE_DIM(ionic_qtype_vers); qtype++) {
875 struct ionic_qtype_info *qti = &lif->qtype_info[qtype];
877 /* Filter out the types this driver knows about */
879 case IONIC_QTYPE_ADMINQ:
880 case IONIC_QTYPE_NOTIFYQ:
881 case IONIC_QTYPE_RXQ:
882 case IONIC_QTYPE_TXQ:
888 memset(qti, 0, sizeof(*qti));
890 ionic_dev_cmd_queue_identify(idev, IONIC_LIF_TYPE_CLASSIC,
891 qtype, ionic_qtype_vers[qtype]);
892 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
893 if (err == -EINVAL) {
894 IONIC_PRINT(ERR, "qtype %d not supported\n", qtype);
896 } else if (err == -EIO) {
897 IONIC_PRINT(ERR, "q_ident failed, older FW\n");
900 IONIC_PRINT(ERR, "q_ident failed, qtype %d: %d\n",
905 nwords = RTE_MIN(q_words, cmd_words);
906 for (i = 0; i < nwords; i++)
907 q_ident->words[i] = ioread32(&idev->dev_cmd->data[i]);
909 qti->version = q_ident->version;
910 qti->supported = q_ident->supported;
911 qti->features = rte_le_to_cpu_64(q_ident->features);
912 qti->desc_sz = rte_le_to_cpu_16(q_ident->desc_sz);
913 qti->comp_sz = rte_le_to_cpu_16(q_ident->comp_sz);
914 qti->sg_desc_sz = rte_le_to_cpu_16(q_ident->sg_desc_sz);
915 qti->max_sg_elems = rte_le_to_cpu_16(q_ident->max_sg_elems);
916 qti->sg_desc_stride =
917 rte_le_to_cpu_16(q_ident->sg_desc_stride);
919 IONIC_PRINT(DEBUG, " qtype[%d].version = %d",
920 qtype, qti->version);
921 IONIC_PRINT(DEBUG, " qtype[%d].supported = %#x",
922 qtype, qti->supported);
923 IONIC_PRINT(DEBUG, " qtype[%d].features = %#jx",
924 qtype, qti->features);
925 IONIC_PRINT(DEBUG, " qtype[%d].desc_sz = %d",
926 qtype, qti->desc_sz);
927 IONIC_PRINT(DEBUG, " qtype[%d].comp_sz = %d",
928 qtype, qti->comp_sz);
929 IONIC_PRINT(DEBUG, " qtype[%d].sg_desc_sz = %d",
930 qtype, qti->sg_desc_sz);
931 IONIC_PRINT(DEBUG, " qtype[%d].max_sg_elems = %d",
932 qtype, qti->max_sg_elems);
933 IONIC_PRINT(DEBUG, " qtype[%d].sg_desc_stride = %d",
934 qtype, qti->sg_desc_stride);
939 ionic_lif_alloc(struct ionic_lif *lif)
941 struct ionic_adapter *adapter = lif->adapter;
942 uint32_t socket_id = rte_socket_id();
946 * lif->name was zeroed on allocation.
947 * Copy (sizeof() - 1) bytes to ensure that it is NULL terminated.
949 memcpy(lif->name, lif->eth_dev->data->name, sizeof(lif->name) - 1);
951 IONIC_PRINT(DEBUG, "LIF: %s", lif->name);
953 ionic_lif_queue_identify(lif);
955 if (lif->qtype_info[IONIC_QTYPE_TXQ].version < 1) {
956 IONIC_PRINT(ERR, "FW too old, please upgrade");
960 IONIC_PRINT(DEBUG, "Allocating Lif Info");
962 rte_spinlock_init(&lif->adminq_lock);
963 rte_spinlock_init(&lif->adminq_service_lock);
965 lif->kern_dbpage = ionic_bus_map_dbpage(adapter, 0);
966 if (!lif->kern_dbpage) {
967 IONIC_PRINT(ERR, "Cannot map dbpage, aborting");
971 lif->txqcqs = rte_zmalloc("ionic", sizeof(*lif->txqcqs) *
972 adapter->max_ntxqs_per_lif, 0);
975 IONIC_PRINT(ERR, "Cannot allocate tx queues array");
979 lif->rxqcqs = rte_zmalloc("ionic", sizeof(*lif->rxqcqs) *
980 adapter->max_nrxqs_per_lif, 0);
983 IONIC_PRINT(ERR, "Cannot allocate rx queues array");
987 IONIC_PRINT(DEBUG, "Allocating Notify Queue");
989 err = ionic_notify_qcq_alloc(lif);
991 IONIC_PRINT(ERR, "Cannot allocate notify queue");
995 IONIC_PRINT(DEBUG, "Allocating Admin Queue");
997 err = ionic_admin_qcq_alloc(lif);
999 IONIC_PRINT(ERR, "Cannot allocate admin queue");
1003 IONIC_PRINT(DEBUG, "Allocating Lif Info");
1005 lif->info_sz = RTE_ALIGN(sizeof(*lif->info), PAGE_SIZE);
1007 lif->info_z = rte_eth_dma_zone_reserve(lif->eth_dev,
1008 "lif_info", 0 /* queue_idx*/,
1009 lif->info_sz, IONIC_ALIGN, socket_id);
1011 IONIC_PRINT(ERR, "Cannot allocate lif info memory");
1015 lif->info = lif->info_z->addr;
1016 lif->info_pa = lif->info_z->iova;
1022 ionic_lif_free(struct ionic_lif *lif)
1024 if (lif->notifyqcq) {
1025 ionic_qcq_free(&lif->notifyqcq->qcq);
1026 lif->notifyqcq = NULL;
1029 if (lif->adminqcq) {
1030 ionic_qcq_free(&lif->adminqcq->qcq);
1031 lif->adminqcq = NULL;
1035 rte_free(lif->txqcqs);
1040 rte_free(lif->rxqcqs);
1045 rte_memzone_free(lif->info_z);
1051 ionic_lif_free_queues(struct ionic_lif *lif)
1055 for (i = 0; i < lif->ntxqcqs; i++) {
1056 ionic_dev_tx_queue_release(lif->eth_dev->data->tx_queues[i]);
1057 lif->eth_dev->data->tx_queues[i] = NULL;
1059 for (i = 0; i < lif->nrxqcqs; i++) {
1060 ionic_dev_rx_queue_release(lif->eth_dev->data->rx_queues[i]);
1061 lif->eth_dev->data->rx_queues[i] = NULL;
1066 ionic_lif_rss_config(struct ionic_lif *lif,
1067 const uint16_t types, const uint8_t *key, const uint32_t *indir)
1069 struct ionic_adapter *adapter = lif->adapter;
1070 struct ionic_admin_ctx ctx = {
1071 .pending_work = true,
1072 .cmd.lif_setattr = {
1073 .opcode = IONIC_CMD_LIF_SETATTR,
1074 .attr = IONIC_LIF_ATTR_RSS,
1075 .rss.types = rte_cpu_to_le_16(types),
1076 .rss.addr = rte_cpu_to_le_64(lif->rss_ind_tbl_pa),
1081 rte_le_to_cpu_16(adapter->ident.lif.eth.rss_ind_tbl_sz);
1085 lif->rss_types = types;
1088 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE);
1091 for (i = 0; i < tbl_sz; i++)
1092 lif->rss_ind_tbl[i] = indir[i];
1094 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key,
1095 IONIC_RSS_HASH_KEY_SIZE);
1097 return ionic_adminq_post_wait(lif, &ctx);
1101 ionic_lif_rss_setup(struct ionic_lif *lif)
1103 struct ionic_adapter *adapter = lif->adapter;
1104 static const uint8_t toeplitz_symmetric_key[] = {
1105 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
1106 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
1107 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
1108 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
1109 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
1113 rte_le_to_cpu_16(adapter->ident.lif.eth.rss_ind_tbl_sz);
1117 if (!lif->rss_ind_tbl_z) {
1118 lif->rss_ind_tbl_z = rte_eth_dma_zone_reserve(lif->eth_dev,
1119 "rss_ind_tbl", 0 /* queue_idx */,
1120 sizeof(*lif->rss_ind_tbl) * tbl_sz,
1121 IONIC_ALIGN, rte_socket_id());
1122 if (!lif->rss_ind_tbl_z) {
1123 IONIC_PRINT(ERR, "OOM");
1127 lif->rss_ind_tbl = lif->rss_ind_tbl_z->addr;
1128 lif->rss_ind_tbl_pa = lif->rss_ind_tbl_z->iova;
1131 if (lif->rss_ind_tbl_nrxqcqs != lif->nrxqcqs) {
1132 lif->rss_ind_tbl_nrxqcqs = lif->nrxqcqs;
1134 /* Fill indirection table with 'default' values */
1135 for (i = 0; i < tbl_sz; i++)
1136 lif->rss_ind_tbl[i] = i % lif->nrxqcqs;
1139 return ionic_lif_rss_config(lif, IONIC_RSS_OFFLOAD_ALL,
1140 toeplitz_symmetric_key, NULL);
1144 ionic_lif_rss_teardown(struct ionic_lif *lif)
1146 if (!lif->rss_ind_tbl)
1149 if (lif->rss_ind_tbl_z) {
1150 /* Disable RSS on the NIC */
1151 ionic_lif_rss_config(lif, 0x0, NULL, NULL);
1153 lif->rss_ind_tbl = NULL;
1154 lif->rss_ind_tbl_pa = 0;
1155 rte_memzone_free(lif->rss_ind_tbl_z);
1156 lif->rss_ind_tbl_z = NULL;
1161 ionic_lif_txq_deinit(struct ionic_tx_qcq *txq)
1163 txq->flags &= ~IONIC_QCQ_F_INITED;
1167 ionic_lif_rxq_deinit(struct ionic_rx_qcq *rxq)
1169 rxq->flags &= ~IONIC_QCQ_F_INITED;
1173 ionic_lif_adminq_deinit(struct ionic_lif *lif)
1175 lif->adminqcq->flags &= ~IONIC_QCQ_F_INITED;
1179 ionic_lif_notifyq_deinit(struct ionic_lif *lif)
1181 struct ionic_notify_qcq *nqcq = lif->notifyqcq;
1182 struct ionic_dev *idev = &lif->adapter->idev;
1184 if (!(nqcq->flags & IONIC_QCQ_F_INITED))
1187 ionic_intr_mask(idev->intr_ctrl, nqcq->intr.index,
1188 IONIC_INTR_MASK_SET);
1190 nqcq->flags &= ~IONIC_QCQ_F_INITED;
1193 /* This acts like ionic_napi */
1195 ionic_qcq_service(struct ionic_qcq *qcq, int budget, ionic_cq_cb cb,
1198 struct ionic_cq *cq = &qcq->cq;
1201 work_done = ionic_cq_service(cq, budget, cb, cb_arg);
1207 ionic_link_status_check(struct ionic_lif *lif)
1209 struct ionic_adapter *adapter = lif->adapter;
1212 lif->state &= ~IONIC_LIF_F_LINK_CHECK_NEEDED;
1217 link_up = (lif->info->status.link_status == IONIC_PORT_OPER_STATUS_UP);
1219 if ((link_up && adapter->link_up) ||
1220 (!link_up && !adapter->link_up))
1224 adapter->link_speed =
1225 rte_le_to_cpu_32(lif->info->status.link_speed);
1226 IONIC_PRINT(DEBUG, "Link up - %d Gbps",
1227 adapter->link_speed);
1229 IONIC_PRINT(DEBUG, "Link down");
1232 adapter->link_up = link_up;
1233 ionic_dev_link_update(lif->eth_dev, 0);
1237 ionic_lif_handle_fw_down(struct ionic_lif *lif)
1239 if (lif->state & IONIC_LIF_F_FW_RESET)
1242 lif->state |= IONIC_LIF_F_FW_RESET;
1244 if (lif->state & IONIC_LIF_F_UP) {
1246 "Surprise FW stop, stopping %s\n", lif->name);
1247 ionic_lif_stop(lif);
1250 IONIC_PRINT(NOTICE, "FW down, %s stopped", lif->name);
1254 ionic_notifyq_cb(struct ionic_cq *cq, uint16_t cq_desc_index, void *cb_arg)
1256 union ionic_notifyq_comp *cq_desc_base = cq->base;
1257 union ionic_notifyq_comp *cq_desc = &cq_desc_base[cq_desc_index];
1258 struct ionic_lif *lif = cb_arg;
1260 IONIC_PRINT(DEBUG, "Notifyq callback eid = %jd ecode = %d",
1261 cq_desc->event.eid, cq_desc->event.ecode);
1263 /* Have we run out of new completions to process? */
1264 if (!(cq_desc->event.eid > lif->last_eid))
1267 lif->last_eid = cq_desc->event.eid;
1269 switch (cq_desc->event.ecode) {
1270 case IONIC_EVENT_LINK_CHANGE:
1272 "Notifyq IONIC_EVENT_LINK_CHANGE %s "
1273 "eid=%jd link_status=%d link_speed=%d",
1276 cq_desc->link_change.link_status,
1277 cq_desc->link_change.link_speed);
1279 lif->state |= IONIC_LIF_F_LINK_CHECK_NEEDED;
1282 case IONIC_EVENT_RESET:
1284 "Notifyq IONIC_EVENT_RESET %s "
1285 "eid=%jd, reset_code=%d state=%d",
1288 cq_desc->reset.reset_code,
1289 cq_desc->reset.state);
1290 ionic_lif_handle_fw_down(lif);
1294 IONIC_PRINT(WARNING, "Notifyq bad event ecode=%d eid=%jd",
1295 cq_desc->event.ecode, cq_desc->event.eid);
1303 ionic_notifyq_handler(struct ionic_lif *lif, int budget)
1305 struct ionic_dev *idev = &lif->adapter->idev;
1306 struct ionic_notify_qcq *nqcq = lif->notifyqcq;
1309 if (!(nqcq->flags & IONIC_QCQ_F_INITED)) {
1310 IONIC_PRINT(DEBUG, "Notifyq not yet initialized");
1314 ionic_intr_mask(idev->intr_ctrl, nqcq->intr.index,
1315 IONIC_INTR_MASK_SET);
1317 work_done = ionic_qcq_service(&nqcq->qcq, budget,
1318 ionic_notifyq_cb, lif);
1320 if (lif->state & IONIC_LIF_F_LINK_CHECK_NEEDED)
1321 ionic_link_status_check(lif);
1323 ionic_intr_credits(idev->intr_ctrl, nqcq->intr.index,
1324 work_done, IONIC_INTR_CRED_RESET_COALESCE);
1326 ionic_intr_mask(idev->intr_ctrl, nqcq->intr.index,
1327 IONIC_INTR_MASK_CLEAR);
1333 ionic_lif_adminq_init(struct ionic_lif *lif)
1335 struct ionic_dev *idev = &lif->adapter->idev;
1336 struct ionic_admin_qcq *aqcq = lif->adminqcq;
1337 struct ionic_queue *q = &aqcq->qcq.q;
1338 struct ionic_q_init_comp comp;
1341 ionic_dev_cmd_adminq_init(idev, &aqcq->qcq);
1342 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1346 ionic_dev_cmd_comp(idev, &comp);
1348 q->hw_type = comp.hw_type;
1349 q->hw_index = rte_le_to_cpu_32(comp.hw_index);
1350 q->db = ionic_db_map(lif, q);
1352 IONIC_PRINT(DEBUG, "adminq->hw_type %d", q->hw_type);
1353 IONIC_PRINT(DEBUG, "adminq->hw_index %d", q->hw_index);
1354 IONIC_PRINT(DEBUG, "adminq->db %p", q->db);
1356 aqcq->flags |= IONIC_QCQ_F_INITED;
1362 ionic_lif_notifyq_init(struct ionic_lif *lif)
1364 struct ionic_dev *idev = &lif->adapter->idev;
1365 struct ionic_notify_qcq *nqcq = lif->notifyqcq;
1366 struct ionic_queue *q = &nqcq->qcq.q;
1369 struct ionic_admin_ctx ctx = {
1370 .pending_work = true,
1372 .opcode = IONIC_CMD_Q_INIT,
1374 .ver = lif->qtype_info[q->type].version,
1375 .index = rte_cpu_to_le_32(q->index),
1376 .intr_index = rte_cpu_to_le_16(nqcq->intr.index),
1377 .flags = rte_cpu_to_le_16(IONIC_QINIT_F_IRQ |
1379 .ring_size = rte_log2_u32(q->num_descs),
1380 .ring_base = rte_cpu_to_le_64(q->base_pa),
1384 IONIC_PRINT(DEBUG, "notifyq_init.index %d", q->index);
1385 IONIC_PRINT(DEBUG, "notifyq_init.ring_base 0x%" PRIx64 "", q->base_pa);
1386 IONIC_PRINT(DEBUG, "notifyq_init.ring_size %d",
1387 ctx.cmd.q_init.ring_size);
1388 IONIC_PRINT(DEBUG, "notifyq_init.ver %u", ctx.cmd.q_init.ver);
1390 err = ionic_adminq_post_wait(lif, &ctx);
1394 q->hw_type = ctx.comp.q_init.hw_type;
1395 q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index);
1398 IONIC_PRINT(DEBUG, "notifyq->hw_type %d", q->hw_type);
1399 IONIC_PRINT(DEBUG, "notifyq->hw_index %d", q->hw_index);
1400 IONIC_PRINT(DEBUG, "notifyq->db %p", q->db);
1402 ionic_intr_mask(idev->intr_ctrl, nqcq->intr.index,
1403 IONIC_INTR_MASK_CLEAR);
1405 nqcq->flags |= IONIC_QCQ_F_INITED;
1411 ionic_lif_set_features(struct ionic_lif *lif)
1413 struct ionic_admin_ctx ctx = {
1414 .pending_work = true,
1415 .cmd.lif_setattr = {
1416 .opcode = IONIC_CMD_LIF_SETATTR,
1417 .attr = IONIC_LIF_ATTR_FEATURES,
1418 .features = rte_cpu_to_le_64(lif->features),
1423 err = ionic_adminq_post_wait(lif, &ctx);
1427 lif->hw_features = rte_le_to_cpu_64(ctx.cmd.lif_setattr.features &
1428 ctx.comp.lif_setattr.features);
1430 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
1431 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_TX_TAG");
1432 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
1433 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_STRIP");
1434 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
1435 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_FILTER");
1436 if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
1437 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_HASH");
1438 if (lif->hw_features & IONIC_ETH_HW_TX_SG)
1439 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_SG");
1440 if (lif->hw_features & IONIC_ETH_HW_RX_SG)
1441 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_SG");
1442 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
1443 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_CSUM");
1444 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
1445 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_CSUM");
1446 if (lif->hw_features & IONIC_ETH_HW_TSO)
1447 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO");
1448 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
1449 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPV6");
1450 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
1451 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_ECN");
1452 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
1453 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE");
1454 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
1455 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE_CSUM");
1456 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
1457 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP4");
1458 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
1459 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP6");
1460 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
1461 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP");
1462 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
1463 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP_CSUM");
1469 ionic_lif_txq_init(struct ionic_tx_qcq *txq)
1471 struct ionic_qcq *qcq = &txq->qcq;
1472 struct ionic_queue *q = &qcq->q;
1473 struct ionic_lif *lif = qcq->lif;
1474 struct ionic_cq *cq = &qcq->cq;
1475 struct ionic_admin_ctx ctx = {
1476 .pending_work = true,
1478 .opcode = IONIC_CMD_Q_INIT,
1480 .ver = lif->qtype_info[q->type].version,
1481 .index = rte_cpu_to_le_32(q->index),
1482 .flags = rte_cpu_to_le_16(IONIC_QINIT_F_SG |
1484 .intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE),
1485 .ring_size = rte_log2_u32(q->num_descs),
1486 .ring_base = rte_cpu_to_le_64(q->base_pa),
1487 .cq_ring_base = rte_cpu_to_le_64(cq->base_pa),
1488 .sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa),
1493 IONIC_PRINT(DEBUG, "txq_init.index %d", q->index);
1494 IONIC_PRINT(DEBUG, "txq_init.ring_base 0x%" PRIx64 "", q->base_pa);
1495 IONIC_PRINT(DEBUG, "txq_init.ring_size %d",
1496 ctx.cmd.q_init.ring_size);
1497 IONIC_PRINT(DEBUG, "txq_init.ver %u", ctx.cmd.q_init.ver);
1499 err = ionic_adminq_post_wait(lif, &ctx);
1503 q->hw_type = ctx.comp.q_init.hw_type;
1504 q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index);
1505 q->db = ionic_db_map(lif, q);
1507 IONIC_PRINT(DEBUG, "txq->hw_type %d", q->hw_type);
1508 IONIC_PRINT(DEBUG, "txq->hw_index %d", q->hw_index);
1509 IONIC_PRINT(DEBUG, "txq->db %p", q->db);
1511 txq->flags |= IONIC_QCQ_F_INITED;
1517 ionic_lif_rxq_init(struct ionic_rx_qcq *rxq)
1519 struct ionic_qcq *qcq = &rxq->qcq;
1520 struct ionic_queue *q = &qcq->q;
1521 struct ionic_lif *lif = qcq->lif;
1522 struct ionic_cq *cq = &qcq->cq;
1523 struct ionic_admin_ctx ctx = {
1524 .pending_work = true,
1526 .opcode = IONIC_CMD_Q_INIT,
1528 .ver = lif->qtype_info[q->type].version,
1529 .index = rte_cpu_to_le_32(q->index),
1530 .flags = rte_cpu_to_le_16(IONIC_QINIT_F_SG |
1532 .intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE),
1533 .ring_size = rte_log2_u32(q->num_descs),
1534 .ring_base = rte_cpu_to_le_64(q->base_pa),
1535 .cq_ring_base = rte_cpu_to_le_64(cq->base_pa),
1536 .sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa),
1541 IONIC_PRINT(DEBUG, "rxq_init.index %d", q->index);
1542 IONIC_PRINT(DEBUG, "rxq_init.ring_base 0x%" PRIx64 "", q->base_pa);
1543 IONIC_PRINT(DEBUG, "rxq_init.ring_size %d",
1544 ctx.cmd.q_init.ring_size);
1545 IONIC_PRINT(DEBUG, "rxq_init.ver %u", ctx.cmd.q_init.ver);
1547 err = ionic_adminq_post_wait(lif, &ctx);
1551 q->hw_type = ctx.comp.q_init.hw_type;
1552 q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index);
1553 q->db = ionic_db_map(lif, q);
1555 rxq->flags |= IONIC_QCQ_F_INITED;
1557 IONIC_PRINT(DEBUG, "rxq->hw_type %d", q->hw_type);
1558 IONIC_PRINT(DEBUG, "rxq->hw_index %d", q->hw_index);
1559 IONIC_PRINT(DEBUG, "rxq->db %p", q->db);
1565 ionic_station_set(struct ionic_lif *lif)
1567 struct ionic_admin_ctx ctx = {
1568 .pending_work = true,
1569 .cmd.lif_getattr = {
1570 .opcode = IONIC_CMD_LIF_GETATTR,
1571 .attr = IONIC_LIF_ATTR_MAC,
1578 err = ionic_adminq_post_wait(lif, &ctx);
1582 memcpy(lif->mac_addr, ctx.comp.lif_getattr.mac, RTE_ETHER_ADDR_LEN);
1588 ionic_lif_set_name(struct ionic_lif *lif)
1590 struct ionic_admin_ctx ctx = {
1591 .pending_work = true,
1592 .cmd.lif_setattr = {
1593 .opcode = IONIC_CMD_LIF_SETATTR,
1594 .attr = IONIC_LIF_ATTR_NAME,
1598 memcpy(ctx.cmd.lif_setattr.name, lif->name,
1599 sizeof(ctx.cmd.lif_setattr.name) - 1);
1601 ionic_adminq_post_wait(lif, &ctx);
1605 ionic_lif_init(struct ionic_lif *lif)
1607 struct ionic_dev *idev = &lif->adapter->idev;
1608 struct ionic_q_init_comp comp;
1611 memset(&lif->stats_base, 0, sizeof(lif->stats_base));
1613 ionic_dev_cmd_lif_init(idev, lif->info_pa);
1614 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1615 ionic_dev_cmd_comp(idev, &comp);
1619 lif->hw_index = rte_cpu_to_le_16(comp.hw_index);
1621 err = ionic_lif_adminq_init(lif);
1625 err = ionic_lif_notifyq_init(lif);
1627 goto err_out_adminq_deinit;
1630 * Configure initial feature set
1631 * This will be updated later by the dev_configure() step
1633 lif->features = IONIC_ETH_HW_RX_HASH | IONIC_ETH_HW_VLAN_RX_FILTER;
1635 err = ionic_lif_set_features(lif);
1637 goto err_out_notifyq_deinit;
1639 err = ionic_rx_filters_init(lif);
1641 goto err_out_notifyq_deinit;
1643 err = ionic_station_set(lif);
1645 goto err_out_rx_filter_deinit;
1647 ionic_lif_set_name(lif);
1649 lif->state |= IONIC_LIF_F_INITED;
1653 err_out_rx_filter_deinit:
1654 ionic_rx_filters_deinit(lif);
1656 err_out_notifyq_deinit:
1657 ionic_lif_notifyq_deinit(lif);
1659 err_out_adminq_deinit:
1660 ionic_lif_adminq_deinit(lif);
1666 ionic_lif_deinit(struct ionic_lif *lif)
1668 if (!(lif->state & IONIC_LIF_F_INITED))
1671 ionic_rx_filters_deinit(lif);
1672 ionic_lif_rss_teardown(lif);
1673 ionic_lif_notifyq_deinit(lif);
1674 ionic_lif_adminq_deinit(lif);
1676 lif->state &= ~IONIC_LIF_F_INITED;
1680 ionic_lif_configure_vlan_offload(struct ionic_lif *lif, int mask)
1682 struct rte_eth_dev *eth_dev = lif->eth_dev;
1683 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1686 * IONIC_ETH_HW_VLAN_RX_FILTER cannot be turned off, so
1687 * set DEV_RX_OFFLOAD_VLAN_FILTER and ignore ETH_VLAN_FILTER_MASK
1689 rxmode->offloads |= DEV_RX_OFFLOAD_VLAN_FILTER;
1691 if (mask & ETH_VLAN_STRIP_MASK) {
1692 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1693 lif->features |= IONIC_ETH_HW_VLAN_RX_STRIP;
1695 lif->features &= ~IONIC_ETH_HW_VLAN_RX_STRIP;
1700 ionic_lif_configure(struct ionic_lif *lif)
1702 struct rte_eth_rxmode *rxmode = &lif->eth_dev->data->dev_conf.rxmode;
1703 struct rte_eth_txmode *txmode = &lif->eth_dev->data->dev_conf.txmode;
1704 struct ionic_identity *ident = &lif->adapter->ident;
1705 union ionic_lif_config *cfg = &ident->lif.eth.config;
1706 uint32_t ntxqs_per_lif =
1707 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]);
1708 uint32_t nrxqs_per_lif =
1709 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]);
1710 uint32_t nrxqs = lif->eth_dev->data->nb_rx_queues;
1711 uint32_t ntxqs = lif->eth_dev->data->nb_tx_queues;
1713 lif->port_id = lif->eth_dev->data->port_id;
1715 IONIC_PRINT(DEBUG, "Configuring LIF on port %u",
1719 nrxqs_per_lif = RTE_MIN(nrxqs_per_lif, nrxqs);
1722 ntxqs_per_lif = RTE_MIN(ntxqs_per_lif, ntxqs);
1724 lif->nrxqcqs = nrxqs_per_lif;
1725 lif->ntxqcqs = ntxqs_per_lif;
1727 /* Update the LIF configuration based on the eth_dev */
1730 * NB: While it is true that RSS_HASH is always enabled on ionic,
1731 * setting this flag unconditionally causes problems in DTS.
1732 * rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1737 if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM ||
1738 rxmode->offloads & DEV_RX_OFFLOAD_UDP_CKSUM ||
1739 rxmode->offloads & DEV_RX_OFFLOAD_TCP_CKSUM)
1740 lif->features |= IONIC_ETH_HW_RX_CSUM;
1742 lif->features &= ~IONIC_ETH_HW_RX_CSUM;
1744 if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER) {
1745 lif->features |= IONIC_ETH_HW_RX_SG;
1746 lif->eth_dev->data->scattered_rx = 1;
1748 lif->features &= ~IONIC_ETH_HW_RX_SG;
1749 lif->eth_dev->data->scattered_rx = 0;
1752 /* Covers VLAN_STRIP */
1753 ionic_lif_configure_vlan_offload(lif, ETH_VLAN_STRIP_MASK);
1757 if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
1758 txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
1759 txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM ||
1760 txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
1761 txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)
1762 lif->features |= IONIC_ETH_HW_TX_CSUM;
1764 lif->features &= ~IONIC_ETH_HW_TX_CSUM;
1766 if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
1767 lif->features |= IONIC_ETH_HW_VLAN_TX_TAG;
1769 lif->features &= ~IONIC_ETH_HW_VLAN_TX_TAG;
1771 if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
1772 lif->features |= IONIC_ETH_HW_TX_SG;
1774 lif->features &= ~IONIC_ETH_HW_TX_SG;
1776 if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
1777 lif->features |= IONIC_ETH_HW_TSO;
1778 lif->features |= IONIC_ETH_HW_TSO_IPV6;
1779 lif->features |= IONIC_ETH_HW_TSO_ECN;
1781 lif->features &= ~IONIC_ETH_HW_TSO;
1782 lif->features &= ~IONIC_ETH_HW_TSO_IPV6;
1783 lif->features &= ~IONIC_ETH_HW_TSO_ECN;
1788 ionic_lif_start(struct ionic_lif *lif)
1794 err = ionic_lif_rss_setup(lif);
1798 if (!lif->rx_mode) {
1799 IONIC_PRINT(DEBUG, "Setting RX mode on %s",
1802 rx_mode = IONIC_RX_MODE_F_UNICAST;
1803 rx_mode |= IONIC_RX_MODE_F_MULTICAST;
1804 rx_mode |= IONIC_RX_MODE_F_BROADCAST;
1806 ionic_set_rx_mode(lif, rx_mode);
1809 IONIC_PRINT(DEBUG, "Starting %u RX queues and %u TX queues "
1811 lif->nrxqcqs, lif->ntxqcqs, lif->port_id);
1813 for (i = 0; i < lif->nrxqcqs; i++) {
1814 struct ionic_rx_qcq *rxq = lif->rxqcqs[i];
1815 if (!(rxq->flags & IONIC_QCQ_F_DEFERRED)) {
1816 err = ionic_dev_rx_queue_start(lif->eth_dev, i);
1823 for (i = 0; i < lif->ntxqcqs; i++) {
1824 struct ionic_tx_qcq *txq = lif->txqcqs[i];
1825 if (!(txq->flags & IONIC_QCQ_F_DEFERRED)) {
1826 err = ionic_dev_tx_queue_start(lif->eth_dev, i);
1833 /* Carrier ON here */
1834 lif->state |= IONIC_LIF_F_UP;
1836 ionic_link_status_check(lif);
1842 ionic_lif_identify(struct ionic_adapter *adapter)
1844 struct ionic_dev *idev = &adapter->idev;
1845 struct ionic_identity *ident = &adapter->ident;
1846 union ionic_lif_config *cfg = &ident->lif.eth.config;
1847 uint32_t lif_words = RTE_DIM(ident->lif.words);
1848 uint32_t cmd_words = RTE_DIM(idev->dev_cmd->data);
1852 ionic_dev_cmd_lif_identify(idev, IONIC_LIF_TYPE_CLASSIC,
1853 IONIC_IDENTITY_VERSION_1);
1854 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1858 nwords = RTE_MIN(lif_words, cmd_words);
1859 for (i = 0; i < nwords; i++)
1860 ident->lif.words[i] = ioread32(&idev->dev_cmd->data[i]);
1862 IONIC_PRINT(INFO, "capabilities 0x%" PRIx64 " ",
1863 rte_le_to_cpu_64(ident->lif.capabilities));
1865 IONIC_PRINT(INFO, "eth.max_ucast_filters 0x%" PRIx32 " ",
1866 rte_le_to_cpu_32(ident->lif.eth.max_ucast_filters));
1867 IONIC_PRINT(INFO, "eth.max_mcast_filters 0x%" PRIx32 " ",
1868 rte_le_to_cpu_32(ident->lif.eth.max_mcast_filters));
1870 IONIC_PRINT(INFO, "eth.features 0x%" PRIx64 " ",
1871 rte_le_to_cpu_64(cfg->features));
1872 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_ADMINQ] 0x%" PRIx32 " ",
1873 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_ADMINQ]));
1874 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] 0x%" PRIx32 " ",
1875 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_NOTIFYQ]));
1876 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_RXQ] 0x%" PRIx32 " ",
1877 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]));
1878 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_TXQ] 0x%" PRIx32 " ",
1879 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]));
1885 ionic_lifs_size(struct ionic_adapter *adapter)
1887 struct ionic_identity *ident = &adapter->ident;
1888 union ionic_lif_config *cfg = &ident->lif.eth.config;
1889 uint32_t nintrs, dev_nintrs = rte_le_to_cpu_32(ident->dev.nintrs);
1891 adapter->max_ntxqs_per_lif =
1892 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]);
1893 adapter->max_nrxqs_per_lif =
1894 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]);
1896 nintrs = 1 /* notifyq */;
1898 if (nintrs > dev_nintrs) {
1900 "At most %d intr supported, minimum req'd is %u",
1901 dev_nintrs, nintrs);
1905 adapter->nintrs = nintrs;