1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
5 #include <rte_malloc.h>
6 #include <rte_ethdev_driver.h>
9 #include "ionic_logs.h"
10 #include "ionic_lif.h"
11 #include "ionic_ethdev.h"
12 #include "ionic_rx_filter.h"
13 #include "ionic_rxtx.h"
15 static int ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr);
16 static int ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr);
19 ionic_qcq_enable(struct ionic_qcq *qcq)
21 struct ionic_queue *q = &qcq->q;
22 struct ionic_lif *lif = q->lif;
23 struct ionic_dev *idev = &lif->adapter->idev;
24 struct ionic_admin_ctx ctx = {
27 .opcode = IONIC_CMD_Q_CONTROL,
28 .lif_index = lif->index,
31 .oper = IONIC_Q_ENABLE,
35 if (qcq->flags & IONIC_QCQ_F_INTR) {
36 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
37 IONIC_INTR_MASK_CLEAR);
40 return ionic_adminq_post_wait(lif, &ctx);
44 ionic_qcq_disable(struct ionic_qcq *qcq)
46 struct ionic_queue *q = &qcq->q;
47 struct ionic_lif *lif = q->lif;
48 struct ionic_dev *idev = &lif->adapter->idev;
49 struct ionic_admin_ctx ctx = {
52 .opcode = IONIC_CMD_Q_CONTROL,
53 .lif_index = lif->index,
56 .oper = IONIC_Q_DISABLE,
60 if (qcq->flags & IONIC_QCQ_F_INTR) {
61 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
65 return ionic_adminq_post_wait(lif, &ctx);
69 ionic_lif_stop(struct ionic_lif *lif __rte_unused)
71 /* Carrier OFF here */
77 ionic_lif_reset(struct ionic_lif *lif)
79 struct ionic_dev *idev = &lif->adapter->idev;
83 ionic_dev_cmd_lif_reset(idev, lif->index);
84 ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
88 ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr)
90 struct ionic_admin_ctx ctx = {
92 .cmd.rx_filter_add = {
93 .opcode = IONIC_CMD_RX_FILTER_ADD,
94 .match = IONIC_RX_FILTER_MATCH_MAC,
99 memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, RTE_ETHER_ADDR_LEN);
101 err = ionic_adminq_post_wait(lif, &ctx);
105 IONIC_PRINT(INFO, "rx_filter add (id %d)",
106 ctx.comp.rx_filter_add.filter_id);
108 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);
112 ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr)
114 struct ionic_admin_ctx ctx = {
115 .pending_work = true,
116 .cmd.rx_filter_del = {
117 .opcode = IONIC_CMD_RX_FILTER_DEL,
120 struct ionic_rx_filter *f;
125 rte_spinlock_lock(&lif->rx_filters.lock);
127 f = ionic_rx_filter_by_addr(lif, addr);
129 rte_spinlock_unlock(&lif->rx_filters.lock);
133 ctx.cmd.rx_filter_del.filter_id = f->filter_id;
134 ionic_rx_filter_free(f);
136 rte_spinlock_unlock(&lif->rx_filters.lock);
138 err = ionic_adminq_post_wait(lif, &ctx);
142 IONIC_PRINT(INFO, "rx_filter del (id %d)",
143 ctx.cmd.rx_filter_del.filter_id);
149 ionic_dev_add_mac(struct rte_eth_dev *eth_dev,
150 struct rte_ether_addr *mac_addr,
151 uint32_t index __rte_unused, uint32_t pool __rte_unused)
153 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
157 return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr);
161 ionic_dev_remove_mac(struct rte_eth_dev *eth_dev, uint32_t index __rte_unused)
163 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
164 struct ionic_adapter *adapter = lif->adapter;
168 if (index >= adapter->max_mac_addrs) {
170 "Index %u is above MAC filter limit %u",
171 index, adapter->max_mac_addrs);
175 if (!rte_is_valid_assigned_ether_addr(ð_dev->data->mac_addrs[index]))
178 ionic_lif_addr_del(lif, (const uint8_t *)
179 ð_dev->data->mac_addrs[index]);
183 ionic_dev_set_mac(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr)
185 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
189 if (mac_addr == NULL) {
190 IONIC_PRINT(NOTICE, "New mac is null");
194 if (!rte_is_zero_ether_addr((struct rte_ether_addr *)lif->mac_addr)) {
195 IONIC_PRINT(INFO, "Deleting mac addr %pM",
197 ionic_lif_addr_del(lif, lif->mac_addr);
198 memset(lif->mac_addr, 0, RTE_ETHER_ADDR_LEN);
201 IONIC_PRINT(INFO, "Updating mac addr");
203 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)lif->mac_addr);
205 return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr);
209 ionic_vlan_rx_add_vid(struct ionic_lif *lif, uint16_t vid)
211 struct ionic_admin_ctx ctx = {
212 .pending_work = true,
213 .cmd.rx_filter_add = {
214 .opcode = IONIC_CMD_RX_FILTER_ADD,
215 .match = IONIC_RX_FILTER_MATCH_VLAN,
221 err = ionic_adminq_post_wait(lif, &ctx);
225 IONIC_PRINT(INFO, "rx_filter add VLAN %d (id %d)", vid,
226 ctx.comp.rx_filter_add.filter_id);
228 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);
232 ionic_vlan_rx_kill_vid(struct ionic_lif *lif, uint16_t vid)
234 struct ionic_admin_ctx ctx = {
235 .pending_work = true,
236 .cmd.rx_filter_del = {
237 .opcode = IONIC_CMD_RX_FILTER_DEL,
240 struct ionic_rx_filter *f;
245 rte_spinlock_lock(&lif->rx_filters.lock);
247 f = ionic_rx_filter_by_vlan(lif, vid);
249 rte_spinlock_unlock(&lif->rx_filters.lock);
253 ctx.cmd.rx_filter_del.filter_id = f->filter_id;
254 ionic_rx_filter_free(f);
255 rte_spinlock_unlock(&lif->rx_filters.lock);
257 err = ionic_adminq_post_wait(lif, &ctx);
261 IONIC_PRINT(INFO, "rx_filter del VLAN %d (id %d)", vid,
262 ctx.cmd.rx_filter_del.filter_id);
268 ionic_dev_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id,
271 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
275 err = ionic_vlan_rx_add_vid(lif, vlan_id);
277 err = ionic_vlan_rx_kill_vid(lif, vlan_id);
283 ionic_lif_rx_mode(struct ionic_lif *lif, uint32_t rx_mode)
285 struct ionic_admin_ctx ctx = {
286 .pending_work = true,
288 .opcode = IONIC_CMD_RX_MODE_SET,
289 .lif_index = lif->index,
295 if (rx_mode & IONIC_RX_MODE_F_UNICAST)
296 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_UNICAST");
297 if (rx_mode & IONIC_RX_MODE_F_MULTICAST)
298 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_MULTICAST");
299 if (rx_mode & IONIC_RX_MODE_F_BROADCAST)
300 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_BROADCAST");
301 if (rx_mode & IONIC_RX_MODE_F_PROMISC)
302 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_PROMISC");
303 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI)
304 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_ALLMULTI");
306 err = ionic_adminq_post_wait(lif, &ctx);
308 IONIC_PRINT(ERR, "Failure setting RX mode");
312 ionic_set_rx_mode(struct ionic_lif *lif, uint32_t rx_mode)
314 if (lif->rx_mode != rx_mode) {
315 lif->rx_mode = rx_mode;
316 ionic_lif_rx_mode(lif, rx_mode);
321 ionic_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
323 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
324 uint32_t rx_mode = lif->rx_mode;
328 rx_mode |= IONIC_RX_MODE_F_PROMISC;
330 ionic_set_rx_mode(lif, rx_mode);
336 ionic_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
338 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
339 uint32_t rx_mode = lif->rx_mode;
341 rx_mode &= ~IONIC_RX_MODE_F_PROMISC;
343 ionic_set_rx_mode(lif, rx_mode);
349 ionic_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
351 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
352 uint32_t rx_mode = lif->rx_mode;
354 rx_mode |= IONIC_RX_MODE_F_ALLMULTI;
356 ionic_set_rx_mode(lif, rx_mode);
362 ionic_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
364 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
365 uint32_t rx_mode = lif->rx_mode;
367 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI;
369 ionic_set_rx_mode(lif, rx_mode);
375 ionic_lif_change_mtu(struct ionic_lif *lif, int new_mtu)
377 struct ionic_admin_ctx ctx = {
378 .pending_work = true,
380 .opcode = IONIC_CMD_LIF_SETATTR,
382 .attr = IONIC_LIF_ATTR_MTU,
388 err = ionic_adminq_post_wait(lif, &ctx);
398 ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr)
400 struct ionic_adapter *adapter = lif->adapter;
401 struct ionic_dev *idev = &adapter->idev;
405 * Note: interrupt handler is called for index = 0 only
406 * (we use interrupts for the notifyq only anyway,
407 * which hash index = 0)
410 for (index = 0; index < adapter->nintrs; index++)
411 if (!adapter->intrs[index])
414 if (index == adapter->nintrs)
417 adapter->intrs[index] = true;
419 ionic_intr_init(idev, intr, index);
425 ionic_intr_free(struct ionic_lif *lif, struct ionic_intr_info *intr)
427 if (intr->index != IONIC_INTR_INDEX_NOT_ASSIGNED)
428 lif->adapter->intrs[intr->index] = false;
432 ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type,
434 const char *base, uint32_t flags,
437 uint32_t cq_desc_size,
438 uint32_t sg_desc_size,
439 uint32_t pid, struct ionic_qcq **qcq)
441 struct ionic_dev *idev = &lif->adapter->idev;
442 struct ionic_qcq *new;
443 uint32_t q_size, cq_size, sg_size, total_size;
444 void *q_base, *cq_base, *sg_base;
445 rte_iova_t q_base_pa = 0;
446 rte_iova_t cq_base_pa = 0;
447 rte_iova_t sg_base_pa = 0;
448 uint32_t socket_id = rte_socket_id();
453 q_size = num_descs * desc_size;
454 cq_size = num_descs * cq_desc_size;
455 sg_size = num_descs * sg_desc_size;
457 total_size = RTE_ALIGN(q_size, PAGE_SIZE) +
458 RTE_ALIGN(cq_size, PAGE_SIZE);
460 * Note: aligning q_size/cq_size is not enough due to cq_base address
461 * aligning as q_base could be not aligned to the page.
464 total_size += PAGE_SIZE;
466 if (flags & IONIC_QCQ_F_SG) {
467 total_size += RTE_ALIGN(sg_size, PAGE_SIZE);
468 total_size += PAGE_SIZE;
471 new = rte_zmalloc("ionic", sizeof(*new), 0);
473 IONIC_PRINT(ERR, "Cannot allocate queue structure");
480 new->q.info = rte_zmalloc("ionic", sizeof(*new->q.info) * num_descs, 0);
482 IONIC_PRINT(ERR, "Cannot allocate queue info");
488 err = ionic_q_init(lif, idev, &new->q, index, num_descs,
489 desc_size, sg_desc_size, pid);
491 IONIC_PRINT(ERR, "Queue initialization failed");
495 if (flags & IONIC_QCQ_F_INTR) {
496 err = ionic_intr_alloc(lif, &new->intr);
500 ionic_intr_mask_assert(idev->intr_ctrl, new->intr.index,
501 IONIC_INTR_MASK_SET);
503 new->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED;
506 err = ionic_cq_init(lif, &new->cq, &new->intr,
507 num_descs, cq_desc_size);
509 IONIC_PRINT(ERR, "Completion queue initialization failed");
510 goto err_out_free_intr;
513 new->base_z = rte_eth_dma_zone_reserve(lif->eth_dev,
514 base /* name */, index /* queue_idx */,
515 total_size, IONIC_ALIGN, socket_id);
518 IONIC_PRINT(ERR, "Cannot reserve queue DMA memory");
520 goto err_out_free_intr;
523 new->base = new->base_z->addr;
524 new->base_pa = new->base_z->iova;
525 new->total_size = total_size;
528 q_base_pa = new->base_pa;
530 cq_base = (void *)RTE_ALIGN((uintptr_t)q_base + q_size, PAGE_SIZE);
531 cq_base_pa = RTE_ALIGN(q_base_pa + q_size, PAGE_SIZE);
533 if (flags & IONIC_QCQ_F_SG) {
534 sg_base = (void *)RTE_ALIGN((uintptr_t)cq_base + cq_size,
536 sg_base_pa = RTE_ALIGN(cq_base_pa + cq_size, PAGE_SIZE);
537 ionic_q_sg_map(&new->q, sg_base, sg_base_pa);
540 IONIC_PRINT(DEBUG, "Q-Base-PA = %ju CQ-Base-PA = %ju "
542 q_base_pa, cq_base_pa, sg_base_pa);
544 ionic_q_map(&new->q, q_base, q_base_pa);
545 ionic_cq_map(&new->cq, cq_base, cq_base_pa);
546 ionic_cq_bind(&new->cq, &new->q);
553 if (flags & IONIC_QCQ_F_INTR)
554 ionic_intr_free(lif, &new->intr);
560 ionic_qcq_free(struct ionic_qcq *qcq)
565 rte_memzone_free(qcq->base_z);
570 rte_free(qcq->q.info);
578 ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t nrxq_descs,
579 struct ionic_qcq **qcq)
584 flags = IONIC_QCQ_F_SG;
585 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, index, "rx", flags,
587 sizeof(struct ionic_rxq_desc),
588 sizeof(struct ionic_rxq_comp),
589 sizeof(struct ionic_rxq_sg_desc),
590 lif->kern_pid, &lif->rxqcqs[index]);
594 *qcq = lif->rxqcqs[index];
600 ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t ntxq_descs,
601 struct ionic_qcq **qcq)
606 flags = IONIC_QCQ_F_SG;
607 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, index, "tx", flags,
609 sizeof(struct ionic_txq_desc),
610 sizeof(struct ionic_txq_comp),
611 sizeof(struct ionic_txq_sg_desc),
612 lif->kern_pid, &lif->txqcqs[index]);
616 *qcq = lif->txqcqs[index];
622 ionic_admin_qcq_alloc(struct ionic_lif *lif)
628 err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags,
630 sizeof(struct ionic_admin_cmd),
631 sizeof(struct ionic_admin_comp),
633 lif->kern_pid, &lif->adminqcq);
641 ionic_notify_qcq_alloc(struct ionic_lif *lif)
646 flags = IONIC_QCQ_F_NOTIFYQ | IONIC_QCQ_F_INTR;
648 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notify",
650 IONIC_NOTIFYQ_LENGTH,
651 sizeof(struct ionic_notifyq_cmd),
652 sizeof(union ionic_notifyq_comp),
654 lif->kern_pid, &lif->notifyqcq);
662 ionic_bus_map_dbpage(struct ionic_adapter *adapter, int page_num)
664 char *vaddr = adapter->bars[IONIC_PCI_BAR_DBELL].vaddr;
666 if (adapter->num_bars <= IONIC_PCI_BAR_DBELL)
669 return (void *)&vaddr[page_num << PAGE_SHIFT];
673 ionic_lif_alloc(struct ionic_lif *lif)
675 struct ionic_adapter *adapter = lif->adapter;
676 uint32_t socket_id = rte_socket_id();
680 snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index);
682 IONIC_PRINT(DEBUG, "Allocating Lif Info");
684 rte_spinlock_init(&lif->adminq_lock);
685 rte_spinlock_init(&lif->adminq_service_lock);
689 dbpage_num = ionic_db_page_num(lif, 0);
691 lif->kern_dbpage = ionic_bus_map_dbpage(adapter, dbpage_num);
692 if (!lif->kern_dbpage) {
693 IONIC_PRINT(ERR, "Cannot map dbpage, aborting");
697 lif->txqcqs = rte_zmalloc("ionic", sizeof(*lif->txqcqs) *
698 adapter->max_ntxqs_per_lif, 0);
701 IONIC_PRINT(ERR, "Cannot allocate tx queues array");
705 lif->rxqcqs = rte_zmalloc("ionic", sizeof(*lif->rxqcqs) *
706 adapter->max_nrxqs_per_lif, 0);
709 IONIC_PRINT(ERR, "Cannot allocate rx queues array");
713 IONIC_PRINT(DEBUG, "Allocating Notify Queue");
715 err = ionic_notify_qcq_alloc(lif);
717 IONIC_PRINT(ERR, "Cannot allocate notify queue");
721 IONIC_PRINT(DEBUG, "Allocating Admin Queue");
723 IONIC_PRINT(DEBUG, "Allocating Admin Queue");
725 err = ionic_admin_qcq_alloc(lif);
727 IONIC_PRINT(ERR, "Cannot allocate admin queue");
731 IONIC_PRINT(DEBUG, "Allocating Lif Info");
733 lif->info_sz = RTE_ALIGN(sizeof(*lif->info), PAGE_SIZE);
735 lif->info_z = rte_eth_dma_zone_reserve(lif->eth_dev,
736 "lif_info", 0 /* queue_idx*/,
737 lif->info_sz, IONIC_ALIGN, socket_id);
739 IONIC_PRINT(ERR, "Cannot allocate lif info memory");
743 lif->info = lif->info_z->addr;
744 lif->info_pa = lif->info_z->iova;
750 ionic_lif_free(struct ionic_lif *lif)
752 if (lif->notifyqcq) {
753 ionic_qcq_free(lif->notifyqcq);
754 lif->notifyqcq = NULL;
758 ionic_qcq_free(lif->adminqcq);
759 lif->adminqcq = NULL;
763 rte_free(lif->txqcqs);
768 rte_free(lif->rxqcqs);
773 rte_memzone_free(lif->info_z);
779 ionic_lif_rss_config(struct ionic_lif *lif,
780 const uint16_t types, const uint8_t *key, const uint32_t *indir)
782 struct ionic_admin_ctx ctx = {
783 .pending_work = true,
785 .opcode = IONIC_CMD_LIF_SETATTR,
786 .attr = IONIC_LIF_ATTR_RSS,
788 .rss.addr = lif->rss_ind_tbl_pa,
795 lif->rss_types = types;
798 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE);
801 for (i = 0; i < lif->adapter->ident.lif.eth.rss_ind_tbl_sz; i++)
802 lif->rss_ind_tbl[i] = indir[i];
804 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key,
805 IONIC_RSS_HASH_KEY_SIZE);
807 return ionic_adminq_post_wait(lif, &ctx);
811 ionic_lif_rss_setup(struct ionic_lif *lif)
813 size_t tbl_size = sizeof(*lif->rss_ind_tbl) *
814 lif->adapter->ident.lif.eth.rss_ind_tbl_sz;
815 static const uint8_t toeplitz_symmetric_key[] = {
816 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
817 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
818 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
819 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
820 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
822 uint32_t socket_id = rte_socket_id();
828 lif->rss_ind_tbl_z = rte_eth_dma_zone_reserve(lif->eth_dev,
830 0 /* queue_idx*/, tbl_size, IONIC_ALIGN, socket_id);
832 if (!lif->rss_ind_tbl_z) {
833 IONIC_PRINT(ERR, "OOM");
837 lif->rss_ind_tbl = lif->rss_ind_tbl_z->addr;
838 lif->rss_ind_tbl_pa = lif->rss_ind_tbl_z->iova;
840 /* Fill indirection table with 'default' values */
841 for (i = 0; i < lif->adapter->ident.lif.eth.rss_ind_tbl_sz; i++)
842 lif->rss_ind_tbl[i] = i % lif->nrxqcqs;
844 err = ionic_lif_rss_config(lif, IONIC_RSS_OFFLOAD_ALL,
845 toeplitz_symmetric_key, NULL);
853 ionic_lif_rss_teardown(struct ionic_lif *lif)
855 if (!lif->rss_ind_tbl)
858 if (lif->rss_ind_tbl_z) {
859 /* Disable RSS on the NIC */
860 ionic_lif_rss_config(lif, 0x0, NULL, NULL);
862 lif->rss_ind_tbl = NULL;
863 lif->rss_ind_tbl_pa = 0;
864 rte_memzone_free(lif->rss_ind_tbl_z);
865 lif->rss_ind_tbl_z = NULL;
870 ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq)
872 struct ionic_dev *idev = &lif->adapter->idev;
874 if (!(qcq->flags & IONIC_QCQ_F_INITED))
877 if (qcq->flags & IONIC_QCQ_F_INTR)
878 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
879 IONIC_INTR_MASK_SET);
881 qcq->flags &= ~IONIC_QCQ_F_INITED;
885 ionic_lif_txq_deinit(struct ionic_qcq *qcq)
887 ionic_lif_qcq_deinit(qcq->lif, qcq);
891 ionic_lif_rxq_deinit(struct ionic_qcq *qcq)
893 ionic_lif_qcq_deinit(qcq->lif, qcq);
897 ionic_adminq_service(struct ionic_cq *cq, uint32_t cq_desc_index,
898 void *cb_arg __rte_unused)
900 struct ionic_admin_comp *cq_desc_base = cq->base;
901 struct ionic_admin_comp *cq_desc = &cq_desc_base[cq_desc_index];
903 if (!color_match(cq_desc->color, cq->done_color))
906 ionic_q_service(cq->bound_q, cq_desc_index, cq_desc->comp_index, NULL);
911 /* This acts like ionic_napi */
913 ionic_qcq_service(struct ionic_qcq *qcq, int budget, ionic_cq_cb cb,
916 struct ionic_cq *cq = &qcq->cq;
919 work_done = ionic_cq_service(cq, budget, cb, cb_arg);
925 ionic_link_status_check(struct ionic_lif *lif)
927 struct ionic_adapter *adapter = lif->adapter;
930 lif->state &= ~IONIC_LIF_F_LINK_CHECK_NEEDED;
935 link_up = (lif->info->status.link_status == IONIC_PORT_OPER_STATUS_UP);
937 if ((link_up && adapter->link_up) ||
938 (!link_up && !adapter->link_up))
942 IONIC_PRINT(DEBUG, "Link up - %d Gbps",
943 lif->info->status.link_speed);
944 adapter->link_speed = lif->info->status.link_speed;
946 IONIC_PRINT(DEBUG, "Link down");
949 adapter->link_up = link_up;
953 ionic_notifyq_cb(struct ionic_cq *cq, uint32_t cq_desc_index, void *cb_arg)
955 union ionic_notifyq_comp *cq_desc_base = cq->base;
956 union ionic_notifyq_comp *cq_desc = &cq_desc_base[cq_desc_index];
957 struct ionic_lif *lif = cb_arg;
959 IONIC_PRINT(DEBUG, "Notifyq callback eid = %jd ecode = %d",
960 cq_desc->event.eid, cq_desc->event.ecode);
962 /* Have we run out of new completions to process? */
963 if (!(cq_desc->event.eid > lif->last_eid))
966 lif->last_eid = cq_desc->event.eid;
968 switch (cq_desc->event.ecode) {
969 case IONIC_EVENT_LINK_CHANGE:
971 "Notifyq IONIC_EVENT_LINK_CHANGE eid=%jd link_status=%d link_speed=%d",
973 cq_desc->link_change.link_status,
974 cq_desc->link_change.link_speed);
976 lif->state |= IONIC_LIF_F_LINK_CHECK_NEEDED;
980 IONIC_PRINT(WARNING, "Notifyq bad event ecode=%d eid=%jd",
981 cq_desc->event.ecode, cq_desc->event.eid);
989 ionic_notifyq_handler(struct ionic_lif *lif, int budget)
991 struct ionic_dev *idev = &lif->adapter->idev;
992 struct ionic_qcq *qcq = lif->notifyqcq;
995 if (!(qcq->flags & IONIC_QCQ_F_INITED)) {
996 IONIC_PRINT(DEBUG, "Notifyq not yet initialized");
1000 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1001 IONIC_INTR_MASK_SET);
1003 work_done = ionic_qcq_service(qcq, budget, ionic_notifyq_cb, lif);
1005 if (lif->state & IONIC_LIF_F_LINK_CHECK_NEEDED)
1006 ionic_link_status_check(lif);
1008 ionic_intr_credits(idev->intr_ctrl, qcq->intr.index,
1009 work_done, IONIC_INTR_CRED_RESET_COALESCE);
1011 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1012 IONIC_INTR_MASK_CLEAR);
1018 ionic_lif_adminq_init(struct ionic_lif *lif)
1020 struct ionic_dev *idev = &lif->adapter->idev;
1021 struct ionic_qcq *qcq = lif->adminqcq;
1022 struct ionic_queue *q = &qcq->q;
1023 struct ionic_q_init_comp comp;
1026 ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index);
1027 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1031 ionic_dev_cmd_comp(idev, &comp);
1033 q->hw_type = comp.hw_type;
1034 q->hw_index = comp.hw_index;
1035 q->db = ionic_db_map(lif, q);
1037 IONIC_PRINT(DEBUG, "adminq->hw_type %d", q->hw_type);
1038 IONIC_PRINT(DEBUG, "adminq->hw_index %d", q->hw_index);
1039 IONIC_PRINT(DEBUG, "adminq->db %p", q->db);
1041 if (qcq->flags & IONIC_QCQ_F_INTR)
1042 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1043 IONIC_INTR_MASK_CLEAR);
1045 qcq->flags |= IONIC_QCQ_F_INITED;
1051 ionic_lif_notifyq_init(struct ionic_lif *lif)
1053 struct ionic_dev *idev = &lif->adapter->idev;
1054 struct ionic_qcq *qcq = lif->notifyqcq;
1055 struct ionic_queue *q = &qcq->q;
1058 struct ionic_admin_ctx ctx = {
1059 .pending_work = true,
1061 .opcode = IONIC_CMD_Q_INIT,
1062 .lif_index = lif->index,
1065 .flags = (IONIC_QINIT_F_IRQ | IONIC_QINIT_F_ENA),
1066 .intr_index = qcq->intr.index,
1068 .ring_size = rte_log2_u32(q->num_descs),
1069 .ring_base = q->base_pa,
1073 IONIC_PRINT(DEBUG, "notifyq_init.pid %d", ctx.cmd.q_init.pid);
1074 IONIC_PRINT(DEBUG, "notifyq_init.index %d",
1075 ctx.cmd.q_init.index);
1076 IONIC_PRINT(DEBUG, "notifyq_init.ring_base 0x%" PRIx64 "",
1077 ctx.cmd.q_init.ring_base);
1078 IONIC_PRINT(DEBUG, "notifyq_init.ring_size %d",
1079 ctx.cmd.q_init.ring_size);
1081 err = ionic_adminq_post_wait(lif, &ctx);
1085 q->hw_type = ctx.comp.q_init.hw_type;
1086 q->hw_index = ctx.comp.q_init.hw_index;
1089 IONIC_PRINT(DEBUG, "notifyq->hw_type %d", q->hw_type);
1090 IONIC_PRINT(DEBUG, "notifyq->hw_index %d", q->hw_index);
1091 IONIC_PRINT(DEBUG, "notifyq->db %p", q->db);
1093 if (qcq->flags & IONIC_QCQ_F_INTR)
1094 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1095 IONIC_INTR_MASK_CLEAR);
1097 qcq->flags |= IONIC_QCQ_F_INITED;
1103 ionic_lif_set_features(struct ionic_lif *lif)
1105 struct ionic_admin_ctx ctx = {
1106 .pending_work = true,
1107 .cmd.lif_setattr = {
1108 .opcode = IONIC_CMD_LIF_SETATTR,
1109 .index = lif->index,
1110 .attr = IONIC_LIF_ATTR_FEATURES,
1111 .features = lif->features,
1116 err = ionic_adminq_post_wait(lif, &ctx);
1120 lif->hw_features = (ctx.cmd.lif_setattr.features &
1121 ctx.comp.lif_setattr.features);
1123 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
1124 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_TX_TAG");
1125 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
1126 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_STRIP");
1127 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
1128 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_FILTER");
1129 if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
1130 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_HASH");
1131 if (lif->hw_features & IONIC_ETH_HW_TX_SG)
1132 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_SG");
1133 if (lif->hw_features & IONIC_ETH_HW_RX_SG)
1134 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_SG");
1135 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
1136 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_CSUM");
1137 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
1138 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_CSUM");
1139 if (lif->hw_features & IONIC_ETH_HW_TSO)
1140 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO");
1141 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
1142 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPV6");
1143 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
1144 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_ECN");
1145 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
1146 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE");
1147 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
1148 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE_CSUM");
1149 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
1150 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP4");
1151 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
1152 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP6");
1153 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
1154 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP");
1155 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
1156 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP_CSUM");
1162 ionic_lif_txq_init(struct ionic_qcq *qcq)
1164 struct ionic_queue *q = &qcq->q;
1165 struct ionic_lif *lif = qcq->lif;
1166 struct ionic_cq *cq = &qcq->cq;
1167 struct ionic_admin_ctx ctx = {
1168 .pending_work = true,
1170 .opcode = IONIC_CMD_Q_INIT,
1171 .lif_index = lif->index,
1174 .flags = IONIC_QINIT_F_SG,
1175 .intr_index = cq->bound_intr->index,
1177 .ring_size = rte_log2_u32(q->num_descs),
1178 .ring_base = q->base_pa,
1179 .cq_ring_base = cq->base_pa,
1180 .sg_ring_base = q->sg_base_pa,
1185 IONIC_PRINT(DEBUG, "txq_init.pid %d", ctx.cmd.q_init.pid);
1186 IONIC_PRINT(DEBUG, "txq_init.index %d", ctx.cmd.q_init.index);
1187 IONIC_PRINT(DEBUG, "txq_init.ring_base 0x%" PRIx64 "",
1188 ctx.cmd.q_init.ring_base);
1189 IONIC_PRINT(DEBUG, "txq_init.ring_size %d",
1190 ctx.cmd.q_init.ring_size);
1192 err = ionic_adminq_post_wait(qcq->lif, &ctx);
1196 q->hw_type = ctx.comp.q_init.hw_type;
1197 q->hw_index = ctx.comp.q_init.hw_index;
1198 q->db = ionic_db_map(lif, q);
1200 IONIC_PRINT(DEBUG, "txq->hw_type %d", q->hw_type);
1201 IONIC_PRINT(DEBUG, "txq->hw_index %d", q->hw_index);
1202 IONIC_PRINT(DEBUG, "txq->db %p", q->db);
1204 qcq->flags |= IONIC_QCQ_F_INITED;
1210 ionic_lif_rxq_init(struct ionic_qcq *qcq)
1212 struct ionic_queue *q = &qcq->q;
1213 struct ionic_lif *lif = qcq->lif;
1214 struct ionic_cq *cq = &qcq->cq;
1215 struct ionic_admin_ctx ctx = {
1216 .pending_work = true,
1218 .opcode = IONIC_CMD_Q_INIT,
1219 .lif_index = lif->index,
1222 .flags = IONIC_QINIT_F_SG,
1223 .intr_index = cq->bound_intr->index,
1225 .ring_size = rte_log2_u32(q->num_descs),
1226 .ring_base = q->base_pa,
1227 .cq_ring_base = cq->base_pa,
1228 .sg_ring_base = q->sg_base_pa,
1233 IONIC_PRINT(DEBUG, "rxq_init.pid %d", ctx.cmd.q_init.pid);
1234 IONIC_PRINT(DEBUG, "rxq_init.index %d", ctx.cmd.q_init.index);
1235 IONIC_PRINT(DEBUG, "rxq_init.ring_base 0x%" PRIx64 "",
1236 ctx.cmd.q_init.ring_base);
1237 IONIC_PRINT(DEBUG, "rxq_init.ring_size %d",
1238 ctx.cmd.q_init.ring_size);
1240 err = ionic_adminq_post_wait(qcq->lif, &ctx);
1244 q->hw_type = ctx.comp.q_init.hw_type;
1245 q->hw_index = ctx.comp.q_init.hw_index;
1246 q->db = ionic_db_map(lif, q);
1248 qcq->flags |= IONIC_QCQ_F_INITED;
1250 IONIC_PRINT(DEBUG, "rxq->hw_type %d", q->hw_type);
1251 IONIC_PRINT(DEBUG, "rxq->hw_index %d", q->hw_index);
1252 IONIC_PRINT(DEBUG, "rxq->db %p", q->db);
1258 ionic_station_set(struct ionic_lif *lif)
1260 struct ionic_admin_ctx ctx = {
1261 .pending_work = true,
1262 .cmd.lif_getattr = {
1263 .opcode = IONIC_CMD_LIF_GETATTR,
1264 .index = lif->index,
1265 .attr = IONIC_LIF_ATTR_MAC,
1272 err = ionic_adminq_post_wait(lif, &ctx);
1276 if (!rte_is_zero_ether_addr((struct rte_ether_addr *)
1278 IONIC_PRINT(INFO, "deleting station MAC addr");
1280 ionic_lif_addr_del(lif, lif->mac_addr);
1283 memcpy(lif->mac_addr, ctx.comp.lif_getattr.mac, RTE_ETHER_ADDR_LEN);
1285 if (rte_is_zero_ether_addr((struct rte_ether_addr *)lif->mac_addr)) {
1286 IONIC_PRINT(NOTICE, "empty MAC addr (VF?)");
1290 IONIC_PRINT(DEBUG, "adding station MAC addr");
1292 ionic_lif_addr_add(lif, lif->mac_addr);
1298 ionic_lif_set_name(struct ionic_lif *lif)
1300 struct ionic_admin_ctx ctx = {
1301 .pending_work = true,
1302 .cmd.lif_setattr = {
1303 .opcode = IONIC_CMD_LIF_SETATTR,
1304 .index = lif->index,
1305 .attr = IONIC_LIF_ATTR_NAME,
1309 snprintf(ctx.cmd.lif_setattr.name, sizeof(ctx.cmd.lif_setattr.name),
1310 "%d", lif->port_id);
1312 ionic_adminq_post_wait(lif, &ctx);
1316 ionic_lif_init(struct ionic_lif *lif)
1318 struct ionic_dev *idev = &lif->adapter->idev;
1319 struct ionic_q_init_comp comp;
1322 ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa);
1323 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1324 ionic_dev_cmd_comp(idev, &comp);
1328 lif->hw_index = comp.hw_index;
1330 err = ionic_lif_adminq_init(lif);
1334 err = ionic_lif_notifyq_init(lif);
1336 goto err_out_adminq_deinit;
1339 IONIC_ETH_HW_VLAN_TX_TAG
1340 | IONIC_ETH_HW_VLAN_RX_STRIP
1341 | IONIC_ETH_HW_VLAN_RX_FILTER
1342 | IONIC_ETH_HW_RX_HASH
1343 | IONIC_ETH_HW_TX_SG
1344 | IONIC_ETH_HW_RX_SG
1345 | IONIC_ETH_HW_RX_CSUM
1347 | IONIC_ETH_HW_TSO_IPV6
1348 | IONIC_ETH_HW_TSO_ECN;
1350 err = ionic_lif_set_features(lif);
1352 goto err_out_notifyq_deinit;
1354 err = ionic_rx_filters_init(lif);
1356 goto err_out_notifyq_deinit;
1358 err = ionic_station_set(lif);
1360 goto err_out_rx_filter_deinit;
1362 ionic_lif_set_name(lif);
1364 lif->state |= IONIC_LIF_F_INITED;
1368 err_out_rx_filter_deinit:
1369 ionic_rx_filters_deinit(lif);
1371 err_out_notifyq_deinit:
1372 ionic_lif_qcq_deinit(lif, lif->notifyqcq);
1374 err_out_adminq_deinit:
1375 ionic_lif_qcq_deinit(lif, lif->adminqcq);
1381 ionic_lif_deinit(struct ionic_lif *lif)
1383 if (!(lif->state & IONIC_LIF_F_INITED))
1386 ionic_rx_filters_deinit(lif);
1387 ionic_lif_rss_teardown(lif);
1388 ionic_lif_qcq_deinit(lif, lif->notifyqcq);
1389 ionic_lif_qcq_deinit(lif, lif->adminqcq);
1391 lif->state &= ~IONIC_LIF_F_INITED;
1395 ionic_lif_configure(struct ionic_lif *lif)
1397 struct ionic_identity *ident = &lif->adapter->ident;
1398 uint32_t ntxqs_per_lif =
1399 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ];
1400 uint32_t nrxqs_per_lif =
1401 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ];
1402 uint32_t nrxqs = lif->eth_dev->data->nb_rx_queues;
1403 uint32_t ntxqs = lif->eth_dev->data->nb_tx_queues;
1405 lif->port_id = lif->eth_dev->data->port_id;
1407 IONIC_PRINT(DEBUG, "Configuring LIF on port %u",
1411 nrxqs_per_lif = RTE_MIN(nrxqs_per_lif, nrxqs);
1414 ntxqs_per_lif = RTE_MIN(ntxqs_per_lif, ntxqs);
1416 lif->nrxqcqs = nrxqs_per_lif;
1417 lif->ntxqcqs = ntxqs_per_lif;
1423 ionic_lif_start(struct ionic_lif *lif)
1425 uint32_t rx_mode = 0;
1429 IONIC_PRINT(DEBUG, "Setting RSS configuration on port %u",
1432 err = ionic_lif_rss_setup(lif);
1436 IONIC_PRINT(DEBUG, "Setting RX mode on port %u",
1439 rx_mode |= IONIC_RX_MODE_F_UNICAST;
1440 rx_mode |= IONIC_RX_MODE_F_MULTICAST;
1441 rx_mode |= IONIC_RX_MODE_F_BROADCAST;
1443 lif->rx_mode = 0; /* set by ionic_set_rx_mode */
1445 ionic_set_rx_mode(lif, rx_mode);
1447 IONIC_PRINT(DEBUG, "Starting %u RX queues and %u TX queues "
1449 lif->nrxqcqs, lif->ntxqcqs, lif->port_id);
1451 for (i = 0; i < lif->nrxqcqs; i++) {
1452 struct ionic_qcq *rxq = lif->rxqcqs[i];
1453 if (!rxq->deferred_start) {
1454 err = ionic_dev_rx_queue_start(lif->eth_dev, i);
1461 for (i = 0; i < lif->ntxqcqs; i++) {
1462 struct ionic_qcq *txq = lif->txqcqs[i];
1463 if (!txq->deferred_start) {
1464 err = ionic_dev_tx_queue_start(lif->eth_dev, i);
1471 ionic_link_status_check(lif);
1473 /* Carrier ON here */
1479 ionic_lif_identify(struct ionic_adapter *adapter)
1481 struct ionic_dev *idev = &adapter->idev;
1482 struct ionic_identity *ident = &adapter->ident;
1485 unsigned int lif_words = sizeof(ident->lif.words) /
1486 sizeof(ident->lif.words[0]);
1487 unsigned int cmd_words = sizeof(idev->dev_cmd->data) /
1488 sizeof(idev->dev_cmd->data[0]);
1489 unsigned int nwords;
1491 ionic_dev_cmd_lif_identify(idev, IONIC_LIF_TYPE_CLASSIC,
1492 IONIC_IDENTITY_VERSION_1);
1493 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1497 nwords = RTE_MIN(lif_words, cmd_words);
1498 for (i = 0; i < nwords; i++)
1499 ident->lif.words[i] = ioread32(&idev->dev_cmd->data[i]);
1501 IONIC_PRINT(INFO, "capabilities 0x%" PRIx64 " ",
1502 ident->lif.capabilities);
1504 IONIC_PRINT(INFO, "eth.max_ucast_filters 0x%" PRIx32 " ",
1505 ident->lif.eth.max_ucast_filters);
1506 IONIC_PRINT(INFO, "eth.max_mcast_filters 0x%" PRIx32 " ",
1507 ident->lif.eth.max_mcast_filters);
1509 IONIC_PRINT(INFO, "eth.features 0x%" PRIx64 " ",
1510 ident->lif.eth.config.features);
1511 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_ADMINQ] 0x%" PRIx32 " ",
1512 ident->lif.eth.config.queue_count[IONIC_QTYPE_ADMINQ]);
1513 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] 0x%" PRIx32 " ",
1514 ident->lif.eth.config.queue_count[IONIC_QTYPE_NOTIFYQ]);
1515 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_RXQ] 0x%" PRIx32 " ",
1516 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ]);
1517 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_TXQ] 0x%" PRIx32 " ",
1518 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ]);
1524 ionic_lifs_size(struct ionic_adapter *adapter)
1526 struct ionic_identity *ident = &adapter->ident;
1527 uint32_t nlifs = ident->dev.nlifs;
1528 uint32_t nintrs, dev_nintrs = ident->dev.nintrs;
1530 adapter->max_ntxqs_per_lif =
1531 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ];
1532 adapter->max_nrxqs_per_lif =
1533 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ];
1535 nintrs = nlifs * 1 /* notifyq */;
1537 if (nintrs > dev_nintrs) {
1538 IONIC_PRINT(ERR, "At most %d intr queues supported, minimum required is %u",
1539 dev_nintrs, nintrs);
1543 adapter->nintrs = nintrs;