1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
5 #include <rte_malloc.h>
6 #include <ethdev_driver.h>
9 #include "ionic_logs.h"
10 #include "ionic_lif.h"
11 #include "ionic_ethdev.h"
12 #include "ionic_rx_filter.h"
13 #include "ionic_rxtx.h"
15 static int ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr);
16 static int ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr);
19 ionic_qcq_enable(struct ionic_qcq *qcq)
21 struct ionic_queue *q = &qcq->q;
22 struct ionic_lif *lif = q->lif;
23 struct ionic_admin_ctx ctx = {
26 .opcode = IONIC_CMD_Q_CONTROL,
29 .oper = IONIC_Q_ENABLE,
33 return ionic_adminq_post_wait(lif, &ctx);
37 ionic_qcq_disable(struct ionic_qcq *qcq)
39 struct ionic_queue *q = &qcq->q;
40 struct ionic_lif *lif = q->lif;
41 struct ionic_admin_ctx ctx = {
44 .opcode = IONIC_CMD_Q_CONTROL,
47 .oper = IONIC_Q_DISABLE,
51 return ionic_adminq_post_wait(lif, &ctx);
55 ionic_lif_stop(struct ionic_lif *lif)
61 lif->state &= ~IONIC_LIF_F_UP;
63 for (i = 0; i < lif->nrxqcqs; i++) {
64 struct ionic_qcq *rxq = lif->rxqcqs[i];
65 if (rxq->flags & IONIC_QCQ_F_INITED)
66 (void)ionic_dev_rx_queue_stop(lif->eth_dev, i);
69 for (i = 0; i < lif->ntxqcqs; i++) {
70 struct ionic_qcq *txq = lif->txqcqs[i];
71 if (txq->flags & IONIC_QCQ_F_INITED)
72 (void)ionic_dev_tx_queue_stop(lif->eth_dev, i);
77 ionic_lif_reset(struct ionic_lif *lif)
79 struct ionic_dev *idev = &lif->adapter->idev;
84 ionic_dev_cmd_lif_reset(idev);
85 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
87 IONIC_PRINT(WARNING, "Failed to reset %s", lif->name);
91 ionic_lif_get_abs_stats(const struct ionic_lif *lif, struct rte_eth_stats *stats)
93 struct ionic_lif_stats *ls = &lif->info->stats;
95 uint32_t num_rx_q_counters = RTE_MIN(lif->nrxqcqs, (uint32_t)
96 RTE_ETHDEV_QUEUE_STAT_CNTRS);
97 uint32_t num_tx_q_counters = RTE_MIN(lif->ntxqcqs, (uint32_t)
98 RTE_ETHDEV_QUEUE_STAT_CNTRS);
100 memset(stats, 0, sizeof(*stats));
103 IONIC_PRINT(DEBUG, "Stats on port %u not yet initialized",
110 stats->ipackets = ls->rx_ucast_packets +
111 ls->rx_mcast_packets +
112 ls->rx_bcast_packets;
114 stats->ibytes = ls->rx_ucast_bytes +
118 for (i = 0; i < lif->nrxqcqs; i++) {
119 struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats.rx;
121 rx_stats->no_cb_arg +
122 rx_stats->bad_cq_status +
128 ls->rx_ucast_drop_packets +
129 ls->rx_mcast_drop_packets +
130 ls->rx_bcast_drop_packets;
135 ls->rx_queue_disabled +
136 ls->rx_desc_fetch_error +
137 ls->rx_desc_data_error;
139 for (i = 0; i < num_rx_q_counters; i++) {
140 struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats.rx;
141 stats->q_ipackets[i] = rx_stats->packets;
142 stats->q_ibytes[i] = rx_stats->bytes;
144 rx_stats->no_cb_arg +
145 rx_stats->bad_cq_status +
152 stats->opackets = ls->tx_ucast_packets +
153 ls->tx_mcast_packets +
154 ls->tx_bcast_packets;
156 stats->obytes = ls->tx_ucast_bytes +
160 for (i = 0; i < lif->ntxqcqs; i++) {
161 struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats.tx;
162 stats->oerrors += tx_stats->drop;
166 ls->tx_ucast_drop_packets +
167 ls->tx_mcast_drop_packets +
168 ls->tx_bcast_drop_packets;
172 ls->tx_queue_disabled +
173 ls->tx_desc_fetch_error +
174 ls->tx_desc_data_error;
176 for (i = 0; i < num_tx_q_counters; i++) {
177 struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats.tx;
178 stats->q_opackets[i] = tx_stats->packets;
179 stats->q_obytes[i] = tx_stats->bytes;
184 ionic_lif_get_stats(const struct ionic_lif *lif,
185 struct rte_eth_stats *stats)
187 ionic_lif_get_abs_stats(lif, stats);
189 stats->ipackets -= lif->stats_base.ipackets;
190 stats->opackets -= lif->stats_base.opackets;
191 stats->ibytes -= lif->stats_base.ibytes;
192 stats->obytes -= lif->stats_base.obytes;
193 stats->imissed -= lif->stats_base.imissed;
194 stats->ierrors -= lif->stats_base.ierrors;
195 stats->oerrors -= lif->stats_base.oerrors;
196 stats->rx_nombuf -= lif->stats_base.rx_nombuf;
200 ionic_lif_reset_stats(struct ionic_lif *lif)
204 for (i = 0; i < lif->nrxqcqs; i++) {
205 memset(&lif->rxqcqs[i]->stats.rx, 0,
206 sizeof(struct ionic_rx_stats));
207 memset(&lif->txqcqs[i]->stats.tx, 0,
208 sizeof(struct ionic_tx_stats));
211 ionic_lif_get_abs_stats(lif, &lif->stats_base);
215 ionic_lif_get_hw_stats(struct ionic_lif *lif, struct ionic_lif_stats *stats)
217 uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t);
218 uint64_t *stats64 = (uint64_t *)stats;
219 uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats;
220 uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base;
222 for (i = 0; i < count; i++)
223 stats64[i] = lif_stats64[i] - lif_stats64_base[i];
227 ionic_lif_reset_hw_stats(struct ionic_lif *lif)
229 uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t);
230 uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats;
231 uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base;
233 for (i = 0; i < count; i++)
234 lif_stats64_base[i] = lif_stats64[i];
238 ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr)
240 struct ionic_admin_ctx ctx = {
241 .pending_work = true,
242 .cmd.rx_filter_add = {
243 .opcode = IONIC_CMD_RX_FILTER_ADD,
244 .match = IONIC_RX_FILTER_MATCH_MAC,
249 memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, RTE_ETHER_ADDR_LEN);
251 err = ionic_adminq_post_wait(lif, &ctx);
255 IONIC_PRINT(INFO, "rx_filter add (id %d)",
256 ctx.comp.rx_filter_add.filter_id);
258 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);
262 ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr)
264 struct ionic_admin_ctx ctx = {
265 .pending_work = true,
266 .cmd.rx_filter_del = {
267 .opcode = IONIC_CMD_RX_FILTER_DEL,
270 struct ionic_rx_filter *f;
275 rte_spinlock_lock(&lif->rx_filters.lock);
277 f = ionic_rx_filter_by_addr(lif, addr);
279 rte_spinlock_unlock(&lif->rx_filters.lock);
283 ctx.cmd.rx_filter_del.filter_id = f->filter_id;
284 ionic_rx_filter_free(f);
286 rte_spinlock_unlock(&lif->rx_filters.lock);
288 err = ionic_adminq_post_wait(lif, &ctx);
292 IONIC_PRINT(INFO, "rx_filter del (id %d)",
293 ctx.cmd.rx_filter_del.filter_id);
299 ionic_dev_add_mac(struct rte_eth_dev *eth_dev,
300 struct rte_ether_addr *mac_addr,
301 uint32_t index __rte_unused, uint32_t pool __rte_unused)
303 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
307 return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr);
311 ionic_dev_remove_mac(struct rte_eth_dev *eth_dev, uint32_t index)
313 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
314 struct ionic_adapter *adapter = lif->adapter;
315 struct rte_ether_addr *mac_addr;
319 if (index >= adapter->max_mac_addrs) {
321 "Index %u is above MAC filter limit %u",
322 index, adapter->max_mac_addrs);
326 mac_addr = ð_dev->data->mac_addrs[index];
328 if (!rte_is_valid_assigned_ether_addr(mac_addr))
331 ionic_lif_addr_del(lif, (const uint8_t *)mac_addr);
335 ionic_dev_set_mac(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr)
337 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
341 if (mac_addr == NULL) {
342 IONIC_PRINT(NOTICE, "New mac is null");
346 if (!rte_is_zero_ether_addr((struct rte_ether_addr *)lif->mac_addr)) {
347 IONIC_PRINT(INFO, "Deleting mac addr %pM",
349 ionic_lif_addr_del(lif, lif->mac_addr);
350 memset(lif->mac_addr, 0, RTE_ETHER_ADDR_LEN);
353 IONIC_PRINT(INFO, "Updating mac addr");
355 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)lif->mac_addr);
357 return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr);
361 ionic_vlan_rx_add_vid(struct ionic_lif *lif, uint16_t vid)
363 struct ionic_admin_ctx ctx = {
364 .pending_work = true,
365 .cmd.rx_filter_add = {
366 .opcode = IONIC_CMD_RX_FILTER_ADD,
367 .match = IONIC_RX_FILTER_MATCH_VLAN,
373 err = ionic_adminq_post_wait(lif, &ctx);
377 IONIC_PRINT(INFO, "rx_filter add VLAN %d (id %d)", vid,
378 ctx.comp.rx_filter_add.filter_id);
380 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);
384 ionic_vlan_rx_kill_vid(struct ionic_lif *lif, uint16_t vid)
386 struct ionic_admin_ctx ctx = {
387 .pending_work = true,
388 .cmd.rx_filter_del = {
389 .opcode = IONIC_CMD_RX_FILTER_DEL,
392 struct ionic_rx_filter *f;
397 rte_spinlock_lock(&lif->rx_filters.lock);
399 f = ionic_rx_filter_by_vlan(lif, vid);
401 rte_spinlock_unlock(&lif->rx_filters.lock);
405 ctx.cmd.rx_filter_del.filter_id = f->filter_id;
406 ionic_rx_filter_free(f);
407 rte_spinlock_unlock(&lif->rx_filters.lock);
409 err = ionic_adminq_post_wait(lif, &ctx);
413 IONIC_PRINT(INFO, "rx_filter del VLAN %d (id %d)", vid,
414 ctx.cmd.rx_filter_del.filter_id);
420 ionic_dev_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id,
423 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
427 err = ionic_vlan_rx_add_vid(lif, vlan_id);
429 err = ionic_vlan_rx_kill_vid(lif, vlan_id);
435 ionic_lif_rx_mode(struct ionic_lif *lif, uint32_t rx_mode)
437 struct ionic_admin_ctx ctx = {
438 .pending_work = true,
440 .opcode = IONIC_CMD_RX_MODE_SET,
446 if (rx_mode & IONIC_RX_MODE_F_UNICAST)
447 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_UNICAST");
448 if (rx_mode & IONIC_RX_MODE_F_MULTICAST)
449 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_MULTICAST");
450 if (rx_mode & IONIC_RX_MODE_F_BROADCAST)
451 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_BROADCAST");
452 if (rx_mode & IONIC_RX_MODE_F_PROMISC)
453 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_PROMISC");
454 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI)
455 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_ALLMULTI");
457 err = ionic_adminq_post_wait(lif, &ctx);
459 IONIC_PRINT(ERR, "Failure setting RX mode");
463 ionic_set_rx_mode(struct ionic_lif *lif, uint32_t rx_mode)
465 if (lif->rx_mode != rx_mode) {
466 lif->rx_mode = rx_mode;
467 ionic_lif_rx_mode(lif, rx_mode);
472 ionic_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
474 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
475 uint32_t rx_mode = lif->rx_mode;
479 rx_mode |= IONIC_RX_MODE_F_PROMISC;
481 ionic_set_rx_mode(lif, rx_mode);
487 ionic_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
489 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
490 uint32_t rx_mode = lif->rx_mode;
492 rx_mode &= ~IONIC_RX_MODE_F_PROMISC;
494 ionic_set_rx_mode(lif, rx_mode);
500 ionic_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
502 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
503 uint32_t rx_mode = lif->rx_mode;
505 rx_mode |= IONIC_RX_MODE_F_ALLMULTI;
507 ionic_set_rx_mode(lif, rx_mode);
513 ionic_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
515 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
516 uint32_t rx_mode = lif->rx_mode;
518 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI;
520 ionic_set_rx_mode(lif, rx_mode);
526 ionic_lif_change_mtu(struct ionic_lif *lif, int new_mtu)
528 struct ionic_admin_ctx ctx = {
529 .pending_work = true,
531 .opcode = IONIC_CMD_LIF_SETATTR,
532 .attr = IONIC_LIF_ATTR_MTU,
538 err = ionic_adminq_post_wait(lif, &ctx);
546 ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr)
548 struct ionic_adapter *adapter = lif->adapter;
549 struct ionic_dev *idev = &adapter->idev;
553 * Note: interrupt handler is called for index = 0 only
554 * (we use interrupts for the notifyq only anyway,
555 * which has index = 0)
558 for (index = 0; index < adapter->nintrs; index++)
559 if (!adapter->intrs[index])
562 if (index == adapter->nintrs)
565 adapter->intrs[index] = true;
567 ionic_intr_init(idev, intr, index);
573 ionic_intr_free(struct ionic_lif *lif, struct ionic_intr_info *intr)
575 if (intr->index != IONIC_INTR_NONE)
576 lif->adapter->intrs[intr->index] = false;
580 ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type,
582 const char *base, uint32_t flags,
585 uint32_t cq_desc_size,
586 uint32_t sg_desc_size,
587 struct ionic_qcq **qcq)
589 struct ionic_dev *idev = &lif->adapter->idev;
590 struct ionic_qcq *new;
591 uint32_t q_size, cq_size, sg_size, total_size;
592 void *q_base, *cq_base, *sg_base;
593 rte_iova_t q_base_pa = 0;
594 rte_iova_t cq_base_pa = 0;
595 rte_iova_t sg_base_pa = 0;
596 uint32_t socket_id = rte_socket_id();
601 q_size = num_descs * desc_size;
602 cq_size = num_descs * cq_desc_size;
603 sg_size = num_descs * sg_desc_size;
605 total_size = RTE_ALIGN(q_size, PAGE_SIZE) +
606 RTE_ALIGN(cq_size, PAGE_SIZE);
608 * Note: aligning q_size/cq_size is not enough due to cq_base address
609 * aligning as q_base could be not aligned to the page.
612 total_size += PAGE_SIZE;
614 if (flags & IONIC_QCQ_F_SG) {
615 total_size += RTE_ALIGN(sg_size, PAGE_SIZE);
616 total_size += PAGE_SIZE;
619 new = rte_zmalloc("ionic", sizeof(*new), 0);
621 IONIC_PRINT(ERR, "Cannot allocate queue structure");
628 new->q.info = rte_zmalloc("ionic", sizeof(*new->q.info) * num_descs, 0);
630 IONIC_PRINT(ERR, "Cannot allocate queue info");
632 goto err_out_free_qcq;
637 err = ionic_q_init(lif, idev, &new->q, index, num_descs,
638 desc_size, sg_desc_size);
640 IONIC_PRINT(ERR, "Queue initialization failed");
641 goto err_out_free_info;
644 err = ionic_cq_init(lif, &new->cq, num_descs, cq_desc_size);
646 IONIC_PRINT(ERR, "Completion queue initialization failed");
647 goto err_out_free_info;
650 new->base_z = rte_eth_dma_zone_reserve(lif->eth_dev,
651 base /* name */, index /* queue_idx */,
652 total_size, IONIC_ALIGN, socket_id);
655 IONIC_PRINT(ERR, "Cannot reserve queue DMA memory");
657 goto err_out_free_info;
660 new->base = new->base_z->addr;
661 new->base_pa = new->base_z->iova;
662 new->total_size = total_size;
665 q_base_pa = new->base_pa;
667 cq_base = (void *)RTE_ALIGN((uintptr_t)q_base + q_size, PAGE_SIZE);
668 cq_base_pa = RTE_ALIGN(q_base_pa + q_size, PAGE_SIZE);
670 if (flags & IONIC_QCQ_F_SG) {
671 sg_base = (void *)RTE_ALIGN((uintptr_t)cq_base + cq_size,
673 sg_base_pa = RTE_ALIGN(cq_base_pa + cq_size, PAGE_SIZE);
674 ionic_q_sg_map(&new->q, sg_base, sg_base_pa);
677 IONIC_PRINT(DEBUG, "Q-Base-PA = %#jx CQ-Base-PA = %#jx "
679 q_base_pa, cq_base_pa, sg_base_pa);
681 ionic_q_map(&new->q, q_base, q_base_pa);
682 ionic_cq_map(&new->cq, cq_base, cq_base_pa);
683 ionic_cq_bind(&new->cq, &new->q);
690 rte_free(new->q.info);
698 ionic_qcq_free(struct ionic_qcq *qcq)
703 rte_memzone_free(qcq->base_z);
708 rte_free(qcq->q.info);
716 ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t nrxq_descs,
717 struct ionic_qcq **qcq)
722 flags = IONIC_QCQ_F_SG;
723 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, index, "rx", flags,
725 sizeof(struct ionic_rxq_desc),
726 sizeof(struct ionic_rxq_comp),
727 sizeof(struct ionic_rxq_sg_desc),
728 &lif->rxqcqs[index]);
732 *qcq = lif->rxqcqs[index];
738 ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t ntxq_descs,
739 struct ionic_qcq **qcq)
744 flags = IONIC_QCQ_F_SG;
745 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, index, "tx", flags,
747 sizeof(struct ionic_txq_desc),
748 sizeof(struct ionic_txq_comp),
749 sizeof(struct ionic_txq_sg_desc),
750 &lif->txqcqs[index]);
754 *qcq = lif->txqcqs[index];
760 ionic_admin_qcq_alloc(struct ionic_lif *lif)
766 err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags,
768 sizeof(struct ionic_admin_cmd),
769 sizeof(struct ionic_admin_comp),
779 ionic_notify_qcq_alloc(struct ionic_lif *lif)
781 struct ionic_qcq *nqcq;
782 struct ionic_dev *idev = &lif->adapter->idev;
786 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notify",
788 IONIC_NOTIFYQ_LENGTH,
789 sizeof(struct ionic_notifyq_cmd),
790 sizeof(union ionic_notifyq_comp),
796 err = ionic_intr_alloc(lif, &nqcq->intr);
798 ionic_qcq_free(nqcq);
802 ionic_intr_mask_assert(idev->intr_ctrl, nqcq->intr.index,
803 IONIC_INTR_MASK_SET);
805 lif->notifyqcq = nqcq;
811 ionic_bus_map_dbpage(struct ionic_adapter *adapter, int page_num)
813 char *vaddr = adapter->bars[IONIC_PCI_BAR_DBELL].vaddr;
815 if (adapter->num_bars <= IONIC_PCI_BAR_DBELL)
818 return (void *)&vaddr[page_num << PAGE_SHIFT];
822 ionic_lif_alloc(struct ionic_lif *lif)
824 struct ionic_adapter *adapter = lif->adapter;
825 uint32_t socket_id = rte_socket_id();
829 * lif->name was zeroed on allocation.
830 * Copy (sizeof() - 1) bytes to ensure that it is NULL terminated.
832 memcpy(lif->name, lif->eth_dev->data->name, sizeof(lif->name) - 1);
834 IONIC_PRINT(DEBUG, "LIF: %s", lif->name);
836 IONIC_PRINT(DEBUG, "Allocating Lif Info");
838 rte_spinlock_init(&lif->adminq_lock);
839 rte_spinlock_init(&lif->adminq_service_lock);
841 lif->kern_dbpage = ionic_bus_map_dbpage(adapter, 0);
842 if (!lif->kern_dbpage) {
843 IONIC_PRINT(ERR, "Cannot map dbpage, aborting");
847 lif->txqcqs = rte_zmalloc("ionic", sizeof(*lif->txqcqs) *
848 adapter->max_ntxqs_per_lif, 0);
851 IONIC_PRINT(ERR, "Cannot allocate tx queues array");
855 lif->rxqcqs = rte_zmalloc("ionic", sizeof(*lif->rxqcqs) *
856 adapter->max_nrxqs_per_lif, 0);
859 IONIC_PRINT(ERR, "Cannot allocate rx queues array");
863 IONIC_PRINT(DEBUG, "Allocating Notify Queue");
865 err = ionic_notify_qcq_alloc(lif);
867 IONIC_PRINT(ERR, "Cannot allocate notify queue");
871 IONIC_PRINT(DEBUG, "Allocating Admin Queue");
873 err = ionic_admin_qcq_alloc(lif);
875 IONIC_PRINT(ERR, "Cannot allocate admin queue");
879 IONIC_PRINT(DEBUG, "Allocating Lif Info");
881 lif->info_sz = RTE_ALIGN(sizeof(*lif->info), PAGE_SIZE);
883 lif->info_z = rte_eth_dma_zone_reserve(lif->eth_dev,
884 "lif_info", 0 /* queue_idx*/,
885 lif->info_sz, IONIC_ALIGN, socket_id);
887 IONIC_PRINT(ERR, "Cannot allocate lif info memory");
891 lif->info = lif->info_z->addr;
892 lif->info_pa = lif->info_z->iova;
898 ionic_lif_free(struct ionic_lif *lif)
900 if (lif->notifyqcq) {
901 ionic_qcq_free(lif->notifyqcq);
902 lif->notifyqcq = NULL;
906 ionic_qcq_free(lif->adminqcq);
907 lif->adminqcq = NULL;
911 rte_free(lif->txqcqs);
916 rte_free(lif->rxqcqs);
921 rte_memzone_free(lif->info_z);
927 ionic_lif_free_queues(struct ionic_lif *lif)
931 for (i = 0; i < lif->ntxqcqs; i++) {
932 ionic_dev_tx_queue_release(lif->eth_dev->data->tx_queues[i]);
933 lif->eth_dev->data->tx_queues[i] = NULL;
935 for (i = 0; i < lif->nrxqcqs; i++) {
936 ionic_dev_rx_queue_release(lif->eth_dev->data->rx_queues[i]);
937 lif->eth_dev->data->rx_queues[i] = NULL;
942 ionic_lif_rss_config(struct ionic_lif *lif,
943 const uint16_t types, const uint8_t *key, const uint32_t *indir)
945 struct ionic_admin_ctx ctx = {
946 .pending_work = true,
948 .opcode = IONIC_CMD_LIF_SETATTR,
949 .attr = IONIC_LIF_ATTR_RSS,
951 .rss.addr = lif->rss_ind_tbl_pa,
958 lif->rss_types = types;
961 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE);
964 for (i = 0; i < lif->adapter->ident.lif.eth.rss_ind_tbl_sz; i++)
965 lif->rss_ind_tbl[i] = indir[i];
967 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key,
968 IONIC_RSS_HASH_KEY_SIZE);
970 return ionic_adminq_post_wait(lif, &ctx);
974 ionic_lif_rss_setup(struct ionic_lif *lif)
976 static const uint8_t toeplitz_symmetric_key[] = {
977 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
978 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
979 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
980 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
981 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
984 uint16_t tbl_sz = lif->adapter->ident.lif.eth.rss_ind_tbl_sz;
988 if (!lif->rss_ind_tbl_z) {
989 lif->rss_ind_tbl_z = rte_eth_dma_zone_reserve(lif->eth_dev,
990 "rss_ind_tbl", 0 /* queue_idx */,
991 sizeof(*lif->rss_ind_tbl) * tbl_sz,
992 IONIC_ALIGN, rte_socket_id());
993 if (!lif->rss_ind_tbl_z) {
994 IONIC_PRINT(ERR, "OOM");
998 lif->rss_ind_tbl = lif->rss_ind_tbl_z->addr;
999 lif->rss_ind_tbl_pa = lif->rss_ind_tbl_z->iova;
1002 if (lif->rss_ind_tbl_nrxqcqs != lif->nrxqcqs) {
1003 lif->rss_ind_tbl_nrxqcqs = lif->nrxqcqs;
1005 /* Fill indirection table with 'default' values */
1006 for (i = 0; i < tbl_sz; i++)
1007 lif->rss_ind_tbl[i] = i % lif->nrxqcqs;
1010 return ionic_lif_rss_config(lif, IONIC_RSS_OFFLOAD_ALL,
1011 toeplitz_symmetric_key, NULL);
1015 ionic_lif_rss_teardown(struct ionic_lif *lif)
1017 if (!lif->rss_ind_tbl)
1020 if (lif->rss_ind_tbl_z) {
1021 /* Disable RSS on the NIC */
1022 ionic_lif_rss_config(lif, 0x0, NULL, NULL);
1024 lif->rss_ind_tbl = NULL;
1025 lif->rss_ind_tbl_pa = 0;
1026 rte_memzone_free(lif->rss_ind_tbl_z);
1027 lif->rss_ind_tbl_z = NULL;
1032 ionic_lif_qcq_deinit(struct ionic_qcq *qcq)
1034 qcq->flags &= ~IONIC_QCQ_F_INITED;
1038 ionic_lif_txq_deinit(struct ionic_qcq *qcq)
1040 ionic_lif_qcq_deinit(qcq);
1044 ionic_lif_rxq_deinit(struct ionic_qcq *qcq)
1046 ionic_lif_qcq_deinit(qcq);
1050 ionic_lif_notifyq_deinit(struct ionic_lif *lif)
1052 struct ionic_qcq *nqcq = lif->notifyqcq;
1053 struct ionic_dev *idev = &lif->adapter->idev;
1055 if (!(nqcq->flags & IONIC_QCQ_F_INITED))
1058 ionic_intr_mask(idev->intr_ctrl, nqcq->intr.index,
1059 IONIC_INTR_MASK_SET);
1061 nqcq->flags &= ~IONIC_QCQ_F_INITED;
1065 ionic_adminq_service(struct ionic_cq *cq, uint32_t cq_desc_index,
1066 void *cb_arg __rte_unused)
1068 struct ionic_admin_comp *cq_desc_base = cq->base;
1069 struct ionic_admin_comp *cq_desc = &cq_desc_base[cq_desc_index];
1071 if (!color_match(cq_desc->color, cq->done_color))
1074 ionic_q_service(cq->bound_q, cq_desc_index, cq_desc->comp_index, NULL);
1079 /* This acts like ionic_napi */
1081 ionic_qcq_service(struct ionic_qcq *qcq, int budget, ionic_cq_cb cb,
1084 struct ionic_cq *cq = &qcq->cq;
1087 work_done = ionic_cq_service(cq, budget, cb, cb_arg);
1093 ionic_link_status_check(struct ionic_lif *lif)
1095 struct ionic_adapter *adapter = lif->adapter;
1098 lif->state &= ~IONIC_LIF_F_LINK_CHECK_NEEDED;
1103 link_up = (lif->info->status.link_status == IONIC_PORT_OPER_STATUS_UP);
1105 if ((link_up && adapter->link_up) ||
1106 (!link_up && !adapter->link_up))
1110 adapter->link_speed = lif->info->status.link_speed;
1111 IONIC_PRINT(DEBUG, "Link up - %d Gbps",
1112 adapter->link_speed);
1114 IONIC_PRINT(DEBUG, "Link down");
1117 adapter->link_up = link_up;
1118 ionic_dev_link_update(lif->eth_dev, 0);
1122 ionic_lif_handle_fw_down(struct ionic_lif *lif)
1124 if (lif->state & IONIC_LIF_F_FW_RESET)
1127 lif->state |= IONIC_LIF_F_FW_RESET;
1129 if (lif->state & IONIC_LIF_F_UP) {
1131 "Surprise FW stop, stopping %s\n", lif->name);
1132 ionic_lif_stop(lif);
1135 IONIC_PRINT(NOTICE, "FW down, %s stopped", lif->name);
1139 ionic_notifyq_cb(struct ionic_cq *cq, uint32_t cq_desc_index, void *cb_arg)
1141 union ionic_notifyq_comp *cq_desc_base = cq->base;
1142 union ionic_notifyq_comp *cq_desc = &cq_desc_base[cq_desc_index];
1143 struct ionic_lif *lif = cb_arg;
1145 IONIC_PRINT(DEBUG, "Notifyq callback eid = %jd ecode = %d",
1146 cq_desc->event.eid, cq_desc->event.ecode);
1148 /* Have we run out of new completions to process? */
1149 if (!(cq_desc->event.eid > lif->last_eid))
1152 lif->last_eid = cq_desc->event.eid;
1154 switch (cq_desc->event.ecode) {
1155 case IONIC_EVENT_LINK_CHANGE:
1157 "Notifyq IONIC_EVENT_LINK_CHANGE %s "
1158 "eid=%jd link_status=%d link_speed=%d",
1161 cq_desc->link_change.link_status,
1162 cq_desc->link_change.link_speed);
1164 lif->state |= IONIC_LIF_F_LINK_CHECK_NEEDED;
1167 case IONIC_EVENT_RESET:
1169 "Notifyq IONIC_EVENT_RESET %s "
1170 "eid=%jd, reset_code=%d state=%d",
1173 cq_desc->reset.reset_code,
1174 cq_desc->reset.state);
1175 ionic_lif_handle_fw_down(lif);
1179 IONIC_PRINT(WARNING, "Notifyq bad event ecode=%d eid=%jd",
1180 cq_desc->event.ecode, cq_desc->event.eid);
1188 ionic_notifyq_handler(struct ionic_lif *lif, int budget)
1190 struct ionic_dev *idev = &lif->adapter->idev;
1191 struct ionic_qcq *qcq = lif->notifyqcq;
1194 if (!(qcq->flags & IONIC_QCQ_F_INITED)) {
1195 IONIC_PRINT(DEBUG, "Notifyq not yet initialized");
1199 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1200 IONIC_INTR_MASK_SET);
1202 work_done = ionic_qcq_service(qcq, budget, ionic_notifyq_cb, lif);
1204 if (lif->state & IONIC_LIF_F_LINK_CHECK_NEEDED)
1205 ionic_link_status_check(lif);
1207 ionic_intr_credits(idev->intr_ctrl, qcq->intr.index,
1208 work_done, IONIC_INTR_CRED_RESET_COALESCE);
1210 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1211 IONIC_INTR_MASK_CLEAR);
1217 ionic_lif_adminq_init(struct ionic_lif *lif)
1219 struct ionic_dev *idev = &lif->adapter->idev;
1220 struct ionic_qcq *qcq = lif->adminqcq;
1221 struct ionic_queue *q = &qcq->q;
1222 struct ionic_q_init_comp comp;
1225 ionic_dev_cmd_adminq_init(idev, qcq);
1226 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1230 ionic_dev_cmd_comp(idev, &comp);
1232 q->hw_type = comp.hw_type;
1233 q->hw_index = comp.hw_index;
1234 q->db = ionic_db_map(lif, q);
1236 IONIC_PRINT(DEBUG, "adminq->hw_type %d", q->hw_type);
1237 IONIC_PRINT(DEBUG, "adminq->hw_index %d", q->hw_index);
1238 IONIC_PRINT(DEBUG, "adminq->db %p", q->db);
1240 qcq->flags |= IONIC_QCQ_F_INITED;
1246 ionic_lif_notifyq_init(struct ionic_lif *lif)
1248 struct ionic_dev *idev = &lif->adapter->idev;
1249 struct ionic_qcq *qcq = lif->notifyqcq;
1250 struct ionic_queue *q = &qcq->q;
1253 struct ionic_admin_ctx ctx = {
1254 .pending_work = true,
1256 .opcode = IONIC_CMD_Q_INIT,
1259 .flags = (IONIC_QINIT_F_IRQ | IONIC_QINIT_F_ENA),
1260 .intr_index = qcq->intr.index,
1261 .ring_size = rte_log2_u32(q->num_descs),
1262 .ring_base = q->base_pa,
1266 IONIC_PRINT(DEBUG, "notifyq_init.index %d",
1267 ctx.cmd.q_init.index);
1268 IONIC_PRINT(DEBUG, "notifyq_init.ring_base 0x%" PRIx64 "",
1269 ctx.cmd.q_init.ring_base);
1270 IONIC_PRINT(DEBUG, "notifyq_init.ring_size %d",
1271 ctx.cmd.q_init.ring_size);
1272 IONIC_PRINT(DEBUG, "notifyq_init.ver %u", ctx.cmd.q_init.ver);
1274 err = ionic_adminq_post_wait(lif, &ctx);
1278 q->hw_type = ctx.comp.q_init.hw_type;
1279 q->hw_index = ctx.comp.q_init.hw_index;
1282 IONIC_PRINT(DEBUG, "notifyq->hw_type %d", q->hw_type);
1283 IONIC_PRINT(DEBUG, "notifyq->hw_index %d", q->hw_index);
1284 IONIC_PRINT(DEBUG, "notifyq->db %p", q->db);
1286 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1287 IONIC_INTR_MASK_CLEAR);
1289 qcq->flags |= IONIC_QCQ_F_INITED;
1295 ionic_lif_set_features(struct ionic_lif *lif)
1297 struct ionic_admin_ctx ctx = {
1298 .pending_work = true,
1299 .cmd.lif_setattr = {
1300 .opcode = IONIC_CMD_LIF_SETATTR,
1301 .attr = IONIC_LIF_ATTR_FEATURES,
1302 .features = lif->features,
1307 err = ionic_adminq_post_wait(lif, &ctx);
1311 lif->hw_features = (ctx.cmd.lif_setattr.features &
1312 ctx.comp.lif_setattr.features);
1314 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
1315 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_TX_TAG");
1316 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
1317 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_STRIP");
1318 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
1319 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_FILTER");
1320 if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
1321 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_HASH");
1322 if (lif->hw_features & IONIC_ETH_HW_TX_SG)
1323 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_SG");
1324 if (lif->hw_features & IONIC_ETH_HW_RX_SG)
1325 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_SG");
1326 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
1327 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_CSUM");
1328 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
1329 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_CSUM");
1330 if (lif->hw_features & IONIC_ETH_HW_TSO)
1331 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO");
1332 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
1333 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPV6");
1334 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
1335 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_ECN");
1336 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
1337 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE");
1338 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
1339 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE_CSUM");
1340 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
1341 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP4");
1342 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
1343 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP6");
1344 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
1345 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP");
1346 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
1347 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP_CSUM");
1353 ionic_lif_txq_init(struct ionic_qcq *qcq)
1355 struct ionic_queue *q = &qcq->q;
1356 struct ionic_lif *lif = qcq->lif;
1357 struct ionic_cq *cq = &qcq->cq;
1358 struct ionic_admin_ctx ctx = {
1359 .pending_work = true,
1361 .opcode = IONIC_CMD_Q_INIT,
1364 .flags = IONIC_QINIT_F_SG | IONIC_QINIT_F_ENA,
1365 .intr_index = IONIC_INTR_NONE,
1366 .ring_size = rte_log2_u32(q->num_descs),
1367 .ring_base = q->base_pa,
1368 .cq_ring_base = cq->base_pa,
1369 .sg_ring_base = q->sg_base_pa,
1374 IONIC_PRINT(DEBUG, "txq_init.index %d", ctx.cmd.q_init.index);
1375 IONIC_PRINT(DEBUG, "txq_init.ring_base 0x%" PRIx64 "",
1376 ctx.cmd.q_init.ring_base);
1377 IONIC_PRINT(DEBUG, "txq_init.ring_size %d",
1378 ctx.cmd.q_init.ring_size);
1379 IONIC_PRINT(DEBUG, "txq_init.ver %u", ctx.cmd.q_init.ver);
1381 err = ionic_adminq_post_wait(qcq->lif, &ctx);
1385 q->hw_type = ctx.comp.q_init.hw_type;
1386 q->hw_index = ctx.comp.q_init.hw_index;
1387 q->db = ionic_db_map(lif, q);
1389 IONIC_PRINT(DEBUG, "txq->hw_type %d", q->hw_type);
1390 IONIC_PRINT(DEBUG, "txq->hw_index %d", q->hw_index);
1391 IONIC_PRINT(DEBUG, "txq->db %p", q->db);
1393 qcq->flags |= IONIC_QCQ_F_INITED;
1399 ionic_lif_rxq_init(struct ionic_qcq *qcq)
1401 struct ionic_queue *q = &qcq->q;
1402 struct ionic_lif *lif = qcq->lif;
1403 struct ionic_cq *cq = &qcq->cq;
1404 struct ionic_admin_ctx ctx = {
1405 .pending_work = true,
1407 .opcode = IONIC_CMD_Q_INIT,
1410 .flags = IONIC_QINIT_F_SG | IONIC_QINIT_F_ENA,
1411 .intr_index = IONIC_INTR_NONE,
1412 .ring_size = rte_log2_u32(q->num_descs),
1413 .ring_base = q->base_pa,
1414 .cq_ring_base = cq->base_pa,
1415 .sg_ring_base = q->sg_base_pa,
1420 IONIC_PRINT(DEBUG, "rxq_init.index %d", ctx.cmd.q_init.index);
1421 IONIC_PRINT(DEBUG, "rxq_init.ring_base 0x%" PRIx64 "",
1422 ctx.cmd.q_init.ring_base);
1423 IONIC_PRINT(DEBUG, "rxq_init.ring_size %d",
1424 ctx.cmd.q_init.ring_size);
1425 IONIC_PRINT(DEBUG, "rxq_init.ver %u", ctx.cmd.q_init.ver);
1427 err = ionic_adminq_post_wait(qcq->lif, &ctx);
1431 q->hw_type = ctx.comp.q_init.hw_type;
1432 q->hw_index = ctx.comp.q_init.hw_index;
1433 q->db = ionic_db_map(lif, q);
1435 qcq->flags |= IONIC_QCQ_F_INITED;
1437 IONIC_PRINT(DEBUG, "rxq->hw_type %d", q->hw_type);
1438 IONIC_PRINT(DEBUG, "rxq->hw_index %d", q->hw_index);
1439 IONIC_PRINT(DEBUG, "rxq->db %p", q->db);
1445 ionic_station_set(struct ionic_lif *lif)
1447 struct ionic_admin_ctx ctx = {
1448 .pending_work = true,
1449 .cmd.lif_getattr = {
1450 .opcode = IONIC_CMD_LIF_GETATTR,
1451 .attr = IONIC_LIF_ATTR_MAC,
1458 err = ionic_adminq_post_wait(lif, &ctx);
1462 memcpy(lif->mac_addr, ctx.comp.lif_getattr.mac, RTE_ETHER_ADDR_LEN);
1468 ionic_lif_set_name(struct ionic_lif *lif)
1470 struct ionic_admin_ctx ctx = {
1471 .pending_work = true,
1472 .cmd.lif_setattr = {
1473 .opcode = IONIC_CMD_LIF_SETATTR,
1474 .attr = IONIC_LIF_ATTR_NAME,
1478 memcpy(ctx.cmd.lif_setattr.name, lif->name,
1479 sizeof(ctx.cmd.lif_setattr.name) - 1);
1481 ionic_adminq_post_wait(lif, &ctx);
1485 ionic_lif_init(struct ionic_lif *lif)
1487 struct ionic_dev *idev = &lif->adapter->idev;
1488 struct ionic_q_init_comp comp;
1491 memset(&lif->stats_base, 0, sizeof(lif->stats_base));
1493 ionic_dev_cmd_lif_init(idev, lif->info_pa);
1494 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1495 ionic_dev_cmd_comp(idev, &comp);
1499 lif->hw_index = comp.hw_index;
1501 err = ionic_lif_adminq_init(lif);
1505 err = ionic_lif_notifyq_init(lif);
1507 goto err_out_adminq_deinit;
1510 * Configure initial feature set
1511 * This will be updated later by the dev_configure() step
1513 lif->features = IONIC_ETH_HW_RX_HASH | IONIC_ETH_HW_VLAN_RX_FILTER;
1515 err = ionic_lif_set_features(lif);
1517 goto err_out_notifyq_deinit;
1519 err = ionic_rx_filters_init(lif);
1521 goto err_out_notifyq_deinit;
1523 err = ionic_station_set(lif);
1525 goto err_out_rx_filter_deinit;
1527 ionic_lif_set_name(lif);
1529 lif->state |= IONIC_LIF_F_INITED;
1533 err_out_rx_filter_deinit:
1534 ionic_rx_filters_deinit(lif);
1536 err_out_notifyq_deinit:
1537 ionic_lif_notifyq_deinit(lif);
1539 err_out_adminq_deinit:
1540 ionic_lif_qcq_deinit(lif->adminqcq);
1546 ionic_lif_deinit(struct ionic_lif *lif)
1548 if (!(lif->state & IONIC_LIF_F_INITED))
1551 ionic_rx_filters_deinit(lif);
1552 ionic_lif_rss_teardown(lif);
1553 ionic_lif_notifyq_deinit(lif);
1554 ionic_lif_qcq_deinit(lif->adminqcq);
1556 lif->state &= ~IONIC_LIF_F_INITED;
1560 ionic_lif_configure_vlan_offload(struct ionic_lif *lif, int mask)
1562 struct rte_eth_dev *eth_dev = lif->eth_dev;
1563 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1566 * IONIC_ETH_HW_VLAN_RX_FILTER cannot be turned off, so
1567 * set DEV_RX_OFFLOAD_VLAN_FILTER and ignore ETH_VLAN_FILTER_MASK
1569 rxmode->offloads |= DEV_RX_OFFLOAD_VLAN_FILTER;
1571 if (mask & ETH_VLAN_STRIP_MASK) {
1572 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1573 lif->features |= IONIC_ETH_HW_VLAN_RX_STRIP;
1575 lif->features &= ~IONIC_ETH_HW_VLAN_RX_STRIP;
1580 ionic_lif_configure(struct ionic_lif *lif)
1582 struct rte_eth_rxmode *rxmode = &lif->eth_dev->data->dev_conf.rxmode;
1583 struct rte_eth_txmode *txmode = &lif->eth_dev->data->dev_conf.txmode;
1584 struct ionic_identity *ident = &lif->adapter->ident;
1585 uint32_t ntxqs_per_lif =
1586 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ];
1587 uint32_t nrxqs_per_lif =
1588 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ];
1589 uint32_t nrxqs = lif->eth_dev->data->nb_rx_queues;
1590 uint32_t ntxqs = lif->eth_dev->data->nb_tx_queues;
1592 lif->port_id = lif->eth_dev->data->port_id;
1594 IONIC_PRINT(DEBUG, "Configuring LIF on port %u",
1598 nrxqs_per_lif = RTE_MIN(nrxqs_per_lif, nrxqs);
1601 ntxqs_per_lif = RTE_MIN(ntxqs_per_lif, ntxqs);
1603 lif->nrxqcqs = nrxqs_per_lif;
1604 lif->ntxqcqs = ntxqs_per_lif;
1606 /* Update the LIF configuration based on the eth_dev */
1609 * NB: While it is true that RSS_HASH is always enabled on ionic,
1610 * setting this flag unconditionally causes problems in DTS.
1611 * rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1616 if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM ||
1617 rxmode->offloads & DEV_RX_OFFLOAD_UDP_CKSUM ||
1618 rxmode->offloads & DEV_RX_OFFLOAD_TCP_CKSUM)
1619 lif->features |= IONIC_ETH_HW_RX_CSUM;
1621 lif->features &= ~IONIC_ETH_HW_RX_CSUM;
1623 if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER) {
1624 lif->features |= IONIC_ETH_HW_RX_SG;
1625 lif->eth_dev->data->scattered_rx = 1;
1627 lif->features &= ~IONIC_ETH_HW_RX_SG;
1628 lif->eth_dev->data->scattered_rx = 0;
1631 /* Covers VLAN_STRIP */
1632 ionic_lif_configure_vlan_offload(lif, ETH_VLAN_STRIP_MASK);
1636 if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
1637 txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
1638 txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM ||
1639 txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
1640 txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)
1641 lif->features |= IONIC_ETH_HW_TX_CSUM;
1643 lif->features &= ~IONIC_ETH_HW_TX_CSUM;
1645 if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
1646 lif->features |= IONIC_ETH_HW_VLAN_TX_TAG;
1648 lif->features &= ~IONIC_ETH_HW_VLAN_TX_TAG;
1650 if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
1651 lif->features |= IONIC_ETH_HW_TX_SG;
1653 lif->features &= ~IONIC_ETH_HW_TX_SG;
1655 if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
1656 lif->features |= IONIC_ETH_HW_TSO;
1657 lif->features |= IONIC_ETH_HW_TSO_IPV6;
1658 lif->features |= IONIC_ETH_HW_TSO_ECN;
1660 lif->features &= ~IONIC_ETH_HW_TSO;
1661 lif->features &= ~IONIC_ETH_HW_TSO_IPV6;
1662 lif->features &= ~IONIC_ETH_HW_TSO_ECN;
1667 ionic_lif_start(struct ionic_lif *lif)
1673 err = ionic_lif_rss_setup(lif);
1677 if (!lif->rx_mode) {
1678 IONIC_PRINT(DEBUG, "Setting RX mode on %s",
1681 rx_mode = IONIC_RX_MODE_F_UNICAST;
1682 rx_mode |= IONIC_RX_MODE_F_MULTICAST;
1683 rx_mode |= IONIC_RX_MODE_F_BROADCAST;
1685 ionic_set_rx_mode(lif, rx_mode);
1688 IONIC_PRINT(DEBUG, "Starting %u RX queues and %u TX queues "
1690 lif->nrxqcqs, lif->ntxqcqs, lif->port_id);
1692 for (i = 0; i < lif->nrxqcqs; i++) {
1693 struct ionic_qcq *rxq = lif->rxqcqs[i];
1694 if (!(rxq->flags & IONIC_QCQ_F_DEFERRED)) {
1695 err = ionic_dev_rx_queue_start(lif->eth_dev, i);
1702 for (i = 0; i < lif->ntxqcqs; i++) {
1703 struct ionic_qcq *txq = lif->txqcqs[i];
1704 if (!(txq->flags & IONIC_QCQ_F_DEFERRED)) {
1705 err = ionic_dev_tx_queue_start(lif->eth_dev, i);
1712 /* Carrier ON here */
1713 lif->state |= IONIC_LIF_F_UP;
1715 ionic_link_status_check(lif);
1721 ionic_lif_identify(struct ionic_adapter *adapter)
1723 struct ionic_dev *idev = &adapter->idev;
1724 struct ionic_identity *ident = &adapter->ident;
1727 unsigned int lif_words = sizeof(ident->lif.words) /
1728 sizeof(ident->lif.words[0]);
1729 unsigned int cmd_words = sizeof(idev->dev_cmd->data) /
1730 sizeof(idev->dev_cmd->data[0]);
1731 unsigned int nwords;
1733 ionic_dev_cmd_lif_identify(idev, IONIC_LIF_TYPE_CLASSIC,
1734 IONIC_IDENTITY_VERSION_1);
1735 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1739 nwords = RTE_MIN(lif_words, cmd_words);
1740 for (i = 0; i < nwords; i++)
1741 ident->lif.words[i] = ioread32(&idev->dev_cmd->data[i]);
1743 IONIC_PRINT(INFO, "capabilities 0x%" PRIx64 " ",
1744 ident->lif.capabilities);
1746 IONIC_PRINT(INFO, "eth.max_ucast_filters 0x%" PRIx32 " ",
1747 ident->lif.eth.max_ucast_filters);
1748 IONIC_PRINT(INFO, "eth.max_mcast_filters 0x%" PRIx32 " ",
1749 ident->lif.eth.max_mcast_filters);
1751 IONIC_PRINT(INFO, "eth.features 0x%" PRIx64 " ",
1752 ident->lif.eth.config.features);
1753 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_ADMINQ] 0x%" PRIx32 " ",
1754 ident->lif.eth.config.queue_count[IONIC_QTYPE_ADMINQ]);
1755 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] 0x%" PRIx32 " ",
1756 ident->lif.eth.config.queue_count[IONIC_QTYPE_NOTIFYQ]);
1757 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_RXQ] 0x%" PRIx32 " ",
1758 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ]);
1759 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_TXQ] 0x%" PRIx32 " ",
1760 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ]);
1766 ionic_lifs_size(struct ionic_adapter *adapter)
1768 struct ionic_identity *ident = &adapter->ident;
1769 uint32_t nintrs, dev_nintrs = ident->dev.nintrs;
1771 adapter->max_ntxqs_per_lif =
1772 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ];
1773 adapter->max_nrxqs_per_lif =
1774 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ];
1776 nintrs = 1 /* notifyq */;
1778 if (nintrs > dev_nintrs) {
1780 "At most %d intr supported, minimum req'd is %u",
1781 dev_nintrs, nintrs);
1785 adapter->nintrs = nintrs;