1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
5 #include <rte_malloc.h>
6 #include <rte_ethdev_driver.h>
9 #include "ionic_logs.h"
10 #include "ionic_lif.h"
11 #include "ionic_ethdev.h"
12 #include "ionic_rx_filter.h"
13 #include "ionic_rxtx.h"
15 static int ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr);
16 static int ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr);
19 ionic_qcq_enable(struct ionic_qcq *qcq)
21 struct ionic_queue *q = &qcq->q;
22 struct ionic_lif *lif = q->lif;
23 struct ionic_dev *idev = &lif->adapter->idev;
24 struct ionic_admin_ctx ctx = {
27 .opcode = IONIC_CMD_Q_CONTROL,
28 .lif_index = lif->index,
31 .oper = IONIC_Q_ENABLE,
35 if (qcq->flags & IONIC_QCQ_F_INTR) {
36 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
37 IONIC_INTR_MASK_CLEAR);
40 return ionic_adminq_post_wait(lif, &ctx);
44 ionic_qcq_disable(struct ionic_qcq *qcq)
46 struct ionic_queue *q = &qcq->q;
47 struct ionic_lif *lif = q->lif;
48 struct ionic_dev *idev = &lif->adapter->idev;
49 struct ionic_admin_ctx ctx = {
52 .opcode = IONIC_CMD_Q_CONTROL,
53 .lif_index = lif->index,
56 .oper = IONIC_Q_DISABLE,
60 if (qcq->flags & IONIC_QCQ_F_INTR) {
61 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
65 return ionic_adminq_post_wait(lif, &ctx);
69 ionic_lif_stop(struct ionic_lif *lif __rte_unused)
71 /* Carrier OFF here */
77 ionic_lif_reset(struct ionic_lif *lif)
79 struct ionic_dev *idev = &lif->adapter->idev;
83 ionic_dev_cmd_lif_reset(idev, lif->index);
84 ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
88 ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr)
90 struct ionic_admin_ctx ctx = {
92 .cmd.rx_filter_add = {
93 .opcode = IONIC_CMD_RX_FILTER_ADD,
94 .match = IONIC_RX_FILTER_MATCH_MAC,
99 memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, RTE_ETHER_ADDR_LEN);
101 err = ionic_adminq_post_wait(lif, &ctx);
105 IONIC_PRINT(INFO, "rx_filter add (id %d)",
106 ctx.comp.rx_filter_add.filter_id);
108 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);
112 ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr)
114 struct ionic_admin_ctx ctx = {
115 .pending_work = true,
116 .cmd.rx_filter_del = {
117 .opcode = IONIC_CMD_RX_FILTER_DEL,
120 struct ionic_rx_filter *f;
125 rte_spinlock_lock(&lif->rx_filters.lock);
127 f = ionic_rx_filter_by_addr(lif, addr);
129 rte_spinlock_unlock(&lif->rx_filters.lock);
133 ctx.cmd.rx_filter_del.filter_id = f->filter_id;
134 ionic_rx_filter_free(f);
136 rte_spinlock_unlock(&lif->rx_filters.lock);
138 err = ionic_adminq_post_wait(lif, &ctx);
142 IONIC_PRINT(INFO, "rx_filter del (id %d)",
143 ctx.cmd.rx_filter_del.filter_id);
149 ionic_dev_add_mac(struct rte_eth_dev *eth_dev,
150 struct rte_ether_addr *mac_addr,
151 uint32_t index __rte_unused, uint32_t pool __rte_unused)
153 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
157 return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr);
161 ionic_dev_remove_mac(struct rte_eth_dev *eth_dev, uint32_t index __rte_unused)
163 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
164 struct ionic_adapter *adapter = lif->adapter;
168 if (index >= adapter->max_mac_addrs) {
170 "Index %u is above MAC filter limit %u",
171 index, adapter->max_mac_addrs);
175 if (!rte_is_valid_assigned_ether_addr(ð_dev->data->mac_addrs[index]))
178 ionic_lif_addr_del(lif, (const uint8_t *)
179 ð_dev->data->mac_addrs[index]);
183 ionic_dev_set_mac(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr)
185 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
189 if (mac_addr == NULL) {
190 IONIC_PRINT(NOTICE, "New mac is null");
194 if (!rte_is_zero_ether_addr((struct rte_ether_addr *)lif->mac_addr)) {
195 IONIC_PRINT(INFO, "Deleting mac addr %pM",
197 ionic_lif_addr_del(lif, lif->mac_addr);
198 memset(lif->mac_addr, 0, RTE_ETHER_ADDR_LEN);
201 IONIC_PRINT(INFO, "Updating mac addr");
203 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)lif->mac_addr);
205 return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr);
209 ionic_vlan_rx_add_vid(struct ionic_lif *lif, uint16_t vid)
211 struct ionic_admin_ctx ctx = {
212 .pending_work = true,
213 .cmd.rx_filter_add = {
214 .opcode = IONIC_CMD_RX_FILTER_ADD,
215 .match = IONIC_RX_FILTER_MATCH_VLAN,
221 err = ionic_adminq_post_wait(lif, &ctx);
225 IONIC_PRINT(INFO, "rx_filter add VLAN %d (id %d)", vid,
226 ctx.comp.rx_filter_add.filter_id);
228 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);
232 ionic_vlan_rx_kill_vid(struct ionic_lif *lif, uint16_t vid)
234 struct ionic_admin_ctx ctx = {
235 .pending_work = true,
236 .cmd.rx_filter_del = {
237 .opcode = IONIC_CMD_RX_FILTER_DEL,
240 struct ionic_rx_filter *f;
245 rte_spinlock_lock(&lif->rx_filters.lock);
247 f = ionic_rx_filter_by_vlan(lif, vid);
249 rte_spinlock_unlock(&lif->rx_filters.lock);
253 ctx.cmd.rx_filter_del.filter_id = f->filter_id;
254 ionic_rx_filter_free(f);
255 rte_spinlock_unlock(&lif->rx_filters.lock);
257 err = ionic_adminq_post_wait(lif, &ctx);
261 IONIC_PRINT(INFO, "rx_filter del VLAN %d (id %d)", vid,
262 ctx.cmd.rx_filter_del.filter_id);
268 ionic_dev_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id,
271 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
275 err = ionic_vlan_rx_add_vid(lif, vlan_id);
277 err = ionic_vlan_rx_kill_vid(lif, vlan_id);
283 ionic_lif_rx_mode(struct ionic_lif *lif, uint32_t rx_mode)
285 struct ionic_admin_ctx ctx = {
286 .pending_work = true,
288 .opcode = IONIC_CMD_RX_MODE_SET,
289 .lif_index = lif->index,
295 if (rx_mode & IONIC_RX_MODE_F_UNICAST)
296 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_UNICAST");
297 if (rx_mode & IONIC_RX_MODE_F_MULTICAST)
298 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_MULTICAST");
299 if (rx_mode & IONIC_RX_MODE_F_BROADCAST)
300 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_BROADCAST");
301 if (rx_mode & IONIC_RX_MODE_F_PROMISC)
302 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_PROMISC");
303 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI)
304 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_ALLMULTI");
306 err = ionic_adminq_post_wait(lif, &ctx);
308 IONIC_PRINT(ERR, "Failure setting RX mode");
312 ionic_set_rx_mode(struct ionic_lif *lif, uint32_t rx_mode)
314 if (lif->rx_mode != rx_mode) {
315 lif->rx_mode = rx_mode;
316 ionic_lif_rx_mode(lif, rx_mode);
321 ionic_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
323 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
324 uint32_t rx_mode = lif->rx_mode;
328 rx_mode |= IONIC_RX_MODE_F_PROMISC;
330 ionic_set_rx_mode(lif, rx_mode);
336 ionic_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
338 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
339 uint32_t rx_mode = lif->rx_mode;
341 rx_mode &= ~IONIC_RX_MODE_F_PROMISC;
343 ionic_set_rx_mode(lif, rx_mode);
349 ionic_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
351 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
352 uint32_t rx_mode = lif->rx_mode;
354 rx_mode |= IONIC_RX_MODE_F_ALLMULTI;
356 ionic_set_rx_mode(lif, rx_mode);
362 ionic_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
364 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
365 uint32_t rx_mode = lif->rx_mode;
367 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI;
369 ionic_set_rx_mode(lif, rx_mode);
375 ionic_lif_change_mtu(struct ionic_lif *lif, int new_mtu)
377 struct ionic_admin_ctx ctx = {
378 .pending_work = true,
380 .opcode = IONIC_CMD_LIF_SETATTR,
382 .attr = IONIC_LIF_ATTR_MTU,
388 err = ionic_adminq_post_wait(lif, &ctx);
398 ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr)
400 struct ionic_adapter *adapter = lif->adapter;
401 struct ionic_dev *idev = &adapter->idev;
405 * Note: interrupt handler is called for index = 0 only
406 * (we use interrupts for the notifyq only anyway,
407 * which hash index = 0)
410 for (index = 0; index < adapter->nintrs; index++)
411 if (!adapter->intrs[index])
414 if (index == adapter->nintrs)
417 adapter->intrs[index] = true;
419 ionic_intr_init(idev, intr, index);
425 ionic_intr_free(struct ionic_lif *lif, struct ionic_intr_info *intr)
427 if (intr->index != IONIC_INTR_INDEX_NOT_ASSIGNED)
428 lif->adapter->intrs[intr->index] = false;
432 ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type,
434 const char *base, uint32_t flags,
437 uint32_t cq_desc_size,
438 uint32_t sg_desc_size,
439 uint32_t pid, struct ionic_qcq **qcq)
441 struct ionic_dev *idev = &lif->adapter->idev;
442 struct ionic_qcq *new;
443 uint32_t q_size, cq_size, sg_size, total_size;
444 void *q_base, *cq_base, *sg_base;
445 rte_iova_t q_base_pa = 0;
446 rte_iova_t cq_base_pa = 0;
447 rte_iova_t sg_base_pa = 0;
448 uint32_t socket_id = rte_socket_id();
453 q_size = num_descs * desc_size;
454 cq_size = num_descs * cq_desc_size;
455 sg_size = num_descs * sg_desc_size;
457 total_size = RTE_ALIGN(q_size, PAGE_SIZE) +
458 RTE_ALIGN(cq_size, PAGE_SIZE);
460 * Note: aligning q_size/cq_size is not enough due to cq_base address
461 * aligning as q_base could be not aligned to the page.
464 total_size += PAGE_SIZE;
466 if (flags & IONIC_QCQ_F_SG) {
467 total_size += RTE_ALIGN(sg_size, PAGE_SIZE);
468 total_size += PAGE_SIZE;
471 new = rte_zmalloc("ionic", sizeof(*new), 0);
473 IONIC_PRINT(ERR, "Cannot allocate queue structure");
480 new->q.info = rte_zmalloc("ionic", sizeof(*new->q.info) * num_descs, 0);
482 IONIC_PRINT(ERR, "Cannot allocate queue info");
488 err = ionic_q_init(lif, idev, &new->q, index, num_descs,
489 desc_size, sg_desc_size, pid);
491 IONIC_PRINT(ERR, "Queue initialization failed");
495 if (flags & IONIC_QCQ_F_INTR) {
496 err = ionic_intr_alloc(lif, &new->intr);
500 ionic_intr_mask_assert(idev->intr_ctrl, new->intr.index,
501 IONIC_INTR_MASK_SET);
503 new->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED;
506 err = ionic_cq_init(lif, &new->cq, &new->intr,
507 num_descs, cq_desc_size);
509 IONIC_PRINT(ERR, "Completion queue initialization failed");
510 goto err_out_free_intr;
513 new->base_z = rte_eth_dma_zone_reserve(lif->eth_dev,
514 base /* name */, index /* queue_idx */,
515 total_size, IONIC_ALIGN, socket_id);
518 IONIC_PRINT(ERR, "Cannot reserve queue DMA memory");
520 goto err_out_free_intr;
523 new->base = new->base_z->addr;
524 new->base_pa = new->base_z->iova;
525 new->total_size = total_size;
528 q_base_pa = new->base_pa;
530 cq_base = (void *)RTE_ALIGN((uintptr_t)q_base + q_size, PAGE_SIZE);
531 cq_base_pa = RTE_ALIGN(q_base_pa + q_size, PAGE_SIZE);
533 if (flags & IONIC_QCQ_F_SG) {
534 sg_base = (void *)RTE_ALIGN((uintptr_t)cq_base + cq_size,
536 sg_base_pa = RTE_ALIGN(cq_base_pa + cq_size, PAGE_SIZE);
537 ionic_q_sg_map(&new->q, sg_base, sg_base_pa);
540 IONIC_PRINT(DEBUG, "Q-Base-PA = %ju CQ-Base-PA = %ju "
542 q_base_pa, cq_base_pa, sg_base_pa);
544 ionic_q_map(&new->q, q_base, q_base_pa);
545 ionic_cq_map(&new->cq, cq_base, cq_base_pa);
546 ionic_cq_bind(&new->cq, &new->q);
553 if (flags & IONIC_QCQ_F_INTR)
554 ionic_intr_free(lif, &new->intr);
560 ionic_qcq_free(struct ionic_qcq *qcq)
565 rte_memzone_free(qcq->base_z);
570 rte_free(qcq->q.info);
578 ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t nrxq_descs,
579 struct ionic_qcq **qcq)
584 flags = IONIC_QCQ_F_SG;
585 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, index, "rx", flags,
587 sizeof(struct ionic_rxq_desc),
588 sizeof(struct ionic_rxq_comp),
589 sizeof(struct ionic_rxq_sg_desc),
590 lif->kern_pid, &lif->rxqcqs[index]);
594 *qcq = lif->rxqcqs[index];
600 ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t ntxq_descs,
601 struct ionic_qcq **qcq)
606 flags = IONIC_QCQ_F_SG;
607 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, index, "tx", flags,
609 sizeof(struct ionic_txq_desc),
610 sizeof(struct ionic_txq_comp),
611 sizeof(struct ionic_txq_sg_desc),
612 lif->kern_pid, &lif->txqcqs[index]);
616 *qcq = lif->txqcqs[index];
622 ionic_admin_qcq_alloc(struct ionic_lif *lif)
628 err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags,
630 sizeof(struct ionic_admin_cmd),
631 sizeof(struct ionic_admin_comp),
633 lif->kern_pid, &lif->adminqcq);
641 ionic_notify_qcq_alloc(struct ionic_lif *lif)
646 flags = IONIC_QCQ_F_NOTIFYQ | IONIC_QCQ_F_INTR;
648 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notify",
650 IONIC_NOTIFYQ_LENGTH,
651 sizeof(struct ionic_notifyq_cmd),
652 sizeof(union ionic_notifyq_comp),
654 lif->kern_pid, &lif->notifyqcq);
662 ionic_bus_map_dbpage(struct ionic_adapter *adapter, int page_num)
664 char *vaddr = adapter->bars[IONIC_PCI_BAR_DBELL].vaddr;
666 if (adapter->num_bars <= IONIC_PCI_BAR_DBELL)
669 return (void *)&vaddr[page_num << PAGE_SHIFT];
673 ionic_lif_alloc(struct ionic_lif *lif)
675 struct ionic_adapter *adapter = lif->adapter;
676 uint32_t socket_id = rte_socket_id();
680 snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index);
682 IONIC_PRINT(DEBUG, "Allocating Lif Info");
684 rte_spinlock_init(&lif->adminq_lock);
685 rte_spinlock_init(&lif->adminq_service_lock);
689 dbpage_num = ionic_db_page_num(lif, 0);
691 lif->kern_dbpage = ionic_bus_map_dbpage(adapter, dbpage_num);
692 if (!lif->kern_dbpage) {
693 IONIC_PRINT(ERR, "Cannot map dbpage, aborting");
697 lif->txqcqs = rte_zmalloc("ionic", sizeof(*lif->txqcqs) *
698 adapter->max_ntxqs_per_lif, 0);
701 IONIC_PRINT(ERR, "Cannot allocate tx queues array");
705 lif->rxqcqs = rte_zmalloc("ionic", sizeof(*lif->rxqcqs) *
706 adapter->max_nrxqs_per_lif, 0);
709 IONIC_PRINT(ERR, "Cannot allocate rx queues array");
713 IONIC_PRINT(DEBUG, "Allocating Notify Queue");
715 err = ionic_notify_qcq_alloc(lif);
717 IONIC_PRINT(ERR, "Cannot allocate notify queue");
721 IONIC_PRINT(DEBUG, "Allocating Admin Queue");
723 IONIC_PRINT(DEBUG, "Allocating Admin Queue");
725 err = ionic_admin_qcq_alloc(lif);
727 IONIC_PRINT(ERR, "Cannot allocate admin queue");
731 IONIC_PRINT(DEBUG, "Allocating Lif Info");
733 lif->info_sz = RTE_ALIGN(sizeof(*lif->info), PAGE_SIZE);
735 lif->info_z = rte_eth_dma_zone_reserve(lif->eth_dev,
736 "lif_info", 0 /* queue_idx*/,
737 lif->info_sz, IONIC_ALIGN, socket_id);
739 IONIC_PRINT(ERR, "Cannot allocate lif info memory");
743 lif->info = lif->info_z->addr;
744 lif->info_pa = lif->info_z->iova;
750 ionic_lif_free(struct ionic_lif *lif)
752 if (lif->notifyqcq) {
753 ionic_qcq_free(lif->notifyqcq);
754 lif->notifyqcq = NULL;
758 ionic_qcq_free(lif->adminqcq);
759 lif->adminqcq = NULL;
763 rte_free(lif->txqcqs);
768 rte_free(lif->rxqcqs);
773 rte_memzone_free(lif->info_z);
779 ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq)
781 struct ionic_dev *idev = &lif->adapter->idev;
783 if (!(qcq->flags & IONIC_QCQ_F_INITED))
786 if (qcq->flags & IONIC_QCQ_F_INTR)
787 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
788 IONIC_INTR_MASK_SET);
790 qcq->flags &= ~IONIC_QCQ_F_INITED;
794 ionic_lif_txq_deinit(struct ionic_qcq *qcq)
796 ionic_lif_qcq_deinit(qcq->lif, qcq);
800 ionic_lif_rxq_deinit(struct ionic_qcq *qcq)
802 ionic_lif_qcq_deinit(qcq->lif, qcq);
806 ionic_adminq_service(struct ionic_cq *cq, uint32_t cq_desc_index,
807 void *cb_arg __rte_unused)
809 struct ionic_admin_comp *cq_desc_base = cq->base;
810 struct ionic_admin_comp *cq_desc = &cq_desc_base[cq_desc_index];
812 if (!color_match(cq_desc->color, cq->done_color))
815 ionic_q_service(cq->bound_q, cq_desc_index, cq_desc->comp_index, NULL);
820 /* This acts like ionic_napi */
822 ionic_qcq_service(struct ionic_qcq *qcq, int budget, ionic_cq_cb cb,
825 struct ionic_cq *cq = &qcq->cq;
828 work_done = ionic_cq_service(cq, budget, cb, cb_arg);
834 ionic_link_status_check(struct ionic_lif *lif)
836 struct ionic_adapter *adapter = lif->adapter;
839 lif->state &= ~IONIC_LIF_F_LINK_CHECK_NEEDED;
844 link_up = (lif->info->status.link_status == IONIC_PORT_OPER_STATUS_UP);
846 if ((link_up && adapter->link_up) ||
847 (!link_up && !adapter->link_up))
851 IONIC_PRINT(DEBUG, "Link up - %d Gbps",
852 lif->info->status.link_speed);
853 adapter->link_speed = lif->info->status.link_speed;
855 IONIC_PRINT(DEBUG, "Link down");
858 adapter->link_up = link_up;
862 ionic_notifyq_cb(struct ionic_cq *cq, uint32_t cq_desc_index, void *cb_arg)
864 union ionic_notifyq_comp *cq_desc_base = cq->base;
865 union ionic_notifyq_comp *cq_desc = &cq_desc_base[cq_desc_index];
866 struct ionic_lif *lif = cb_arg;
868 IONIC_PRINT(DEBUG, "Notifyq callback eid = %jd ecode = %d",
869 cq_desc->event.eid, cq_desc->event.ecode);
871 /* Have we run out of new completions to process? */
872 if (!(cq_desc->event.eid > lif->last_eid))
875 lif->last_eid = cq_desc->event.eid;
877 switch (cq_desc->event.ecode) {
878 case IONIC_EVENT_LINK_CHANGE:
880 "Notifyq IONIC_EVENT_LINK_CHANGE eid=%jd link_status=%d link_speed=%d",
882 cq_desc->link_change.link_status,
883 cq_desc->link_change.link_speed);
885 lif->state |= IONIC_LIF_F_LINK_CHECK_NEEDED;
889 IONIC_PRINT(WARNING, "Notifyq bad event ecode=%d eid=%jd",
890 cq_desc->event.ecode, cq_desc->event.eid);
898 ionic_notifyq_handler(struct ionic_lif *lif, int budget)
900 struct ionic_dev *idev = &lif->adapter->idev;
901 struct ionic_qcq *qcq = lif->notifyqcq;
904 if (!(qcq->flags & IONIC_QCQ_F_INITED)) {
905 IONIC_PRINT(DEBUG, "Notifyq not yet initialized");
909 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
910 IONIC_INTR_MASK_SET);
912 work_done = ionic_qcq_service(qcq, budget, ionic_notifyq_cb, lif);
914 if (lif->state & IONIC_LIF_F_LINK_CHECK_NEEDED)
915 ionic_link_status_check(lif);
917 ionic_intr_credits(idev->intr_ctrl, qcq->intr.index,
918 work_done, IONIC_INTR_CRED_RESET_COALESCE);
920 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
921 IONIC_INTR_MASK_CLEAR);
927 ionic_lif_adminq_init(struct ionic_lif *lif)
929 struct ionic_dev *idev = &lif->adapter->idev;
930 struct ionic_qcq *qcq = lif->adminqcq;
931 struct ionic_queue *q = &qcq->q;
932 struct ionic_q_init_comp comp;
935 ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index);
936 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
940 ionic_dev_cmd_comp(idev, &comp);
942 q->hw_type = comp.hw_type;
943 q->hw_index = comp.hw_index;
944 q->db = ionic_db_map(lif, q);
946 IONIC_PRINT(DEBUG, "adminq->hw_type %d", q->hw_type);
947 IONIC_PRINT(DEBUG, "adminq->hw_index %d", q->hw_index);
948 IONIC_PRINT(DEBUG, "adminq->db %p", q->db);
950 if (qcq->flags & IONIC_QCQ_F_INTR)
951 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
952 IONIC_INTR_MASK_CLEAR);
954 qcq->flags |= IONIC_QCQ_F_INITED;
960 ionic_lif_notifyq_init(struct ionic_lif *lif)
962 struct ionic_dev *idev = &lif->adapter->idev;
963 struct ionic_qcq *qcq = lif->notifyqcq;
964 struct ionic_queue *q = &qcq->q;
967 struct ionic_admin_ctx ctx = {
968 .pending_work = true,
970 .opcode = IONIC_CMD_Q_INIT,
971 .lif_index = lif->index,
974 .flags = (IONIC_QINIT_F_IRQ | IONIC_QINIT_F_ENA),
975 .intr_index = qcq->intr.index,
977 .ring_size = rte_log2_u32(q->num_descs),
978 .ring_base = q->base_pa,
982 IONIC_PRINT(DEBUG, "notifyq_init.pid %d", ctx.cmd.q_init.pid);
983 IONIC_PRINT(DEBUG, "notifyq_init.index %d",
984 ctx.cmd.q_init.index);
985 IONIC_PRINT(DEBUG, "notifyq_init.ring_base 0x%" PRIx64 "",
986 ctx.cmd.q_init.ring_base);
987 IONIC_PRINT(DEBUG, "notifyq_init.ring_size %d",
988 ctx.cmd.q_init.ring_size);
990 err = ionic_adminq_post_wait(lif, &ctx);
994 q->hw_type = ctx.comp.q_init.hw_type;
995 q->hw_index = ctx.comp.q_init.hw_index;
998 IONIC_PRINT(DEBUG, "notifyq->hw_type %d", q->hw_type);
999 IONIC_PRINT(DEBUG, "notifyq->hw_index %d", q->hw_index);
1000 IONIC_PRINT(DEBUG, "notifyq->db %p", q->db);
1002 if (qcq->flags & IONIC_QCQ_F_INTR)
1003 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1004 IONIC_INTR_MASK_CLEAR);
1006 qcq->flags |= IONIC_QCQ_F_INITED;
1012 ionic_lif_set_features(struct ionic_lif *lif)
1014 struct ionic_admin_ctx ctx = {
1015 .pending_work = true,
1016 .cmd.lif_setattr = {
1017 .opcode = IONIC_CMD_LIF_SETATTR,
1018 .index = lif->index,
1019 .attr = IONIC_LIF_ATTR_FEATURES,
1020 .features = lif->features,
1025 err = ionic_adminq_post_wait(lif, &ctx);
1029 lif->hw_features = (ctx.cmd.lif_setattr.features &
1030 ctx.comp.lif_setattr.features);
1032 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
1033 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_TX_TAG");
1034 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
1035 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_STRIP");
1036 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
1037 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_FILTER");
1038 if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
1039 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_HASH");
1040 if (lif->hw_features & IONIC_ETH_HW_TX_SG)
1041 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_SG");
1042 if (lif->hw_features & IONIC_ETH_HW_RX_SG)
1043 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_SG");
1044 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
1045 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_CSUM");
1046 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
1047 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_CSUM");
1048 if (lif->hw_features & IONIC_ETH_HW_TSO)
1049 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO");
1050 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
1051 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPV6");
1052 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
1053 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_ECN");
1054 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
1055 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE");
1056 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
1057 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE_CSUM");
1058 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
1059 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP4");
1060 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
1061 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP6");
1062 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
1063 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP");
1064 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
1065 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP_CSUM");
1071 ionic_lif_txq_init(struct ionic_qcq *qcq)
1073 struct ionic_queue *q = &qcq->q;
1074 struct ionic_lif *lif = qcq->lif;
1075 struct ionic_cq *cq = &qcq->cq;
1076 struct ionic_admin_ctx ctx = {
1077 .pending_work = true,
1079 .opcode = IONIC_CMD_Q_INIT,
1080 .lif_index = lif->index,
1083 .flags = IONIC_QINIT_F_SG,
1084 .intr_index = cq->bound_intr->index,
1086 .ring_size = rte_log2_u32(q->num_descs),
1087 .ring_base = q->base_pa,
1088 .cq_ring_base = cq->base_pa,
1089 .sg_ring_base = q->sg_base_pa,
1094 IONIC_PRINT(DEBUG, "txq_init.pid %d", ctx.cmd.q_init.pid);
1095 IONIC_PRINT(DEBUG, "txq_init.index %d", ctx.cmd.q_init.index);
1096 IONIC_PRINT(DEBUG, "txq_init.ring_base 0x%" PRIx64 "",
1097 ctx.cmd.q_init.ring_base);
1098 IONIC_PRINT(DEBUG, "txq_init.ring_size %d",
1099 ctx.cmd.q_init.ring_size);
1101 err = ionic_adminq_post_wait(qcq->lif, &ctx);
1105 q->hw_type = ctx.comp.q_init.hw_type;
1106 q->hw_index = ctx.comp.q_init.hw_index;
1107 q->db = ionic_db_map(lif, q);
1109 IONIC_PRINT(DEBUG, "txq->hw_type %d", q->hw_type);
1110 IONIC_PRINT(DEBUG, "txq->hw_index %d", q->hw_index);
1111 IONIC_PRINT(DEBUG, "txq->db %p", q->db);
1113 qcq->flags |= IONIC_QCQ_F_INITED;
1119 ionic_lif_rxq_init(struct ionic_qcq *qcq)
1121 struct ionic_queue *q = &qcq->q;
1122 struct ionic_lif *lif = qcq->lif;
1123 struct ionic_cq *cq = &qcq->cq;
1124 struct ionic_admin_ctx ctx = {
1125 .pending_work = true,
1127 .opcode = IONIC_CMD_Q_INIT,
1128 .lif_index = lif->index,
1131 .flags = IONIC_QINIT_F_SG,
1132 .intr_index = cq->bound_intr->index,
1134 .ring_size = rte_log2_u32(q->num_descs),
1135 .ring_base = q->base_pa,
1136 .cq_ring_base = cq->base_pa,
1137 .sg_ring_base = q->sg_base_pa,
1142 IONIC_PRINT(DEBUG, "rxq_init.pid %d", ctx.cmd.q_init.pid);
1143 IONIC_PRINT(DEBUG, "rxq_init.index %d", ctx.cmd.q_init.index);
1144 IONIC_PRINT(DEBUG, "rxq_init.ring_base 0x%" PRIx64 "",
1145 ctx.cmd.q_init.ring_base);
1146 IONIC_PRINT(DEBUG, "rxq_init.ring_size %d",
1147 ctx.cmd.q_init.ring_size);
1149 err = ionic_adminq_post_wait(qcq->lif, &ctx);
1153 q->hw_type = ctx.comp.q_init.hw_type;
1154 q->hw_index = ctx.comp.q_init.hw_index;
1155 q->db = ionic_db_map(lif, q);
1157 qcq->flags |= IONIC_QCQ_F_INITED;
1159 IONIC_PRINT(DEBUG, "rxq->hw_type %d", q->hw_type);
1160 IONIC_PRINT(DEBUG, "rxq->hw_index %d", q->hw_index);
1161 IONIC_PRINT(DEBUG, "rxq->db %p", q->db);
1167 ionic_station_set(struct ionic_lif *lif)
1169 struct ionic_admin_ctx ctx = {
1170 .pending_work = true,
1171 .cmd.lif_getattr = {
1172 .opcode = IONIC_CMD_LIF_GETATTR,
1173 .index = lif->index,
1174 .attr = IONIC_LIF_ATTR_MAC,
1181 err = ionic_adminq_post_wait(lif, &ctx);
1185 if (!rte_is_zero_ether_addr((struct rte_ether_addr *)
1187 IONIC_PRINT(INFO, "deleting station MAC addr");
1189 ionic_lif_addr_del(lif, lif->mac_addr);
1192 memcpy(lif->mac_addr, ctx.comp.lif_getattr.mac, RTE_ETHER_ADDR_LEN);
1194 if (rte_is_zero_ether_addr((struct rte_ether_addr *)lif->mac_addr)) {
1195 IONIC_PRINT(NOTICE, "empty MAC addr (VF?)");
1199 IONIC_PRINT(DEBUG, "adding station MAC addr");
1201 ionic_lif_addr_add(lif, lif->mac_addr);
1207 ionic_lif_set_name(struct ionic_lif *lif)
1209 struct ionic_admin_ctx ctx = {
1210 .pending_work = true,
1211 .cmd.lif_setattr = {
1212 .opcode = IONIC_CMD_LIF_SETATTR,
1213 .index = lif->index,
1214 .attr = IONIC_LIF_ATTR_NAME,
1218 snprintf(ctx.cmd.lif_setattr.name, sizeof(ctx.cmd.lif_setattr.name),
1219 "%d", lif->port_id);
1221 ionic_adminq_post_wait(lif, &ctx);
1225 ionic_lif_init(struct ionic_lif *lif)
1227 struct ionic_dev *idev = &lif->adapter->idev;
1228 struct ionic_q_init_comp comp;
1231 ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa);
1232 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1233 ionic_dev_cmd_comp(idev, &comp);
1237 lif->hw_index = comp.hw_index;
1239 err = ionic_lif_adminq_init(lif);
1243 err = ionic_lif_notifyq_init(lif);
1245 goto err_out_adminq_deinit;
1248 IONIC_ETH_HW_VLAN_TX_TAG
1249 | IONIC_ETH_HW_VLAN_RX_STRIP
1250 | IONIC_ETH_HW_VLAN_RX_FILTER
1251 | IONIC_ETH_HW_RX_HASH
1252 | IONIC_ETH_HW_TX_SG
1253 | IONIC_ETH_HW_RX_SG
1254 | IONIC_ETH_HW_RX_CSUM
1256 | IONIC_ETH_HW_TSO_IPV6
1257 | IONIC_ETH_HW_TSO_ECN;
1259 err = ionic_lif_set_features(lif);
1261 goto err_out_notifyq_deinit;
1263 err = ionic_rx_filters_init(lif);
1265 goto err_out_notifyq_deinit;
1267 err = ionic_station_set(lif);
1269 goto err_out_rx_filter_deinit;
1271 ionic_lif_set_name(lif);
1273 lif->state |= IONIC_LIF_F_INITED;
1277 err_out_rx_filter_deinit:
1278 ionic_rx_filters_deinit(lif);
1280 err_out_notifyq_deinit:
1281 ionic_lif_qcq_deinit(lif, lif->notifyqcq);
1283 err_out_adminq_deinit:
1284 ionic_lif_qcq_deinit(lif, lif->adminqcq);
1290 ionic_lif_deinit(struct ionic_lif *lif)
1292 if (!(lif->state & IONIC_LIF_F_INITED))
1295 ionic_rx_filters_deinit(lif);
1296 ionic_lif_qcq_deinit(lif, lif->notifyqcq);
1297 ionic_lif_qcq_deinit(lif, lif->adminqcq);
1299 lif->state &= ~IONIC_LIF_F_INITED;
1303 ionic_lif_configure(struct ionic_lif *lif)
1305 lif->port_id = lif->eth_dev->data->port_id;
1314 ionic_lif_start(struct ionic_lif *lif)
1316 uint32_t rx_mode = 0;
1320 IONIC_PRINT(DEBUG, "Setting RX mode on port %u",
1323 rx_mode |= IONIC_RX_MODE_F_UNICAST;
1324 rx_mode |= IONIC_RX_MODE_F_MULTICAST;
1325 rx_mode |= IONIC_RX_MODE_F_BROADCAST;
1327 lif->rx_mode = 0; /* set by ionic_set_rx_mode */
1329 ionic_set_rx_mode(lif, rx_mode);
1331 IONIC_PRINT(DEBUG, "Starting %u RX queues and %u TX queues "
1333 lif->nrxqcqs, lif->ntxqcqs, lif->port_id);
1335 for (i = 0; i < lif->nrxqcqs; i++) {
1336 struct ionic_qcq *rxq = lif->rxqcqs[i];
1337 if (!rxq->deferred_start) {
1338 err = ionic_dev_rx_queue_start(lif->eth_dev, i);
1345 for (i = 0; i < lif->ntxqcqs; i++) {
1346 struct ionic_qcq *txq = lif->txqcqs[i];
1347 if (!txq->deferred_start) {
1348 err = ionic_dev_tx_queue_start(lif->eth_dev, i);
1355 ionic_link_status_check(lif);
1357 /* Carrier ON here */
1363 ionic_lif_identify(struct ionic_adapter *adapter)
1365 struct ionic_dev *idev = &adapter->idev;
1366 struct ionic_identity *ident = &adapter->ident;
1369 unsigned int lif_words = sizeof(ident->lif.words) /
1370 sizeof(ident->lif.words[0]);
1371 unsigned int cmd_words = sizeof(idev->dev_cmd->data) /
1372 sizeof(idev->dev_cmd->data[0]);
1373 unsigned int nwords;
1375 ionic_dev_cmd_lif_identify(idev, IONIC_LIF_TYPE_CLASSIC,
1376 IONIC_IDENTITY_VERSION_1);
1377 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1381 nwords = RTE_MIN(lif_words, cmd_words);
1382 for (i = 0; i < nwords; i++)
1383 ident->lif.words[i] = ioread32(&idev->dev_cmd->data[i]);
1385 IONIC_PRINT(INFO, "capabilities 0x%" PRIx64 " ",
1386 ident->lif.capabilities);
1388 IONIC_PRINT(INFO, "eth.max_ucast_filters 0x%" PRIx32 " ",
1389 ident->lif.eth.max_ucast_filters);
1390 IONIC_PRINT(INFO, "eth.max_mcast_filters 0x%" PRIx32 " ",
1391 ident->lif.eth.max_mcast_filters);
1393 IONIC_PRINT(INFO, "eth.features 0x%" PRIx64 " ",
1394 ident->lif.eth.config.features);
1395 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_ADMINQ] 0x%" PRIx32 " ",
1396 ident->lif.eth.config.queue_count[IONIC_QTYPE_ADMINQ]);
1397 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] 0x%" PRIx32 " ",
1398 ident->lif.eth.config.queue_count[IONIC_QTYPE_NOTIFYQ]);
1399 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_RXQ] 0x%" PRIx32 " ",
1400 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ]);
1401 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_TXQ] 0x%" PRIx32 " ",
1402 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ]);
1408 ionic_lifs_size(struct ionic_adapter *adapter)
1410 struct ionic_identity *ident = &adapter->ident;
1411 uint32_t nlifs = ident->dev.nlifs;
1412 uint32_t nintrs, dev_nintrs = ident->dev.nintrs;
1414 adapter->max_ntxqs_per_lif =
1415 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ];
1416 adapter->max_nrxqs_per_lif =
1417 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ];
1419 nintrs = nlifs * 1 /* notifyq */;
1421 if (nintrs > dev_nintrs) {
1422 IONIC_PRINT(ERR, "At most %d intr queues supported, minimum required is %u",
1423 dev_nintrs, nintrs);
1427 adapter->nintrs = nintrs;