drivers/net/ionic/ionic_lif.c

   1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
   2  * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
   3  */
   4
   5 #include <rte_malloc.h>
   6 #include <ethdev_driver.h>
   7
   8 #include "ionic.h"
   9 #include "ionic_logs.h"
  10 #include "ionic_lif.h"
  11 #include "ionic_ethdev.h"
  12 #include "ionic_rx_filter.h"
  13 #include "ionic_rxtx.h"
  14
  15 /* queuetype support level */
  16 static const uint8_t ionic_qtype_vers[IONIC_QTYPE_MAX] = {
  17         [IONIC_QTYPE_ADMINQ]  = 0,   /* 0 = Base version with CQ support */
  18         [IONIC_QTYPE_NOTIFYQ] = 0,   /* 0 = Base version */
  19         [IONIC_QTYPE_RXQ]     = 2,   /* 0 = Base version with CQ+SG support
  20                                       * 1 =       ... with EQ
  21                                       * 2 =       ... with CMB
  22                                       */
  23         [IONIC_QTYPE_TXQ]     = 3,   /* 0 = Base version with CQ+SG support
  24                                       * 1 =   ... with Tx SG version 1
  25                                       * 2 =       ... with EQ
  26                                       * 3 =       ... with CMB
  27                                       */
  28 };
  29
  30 static int ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr);
  31 static int ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr);
  32
  33 int
  34 ionic_qcq_enable(struct ionic_qcq *qcq)
  35 {
  36         struct ionic_queue *q = &qcq->q;
  37         struct ionic_lif *lif = q->lif;
  38         struct ionic_admin_ctx ctx = {
  39                 .pending_work = true,
  40                 .cmd.q_control = {
  41                         .opcode = IONIC_CMD_Q_CONTROL,
  42                         .type = q->type,
  43                         .index = rte_cpu_to_le_32(q->index),
  44                         .oper = IONIC_Q_ENABLE,
  45                 },
  46         };
  47
  48         return ionic_adminq_post_wait(lif, &ctx);
  49 }
  50
  51 int
  52 ionic_qcq_disable(struct ionic_qcq *qcq)
  53 {
  54         struct ionic_queue *q = &qcq->q;
  55         struct ionic_lif *lif = q->lif;
  56         struct ionic_admin_ctx ctx = {
  57                 .pending_work = true,
  58                 .cmd.q_control = {
  59                         .opcode = IONIC_CMD_Q_CONTROL,
  60                         .type = q->type,
  61                         .index = rte_cpu_to_le_32(q->index),
  62                         .oper = IONIC_Q_DISABLE,
  63                 },
  64         };
  65
  66         return ionic_adminq_post_wait(lif, &ctx);
  67 }
  68
  69 void
  70 ionic_lif_stop(struct ionic_lif *lif)
  71 {
  72         uint32_t i;
  73
  74         IONIC_PRINT_CALL();
  75
  76         lif->state &= ~IONIC_LIF_F_UP;
  77
  78         for (i = 0; i < lif->nrxqcqs; i++) {
  79                 struct ionic_qcq *rxq = lif->rxqcqs[i];
  80                 if (rxq->flags & IONIC_QCQ_F_INITED)
  81                         (void)ionic_dev_rx_queue_stop(lif->eth_dev, i);
  82         }
  83
  84         for (i = 0; i < lif->ntxqcqs; i++) {
  85                 struct ionic_qcq *txq = lif->txqcqs[i];
  86                 if (txq->flags & IONIC_QCQ_F_INITED)
  87                         (void)ionic_dev_tx_queue_stop(lif->eth_dev, i);
  88         }
  89 }
  90
  91 void
  92 ionic_lif_reset(struct ionic_lif *lif)
  93 {
  94         struct ionic_dev *idev = &lif->adapter->idev;
  95         int err;
  96
  97         IONIC_PRINT_CALL();
  98
  99         ionic_dev_cmd_lif_reset(idev);
 100         err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
 101         if (err)
 102                 IONIC_PRINT(WARNING, "Failed to reset %s", lif->name);
 103 }
 104
 105 static void
 106 ionic_lif_get_abs_stats(const struct ionic_lif *lif, struct rte_eth_stats *stats)
 107 {
 108         struct ionic_lif_stats *ls = &lif->info->stats;
 109         uint32_t i;
 110         uint32_t num_rx_q_counters = RTE_MIN(lif->nrxqcqs, (uint32_t)
 111                         RTE_ETHDEV_QUEUE_STAT_CNTRS);
 112         uint32_t num_tx_q_counters = RTE_MIN(lif->ntxqcqs, (uint32_t)
 113                         RTE_ETHDEV_QUEUE_STAT_CNTRS);
 114
 115         memset(stats, 0, sizeof(*stats));
 116
 117         if (ls == NULL) {
 118                 IONIC_PRINT(DEBUG, "Stats on port %u not yet initialized",
 119                         lif->port_id);
 120                 return;
 121         }
 122
 123         /* RX */
 124
 125         stats->ipackets = ls->rx_ucast_packets +
 126                 ls->rx_mcast_packets +
 127                 ls->rx_bcast_packets;
 128
 129         stats->ibytes = ls->rx_ucast_bytes +
 130                 ls->rx_mcast_bytes +
 131                 ls->rx_bcast_bytes;
 132
 133         for (i = 0; i < lif->nrxqcqs; i++) {
 134                 struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats.rx;
 135                 stats->imissed +=
 136                         rx_stats->no_cb_arg +
 137                         rx_stats->bad_cq_status +
 138                         rx_stats->no_room +
 139                         rx_stats->bad_len;
 140         }
 141
 142         stats->imissed +=
 143                 ls->rx_ucast_drop_packets +
 144                 ls->rx_mcast_drop_packets +
 145                 ls->rx_bcast_drop_packets;
 146
 147         stats->imissed +=
 148                 ls->rx_queue_empty +
 149                 ls->rx_dma_error +
 150                 ls->rx_queue_disabled +
 151                 ls->rx_desc_fetch_error +
 152                 ls->rx_desc_data_error;
 153
 154         for (i = 0; i < num_rx_q_counters; i++) {
 155                 struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats.rx;
 156                 stats->q_ipackets[i] = rx_stats->packets;
 157                 stats->q_ibytes[i] = rx_stats->bytes;
 158                 stats->q_errors[i] =
 159                         rx_stats->no_cb_arg +
 160                         rx_stats->bad_cq_status +
 161                         rx_stats->no_room +
 162                         rx_stats->bad_len;
 163         }
 164
 165         /* TX */
 166
 167         stats->opackets = ls->tx_ucast_packets +
 168                 ls->tx_mcast_packets +
 169                 ls->tx_bcast_packets;
 170
 171         stats->obytes = ls->tx_ucast_bytes +
 172                 ls->tx_mcast_bytes +
 173                 ls->tx_bcast_bytes;
 174
 175         for (i = 0; i < lif->ntxqcqs; i++) {
 176                 struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats.tx;
 177                 stats->oerrors += tx_stats->drop;
 178         }
 179
 180         stats->oerrors +=
 181                 ls->tx_ucast_drop_packets +
 182                 ls->tx_mcast_drop_packets +
 183                 ls->tx_bcast_drop_packets;
 184
 185         stats->oerrors +=
 186                 ls->tx_dma_error +
 187                 ls->tx_queue_disabled +
 188                 ls->tx_desc_fetch_error +
 189                 ls->tx_desc_data_error;
 190
 191         for (i = 0; i < num_tx_q_counters; i++) {
 192                 struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats.tx;
 193                 stats->q_opackets[i] = tx_stats->packets;
 194                 stats->q_obytes[i] = tx_stats->bytes;
 195         }
 196 }
 197
 198 void
 199 ionic_lif_get_stats(const struct ionic_lif *lif,
 200                 struct rte_eth_stats *stats)
 201 {
 202         ionic_lif_get_abs_stats(lif, stats);
 203
 204         stats->ipackets  -= lif->stats_base.ipackets;
 205         stats->opackets  -= lif->stats_base.opackets;
 206         stats->ibytes    -= lif->stats_base.ibytes;
 207         stats->obytes    -= lif->stats_base.obytes;
 208         stats->imissed   -= lif->stats_base.imissed;
 209         stats->ierrors   -= lif->stats_base.ierrors;
 210         stats->oerrors   -= lif->stats_base.oerrors;
 211         stats->rx_nombuf -= lif->stats_base.rx_nombuf;
 212 }
 213
 214 void
 215 ionic_lif_reset_stats(struct ionic_lif *lif)
 216 {
 217         uint32_t i;
 218
 219         for (i = 0; i < lif->nrxqcqs; i++) {
 220                 memset(&lif->rxqcqs[i]->stats.rx, 0,
 221                         sizeof(struct ionic_rx_stats));
 222                 memset(&lif->txqcqs[i]->stats.tx, 0,
 223                         sizeof(struct ionic_tx_stats));
 224         }
 225
 226         ionic_lif_get_abs_stats(lif, &lif->stats_base);
 227 }
 228
 229 void
 230 ionic_lif_get_hw_stats(struct ionic_lif *lif, struct ionic_lif_stats *stats)
 231 {
 232         uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t);
 233         uint64_t *stats64 = (uint64_t *)stats;
 234         uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats;
 235         uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base;
 236
 237         for (i = 0; i < count; i++)
 238                 stats64[i] = lif_stats64[i] - lif_stats64_base[i];
 239 }
 240
 241 void
 242 ionic_lif_reset_hw_stats(struct ionic_lif *lif)
 243 {
 244         uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t);
 245         uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats;
 246         uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base;
 247
 248         for (i = 0; i < count; i++)
 249                 lif_stats64_base[i] = lif_stats64[i];
 250 }
 251
 252 static int
 253 ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr)
 254 {
 255         struct ionic_admin_ctx ctx = {
 256                 .pending_work = true,
 257                 .cmd.rx_filter_add = {
 258                         .opcode = IONIC_CMD_RX_FILTER_ADD,
 259                         .match = rte_cpu_to_le_16(IONIC_RX_FILTER_MATCH_MAC),
 260                 },
 261         };
 262         int err;
 263
 264         memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, RTE_ETHER_ADDR_LEN);
 265
 266         err = ionic_adminq_post_wait(lif, &ctx);
 267         if (err)
 268                 return err;
 269
 270         IONIC_PRINT(INFO, "rx_filter add (id %d)",
 271                 rte_le_to_cpu_32(ctx.comp.rx_filter_add.filter_id));
 272
 273         return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);
 274 }
 275
 276 static int
 277 ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr)
 278 {
 279         struct ionic_admin_ctx ctx = {
 280                 .pending_work = true,
 281                 .cmd.rx_filter_del = {
 282                         .opcode = IONIC_CMD_RX_FILTER_DEL,
 283                 },
 284         };
 285         struct ionic_rx_filter *f;
 286         int err;
 287
 288         IONIC_PRINT_CALL();
 289
 290         rte_spinlock_lock(&lif->rx_filters.lock);
 291
 292         f = ionic_rx_filter_by_addr(lif, addr);
 293         if (!f) {
 294                 rte_spinlock_unlock(&lif->rx_filters.lock);
 295                 return -ENOENT;
 296         }
 297
 298         ctx.cmd.rx_filter_del.filter_id = rte_cpu_to_le_32(f->filter_id);
 299         ionic_rx_filter_free(f);
 300
 301         rte_spinlock_unlock(&lif->rx_filters.lock);
 302
 303         err = ionic_adminq_post_wait(lif, &ctx);
 304         if (err)
 305                 return err;
 306
 307         IONIC_PRINT(INFO, "rx_filter del (id %d)",
 308                 rte_le_to_cpu_32(ctx.cmd.rx_filter_del.filter_id));
 309
 310         return 0;
 311 }
 312
 313 int
 314 ionic_dev_add_mac(struct rte_eth_dev *eth_dev,
 315                 struct rte_ether_addr *mac_addr,
 316                 uint32_t index __rte_unused, uint32_t pool __rte_unused)
 317 {
 318         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 319
 320         IONIC_PRINT_CALL();
 321
 322         return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr);
 323 }
 324
 325 void
 326 ionic_dev_remove_mac(struct rte_eth_dev *eth_dev, uint32_t index)
 327 {
 328         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 329         struct ionic_adapter *adapter = lif->adapter;
 330         struct rte_ether_addr *mac_addr;
 331
 332         IONIC_PRINT_CALL();
 333
 334         if (index >= adapter->max_mac_addrs) {
 335                 IONIC_PRINT(WARNING,
 336                         "Index %u is above MAC filter limit %u",
 337                         index, adapter->max_mac_addrs);
 338                 return;
 339         }
 340
 341         mac_addr = &eth_dev->data->mac_addrs[index];
 342
 343         if (!rte_is_valid_assigned_ether_addr(mac_addr))
 344                 return;
 345
 346         ionic_lif_addr_del(lif, (const uint8_t *)mac_addr);
 347 }
 348
 349 int
 350 ionic_dev_set_mac(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr)
 351 {
 352         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 353
 354         IONIC_PRINT_CALL();
 355
 356         if (mac_addr == NULL) {
 357                 IONIC_PRINT(NOTICE, "New mac is null");
 358                 return -1;
 359         }
 360
 361         if (!rte_is_zero_ether_addr((struct rte_ether_addr *)lif->mac_addr)) {
 362                 IONIC_PRINT(INFO, "Deleting mac addr %pM",
 363                         lif->mac_addr);
 364                 ionic_lif_addr_del(lif, lif->mac_addr);
 365                 memset(lif->mac_addr, 0, RTE_ETHER_ADDR_LEN);
 366         }
 367
 368         IONIC_PRINT(INFO, "Updating mac addr");
 369
 370         rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)lif->mac_addr);
 371
 372         return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr);
 373 }
 374
 375 static int
 376 ionic_vlan_rx_add_vid(struct ionic_lif *lif, uint16_t vid)
 377 {
 378         struct ionic_admin_ctx ctx = {
 379                 .pending_work = true,
 380                 .cmd.rx_filter_add = {
 381                         .opcode = IONIC_CMD_RX_FILTER_ADD,
 382                         .match = rte_cpu_to_le_16(IONIC_RX_FILTER_MATCH_VLAN),
 383                         .vlan.vlan = rte_cpu_to_le_16(vid),
 384                 },
 385         };
 386         int err;
 387
 388         err = ionic_adminq_post_wait(lif, &ctx);
 389         if (err)
 390                 return err;
 391
 392         IONIC_PRINT(INFO, "rx_filter add VLAN %d (id %d)", vid,
 393                 rte_le_to_cpu_32(ctx.comp.rx_filter_add.filter_id));
 394
 395         return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);
 396 }
 397
 398 static int
 399 ionic_vlan_rx_kill_vid(struct ionic_lif *lif, uint16_t vid)
 400 {
 401         struct ionic_admin_ctx ctx = {
 402                 .pending_work = true,
 403                 .cmd.rx_filter_del = {
 404                         .opcode = IONIC_CMD_RX_FILTER_DEL,
 405                 },
 406         };
 407         struct ionic_rx_filter *f;
 408         int err;
 409
 410         IONIC_PRINT_CALL();
 411
 412         rte_spinlock_lock(&lif->rx_filters.lock);
 413
 414         f = ionic_rx_filter_by_vlan(lif, vid);
 415         if (!f) {
 416                 rte_spinlock_unlock(&lif->rx_filters.lock);
 417                 return -ENOENT;
 418         }
 419
 420         ctx.cmd.rx_filter_del.filter_id = rte_cpu_to_le_32(f->filter_id);
 421         ionic_rx_filter_free(f);
 422         rte_spinlock_unlock(&lif->rx_filters.lock);
 423
 424         err = ionic_adminq_post_wait(lif, &ctx);
 425         if (err)
 426                 return err;
 427
 428         IONIC_PRINT(INFO, "rx_filter del VLAN %d (id %d)", vid,
 429                 rte_le_to_cpu_32(ctx.cmd.rx_filter_del.filter_id));
 430
 431         return 0;
 432 }
 433
 434 int
 435 ionic_dev_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id,
 436                 int on)
 437 {
 438         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 439         int err;
 440
 441         if (on)
 442                 err = ionic_vlan_rx_add_vid(lif, vlan_id);
 443         else
 444                 err = ionic_vlan_rx_kill_vid(lif, vlan_id);
 445
 446         return err;
 447 }
 448
 449 static void
 450 ionic_lif_rx_mode(struct ionic_lif *lif, uint32_t rx_mode)
 451 {
 452         struct ionic_admin_ctx ctx = {
 453                 .pending_work = true,
 454                 .cmd.rx_mode_set = {
 455                         .opcode = IONIC_CMD_RX_MODE_SET,
 456                         .rx_mode = rte_cpu_to_le_16(rx_mode),
 457                 },
 458         };
 459         int err;
 460
 461         if (rx_mode & IONIC_RX_MODE_F_UNICAST)
 462                 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_UNICAST");
 463         if (rx_mode & IONIC_RX_MODE_F_MULTICAST)
 464                 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_MULTICAST");
 465         if (rx_mode & IONIC_RX_MODE_F_BROADCAST)
 466                 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_BROADCAST");
 467         if (rx_mode & IONIC_RX_MODE_F_PROMISC)
 468                 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_PROMISC");
 469         if (rx_mode & IONIC_RX_MODE_F_ALLMULTI)
 470                 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_ALLMULTI");
 471
 472         err = ionic_adminq_post_wait(lif, &ctx);
 473         if (err)
 474                 IONIC_PRINT(ERR, "Failure setting RX mode");
 475 }
 476
 477 static void
 478 ionic_set_rx_mode(struct ionic_lif *lif, uint32_t rx_mode)
 479 {
 480         if (lif->rx_mode != rx_mode) {
 481                 lif->rx_mode = rx_mode;
 482                 ionic_lif_rx_mode(lif, rx_mode);
 483         }
 484 }
 485
 486 int
 487 ionic_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
 488 {
 489         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 490         uint32_t rx_mode = lif->rx_mode;
 491
 492         IONIC_PRINT_CALL();
 493
 494         rx_mode |= IONIC_RX_MODE_F_PROMISC;
 495
 496         ionic_set_rx_mode(lif, rx_mode);
 497
 498         return 0;
 499 }
 500
 501 int
 502 ionic_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
 503 {
 504         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 505         uint32_t rx_mode = lif->rx_mode;
 506
 507         rx_mode &= ~IONIC_RX_MODE_F_PROMISC;
 508
 509         ionic_set_rx_mode(lif, rx_mode);
 510
 511         return 0;
 512 }
 513
 514 int
 515 ionic_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
 516 {
 517         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 518         uint32_t rx_mode = lif->rx_mode;
 519
 520         rx_mode |= IONIC_RX_MODE_F_ALLMULTI;
 521
 522         ionic_set_rx_mode(lif, rx_mode);
 523
 524         return 0;
 525 }
 526
 527 int
 528 ionic_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
 529 {
 530         struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
 531         uint32_t rx_mode = lif->rx_mode;
 532
 533         rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI;
 534
 535         ionic_set_rx_mode(lif, rx_mode);
 536
 537         return 0;
 538 }
 539
 540 int
 541 ionic_lif_change_mtu(struct ionic_lif *lif, int new_mtu)
 542 {
 543         struct ionic_admin_ctx ctx = {
 544                 .pending_work = true,
 545                 .cmd.lif_setattr = {
 546                         .opcode = IONIC_CMD_LIF_SETATTR,
 547                         .attr = IONIC_LIF_ATTR_MTU,
 548                         .mtu = rte_cpu_to_le_32(new_mtu),
 549                 },
 550         };
 551         int err;
 552
 553         err = ionic_adminq_post_wait(lif, &ctx);
 554         if (err)
 555                 return err;
 556
 557         return 0;
 558 }
 559
 560 int
 561 ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr)
 562 {
 563         struct ionic_adapter *adapter = lif->adapter;
 564         struct ionic_dev *idev = &adapter->idev;
 565         unsigned long index;
 566
 567         /*
 568          * Note: interrupt handler is called for index = 0 only
 569          * (we use interrupts for the notifyq only anyway,
 570          * which has index = 0)
 571          */
 572
 573         for (index = 0; index < adapter->nintrs; index++)
 574                 if (!adapter->intrs[index])
 575                         break;
 576
 577         if (index == adapter->nintrs)
 578                 return -ENOSPC;
 579
 580         adapter->intrs[index] = true;
 581
 582         ionic_intr_init(idev, intr, index);
 583
 584         return 0;
 585 }
 586
 587 static int
 588 ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type,
 589                 uint32_t index,
 590                 const char *base, uint32_t flags,
 591                 uint32_t num_descs,
 592                 uint32_t desc_size,
 593                 uint32_t cq_desc_size,
 594                 uint32_t sg_desc_size,
 595                 struct ionic_qcq **qcq)
 596 {
 597         struct ionic_dev *idev = &lif->adapter->idev;
 598         struct ionic_qcq *new;
 599         uint32_t q_size, cq_size, sg_size, total_size;
 600         void *q_base, *cq_base, *sg_base;
 601         rte_iova_t q_base_pa = 0;
 602         rte_iova_t cq_base_pa = 0;
 603         rte_iova_t sg_base_pa = 0;
 604         uint32_t socket_id = rte_socket_id();
 605         int err;
 606
 607         *qcq = NULL;
 608
 609         q_size  = num_descs * desc_size;
 610         cq_size = num_descs * cq_desc_size;
 611         sg_size = num_descs * sg_desc_size;
 612
 613         total_size = RTE_ALIGN(q_size, PAGE_SIZE) +
 614                 RTE_ALIGN(cq_size, PAGE_SIZE);
 615         /*
 616          * Note: aligning q_size/cq_size is not enough due to cq_base address
 617          * aligning as q_base could be not aligned to the page.
 618          * Adding PAGE_SIZE.
 619          */
 620         total_size += PAGE_SIZE;
 621
 622         if (flags & IONIC_QCQ_F_SG) {
 623                 total_size += RTE_ALIGN(sg_size, PAGE_SIZE);
 624                 total_size += PAGE_SIZE;
 625         }
 626
 627         new = rte_zmalloc("ionic", sizeof(*new), 0);
 628         if (!new) {
 629                 IONIC_PRINT(ERR, "Cannot allocate queue structure");
 630                 return -ENOMEM;
 631         }
 632
 633         new->lif = lif;
 634         new->flags = flags;
 635
 636         new->q.info = rte_zmalloc("ionic", sizeof(*new->q.info) * num_descs, 0);
 637         if (!new->q.info) {
 638                 IONIC_PRINT(ERR, "Cannot allocate queue info");
 639                 err = -ENOMEM;
 640                 goto err_out_free_qcq;
 641         }
 642
 643         new->q.type = type;
 644
 645         err = ionic_q_init(lif, idev, &new->q, index, num_descs,
 646                 desc_size, sg_desc_size);
 647         if (err) {
 648                 IONIC_PRINT(ERR, "Queue initialization failed");
 649                 goto err_out_free_info;
 650         }
 651
 652         err = ionic_cq_init(&new->cq, num_descs);
 653         if (err) {
 654                 IONIC_PRINT(ERR, "Completion queue initialization failed");
 655                 goto err_out_free_info;
 656         }
 657
 658         new->base_z = rte_eth_dma_zone_reserve(lif->eth_dev,
 659                 base /* name */, index /* queue_idx */,
 660                 total_size, IONIC_ALIGN, socket_id);
 661
 662         if (!new->base_z) {
 663                 IONIC_PRINT(ERR, "Cannot reserve queue DMA memory");
 664                 err = -ENOMEM;
 665                 goto err_out_free_info;
 666         }
 667
 668         new->base = new->base_z->addr;
 669         new->base_pa = new->base_z->iova;
 670         new->total_size = total_size;
 671
 672         q_base = new->base;
 673         q_base_pa = new->base_pa;
 674
 675         cq_base = (void *)RTE_ALIGN((uintptr_t)q_base + q_size, PAGE_SIZE);
 676         cq_base_pa = RTE_ALIGN(q_base_pa + q_size, PAGE_SIZE);
 677
 678         if (flags & IONIC_QCQ_F_SG) {
 679                 sg_base = (void *)RTE_ALIGN((uintptr_t)cq_base + cq_size,
 680                         PAGE_SIZE);
 681                 sg_base_pa = RTE_ALIGN(cq_base_pa + cq_size, PAGE_SIZE);
 682                 ionic_q_sg_map(&new->q, sg_base, sg_base_pa);
 683         }
 684
 685         IONIC_PRINT(DEBUG, "Q-Base-PA = %#jx CQ-Base-PA = %#jx "
 686                 "SG-base-PA = %#jx",
 687                 q_base_pa, cq_base_pa, sg_base_pa);
 688
 689         ionic_q_map(&new->q, q_base, q_base_pa);
 690         ionic_cq_map(&new->cq, cq_base, cq_base_pa);
 691
 692         *qcq = new;
 693
 694         return 0;
 695
 696 err_out_free_info:
 697         rte_free(new->q.info);
 698 err_out_free_qcq:
 699         rte_free(new);
 700
 701         return err;
 702 }
 703
 704 void
 705 ionic_qcq_free(struct ionic_qcq *qcq)
 706 {
 707         if (qcq->base_z) {
 708                 qcq->base = NULL;
 709                 qcq->base_pa = 0;
 710                 rte_memzone_free(qcq->base_z);
 711                 qcq->base_z = NULL;
 712         }
 713
 714         if (qcq->q.info) {
 715                 rte_free(qcq->q.info);
 716                 qcq->q.info = NULL;
 717         }
 718
 719         rte_free(qcq);
 720 }
 721
 722 int
 723 ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t nrxq_descs,
 724                 struct ionic_qcq **qcq)
 725 {
 726         uint32_t flags;
 727         int err = -ENOMEM;
 728
 729         flags = IONIC_QCQ_F_SG;
 730         err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, index, "rx", flags,
 731                 nrxq_descs,
 732                 sizeof(struct ionic_rxq_desc),
 733                 sizeof(struct ionic_rxq_comp),
 734                 sizeof(struct ionic_rxq_sg_desc),
 735                 &lif->rxqcqs[index]);
 736         if (err)
 737                 return err;
 738
 739         *qcq = lif->rxqcqs[index];
 740
 741         return 0;
 742 }
 743
 744 int
 745 ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t ntxq_descs,
 746                 struct ionic_qcq **qcq)
 747 {
 748         uint32_t flags;
 749         int err = -ENOMEM;
 750
 751         flags = IONIC_QCQ_F_SG;
 752         err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, index, "tx", flags,
 753                 ntxq_descs,
 754                 sizeof(struct ionic_txq_desc),
 755                 sizeof(struct ionic_txq_comp),
 756                 sizeof(struct ionic_txq_sg_desc_v1),
 757                 &lif->txqcqs[index]);
 758         if (err)
 759                 return err;
 760
 761         *qcq = lif->txqcqs[index];
 762
 763         return 0;
 764 }
 765
 766 static int
 767 ionic_admin_qcq_alloc(struct ionic_lif *lif)
 768 {
 769         uint32_t flags;
 770         int err = -ENOMEM;
 771
 772         flags = 0;
 773         err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags,
 774                 IONIC_ADMINQ_LENGTH,
 775                 sizeof(struct ionic_admin_cmd),
 776                 sizeof(struct ionic_admin_comp),
 777                 0,
 778                 &lif->adminqcq);
 779         if (err)
 780                 return err;
 781
 782         return 0;
 783 }
 784
 785 static int
 786 ionic_notify_qcq_alloc(struct ionic_lif *lif)
 787 {
 788         struct ionic_qcq *nqcq;
 789         struct ionic_dev *idev = &lif->adapter->idev;
 790         uint32_t flags = 0;
 791         int err = -ENOMEM;
 792
 793         err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notify",
 794                 flags,
 795                 IONIC_NOTIFYQ_LENGTH,
 796                 sizeof(struct ionic_notifyq_cmd),
 797                 sizeof(union ionic_notifyq_comp),
 798                 0,
 799                 &nqcq);
 800         if (err)
 801                 return err;
 802
 803         err = ionic_intr_alloc(lif, &nqcq->intr);
 804         if (err) {
 805                 ionic_qcq_free(nqcq);
 806                 return err;
 807         }
 808
 809         ionic_intr_mask_assert(idev->intr_ctrl, nqcq->intr.index,
 810                 IONIC_INTR_MASK_SET);
 811
 812         lif->notifyqcq = nqcq;
 813
 814         return 0;
 815 }
 816
 817 static void *
 818 ionic_bus_map_dbpage(struct ionic_adapter *adapter, int page_num)
 819 {
 820         char *vaddr = adapter->bars[IONIC_PCI_BAR_DBELL].vaddr;
 821
 822         if (adapter->num_bars <= IONIC_PCI_BAR_DBELL)
 823                 return NULL;
 824
 825         return (void *)&vaddr[page_num << PAGE_SHIFT];
 826 }
 827
 828 static void
 829 ionic_lif_queue_identify(struct ionic_lif *lif)
 830 {
 831         struct ionic_adapter *adapter = lif->adapter;
 832         struct ionic_dev *idev = &adapter->idev;
 833         union ionic_q_identity *q_ident = &adapter->ident.txq;
 834         uint32_t q_words = RTE_DIM(q_ident->words);
 835         uint32_t cmd_words = RTE_DIM(idev->dev_cmd->data);
 836         uint32_t i, nwords, qtype;
 837         int err;
 838
 839         for (qtype = 0; qtype < RTE_DIM(ionic_qtype_vers); qtype++) {
 840                 struct ionic_qtype_info *qti = &lif->qtype_info[qtype];
 841
 842                 /* Filter out the types this driver knows about */
 843                 switch (qtype) {
 844                 case IONIC_QTYPE_ADMINQ:
 845                 case IONIC_QTYPE_NOTIFYQ:
 846                 case IONIC_QTYPE_RXQ:
 847                 case IONIC_QTYPE_TXQ:
 848                         break;
 849                 default:
 850                         continue;
 851                 }
 852
 853                 memset(qti, 0, sizeof(*qti));
 854
 855                 ionic_dev_cmd_queue_identify(idev, IONIC_LIF_TYPE_CLASSIC,
 856                         qtype, ionic_qtype_vers[qtype]);
 857                 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
 858                 if (err == -EINVAL) {
 859                         IONIC_PRINT(ERR, "qtype %d not supported\n", qtype);
 860                         continue;
 861                 } else if (err == -EIO) {
 862                         IONIC_PRINT(ERR, "q_ident failed, older FW\n");
 863                         return;
 864                 } else if (err) {
 865                         IONIC_PRINT(ERR, "q_ident failed, qtype %d: %d\n",
 866                                 qtype, err);
 867                         return;
 868                 }
 869
 870                 nwords = RTE_MIN(q_words, cmd_words);
 871                 for (i = 0; i < nwords; i++)
 872                         q_ident->words[i] = ioread32(&idev->dev_cmd->data[i]);
 873
 874                 qti->version   = q_ident->version;
 875                 qti->supported = q_ident->supported;
 876                 qti->features  = rte_le_to_cpu_64(q_ident->features);
 877                 qti->desc_sz   = rte_le_to_cpu_16(q_ident->desc_sz);
 878                 qti->comp_sz   = rte_le_to_cpu_16(q_ident->comp_sz);
 879                 qti->sg_desc_sz   = rte_le_to_cpu_16(q_ident->sg_desc_sz);
 880                 qti->max_sg_elems = rte_le_to_cpu_16(q_ident->max_sg_elems);
 881                 qti->sg_desc_stride =
 882                         rte_le_to_cpu_16(q_ident->sg_desc_stride);
 883
 884                 IONIC_PRINT(DEBUG, " qtype[%d].version = %d",
 885                         qtype, qti->version);
 886                 IONIC_PRINT(DEBUG, " qtype[%d].supported = %#x",
 887                         qtype, qti->supported);
 888                 IONIC_PRINT(DEBUG, " qtype[%d].features = %#jx",
 889                         qtype, qti->features);
 890                 IONIC_PRINT(DEBUG, " qtype[%d].desc_sz = %d",
 891                         qtype, qti->desc_sz);
 892                 IONIC_PRINT(DEBUG, " qtype[%d].comp_sz = %d",
 893                         qtype, qti->comp_sz);
 894                 IONIC_PRINT(DEBUG, " qtype[%d].sg_desc_sz = %d",
 895                         qtype, qti->sg_desc_sz);
 896                 IONIC_PRINT(DEBUG, " qtype[%d].max_sg_elems = %d",
 897                         qtype, qti->max_sg_elems);
 898                 IONIC_PRINT(DEBUG, " qtype[%d].sg_desc_stride = %d",
 899                         qtype, qti->sg_desc_stride);
 900         }
 901 }
 902
 903 int
 904 ionic_lif_alloc(struct ionic_lif *lif)
 905 {
 906         struct ionic_adapter *adapter = lif->adapter;
 907         uint32_t socket_id = rte_socket_id();
 908         int err;
 909
 910         /*
 911          * lif->name was zeroed on allocation.
 912          * Copy (sizeof() - 1) bytes to ensure that it is NULL terminated.
 913          */
 914         memcpy(lif->name, lif->eth_dev->data->name, sizeof(lif->name) - 1);
 915
 916         IONIC_PRINT(DEBUG, "LIF: %s", lif->name);
 917
 918         ionic_lif_queue_identify(lif);
 919
 920         if (lif->qtype_info[IONIC_QTYPE_TXQ].version < 1) {
 921                 IONIC_PRINT(ERR, "FW too old, please upgrade");
 922                 return -ENXIO;
 923         }
 924
 925         IONIC_PRINT(DEBUG, "Allocating Lif Info");
 926
 927         rte_spinlock_init(&lif->adminq_lock);
 928         rte_spinlock_init(&lif->adminq_service_lock);
 929
 930         lif->kern_dbpage = ionic_bus_map_dbpage(adapter, 0);
 931         if (!lif->kern_dbpage) {
 932                 IONIC_PRINT(ERR, "Cannot map dbpage, aborting");
 933                 return -ENOMEM;
 934         }
 935
 936         lif->txqcqs = rte_zmalloc("ionic", sizeof(*lif->txqcqs) *
 937                 adapter->max_ntxqs_per_lif, 0);
 938
 939         if (!lif->txqcqs) {
 940                 IONIC_PRINT(ERR, "Cannot allocate tx queues array");
 941                 return -ENOMEM;
 942         }
 943
 944         lif->rxqcqs = rte_zmalloc("ionic", sizeof(*lif->rxqcqs) *
 945                 adapter->max_nrxqs_per_lif, 0);
 946
 947         if (!lif->rxqcqs) {
 948                 IONIC_PRINT(ERR, "Cannot allocate rx queues array");
 949                 return -ENOMEM;
 950         }
 951
 952         IONIC_PRINT(DEBUG, "Allocating Notify Queue");
 953
 954         err = ionic_notify_qcq_alloc(lif);
 955         if (err) {
 956                 IONIC_PRINT(ERR, "Cannot allocate notify queue");
 957                 return err;
 958         }
 959
 960         IONIC_PRINT(DEBUG, "Allocating Admin Queue");
 961
 962         err = ionic_admin_qcq_alloc(lif);
 963         if (err) {
 964                 IONIC_PRINT(ERR, "Cannot allocate admin queue");
 965                 return err;
 966         }
 967
 968         IONIC_PRINT(DEBUG, "Allocating Lif Info");
 969
 970         lif->info_sz = RTE_ALIGN(sizeof(*lif->info), PAGE_SIZE);
 971
 972         lif->info_z = rte_eth_dma_zone_reserve(lif->eth_dev,
 973                 "lif_info", 0 /* queue_idx*/,
 974                 lif->info_sz, IONIC_ALIGN, socket_id);
 975         if (!lif->info_z) {
 976                 IONIC_PRINT(ERR, "Cannot allocate lif info memory");
 977                 return -ENOMEM;
 978         }
 979
 980         lif->info = lif->info_z->addr;
 981         lif->info_pa = lif->info_z->iova;
 982
 983         return 0;
 984 }
 985
 986 void
 987 ionic_lif_free(struct ionic_lif *lif)
 988 {
 989         if (lif->notifyqcq) {
 990                 ionic_qcq_free(lif->notifyqcq);
 991                 lif->notifyqcq = NULL;
 992         }
 993
 994         if (lif->adminqcq) {
 995                 ionic_qcq_free(lif->adminqcq);
 996                 lif->adminqcq = NULL;
 997         }
 998
 999         if (lif->txqcqs) {
1000                 rte_free(lif->txqcqs);
1001                 lif->txqcqs = NULL;
1002         }
1003
1004         if (lif->rxqcqs) {
1005                 rte_free(lif->rxqcqs);
1006                 lif->rxqcqs = NULL;
1007         }
1008
1009         if (lif->info) {
1010                 rte_memzone_free(lif->info_z);
1011                 lif->info = NULL;
1012         }
1013 }
1014
1015 void
1016 ionic_lif_free_queues(struct ionic_lif *lif)
1017 {
1018         uint32_t i;
1019
1020         for (i = 0; i < lif->ntxqcqs; i++) {
1021                 ionic_dev_tx_queue_release(lif->eth_dev->data->tx_queues[i]);
1022                 lif->eth_dev->data->tx_queues[i] = NULL;
1023         }
1024         for (i = 0; i < lif->nrxqcqs; i++) {
1025                 ionic_dev_rx_queue_release(lif->eth_dev->data->rx_queues[i]);
1026                 lif->eth_dev->data->rx_queues[i] = NULL;
1027         }
1028 }
1029
1030 int
1031 ionic_lif_rss_config(struct ionic_lif *lif,
1032                 const uint16_t types, const uint8_t *key, const uint32_t *indir)
1033 {
1034         struct ionic_adapter *adapter = lif->adapter;
1035         struct ionic_admin_ctx ctx = {
1036                 .pending_work = true,
1037                 .cmd.lif_setattr = {
1038                         .opcode = IONIC_CMD_LIF_SETATTR,
1039                         .attr = IONIC_LIF_ATTR_RSS,
1040                         .rss.types = rte_cpu_to_le_16(types),
1041                         .rss.addr = rte_cpu_to_le_64(lif->rss_ind_tbl_pa),
1042                 },
1043         };
1044         unsigned int i;
1045         uint16_t tbl_sz =
1046                 rte_le_to_cpu_16(adapter->ident.lif.eth.rss_ind_tbl_sz);
1047
1048         IONIC_PRINT_CALL();
1049
1050         lif->rss_types = types;
1051
1052         if (key)
1053                 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE);
1054
1055         if (indir)
1056                 for (i = 0; i < tbl_sz; i++)
1057                         lif->rss_ind_tbl[i] = indir[i];
1058
1059         memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key,
1060                IONIC_RSS_HASH_KEY_SIZE);
1061
1062         return ionic_adminq_post_wait(lif, &ctx);
1063 }
1064
1065 static int
1066 ionic_lif_rss_setup(struct ionic_lif *lif)
1067 {
1068         struct ionic_adapter *adapter = lif->adapter;
1069         static const uint8_t toeplitz_symmetric_key[] = {
1070                 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
1071                 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
1072                 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
1073                 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
1074                 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
1075         };
1076         uint32_t i;
1077         uint16_t tbl_sz =
1078                 rte_le_to_cpu_16(adapter->ident.lif.eth.rss_ind_tbl_sz);
1079
1080         IONIC_PRINT_CALL();
1081
1082         if (!lif->rss_ind_tbl_z) {
1083                 lif->rss_ind_tbl_z = rte_eth_dma_zone_reserve(lif->eth_dev,
1084                                         "rss_ind_tbl", 0 /* queue_idx */,
1085                                         sizeof(*lif->rss_ind_tbl) * tbl_sz,
1086                                         IONIC_ALIGN, rte_socket_id());
1087                 if (!lif->rss_ind_tbl_z) {
1088                         IONIC_PRINT(ERR, "OOM");
1089                         return -ENOMEM;
1090                 }
1091
1092                 lif->rss_ind_tbl = lif->rss_ind_tbl_z->addr;
1093                 lif->rss_ind_tbl_pa = lif->rss_ind_tbl_z->iova;
1094         }
1095
1096         if (lif->rss_ind_tbl_nrxqcqs != lif->nrxqcqs) {
1097                 lif->rss_ind_tbl_nrxqcqs = lif->nrxqcqs;
1098
1099                 /* Fill indirection table with 'default' values */
1100                 for (i = 0; i < tbl_sz; i++)
1101                         lif->rss_ind_tbl[i] = i % lif->nrxqcqs;
1102         }
1103
1104         return ionic_lif_rss_config(lif, IONIC_RSS_OFFLOAD_ALL,
1105                         toeplitz_symmetric_key, NULL);
1106 }
1107
1108 static void
1109 ionic_lif_rss_teardown(struct ionic_lif *lif)
1110 {
1111         if (!lif->rss_ind_tbl)
1112                 return;
1113
1114         if (lif->rss_ind_tbl_z) {
1115                 /* Disable RSS on the NIC */
1116                 ionic_lif_rss_config(lif, 0x0, NULL, NULL);
1117
1118                 lif->rss_ind_tbl = NULL;
1119                 lif->rss_ind_tbl_pa = 0;
1120                 rte_memzone_free(lif->rss_ind_tbl_z);
1121                 lif->rss_ind_tbl_z = NULL;
1122         }
1123 }
1124
1125 static void
1126 ionic_lif_qcq_deinit(struct ionic_qcq *qcq)
1127 {
1128         qcq->flags &= ~IONIC_QCQ_F_INITED;
1129 }
1130
1131 void
1132 ionic_lif_txq_deinit(struct ionic_qcq *qcq)
1133 {
1134         ionic_lif_qcq_deinit(qcq);
1135 }
1136
1137 void
1138 ionic_lif_rxq_deinit(struct ionic_qcq *qcq)
1139 {
1140         ionic_lif_qcq_deinit(qcq);
1141 }
1142
1143 static void
1144 ionic_lif_notifyq_deinit(struct ionic_lif *lif)
1145 {
1146         struct ionic_qcq *nqcq = lif->notifyqcq;
1147         struct ionic_dev *idev = &lif->adapter->idev;
1148
1149         if (!(nqcq->flags & IONIC_QCQ_F_INITED))
1150                 return;
1151
1152         ionic_intr_mask(idev->intr_ctrl, nqcq->intr.index,
1153                 IONIC_INTR_MASK_SET);
1154
1155         nqcq->flags &= ~IONIC_QCQ_F_INITED;
1156 }
1157
1158 /* This acts like ionic_napi */
1159 int
1160 ionic_qcq_service(struct ionic_qcq *qcq, int budget, ionic_cq_cb cb,
1161                 void *cb_arg)
1162 {
1163         struct ionic_cq *cq = &qcq->cq;
1164         uint32_t work_done;
1165
1166         work_done = ionic_cq_service(cq, budget, cb, cb_arg);
1167
1168         return work_done;
1169 }
1170
1171 static void
1172 ionic_link_status_check(struct ionic_lif *lif)
1173 {
1174         struct ionic_adapter *adapter = lif->adapter;
1175         bool link_up;
1176
1177         lif->state &= ~IONIC_LIF_F_LINK_CHECK_NEEDED;
1178
1179         if (!lif->info)
1180                 return;
1181
1182         link_up = (lif->info->status.link_status == IONIC_PORT_OPER_STATUS_UP);
1183
1184         if ((link_up  && adapter->link_up) ||
1185             (!link_up && !adapter->link_up))
1186                 return;
1187
1188         if (link_up) {
1189                 adapter->link_speed =
1190                         rte_le_to_cpu_32(lif->info->status.link_speed);
1191                 IONIC_PRINT(DEBUG, "Link up - %d Gbps",
1192                         adapter->link_speed);
1193         } else {
1194                 IONIC_PRINT(DEBUG, "Link down");
1195         }
1196
1197         adapter->link_up = link_up;
1198         ionic_dev_link_update(lif->eth_dev, 0);
1199 }
1200
1201 static void
1202 ionic_lif_handle_fw_down(struct ionic_lif *lif)
1203 {
1204         if (lif->state & IONIC_LIF_F_FW_RESET)
1205                 return;
1206
1207         lif->state |= IONIC_LIF_F_FW_RESET;
1208
1209         if (lif->state & IONIC_LIF_F_UP) {
1210                 IONIC_PRINT(NOTICE,
1211                         "Surprise FW stop, stopping %s\n", lif->name);
1212                 ionic_lif_stop(lif);
1213         }
1214
1215         IONIC_PRINT(NOTICE, "FW down, %s stopped", lif->name);
1216 }
1217
1218 static bool
1219 ionic_notifyq_cb(struct ionic_cq *cq, uint32_t cq_desc_index, void *cb_arg)
1220 {
1221         union ionic_notifyq_comp *cq_desc_base = cq->base;
1222         union ionic_notifyq_comp *cq_desc = &cq_desc_base[cq_desc_index];
1223         struct ionic_lif *lif = cb_arg;
1224
1225         IONIC_PRINT(DEBUG, "Notifyq callback eid = %jd ecode = %d",
1226                 cq_desc->event.eid, cq_desc->event.ecode);
1227
1228         /* Have we run out of new completions to process? */
1229         if (!(cq_desc->event.eid > lif->last_eid))
1230                 return false;
1231
1232         lif->last_eid = cq_desc->event.eid;
1233
1234         switch (cq_desc->event.ecode) {
1235         case IONIC_EVENT_LINK_CHANGE:
1236                 IONIC_PRINT(DEBUG,
1237                         "Notifyq IONIC_EVENT_LINK_CHANGE %s "
1238                         "eid=%jd link_status=%d link_speed=%d",
1239                         lif->name,
1240                         cq_desc->event.eid,
1241                         cq_desc->link_change.link_status,
1242                         cq_desc->link_change.link_speed);
1243
1244                 lif->state |= IONIC_LIF_F_LINK_CHECK_NEEDED;
1245                 break;
1246
1247         case IONIC_EVENT_RESET:
1248                 IONIC_PRINT(NOTICE,
1249                         "Notifyq IONIC_EVENT_RESET %s "
1250                         "eid=%jd, reset_code=%d state=%d",
1251                         lif->name,
1252                         cq_desc->event.eid,
1253                         cq_desc->reset.reset_code,
1254                         cq_desc->reset.state);
1255                 ionic_lif_handle_fw_down(lif);
1256                 break;
1257
1258         default:
1259                 IONIC_PRINT(WARNING, "Notifyq bad event ecode=%d eid=%jd",
1260                         cq_desc->event.ecode, cq_desc->event.eid);
1261                 break;
1262         }
1263
1264         return true;
1265 }
1266
1267 int
1268 ionic_notifyq_handler(struct ionic_lif *lif, int budget)
1269 {
1270         struct ionic_dev *idev = &lif->adapter->idev;
1271         struct ionic_qcq *qcq = lif->notifyqcq;
1272         uint32_t work_done;
1273
1274         if (!(qcq->flags & IONIC_QCQ_F_INITED)) {
1275                 IONIC_PRINT(DEBUG, "Notifyq not yet initialized");
1276                 return -1;
1277         }
1278
1279         ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1280                 IONIC_INTR_MASK_SET);
1281
1282         work_done = ionic_qcq_service(qcq, budget, ionic_notifyq_cb, lif);
1283
1284         if (lif->state & IONIC_LIF_F_LINK_CHECK_NEEDED)
1285                 ionic_link_status_check(lif);
1286
1287         ionic_intr_credits(idev->intr_ctrl, qcq->intr.index,
1288                 work_done, IONIC_INTR_CRED_RESET_COALESCE);
1289
1290         ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1291                 IONIC_INTR_MASK_CLEAR);
1292
1293         return 0;
1294 }
1295
1296 static int
1297 ionic_lif_adminq_init(struct ionic_lif *lif)
1298 {
1299         struct ionic_dev *idev = &lif->adapter->idev;
1300         struct ionic_qcq *qcq = lif->adminqcq;
1301         struct ionic_queue *q = &qcq->q;
1302         struct ionic_q_init_comp comp;
1303         int err;
1304
1305         ionic_dev_cmd_adminq_init(idev, qcq);
1306         err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1307         if (err)
1308                 return err;
1309
1310         ionic_dev_cmd_comp(idev, &comp);
1311
1312         q->hw_type = comp.hw_type;
1313         q->hw_index = rte_le_to_cpu_32(comp.hw_index);
1314         q->db = ionic_db_map(lif, q);
1315
1316         IONIC_PRINT(DEBUG, "adminq->hw_type %d", q->hw_type);
1317         IONIC_PRINT(DEBUG, "adminq->hw_index %d", q->hw_index);
1318         IONIC_PRINT(DEBUG, "adminq->db %p", q->db);
1319
1320         qcq->flags |= IONIC_QCQ_F_INITED;
1321
1322         return 0;
1323 }
1324
1325 static int
1326 ionic_lif_notifyq_init(struct ionic_lif *lif)
1327 {
1328         struct ionic_dev *idev = &lif->adapter->idev;
1329         struct ionic_qcq *qcq = lif->notifyqcq;
1330         struct ionic_queue *q = &qcq->q;
1331         int err;
1332
1333         struct ionic_admin_ctx ctx = {
1334                 .pending_work = true,
1335                 .cmd.q_init = {
1336                         .opcode = IONIC_CMD_Q_INIT,
1337                         .type = q->type,
1338                         .ver = lif->qtype_info[q->type].version,
1339                         .index = rte_cpu_to_le_32(q->index),
1340                         .intr_index = rte_cpu_to_le_16(qcq->intr.index),
1341                         .flags = rte_cpu_to_le_16(IONIC_QINIT_F_IRQ |
1342                                                 IONIC_QINIT_F_ENA),
1343                         .ring_size = rte_log2_u32(q->num_descs),
1344                         .ring_base = rte_cpu_to_le_64(q->base_pa),
1345                 }
1346         };
1347
1348         IONIC_PRINT(DEBUG, "notifyq_init.index %d", q->index);
1349         IONIC_PRINT(DEBUG, "notifyq_init.ring_base 0x%" PRIx64 "", q->base_pa);
1350         IONIC_PRINT(DEBUG, "notifyq_init.ring_size %d",
1351                 ctx.cmd.q_init.ring_size);
1352         IONIC_PRINT(DEBUG, "notifyq_init.ver %u", ctx.cmd.q_init.ver);
1353
1354         err = ionic_adminq_post_wait(lif, &ctx);
1355         if (err)
1356                 return err;
1357
1358         q->hw_type = ctx.comp.q_init.hw_type;
1359         q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index);
1360         q->db = NULL;
1361
1362         IONIC_PRINT(DEBUG, "notifyq->hw_type %d", q->hw_type);
1363         IONIC_PRINT(DEBUG, "notifyq->hw_index %d", q->hw_index);
1364         IONIC_PRINT(DEBUG, "notifyq->db %p", q->db);
1365
1366         ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
1367                 IONIC_INTR_MASK_CLEAR);
1368
1369         qcq->flags |= IONIC_QCQ_F_INITED;
1370
1371         return 0;
1372 }
1373
1374 int
1375 ionic_lif_set_features(struct ionic_lif *lif)
1376 {
1377         struct ionic_admin_ctx ctx = {
1378                 .pending_work = true,
1379                 .cmd.lif_setattr = {
1380                         .opcode = IONIC_CMD_LIF_SETATTR,
1381                         .attr = IONIC_LIF_ATTR_FEATURES,
1382                         .features = rte_cpu_to_le_64(lif->features),
1383                 },
1384         };
1385         int err;
1386
1387         err = ionic_adminq_post_wait(lif, &ctx);
1388         if (err)
1389                 return err;
1390
1391         lif->hw_features = rte_le_to_cpu_64(ctx.cmd.lif_setattr.features &
1392                                                 ctx.comp.lif_setattr.features);
1393
1394         if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
1395                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_TX_TAG");
1396         if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
1397                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_STRIP");
1398         if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
1399                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_FILTER");
1400         if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
1401                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_HASH");
1402         if (lif->hw_features & IONIC_ETH_HW_TX_SG)
1403                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_SG");
1404         if (lif->hw_features & IONIC_ETH_HW_RX_SG)
1405                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_SG");
1406         if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
1407                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_CSUM");
1408         if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
1409                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_CSUM");
1410         if (lif->hw_features & IONIC_ETH_HW_TSO)
1411                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO");
1412         if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
1413                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPV6");
1414         if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
1415                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_ECN");
1416         if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
1417                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE");
1418         if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
1419                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE_CSUM");
1420         if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
1421                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP4");
1422         if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
1423                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP6");
1424         if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
1425                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP");
1426         if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
1427                 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP_CSUM");
1428
1429         return 0;
1430 }
1431
1432 int
1433 ionic_lif_txq_init(struct ionic_qcq *qcq)
1434 {
1435         struct ionic_queue *q = &qcq->q;
1436         struct ionic_lif *lif = qcq->lif;
1437         struct ionic_cq *cq = &qcq->cq;
1438         struct ionic_admin_ctx ctx = {
1439                 .pending_work = true,
1440                 .cmd.q_init = {
1441                         .opcode = IONIC_CMD_Q_INIT,
1442                         .type = q->type,
1443                         .ver = lif->qtype_info[q->type].version,
1444                         .index = rte_cpu_to_le_32(q->index),
1445                         .flags = rte_cpu_to_le_16(IONIC_QINIT_F_SG |
1446                                                 IONIC_QINIT_F_ENA),
1447                         .intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE),
1448                         .ring_size = rte_log2_u32(q->num_descs),
1449                         .ring_base = rte_cpu_to_le_64(q->base_pa),
1450                         .cq_ring_base = rte_cpu_to_le_64(cq->base_pa),
1451                         .sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa),
1452                 },
1453         };
1454         int err;
1455
1456         IONIC_PRINT(DEBUG, "txq_init.index %d", q->index);
1457         IONIC_PRINT(DEBUG, "txq_init.ring_base 0x%" PRIx64 "", q->base_pa);
1458         IONIC_PRINT(DEBUG, "txq_init.ring_size %d",
1459                 ctx.cmd.q_init.ring_size);
1460         IONIC_PRINT(DEBUG, "txq_init.ver %u", ctx.cmd.q_init.ver);
1461
1462         err = ionic_adminq_post_wait(qcq->lif, &ctx);
1463         if (err)
1464                 return err;
1465
1466         q->hw_type = ctx.comp.q_init.hw_type;
1467         q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index);
1468         q->db = ionic_db_map(lif, q);
1469
1470         IONIC_PRINT(DEBUG, "txq->hw_type %d", q->hw_type);
1471         IONIC_PRINT(DEBUG, "txq->hw_index %d", q->hw_index);
1472         IONIC_PRINT(DEBUG, "txq->db %p", q->db);
1473
1474         qcq->flags |= IONIC_QCQ_F_INITED;
1475
1476         return 0;
1477 }
1478
1479 int
1480 ionic_lif_rxq_init(struct ionic_qcq *qcq)
1481 {
1482         struct ionic_queue *q = &qcq->q;
1483         struct ionic_lif *lif = qcq->lif;
1484         struct ionic_cq *cq = &qcq->cq;
1485         struct ionic_admin_ctx ctx = {
1486                 .pending_work = true,
1487                 .cmd.q_init = {
1488                         .opcode = IONIC_CMD_Q_INIT,
1489                         .type = q->type,
1490                         .ver = lif->qtype_info[q->type].version,
1491                         .index = rte_cpu_to_le_32(q->index),
1492                         .flags = rte_cpu_to_le_16(IONIC_QINIT_F_SG |
1493                                                 IONIC_QINIT_F_ENA),
1494                         .intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE),
1495                         .ring_size = rte_log2_u32(q->num_descs),
1496                         .ring_base = rte_cpu_to_le_64(q->base_pa),
1497                         .cq_ring_base = rte_cpu_to_le_64(cq->base_pa),
1498                         .sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa),
1499                 },
1500         };
1501         int err;
1502
1503         IONIC_PRINT(DEBUG, "rxq_init.index %d", q->index);
1504         IONIC_PRINT(DEBUG, "rxq_init.ring_base 0x%" PRIx64 "", q->base_pa);
1505         IONIC_PRINT(DEBUG, "rxq_init.ring_size %d",
1506                 ctx.cmd.q_init.ring_size);
1507         IONIC_PRINT(DEBUG, "rxq_init.ver %u", ctx.cmd.q_init.ver);
1508
1509         err = ionic_adminq_post_wait(qcq->lif, &ctx);
1510         if (err)
1511                 return err;
1512
1513         q->hw_type = ctx.comp.q_init.hw_type;
1514         q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index);
1515         q->db = ionic_db_map(lif, q);
1516
1517         qcq->flags |= IONIC_QCQ_F_INITED;
1518
1519         IONIC_PRINT(DEBUG, "rxq->hw_type %d", q->hw_type);
1520         IONIC_PRINT(DEBUG, "rxq->hw_index %d", q->hw_index);
1521         IONIC_PRINT(DEBUG, "rxq->db %p", q->db);
1522
1523         return 0;
1524 }
1525
1526 static int
1527 ionic_station_set(struct ionic_lif *lif)
1528 {
1529         struct ionic_admin_ctx ctx = {
1530                 .pending_work = true,
1531                 .cmd.lif_getattr = {
1532                         .opcode = IONIC_CMD_LIF_GETATTR,
1533                         .attr = IONIC_LIF_ATTR_MAC,
1534                 },
1535         };
1536         int err;
1537
1538         IONIC_PRINT_CALL();
1539
1540         err = ionic_adminq_post_wait(lif, &ctx);
1541         if (err)
1542                 return err;
1543
1544         memcpy(lif->mac_addr, ctx.comp.lif_getattr.mac, RTE_ETHER_ADDR_LEN);
1545
1546         return 0;
1547 }
1548
1549 static void
1550 ionic_lif_set_name(struct ionic_lif *lif)
1551 {
1552         struct ionic_admin_ctx ctx = {
1553                 .pending_work = true,
1554                 .cmd.lif_setattr = {
1555                         .opcode = IONIC_CMD_LIF_SETATTR,
1556                         .attr = IONIC_LIF_ATTR_NAME,
1557                 },
1558         };
1559
1560         memcpy(ctx.cmd.lif_setattr.name, lif->name,
1561                 sizeof(ctx.cmd.lif_setattr.name) - 1);
1562
1563         ionic_adminq_post_wait(lif, &ctx);
1564 }
1565
1566 int
1567 ionic_lif_init(struct ionic_lif *lif)
1568 {
1569         struct ionic_dev *idev = &lif->adapter->idev;
1570         struct ionic_q_init_comp comp;
1571         int err;
1572
1573         memset(&lif->stats_base, 0, sizeof(lif->stats_base));
1574
1575         ionic_dev_cmd_lif_init(idev, lif->info_pa);
1576         err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1577         ionic_dev_cmd_comp(idev, &comp);
1578         if (err)
1579                 return err;
1580
1581         lif->hw_index = rte_cpu_to_le_16(comp.hw_index);
1582
1583         err = ionic_lif_adminq_init(lif);
1584         if (err)
1585                 return err;
1586
1587         err = ionic_lif_notifyq_init(lif);
1588         if (err)
1589                 goto err_out_adminq_deinit;
1590
1591         /*
1592          * Configure initial feature set
1593          * This will be updated later by the dev_configure() step
1594          */
1595         lif->features = IONIC_ETH_HW_RX_HASH | IONIC_ETH_HW_VLAN_RX_FILTER;
1596
1597         err = ionic_lif_set_features(lif);
1598         if (err)
1599                 goto err_out_notifyq_deinit;
1600
1601         err = ionic_rx_filters_init(lif);
1602         if (err)
1603                 goto err_out_notifyq_deinit;
1604
1605         err = ionic_station_set(lif);
1606         if (err)
1607                 goto err_out_rx_filter_deinit;
1608
1609         ionic_lif_set_name(lif);
1610
1611         lif->state |= IONIC_LIF_F_INITED;
1612
1613         return 0;
1614
1615 err_out_rx_filter_deinit:
1616         ionic_rx_filters_deinit(lif);
1617
1618 err_out_notifyq_deinit:
1619         ionic_lif_notifyq_deinit(lif);
1620
1621 err_out_adminq_deinit:
1622         ionic_lif_qcq_deinit(lif->adminqcq);
1623
1624         return err;
1625 }
1626
1627 void
1628 ionic_lif_deinit(struct ionic_lif *lif)
1629 {
1630         if (!(lif->state & IONIC_LIF_F_INITED))
1631                 return;
1632
1633         ionic_rx_filters_deinit(lif);
1634         ionic_lif_rss_teardown(lif);
1635         ionic_lif_notifyq_deinit(lif);
1636         ionic_lif_qcq_deinit(lif->adminqcq);
1637
1638         lif->state &= ~IONIC_LIF_F_INITED;
1639 }
1640
1641 void
1642 ionic_lif_configure_vlan_offload(struct ionic_lif *lif, int mask)
1643 {
1644         struct rte_eth_dev *eth_dev = lif->eth_dev;
1645         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1646
1647         /*
1648          * IONIC_ETH_HW_VLAN_RX_FILTER cannot be turned off, so
1649          * set DEV_RX_OFFLOAD_VLAN_FILTER and ignore ETH_VLAN_FILTER_MASK
1650          */
1651         rxmode->offloads |= DEV_RX_OFFLOAD_VLAN_FILTER;
1652
1653         if (mask & ETH_VLAN_STRIP_MASK) {
1654                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1655                         lif->features |= IONIC_ETH_HW_VLAN_RX_STRIP;
1656                 else
1657                         lif->features &= ~IONIC_ETH_HW_VLAN_RX_STRIP;
1658         }
1659 }
1660
1661 void
1662 ionic_lif_configure(struct ionic_lif *lif)
1663 {
1664         struct rte_eth_rxmode *rxmode = &lif->eth_dev->data->dev_conf.rxmode;
1665         struct rte_eth_txmode *txmode = &lif->eth_dev->data->dev_conf.txmode;
1666         struct ionic_identity *ident = &lif->adapter->ident;
1667         union ionic_lif_config *cfg = &ident->lif.eth.config;
1668         uint32_t ntxqs_per_lif =
1669                 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]);
1670         uint32_t nrxqs_per_lif =
1671                 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]);
1672         uint32_t nrxqs = lif->eth_dev->data->nb_rx_queues;
1673         uint32_t ntxqs = lif->eth_dev->data->nb_tx_queues;
1674
1675         lif->port_id = lif->eth_dev->data->port_id;
1676
1677         IONIC_PRINT(DEBUG, "Configuring LIF on port %u",
1678                 lif->port_id);
1679
1680         if (nrxqs > 0)
1681                 nrxqs_per_lif = RTE_MIN(nrxqs_per_lif, nrxqs);
1682
1683         if (ntxqs > 0)
1684                 ntxqs_per_lif = RTE_MIN(ntxqs_per_lif, ntxqs);
1685
1686         lif->nrxqcqs = nrxqs_per_lif;
1687         lif->ntxqcqs = ntxqs_per_lif;
1688
1689         /* Update the LIF configuration based on the eth_dev */
1690
1691         /*
1692          * NB: While it is true that RSS_HASH is always enabled on ionic,
1693          *     setting this flag unconditionally causes problems in DTS.
1694          * rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1695          */
1696
1697         /* RX per-port */
1698
1699         if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM ||
1700             rxmode->offloads & DEV_RX_OFFLOAD_UDP_CKSUM ||
1701             rxmode->offloads & DEV_RX_OFFLOAD_TCP_CKSUM)
1702                 lif->features |= IONIC_ETH_HW_RX_CSUM;
1703         else
1704                 lif->features &= ~IONIC_ETH_HW_RX_CSUM;
1705
1706         if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER) {
1707                 lif->features |= IONIC_ETH_HW_RX_SG;
1708                 lif->eth_dev->data->scattered_rx = 1;
1709         } else {
1710                 lif->features &= ~IONIC_ETH_HW_RX_SG;
1711                 lif->eth_dev->data->scattered_rx = 0;
1712         }
1713
1714         /* Covers VLAN_STRIP */
1715         ionic_lif_configure_vlan_offload(lif, ETH_VLAN_STRIP_MASK);
1716
1717         /* TX per-port */
1718
1719         if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
1720             txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
1721             txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM ||
1722             txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
1723             txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)
1724                 lif->features |= IONIC_ETH_HW_TX_CSUM;
1725         else
1726                 lif->features &= ~IONIC_ETH_HW_TX_CSUM;
1727
1728         if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
1729                 lif->features |= IONIC_ETH_HW_VLAN_TX_TAG;
1730         else
1731                 lif->features &= ~IONIC_ETH_HW_VLAN_TX_TAG;
1732
1733         if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
1734                 lif->features |= IONIC_ETH_HW_TX_SG;
1735         else
1736                 lif->features &= ~IONIC_ETH_HW_TX_SG;
1737
1738         if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
1739                 lif->features |= IONIC_ETH_HW_TSO;
1740                 lif->features |= IONIC_ETH_HW_TSO_IPV6;
1741                 lif->features |= IONIC_ETH_HW_TSO_ECN;
1742         } else {
1743                 lif->features &= ~IONIC_ETH_HW_TSO;
1744                 lif->features &= ~IONIC_ETH_HW_TSO_IPV6;
1745                 lif->features &= ~IONIC_ETH_HW_TSO_ECN;
1746         }
1747 }
1748
1749 int
1750 ionic_lif_start(struct ionic_lif *lif)
1751 {
1752         uint32_t rx_mode;
1753         uint32_t i;
1754         int err;
1755
1756         err = ionic_lif_rss_setup(lif);
1757         if (err)
1758                 return err;
1759
1760         if (!lif->rx_mode) {
1761                 IONIC_PRINT(DEBUG, "Setting RX mode on %s",
1762                         lif->name);
1763
1764                 rx_mode  = IONIC_RX_MODE_F_UNICAST;
1765                 rx_mode |= IONIC_RX_MODE_F_MULTICAST;
1766                 rx_mode |= IONIC_RX_MODE_F_BROADCAST;
1767
1768                 ionic_set_rx_mode(lif, rx_mode);
1769         }
1770
1771         IONIC_PRINT(DEBUG, "Starting %u RX queues and %u TX queues "
1772                 "on port %u",
1773                 lif->nrxqcqs, lif->ntxqcqs, lif->port_id);
1774
1775         for (i = 0; i < lif->nrxqcqs; i++) {
1776                 struct ionic_qcq *rxq = lif->rxqcqs[i];
1777                 if (!(rxq->flags & IONIC_QCQ_F_DEFERRED)) {
1778                         err = ionic_dev_rx_queue_start(lif->eth_dev, i);
1779
1780                         if (err)
1781                                 return err;
1782                 }
1783         }
1784
1785         for (i = 0; i < lif->ntxqcqs; i++) {
1786                 struct ionic_qcq *txq = lif->txqcqs[i];
1787                 if (!(txq->flags & IONIC_QCQ_F_DEFERRED)) {
1788                         err = ionic_dev_tx_queue_start(lif->eth_dev, i);
1789
1790                         if (err)
1791                                 return err;
1792                 }
1793         }
1794
1795         /* Carrier ON here */
1796         lif->state |= IONIC_LIF_F_UP;
1797
1798         ionic_link_status_check(lif);
1799
1800         return 0;
1801 }
1802
1803 int
1804 ionic_lif_identify(struct ionic_adapter *adapter)
1805 {
1806         struct ionic_dev *idev = &adapter->idev;
1807         struct ionic_identity *ident = &adapter->ident;
1808         union ionic_lif_config *cfg = &ident->lif.eth.config;
1809         uint32_t lif_words = RTE_DIM(ident->lif.words);
1810         uint32_t cmd_words = RTE_DIM(idev->dev_cmd->data);
1811         uint32_t i, nwords;
1812         int err;
1813
1814         ionic_dev_cmd_lif_identify(idev, IONIC_LIF_TYPE_CLASSIC,
1815                 IONIC_IDENTITY_VERSION_1);
1816         err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1817         if (err)
1818                 return (err);
1819
1820         nwords = RTE_MIN(lif_words, cmd_words);
1821         for (i = 0; i < nwords; i++)
1822                 ident->lif.words[i] = ioread32(&idev->dev_cmd->data[i]);
1823
1824         IONIC_PRINT(INFO, "capabilities 0x%" PRIx64 " ",
1825                 rte_le_to_cpu_64(ident->lif.capabilities));
1826
1827         IONIC_PRINT(INFO, "eth.max_ucast_filters 0x%" PRIx32 " ",
1828                 rte_le_to_cpu_32(ident->lif.eth.max_ucast_filters));
1829         IONIC_PRINT(INFO, "eth.max_mcast_filters 0x%" PRIx32 " ",
1830                 rte_le_to_cpu_32(ident->lif.eth.max_mcast_filters));
1831
1832         IONIC_PRINT(INFO, "eth.features 0x%" PRIx64 " ",
1833                 rte_le_to_cpu_64(cfg->features));
1834         IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_ADMINQ] 0x%" PRIx32 " ",
1835                 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_ADMINQ]));
1836         IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] 0x%" PRIx32 " ",
1837                 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_NOTIFYQ]));
1838         IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_RXQ] 0x%" PRIx32 " ",
1839                 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]));
1840         IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_TXQ] 0x%" PRIx32 " ",
1841                 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]));
1842
1843         return 0;
1844 }
1845
1846 int
1847 ionic_lifs_size(struct ionic_adapter *adapter)
1848 {
1849         struct ionic_identity *ident = &adapter->ident;
1850         union ionic_lif_config *cfg = &ident->lif.eth.config;
1851         uint32_t nintrs, dev_nintrs = rte_le_to_cpu_32(ident->dev.nintrs);
1852
1853         adapter->max_ntxqs_per_lif =
1854                 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]);
1855         adapter->max_nrxqs_per_lif =
1856                 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]);
1857
1858         nintrs = 1 /* notifyq */;
1859
1860         if (nintrs > dev_nintrs) {
1861                 IONIC_PRINT(ERR,
1862                         "At most %d intr supported, minimum req'd is %u",
1863                         dev_nintrs, nintrs);
1864                 return -ENOSPC;
1865         }
1866
1867         adapter->nintrs = nintrs;
1868
1869         return 0;
1870 }