1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
5 #include <rte_malloc.h>
6 #include <ethdev_driver.h>
9 #include "ionic_logs.h"
10 #include "ionic_lif.h"
11 #include "ionic_ethdev.h"
12 #include "ionic_rx_filter.h"
13 #include "ionic_rxtx.h"
15 /* queuetype support level */
16 static const uint8_t ionic_qtype_vers[IONIC_QTYPE_MAX] = {
17 [IONIC_QTYPE_ADMINQ] = 0, /* 0 = Base version with CQ support */
18 [IONIC_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */
19 [IONIC_QTYPE_RXQ] = 2, /* 0 = Base version with CQ+SG support
23 [IONIC_QTYPE_TXQ] = 3, /* 0 = Base version with CQ+SG support
24 * 1 = ... with Tx SG version 1
30 static int ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr);
31 static int ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr);
34 ionic_qcq_enable(struct ionic_qcq *qcq)
36 struct ionic_queue *q = &qcq->q;
37 struct ionic_lif *lif = qcq->lif;
38 struct ionic_admin_ctx ctx = {
41 .opcode = IONIC_CMD_Q_CONTROL,
43 .index = rte_cpu_to_le_32(q->index),
44 .oper = IONIC_Q_ENABLE,
48 return ionic_adminq_post_wait(lif, &ctx);
52 ionic_qcq_disable(struct ionic_qcq *qcq)
54 struct ionic_queue *q = &qcq->q;
55 struct ionic_lif *lif = qcq->lif;
56 struct ionic_admin_ctx ctx = {
59 .opcode = IONIC_CMD_Q_CONTROL,
61 .index = rte_cpu_to_le_32(q->index),
62 .oper = IONIC_Q_DISABLE,
66 return ionic_adminq_post_wait(lif, &ctx);
70 ionic_lif_stop(struct ionic_lif *lif)
76 lif->state &= ~IONIC_LIF_F_UP;
78 for (i = 0; i < lif->nrxqcqs; i++) {
79 struct ionic_rx_qcq *rxq = lif->rxqcqs[i];
80 if (rxq->flags & IONIC_QCQ_F_INITED)
81 (void)ionic_dev_rx_queue_stop(lif->eth_dev, i);
84 for (i = 0; i < lif->ntxqcqs; i++) {
85 struct ionic_tx_qcq *txq = lif->txqcqs[i];
86 if (txq->flags & IONIC_QCQ_F_INITED)
87 (void)ionic_dev_tx_queue_stop(lif->eth_dev, i);
92 ionic_lif_reset(struct ionic_lif *lif)
94 struct ionic_dev *idev = &lif->adapter->idev;
99 ionic_dev_cmd_lif_reset(idev);
100 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
102 IONIC_PRINT(WARNING, "Failed to reset %s", lif->name);
106 ionic_lif_get_abs_stats(const struct ionic_lif *lif, struct rte_eth_stats *stats)
108 struct ionic_lif_stats *ls = &lif->info->stats;
110 uint32_t num_rx_q_counters = RTE_MIN(lif->nrxqcqs, (uint32_t)
111 RTE_ETHDEV_QUEUE_STAT_CNTRS);
112 uint32_t num_tx_q_counters = RTE_MIN(lif->ntxqcqs, (uint32_t)
113 RTE_ETHDEV_QUEUE_STAT_CNTRS);
115 memset(stats, 0, sizeof(*stats));
118 IONIC_PRINT(DEBUG, "Stats on port %u not yet initialized",
125 stats->ipackets = ls->rx_ucast_packets +
126 ls->rx_mcast_packets +
127 ls->rx_bcast_packets;
129 stats->ibytes = ls->rx_ucast_bytes +
133 for (i = 0; i < lif->nrxqcqs; i++) {
134 struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats;
136 rx_stats->no_cb_arg +
137 rx_stats->bad_cq_status +
143 ls->rx_ucast_drop_packets +
144 ls->rx_mcast_drop_packets +
145 ls->rx_bcast_drop_packets;
150 ls->rx_queue_disabled +
151 ls->rx_desc_fetch_error +
152 ls->rx_desc_data_error;
154 for (i = 0; i < num_rx_q_counters; i++) {
155 struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats;
156 stats->q_ipackets[i] = rx_stats->packets;
157 stats->q_ibytes[i] = rx_stats->bytes;
159 rx_stats->no_cb_arg +
160 rx_stats->bad_cq_status +
167 stats->opackets = ls->tx_ucast_packets +
168 ls->tx_mcast_packets +
169 ls->tx_bcast_packets;
171 stats->obytes = ls->tx_ucast_bytes +
175 for (i = 0; i < lif->ntxqcqs; i++) {
176 struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats;
177 stats->oerrors += tx_stats->drop;
181 ls->tx_ucast_drop_packets +
182 ls->tx_mcast_drop_packets +
183 ls->tx_bcast_drop_packets;
187 ls->tx_queue_disabled +
188 ls->tx_desc_fetch_error +
189 ls->tx_desc_data_error;
191 for (i = 0; i < num_tx_q_counters; i++) {
192 struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats;
193 stats->q_opackets[i] = tx_stats->packets;
194 stats->q_obytes[i] = tx_stats->bytes;
199 ionic_lif_get_stats(const struct ionic_lif *lif,
200 struct rte_eth_stats *stats)
202 ionic_lif_get_abs_stats(lif, stats);
204 stats->ipackets -= lif->stats_base.ipackets;
205 stats->opackets -= lif->stats_base.opackets;
206 stats->ibytes -= lif->stats_base.ibytes;
207 stats->obytes -= lif->stats_base.obytes;
208 stats->imissed -= lif->stats_base.imissed;
209 stats->ierrors -= lif->stats_base.ierrors;
210 stats->oerrors -= lif->stats_base.oerrors;
211 stats->rx_nombuf -= lif->stats_base.rx_nombuf;
215 ionic_lif_reset_stats(struct ionic_lif *lif)
219 for (i = 0; i < lif->nrxqcqs; i++) {
220 memset(&lif->rxqcqs[i]->stats, 0,
221 sizeof(struct ionic_rx_stats));
222 memset(&lif->txqcqs[i]->stats, 0,
223 sizeof(struct ionic_tx_stats));
226 ionic_lif_get_abs_stats(lif, &lif->stats_base);
230 ionic_lif_get_hw_stats(struct ionic_lif *lif, struct ionic_lif_stats *stats)
232 uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t);
233 uint64_t *stats64 = (uint64_t *)stats;
234 uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats;
235 uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base;
237 for (i = 0; i < count; i++)
238 stats64[i] = lif_stats64[i] - lif_stats64_base[i];
242 ionic_lif_reset_hw_stats(struct ionic_lif *lif)
244 uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t);
245 uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats;
246 uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base;
248 for (i = 0; i < count; i++)
249 lif_stats64_base[i] = lif_stats64[i];
253 ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr)
255 struct ionic_admin_ctx ctx = {
256 .pending_work = true,
257 .cmd.rx_filter_add = {
258 .opcode = IONIC_CMD_RX_FILTER_ADD,
259 .match = rte_cpu_to_le_16(IONIC_RX_FILTER_MATCH_MAC),
264 memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, RTE_ETHER_ADDR_LEN);
266 err = ionic_adminq_post_wait(lif, &ctx);
270 IONIC_PRINT(INFO, "rx_filter add (id %d)",
271 rte_le_to_cpu_32(ctx.comp.rx_filter_add.filter_id));
273 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);
277 ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr)
279 struct ionic_admin_ctx ctx = {
280 .pending_work = true,
281 .cmd.rx_filter_del = {
282 .opcode = IONIC_CMD_RX_FILTER_DEL,
285 struct ionic_rx_filter *f;
290 rte_spinlock_lock(&lif->rx_filters.lock);
292 f = ionic_rx_filter_by_addr(lif, addr);
294 rte_spinlock_unlock(&lif->rx_filters.lock);
298 ctx.cmd.rx_filter_del.filter_id = rte_cpu_to_le_32(f->filter_id);
299 ionic_rx_filter_free(f);
301 rte_spinlock_unlock(&lif->rx_filters.lock);
303 err = ionic_adminq_post_wait(lif, &ctx);
307 IONIC_PRINT(INFO, "rx_filter del (id %d)",
308 rte_le_to_cpu_32(ctx.cmd.rx_filter_del.filter_id));
314 ionic_dev_add_mac(struct rte_eth_dev *eth_dev,
315 struct rte_ether_addr *mac_addr,
316 uint32_t index __rte_unused, uint32_t pool __rte_unused)
318 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
322 return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr);
326 ionic_dev_remove_mac(struct rte_eth_dev *eth_dev, uint32_t index)
328 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
329 struct ionic_adapter *adapter = lif->adapter;
330 struct rte_ether_addr *mac_addr;
334 if (index >= adapter->max_mac_addrs) {
336 "Index %u is above MAC filter limit %u",
337 index, adapter->max_mac_addrs);
341 mac_addr = ð_dev->data->mac_addrs[index];
343 if (!rte_is_valid_assigned_ether_addr(mac_addr))
346 ionic_lif_addr_del(lif, (const uint8_t *)mac_addr);
350 ionic_dev_set_mac(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr)
352 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
356 if (mac_addr == NULL) {
357 IONIC_PRINT(NOTICE, "New mac is null");
361 if (!rte_is_zero_ether_addr((struct rte_ether_addr *)lif->mac_addr)) {
362 IONIC_PRINT(INFO, "Deleting mac addr %pM",
364 ionic_lif_addr_del(lif, lif->mac_addr);
365 memset(lif->mac_addr, 0, RTE_ETHER_ADDR_LEN);
368 IONIC_PRINT(INFO, "Updating mac addr");
370 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)lif->mac_addr);
372 return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr);
376 ionic_vlan_rx_add_vid(struct ionic_lif *lif, uint16_t vid)
378 struct ionic_admin_ctx ctx = {
379 .pending_work = true,
380 .cmd.rx_filter_add = {
381 .opcode = IONIC_CMD_RX_FILTER_ADD,
382 .match = rte_cpu_to_le_16(IONIC_RX_FILTER_MATCH_VLAN),
383 .vlan.vlan = rte_cpu_to_le_16(vid),
388 err = ionic_adminq_post_wait(lif, &ctx);
392 IONIC_PRINT(INFO, "rx_filter add VLAN %d (id %d)", vid,
393 rte_le_to_cpu_32(ctx.comp.rx_filter_add.filter_id));
395 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);
399 ionic_vlan_rx_kill_vid(struct ionic_lif *lif, uint16_t vid)
401 struct ionic_admin_ctx ctx = {
402 .pending_work = true,
403 .cmd.rx_filter_del = {
404 .opcode = IONIC_CMD_RX_FILTER_DEL,
407 struct ionic_rx_filter *f;
412 rte_spinlock_lock(&lif->rx_filters.lock);
414 f = ionic_rx_filter_by_vlan(lif, vid);
416 rte_spinlock_unlock(&lif->rx_filters.lock);
420 ctx.cmd.rx_filter_del.filter_id = rte_cpu_to_le_32(f->filter_id);
421 ionic_rx_filter_free(f);
422 rte_spinlock_unlock(&lif->rx_filters.lock);
424 err = ionic_adminq_post_wait(lif, &ctx);
428 IONIC_PRINT(INFO, "rx_filter del VLAN %d (id %d)", vid,
429 rte_le_to_cpu_32(ctx.cmd.rx_filter_del.filter_id));
435 ionic_dev_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id,
438 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
442 err = ionic_vlan_rx_add_vid(lif, vlan_id);
444 err = ionic_vlan_rx_kill_vid(lif, vlan_id);
450 ionic_lif_rx_mode(struct ionic_lif *lif, uint32_t rx_mode)
452 struct ionic_admin_ctx ctx = {
453 .pending_work = true,
455 .opcode = IONIC_CMD_RX_MODE_SET,
456 .rx_mode = rte_cpu_to_le_16(rx_mode),
461 if (rx_mode & IONIC_RX_MODE_F_UNICAST)
462 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_UNICAST");
463 if (rx_mode & IONIC_RX_MODE_F_MULTICAST)
464 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_MULTICAST");
465 if (rx_mode & IONIC_RX_MODE_F_BROADCAST)
466 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_BROADCAST");
467 if (rx_mode & IONIC_RX_MODE_F_PROMISC)
468 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_PROMISC");
469 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI)
470 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_ALLMULTI");
472 err = ionic_adminq_post_wait(lif, &ctx);
474 IONIC_PRINT(ERR, "Failure setting RX mode");
478 ionic_set_rx_mode(struct ionic_lif *lif, uint32_t rx_mode)
480 if (lif->rx_mode != rx_mode) {
481 lif->rx_mode = rx_mode;
482 ionic_lif_rx_mode(lif, rx_mode);
487 ionic_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
489 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
490 uint32_t rx_mode = lif->rx_mode;
494 rx_mode |= IONIC_RX_MODE_F_PROMISC;
496 ionic_set_rx_mode(lif, rx_mode);
502 ionic_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
504 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
505 uint32_t rx_mode = lif->rx_mode;
507 rx_mode &= ~IONIC_RX_MODE_F_PROMISC;
509 ionic_set_rx_mode(lif, rx_mode);
515 ionic_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
517 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
518 uint32_t rx_mode = lif->rx_mode;
520 rx_mode |= IONIC_RX_MODE_F_ALLMULTI;
522 ionic_set_rx_mode(lif, rx_mode);
528 ionic_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
530 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
531 uint32_t rx_mode = lif->rx_mode;
533 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI;
535 ionic_set_rx_mode(lif, rx_mode);
541 ionic_lif_change_mtu(struct ionic_lif *lif, int new_mtu)
543 struct ionic_admin_ctx ctx = {
544 .pending_work = true,
546 .opcode = IONIC_CMD_LIF_SETATTR,
547 .attr = IONIC_LIF_ATTR_MTU,
548 .mtu = rte_cpu_to_le_32(new_mtu),
553 err = ionic_adminq_post_wait(lif, &ctx);
561 ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr)
563 struct ionic_adapter *adapter = lif->adapter;
564 struct ionic_dev *idev = &adapter->idev;
568 * Note: interrupt handler is called for index = 0 only
569 * (we use interrupts for the notifyq only anyway,
570 * which has index = 0)
573 for (index = 0; index < adapter->nintrs; index++)
574 if (!adapter->intrs[index])
577 if (index == adapter->nintrs)
580 adapter->intrs[index] = true;
582 ionic_intr_init(idev, intr, index);
588 ionic_qcq_alloc(struct ionic_lif *lif,
592 const char *type_name,
596 uint16_t cq_desc_size,
597 uint16_t sg_desc_size,
598 struct ionic_qcq **qcq)
600 struct ionic_qcq *new;
601 uint32_t q_size, cq_size, sg_size, total_size;
602 void *q_base, *cq_base, *sg_base;
603 rte_iova_t q_base_pa = 0;
604 rte_iova_t cq_base_pa = 0;
605 rte_iova_t sg_base_pa = 0;
606 uint32_t socket_id = rte_socket_id();
611 q_size = num_descs * desc_size;
612 cq_size = num_descs * cq_desc_size;
613 sg_size = num_descs * sg_desc_size;
615 total_size = RTE_ALIGN(q_size, PAGE_SIZE) +
616 RTE_ALIGN(cq_size, PAGE_SIZE);
618 * Note: aligning q_size/cq_size is not enough due to cq_base address
619 * aligning as q_base could be not aligned to the page.
622 total_size += PAGE_SIZE;
624 if (flags & IONIC_QCQ_F_SG) {
625 total_size += RTE_ALIGN(sg_size, PAGE_SIZE);
626 total_size += PAGE_SIZE;
629 new = rte_zmalloc("ionic", struct_size, 0);
631 IONIC_PRINT(ERR, "Cannot allocate queue structure");
637 new->q.info = rte_calloc_socket("ionic",
638 num_descs, sizeof(void *),
639 PAGE_SIZE, socket_id);
641 IONIC_PRINT(ERR, "Cannot allocate queue info");
643 goto err_out_free_qcq;
648 err = ionic_q_init(&new->q, index, num_descs);
650 IONIC_PRINT(ERR, "Queue initialization failed");
651 goto err_out_free_info;
654 err = ionic_cq_init(&new->cq, num_descs);
656 IONIC_PRINT(ERR, "Completion queue initialization failed");
657 goto err_out_free_info;
660 new->base_z = rte_eth_dma_zone_reserve(lif->eth_dev,
661 type_name, index /* queue_idx */,
662 total_size, IONIC_ALIGN, socket_id);
665 IONIC_PRINT(ERR, "Cannot reserve queue DMA memory");
667 goto err_out_free_info;
670 new->base = new->base_z->addr;
671 new->base_pa = new->base_z->iova;
674 q_base_pa = new->base_pa;
676 cq_base = (void *)RTE_ALIGN((uintptr_t)q_base + q_size, PAGE_SIZE);
677 cq_base_pa = RTE_ALIGN(q_base_pa + q_size, PAGE_SIZE);
679 if (flags & IONIC_QCQ_F_SG) {
680 sg_base = (void *)RTE_ALIGN((uintptr_t)cq_base + cq_size,
682 sg_base_pa = RTE_ALIGN(cq_base_pa + cq_size, PAGE_SIZE);
683 ionic_q_sg_map(&new->q, sg_base, sg_base_pa);
686 IONIC_PRINT(DEBUG, "Q-Base-PA = %#jx CQ-Base-PA = %#jx "
688 q_base_pa, cq_base_pa, sg_base_pa);
690 ionic_q_map(&new->q, q_base, q_base_pa);
691 ionic_cq_map(&new->cq, cq_base, cq_base_pa);
698 rte_free(new->q.info);
706 ionic_qcq_free(struct ionic_qcq *qcq)
711 rte_memzone_free(qcq->base_z);
716 rte_free(qcq->q.info);
724 ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t index,
725 uint16_t nrxq_descs, struct ionic_rx_qcq **rxq_out)
727 struct ionic_rx_qcq *rxq;
731 flags = IONIC_QCQ_F_SG;
732 err = ionic_qcq_alloc(lif,
734 sizeof(struct ionic_rx_qcq),
739 sizeof(struct ionic_rxq_desc),
740 sizeof(struct ionic_rxq_comp),
741 sizeof(struct ionic_rxq_sg_desc),
742 (struct ionic_qcq **)&rxq);
748 lif->rxqcqs[index] = rxq;
755 ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t index,
756 uint16_t ntxq_descs, struct ionic_tx_qcq **txq_out)
758 struct ionic_tx_qcq *txq;
762 flags = IONIC_QCQ_F_SG;
763 err = ionic_qcq_alloc(lif,
765 sizeof(struct ionic_tx_qcq),
770 sizeof(struct ionic_txq_desc),
771 sizeof(struct ionic_txq_comp),
772 sizeof(struct ionic_txq_sg_desc_v1),
773 (struct ionic_qcq **)&txq);
779 lif->txqcqs[index] = txq;
786 ionic_admin_qcq_alloc(struct ionic_lif *lif)
791 err = ionic_qcq_alloc(lif,
793 sizeof(struct ionic_admin_qcq),
798 sizeof(struct ionic_admin_cmd),
799 sizeof(struct ionic_admin_comp),
801 (struct ionic_qcq **)&lif->adminqcq);
809 ionic_notify_qcq_alloc(struct ionic_lif *lif)
811 struct ionic_notify_qcq *nqcq;
812 struct ionic_dev *idev = &lif->adapter->idev;
816 err = ionic_qcq_alloc(lif,
818 sizeof(struct ionic_notify_qcq),
822 IONIC_NOTIFYQ_LENGTH,
823 sizeof(struct ionic_notifyq_cmd),
824 sizeof(union ionic_notifyq_comp),
826 (struct ionic_qcq **)&nqcq);
830 err = ionic_intr_alloc(lif, &nqcq->intr);
832 ionic_qcq_free(&nqcq->qcq);
836 ionic_intr_mask_assert(idev->intr_ctrl, nqcq->intr.index,
837 IONIC_INTR_MASK_SET);
839 lif->notifyqcq = nqcq;
845 ionic_bus_map_dbpage(struct ionic_adapter *adapter, int page_num)
847 char *vaddr = adapter->bars[IONIC_PCI_BAR_DBELL].vaddr;
849 if (adapter->num_bars <= IONIC_PCI_BAR_DBELL)
852 return (void *)&vaddr[page_num << PAGE_SHIFT];
856 ionic_lif_queue_identify(struct ionic_lif *lif)
858 struct ionic_adapter *adapter = lif->adapter;
859 struct ionic_dev *idev = &adapter->idev;
860 union ionic_q_identity *q_ident = &adapter->ident.txq;
861 uint32_t q_words = RTE_DIM(q_ident->words);
862 uint32_t cmd_words = RTE_DIM(idev->dev_cmd->data);
863 uint32_t i, nwords, qtype;
866 for (qtype = 0; qtype < RTE_DIM(ionic_qtype_vers); qtype++) {
867 struct ionic_qtype_info *qti = &lif->qtype_info[qtype];
869 /* Filter out the types this driver knows about */
871 case IONIC_QTYPE_ADMINQ:
872 case IONIC_QTYPE_NOTIFYQ:
873 case IONIC_QTYPE_RXQ:
874 case IONIC_QTYPE_TXQ:
880 memset(qti, 0, sizeof(*qti));
882 ionic_dev_cmd_queue_identify(idev, IONIC_LIF_TYPE_CLASSIC,
883 qtype, ionic_qtype_vers[qtype]);
884 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
885 if (err == -EINVAL) {
886 IONIC_PRINT(ERR, "qtype %d not supported\n", qtype);
888 } else if (err == -EIO) {
889 IONIC_PRINT(ERR, "q_ident failed, older FW\n");
892 IONIC_PRINT(ERR, "q_ident failed, qtype %d: %d\n",
897 nwords = RTE_MIN(q_words, cmd_words);
898 for (i = 0; i < nwords; i++)
899 q_ident->words[i] = ioread32(&idev->dev_cmd->data[i]);
901 qti->version = q_ident->version;
902 qti->supported = q_ident->supported;
903 qti->features = rte_le_to_cpu_64(q_ident->features);
904 qti->desc_sz = rte_le_to_cpu_16(q_ident->desc_sz);
905 qti->comp_sz = rte_le_to_cpu_16(q_ident->comp_sz);
906 qti->sg_desc_sz = rte_le_to_cpu_16(q_ident->sg_desc_sz);
907 qti->max_sg_elems = rte_le_to_cpu_16(q_ident->max_sg_elems);
908 qti->sg_desc_stride =
909 rte_le_to_cpu_16(q_ident->sg_desc_stride);
911 IONIC_PRINT(DEBUG, " qtype[%d].version = %d",
912 qtype, qti->version);
913 IONIC_PRINT(DEBUG, " qtype[%d].supported = %#x",
914 qtype, qti->supported);
915 IONIC_PRINT(DEBUG, " qtype[%d].features = %#jx",
916 qtype, qti->features);
917 IONIC_PRINT(DEBUG, " qtype[%d].desc_sz = %d",
918 qtype, qti->desc_sz);
919 IONIC_PRINT(DEBUG, " qtype[%d].comp_sz = %d",
920 qtype, qti->comp_sz);
921 IONIC_PRINT(DEBUG, " qtype[%d].sg_desc_sz = %d",
922 qtype, qti->sg_desc_sz);
923 IONIC_PRINT(DEBUG, " qtype[%d].max_sg_elems = %d",
924 qtype, qti->max_sg_elems);
925 IONIC_PRINT(DEBUG, " qtype[%d].sg_desc_stride = %d",
926 qtype, qti->sg_desc_stride);
931 ionic_lif_alloc(struct ionic_lif *lif)
933 struct ionic_adapter *adapter = lif->adapter;
934 uint32_t socket_id = rte_socket_id();
938 * lif->name was zeroed on allocation.
939 * Copy (sizeof() - 1) bytes to ensure that it is NULL terminated.
941 memcpy(lif->name, lif->eth_dev->data->name, sizeof(lif->name) - 1);
943 IONIC_PRINT(DEBUG, "LIF: %s", lif->name);
945 ionic_lif_queue_identify(lif);
947 if (lif->qtype_info[IONIC_QTYPE_TXQ].version < 1) {
948 IONIC_PRINT(ERR, "FW too old, please upgrade");
952 IONIC_PRINT(DEBUG, "Allocating Lif Info");
954 rte_spinlock_init(&lif->adminq_lock);
955 rte_spinlock_init(&lif->adminq_service_lock);
957 lif->kern_dbpage = ionic_bus_map_dbpage(adapter, 0);
958 if (!lif->kern_dbpage) {
959 IONIC_PRINT(ERR, "Cannot map dbpage, aborting");
963 lif->txqcqs = rte_zmalloc("ionic", sizeof(*lif->txqcqs) *
964 adapter->max_ntxqs_per_lif, 0);
967 IONIC_PRINT(ERR, "Cannot allocate tx queues array");
971 lif->rxqcqs = rte_zmalloc("ionic", sizeof(*lif->rxqcqs) *
972 adapter->max_nrxqs_per_lif, 0);
975 IONIC_PRINT(ERR, "Cannot allocate rx queues array");
979 IONIC_PRINT(DEBUG, "Allocating Notify Queue");
981 err = ionic_notify_qcq_alloc(lif);
983 IONIC_PRINT(ERR, "Cannot allocate notify queue");
987 IONIC_PRINT(DEBUG, "Allocating Admin Queue");
989 err = ionic_admin_qcq_alloc(lif);
991 IONIC_PRINT(ERR, "Cannot allocate admin queue");
995 IONIC_PRINT(DEBUG, "Allocating Lif Info");
997 lif->info_sz = RTE_ALIGN(sizeof(*lif->info), PAGE_SIZE);
999 lif->info_z = rte_eth_dma_zone_reserve(lif->eth_dev,
1000 "lif_info", 0 /* queue_idx*/,
1001 lif->info_sz, IONIC_ALIGN, socket_id);
1003 IONIC_PRINT(ERR, "Cannot allocate lif info memory");
1007 lif->info = lif->info_z->addr;
1008 lif->info_pa = lif->info_z->iova;
1014 ionic_lif_free(struct ionic_lif *lif)
1016 if (lif->notifyqcq) {
1017 ionic_qcq_free(&lif->notifyqcq->qcq);
1018 lif->notifyqcq = NULL;
1021 if (lif->adminqcq) {
1022 ionic_qcq_free(&lif->adminqcq->qcq);
1023 lif->adminqcq = NULL;
1027 rte_free(lif->txqcqs);
1032 rte_free(lif->rxqcqs);
1037 rte_memzone_free(lif->info_z);
1043 ionic_lif_free_queues(struct ionic_lif *lif)
1047 for (i = 0; i < lif->ntxqcqs; i++) {
1048 ionic_dev_tx_queue_release(lif->eth_dev->data->tx_queues[i]);
1049 lif->eth_dev->data->tx_queues[i] = NULL;
1051 for (i = 0; i < lif->nrxqcqs; i++) {
1052 ionic_dev_rx_queue_release(lif->eth_dev->data->rx_queues[i]);
1053 lif->eth_dev->data->rx_queues[i] = NULL;
1058 ionic_lif_rss_config(struct ionic_lif *lif,
1059 const uint16_t types, const uint8_t *key, const uint32_t *indir)
1061 struct ionic_adapter *adapter = lif->adapter;
1062 struct ionic_admin_ctx ctx = {
1063 .pending_work = true,
1064 .cmd.lif_setattr = {
1065 .opcode = IONIC_CMD_LIF_SETATTR,
1066 .attr = IONIC_LIF_ATTR_RSS,
1067 .rss.types = rte_cpu_to_le_16(types),
1068 .rss.addr = rte_cpu_to_le_64(lif->rss_ind_tbl_pa),
1073 rte_le_to_cpu_16(adapter->ident.lif.eth.rss_ind_tbl_sz);
1077 lif->rss_types = types;
1080 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE);
1083 for (i = 0; i < tbl_sz; i++)
1084 lif->rss_ind_tbl[i] = indir[i];
1086 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key,
1087 IONIC_RSS_HASH_KEY_SIZE);
1089 return ionic_adminq_post_wait(lif, &ctx);
1093 ionic_lif_rss_setup(struct ionic_lif *lif)
1095 struct ionic_adapter *adapter = lif->adapter;
1096 static const uint8_t toeplitz_symmetric_key[] = {
1097 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
1098 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
1099 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
1100 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
1101 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,
1105 rte_le_to_cpu_16(adapter->ident.lif.eth.rss_ind_tbl_sz);
1109 if (!lif->rss_ind_tbl_z) {
1110 lif->rss_ind_tbl_z = rte_eth_dma_zone_reserve(lif->eth_dev,
1111 "rss_ind_tbl", 0 /* queue_idx */,
1112 sizeof(*lif->rss_ind_tbl) * tbl_sz,
1113 IONIC_ALIGN, rte_socket_id());
1114 if (!lif->rss_ind_tbl_z) {
1115 IONIC_PRINT(ERR, "OOM");
1119 lif->rss_ind_tbl = lif->rss_ind_tbl_z->addr;
1120 lif->rss_ind_tbl_pa = lif->rss_ind_tbl_z->iova;
1123 if (lif->rss_ind_tbl_nrxqcqs != lif->nrxqcqs) {
1124 lif->rss_ind_tbl_nrxqcqs = lif->nrxqcqs;
1126 /* Fill indirection table with 'default' values */
1127 for (i = 0; i < tbl_sz; i++)
1128 lif->rss_ind_tbl[i] = i % lif->nrxqcqs;
1131 return ionic_lif_rss_config(lif, IONIC_RSS_OFFLOAD_ALL,
1132 toeplitz_symmetric_key, NULL);
1136 ionic_lif_rss_teardown(struct ionic_lif *lif)
1138 if (!lif->rss_ind_tbl)
1141 if (lif->rss_ind_tbl_z) {
1142 /* Disable RSS on the NIC */
1143 ionic_lif_rss_config(lif, 0x0, NULL, NULL);
1145 lif->rss_ind_tbl = NULL;
1146 lif->rss_ind_tbl_pa = 0;
1147 rte_memzone_free(lif->rss_ind_tbl_z);
1148 lif->rss_ind_tbl_z = NULL;
1153 ionic_lif_txq_deinit(struct ionic_tx_qcq *txq)
1155 txq->flags &= ~IONIC_QCQ_F_INITED;
1159 ionic_lif_rxq_deinit(struct ionic_rx_qcq *rxq)
1161 rxq->flags &= ~IONIC_QCQ_F_INITED;
1165 ionic_lif_adminq_deinit(struct ionic_lif *lif)
1167 lif->adminqcq->flags &= ~IONIC_QCQ_F_INITED;
1171 ionic_lif_notifyq_deinit(struct ionic_lif *lif)
1173 struct ionic_notify_qcq *nqcq = lif->notifyqcq;
1174 struct ionic_dev *idev = &lif->adapter->idev;
1176 if (!(nqcq->flags & IONIC_QCQ_F_INITED))
1179 ionic_intr_mask(idev->intr_ctrl, nqcq->intr.index,
1180 IONIC_INTR_MASK_SET);
1182 nqcq->flags &= ~IONIC_QCQ_F_INITED;
1185 /* This acts like ionic_napi */
1187 ionic_qcq_service(struct ionic_qcq *qcq, int budget, ionic_cq_cb cb,
1190 struct ionic_cq *cq = &qcq->cq;
1193 work_done = ionic_cq_service(cq, budget, cb, cb_arg);
1199 ionic_link_status_check(struct ionic_lif *lif)
1201 struct ionic_adapter *adapter = lif->adapter;
1204 lif->state &= ~IONIC_LIF_F_LINK_CHECK_NEEDED;
1209 link_up = (lif->info->status.link_status == IONIC_PORT_OPER_STATUS_UP);
1211 if ((link_up && adapter->link_up) ||
1212 (!link_up && !adapter->link_up))
1216 adapter->link_speed =
1217 rte_le_to_cpu_32(lif->info->status.link_speed);
1218 IONIC_PRINT(DEBUG, "Link up - %d Gbps",
1219 adapter->link_speed);
1221 IONIC_PRINT(DEBUG, "Link down");
1224 adapter->link_up = link_up;
1225 ionic_dev_link_update(lif->eth_dev, 0);
1229 ionic_lif_handle_fw_down(struct ionic_lif *lif)
1231 if (lif->state & IONIC_LIF_F_FW_RESET)
1234 lif->state |= IONIC_LIF_F_FW_RESET;
1236 if (lif->state & IONIC_LIF_F_UP) {
1238 "Surprise FW stop, stopping %s\n", lif->name);
1239 ionic_lif_stop(lif);
1242 IONIC_PRINT(NOTICE, "FW down, %s stopped", lif->name);
1246 ionic_notifyq_cb(struct ionic_cq *cq, uint16_t cq_desc_index, void *cb_arg)
1248 union ionic_notifyq_comp *cq_desc_base = cq->base;
1249 union ionic_notifyq_comp *cq_desc = &cq_desc_base[cq_desc_index];
1250 struct ionic_lif *lif = cb_arg;
1252 IONIC_PRINT(DEBUG, "Notifyq callback eid = %jd ecode = %d",
1253 cq_desc->event.eid, cq_desc->event.ecode);
1255 /* Have we run out of new completions to process? */
1256 if (!(cq_desc->event.eid > lif->last_eid))
1259 lif->last_eid = cq_desc->event.eid;
1261 switch (cq_desc->event.ecode) {
1262 case IONIC_EVENT_LINK_CHANGE:
1264 "Notifyq IONIC_EVENT_LINK_CHANGE %s "
1265 "eid=%jd link_status=%d link_speed=%d",
1268 cq_desc->link_change.link_status,
1269 cq_desc->link_change.link_speed);
1271 lif->state |= IONIC_LIF_F_LINK_CHECK_NEEDED;
1274 case IONIC_EVENT_RESET:
1276 "Notifyq IONIC_EVENT_RESET %s "
1277 "eid=%jd, reset_code=%d state=%d",
1280 cq_desc->reset.reset_code,
1281 cq_desc->reset.state);
1282 ionic_lif_handle_fw_down(lif);
1286 IONIC_PRINT(WARNING, "Notifyq bad event ecode=%d eid=%jd",
1287 cq_desc->event.ecode, cq_desc->event.eid);
1295 ionic_notifyq_handler(struct ionic_lif *lif, int budget)
1297 struct ionic_dev *idev = &lif->adapter->idev;
1298 struct ionic_notify_qcq *nqcq = lif->notifyqcq;
1301 if (!(nqcq->flags & IONIC_QCQ_F_INITED)) {
1302 IONIC_PRINT(DEBUG, "Notifyq not yet initialized");
1306 ionic_intr_mask(idev->intr_ctrl, nqcq->intr.index,
1307 IONIC_INTR_MASK_SET);
1309 work_done = ionic_qcq_service(&nqcq->qcq, budget,
1310 ionic_notifyq_cb, lif);
1312 if (lif->state & IONIC_LIF_F_LINK_CHECK_NEEDED)
1313 ionic_link_status_check(lif);
1315 ionic_intr_credits(idev->intr_ctrl, nqcq->intr.index,
1316 work_done, IONIC_INTR_CRED_RESET_COALESCE);
1318 ionic_intr_mask(idev->intr_ctrl, nqcq->intr.index,
1319 IONIC_INTR_MASK_CLEAR);
1325 ionic_lif_adminq_init(struct ionic_lif *lif)
1327 struct ionic_dev *idev = &lif->adapter->idev;
1328 struct ionic_admin_qcq *aqcq = lif->adminqcq;
1329 struct ionic_queue *q = &aqcq->qcq.q;
1330 struct ionic_q_init_comp comp;
1333 ionic_dev_cmd_adminq_init(idev, &aqcq->qcq);
1334 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1338 ionic_dev_cmd_comp(idev, &comp);
1340 q->hw_type = comp.hw_type;
1341 q->hw_index = rte_le_to_cpu_32(comp.hw_index);
1342 q->db = ionic_db_map(lif, q);
1344 IONIC_PRINT(DEBUG, "adminq->hw_type %d", q->hw_type);
1345 IONIC_PRINT(DEBUG, "adminq->hw_index %d", q->hw_index);
1346 IONIC_PRINT(DEBUG, "adminq->db %p", q->db);
1348 aqcq->flags |= IONIC_QCQ_F_INITED;
1354 ionic_lif_notifyq_init(struct ionic_lif *lif)
1356 struct ionic_dev *idev = &lif->adapter->idev;
1357 struct ionic_notify_qcq *nqcq = lif->notifyqcq;
1358 struct ionic_queue *q = &nqcq->qcq.q;
1361 struct ionic_admin_ctx ctx = {
1362 .pending_work = true,
1364 .opcode = IONIC_CMD_Q_INIT,
1366 .ver = lif->qtype_info[q->type].version,
1367 .index = rte_cpu_to_le_32(q->index),
1368 .intr_index = rte_cpu_to_le_16(nqcq->intr.index),
1369 .flags = rte_cpu_to_le_16(IONIC_QINIT_F_IRQ |
1371 .ring_size = rte_log2_u32(q->num_descs),
1372 .ring_base = rte_cpu_to_le_64(q->base_pa),
1376 IONIC_PRINT(DEBUG, "notifyq_init.index %d", q->index);
1377 IONIC_PRINT(DEBUG, "notifyq_init.ring_base 0x%" PRIx64 "", q->base_pa);
1378 IONIC_PRINT(DEBUG, "notifyq_init.ring_size %d",
1379 ctx.cmd.q_init.ring_size);
1380 IONIC_PRINT(DEBUG, "notifyq_init.ver %u", ctx.cmd.q_init.ver);
1382 err = ionic_adminq_post_wait(lif, &ctx);
1386 q->hw_type = ctx.comp.q_init.hw_type;
1387 q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index);
1390 IONIC_PRINT(DEBUG, "notifyq->hw_type %d", q->hw_type);
1391 IONIC_PRINT(DEBUG, "notifyq->hw_index %d", q->hw_index);
1392 IONIC_PRINT(DEBUG, "notifyq->db %p", q->db);
1394 ionic_intr_mask(idev->intr_ctrl, nqcq->intr.index,
1395 IONIC_INTR_MASK_CLEAR);
1397 nqcq->flags |= IONIC_QCQ_F_INITED;
1403 ionic_lif_set_features(struct ionic_lif *lif)
1405 struct ionic_admin_ctx ctx = {
1406 .pending_work = true,
1407 .cmd.lif_setattr = {
1408 .opcode = IONIC_CMD_LIF_SETATTR,
1409 .attr = IONIC_LIF_ATTR_FEATURES,
1410 .features = rte_cpu_to_le_64(lif->features),
1415 err = ionic_adminq_post_wait(lif, &ctx);
1419 lif->hw_features = rte_le_to_cpu_64(ctx.cmd.lif_setattr.features &
1420 ctx.comp.lif_setattr.features);
1422 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
1423 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_TX_TAG");
1424 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
1425 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_STRIP");
1426 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
1427 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_FILTER");
1428 if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
1429 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_HASH");
1430 if (lif->hw_features & IONIC_ETH_HW_TX_SG)
1431 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_SG");
1432 if (lif->hw_features & IONIC_ETH_HW_RX_SG)
1433 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_SG");
1434 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
1435 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_CSUM");
1436 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
1437 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_CSUM");
1438 if (lif->hw_features & IONIC_ETH_HW_TSO)
1439 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO");
1440 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
1441 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPV6");
1442 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
1443 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_ECN");
1444 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
1445 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE");
1446 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
1447 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE_CSUM");
1448 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
1449 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP4");
1450 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
1451 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP6");
1452 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
1453 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP");
1454 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
1455 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP_CSUM");
1461 ionic_lif_txq_init(struct ionic_tx_qcq *txq)
1463 struct ionic_qcq *qcq = &txq->qcq;
1464 struct ionic_queue *q = &qcq->q;
1465 struct ionic_lif *lif = qcq->lif;
1466 struct ionic_cq *cq = &qcq->cq;
1467 struct ionic_admin_ctx ctx = {
1468 .pending_work = true,
1470 .opcode = IONIC_CMD_Q_INIT,
1472 .ver = lif->qtype_info[q->type].version,
1473 .index = rte_cpu_to_le_32(q->index),
1474 .flags = rte_cpu_to_le_16(IONIC_QINIT_F_SG |
1476 .intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE),
1477 .ring_size = rte_log2_u32(q->num_descs),
1478 .ring_base = rte_cpu_to_le_64(q->base_pa),
1479 .cq_ring_base = rte_cpu_to_le_64(cq->base_pa),
1480 .sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa),
1485 IONIC_PRINT(DEBUG, "txq_init.index %d", q->index);
1486 IONIC_PRINT(DEBUG, "txq_init.ring_base 0x%" PRIx64 "", q->base_pa);
1487 IONIC_PRINT(DEBUG, "txq_init.ring_size %d",
1488 ctx.cmd.q_init.ring_size);
1489 IONIC_PRINT(DEBUG, "txq_init.ver %u", ctx.cmd.q_init.ver);
1491 err = ionic_adminq_post_wait(lif, &ctx);
1495 q->hw_type = ctx.comp.q_init.hw_type;
1496 q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index);
1497 q->db = ionic_db_map(lif, q);
1499 IONIC_PRINT(DEBUG, "txq->hw_type %d", q->hw_type);
1500 IONIC_PRINT(DEBUG, "txq->hw_index %d", q->hw_index);
1501 IONIC_PRINT(DEBUG, "txq->db %p", q->db);
1503 txq->flags |= IONIC_QCQ_F_INITED;
1509 ionic_lif_rxq_init(struct ionic_rx_qcq *rxq)
1511 struct ionic_qcq *qcq = &rxq->qcq;
1512 struct ionic_queue *q = &qcq->q;
1513 struct ionic_lif *lif = qcq->lif;
1514 struct ionic_cq *cq = &qcq->cq;
1515 struct ionic_admin_ctx ctx = {
1516 .pending_work = true,
1518 .opcode = IONIC_CMD_Q_INIT,
1520 .ver = lif->qtype_info[q->type].version,
1521 .index = rte_cpu_to_le_32(q->index),
1522 .flags = rte_cpu_to_le_16(IONIC_QINIT_F_SG |
1524 .intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE),
1525 .ring_size = rte_log2_u32(q->num_descs),
1526 .ring_base = rte_cpu_to_le_64(q->base_pa),
1527 .cq_ring_base = rte_cpu_to_le_64(cq->base_pa),
1528 .sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa),
1533 IONIC_PRINT(DEBUG, "rxq_init.index %d", q->index);
1534 IONIC_PRINT(DEBUG, "rxq_init.ring_base 0x%" PRIx64 "", q->base_pa);
1535 IONIC_PRINT(DEBUG, "rxq_init.ring_size %d",
1536 ctx.cmd.q_init.ring_size);
1537 IONIC_PRINT(DEBUG, "rxq_init.ver %u", ctx.cmd.q_init.ver);
1539 err = ionic_adminq_post_wait(lif, &ctx);
1543 q->hw_type = ctx.comp.q_init.hw_type;
1544 q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index);
1545 q->db = ionic_db_map(lif, q);
1547 rxq->flags |= IONIC_QCQ_F_INITED;
1549 IONIC_PRINT(DEBUG, "rxq->hw_type %d", q->hw_type);
1550 IONIC_PRINT(DEBUG, "rxq->hw_index %d", q->hw_index);
1551 IONIC_PRINT(DEBUG, "rxq->db %p", q->db);
1557 ionic_station_set(struct ionic_lif *lif)
1559 struct ionic_admin_ctx ctx = {
1560 .pending_work = true,
1561 .cmd.lif_getattr = {
1562 .opcode = IONIC_CMD_LIF_GETATTR,
1563 .attr = IONIC_LIF_ATTR_MAC,
1570 err = ionic_adminq_post_wait(lif, &ctx);
1574 memcpy(lif->mac_addr, ctx.comp.lif_getattr.mac, RTE_ETHER_ADDR_LEN);
1580 ionic_lif_set_name(struct ionic_lif *lif)
1582 struct ionic_admin_ctx ctx = {
1583 .pending_work = true,
1584 .cmd.lif_setattr = {
1585 .opcode = IONIC_CMD_LIF_SETATTR,
1586 .attr = IONIC_LIF_ATTR_NAME,
1590 memcpy(ctx.cmd.lif_setattr.name, lif->name,
1591 sizeof(ctx.cmd.lif_setattr.name) - 1);
1593 ionic_adminq_post_wait(lif, &ctx);
1597 ionic_lif_init(struct ionic_lif *lif)
1599 struct ionic_dev *idev = &lif->adapter->idev;
1600 struct ionic_q_init_comp comp;
1603 memset(&lif->stats_base, 0, sizeof(lif->stats_base));
1605 ionic_dev_cmd_lif_init(idev, lif->info_pa);
1606 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1607 ionic_dev_cmd_comp(idev, &comp);
1611 lif->hw_index = rte_cpu_to_le_16(comp.hw_index);
1613 err = ionic_lif_adminq_init(lif);
1617 err = ionic_lif_notifyq_init(lif);
1619 goto err_out_adminq_deinit;
1622 * Configure initial feature set
1623 * This will be updated later by the dev_configure() step
1625 lif->features = IONIC_ETH_HW_RX_HASH | IONIC_ETH_HW_VLAN_RX_FILTER;
1627 err = ionic_lif_set_features(lif);
1629 goto err_out_notifyq_deinit;
1631 err = ionic_rx_filters_init(lif);
1633 goto err_out_notifyq_deinit;
1635 err = ionic_station_set(lif);
1637 goto err_out_rx_filter_deinit;
1639 ionic_lif_set_name(lif);
1641 lif->state |= IONIC_LIF_F_INITED;
1645 err_out_rx_filter_deinit:
1646 ionic_rx_filters_deinit(lif);
1648 err_out_notifyq_deinit:
1649 ionic_lif_notifyq_deinit(lif);
1651 err_out_adminq_deinit:
1652 ionic_lif_adminq_deinit(lif);
1658 ionic_lif_deinit(struct ionic_lif *lif)
1660 if (!(lif->state & IONIC_LIF_F_INITED))
1663 ionic_rx_filters_deinit(lif);
1664 ionic_lif_rss_teardown(lif);
1665 ionic_lif_notifyq_deinit(lif);
1666 ionic_lif_adminq_deinit(lif);
1668 lif->state &= ~IONIC_LIF_F_INITED;
1672 ionic_lif_configure_vlan_offload(struct ionic_lif *lif, int mask)
1674 struct rte_eth_dev *eth_dev = lif->eth_dev;
1675 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1678 * IONIC_ETH_HW_VLAN_RX_FILTER cannot be turned off, so
1679 * set DEV_RX_OFFLOAD_VLAN_FILTER and ignore ETH_VLAN_FILTER_MASK
1681 rxmode->offloads |= DEV_RX_OFFLOAD_VLAN_FILTER;
1683 if (mask & ETH_VLAN_STRIP_MASK) {
1684 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1685 lif->features |= IONIC_ETH_HW_VLAN_RX_STRIP;
1687 lif->features &= ~IONIC_ETH_HW_VLAN_RX_STRIP;
1692 ionic_lif_configure(struct ionic_lif *lif)
1694 struct rte_eth_rxmode *rxmode = &lif->eth_dev->data->dev_conf.rxmode;
1695 struct rte_eth_txmode *txmode = &lif->eth_dev->data->dev_conf.txmode;
1696 struct ionic_identity *ident = &lif->adapter->ident;
1697 union ionic_lif_config *cfg = &ident->lif.eth.config;
1698 uint32_t ntxqs_per_lif =
1699 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]);
1700 uint32_t nrxqs_per_lif =
1701 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]);
1702 uint32_t nrxqs = lif->eth_dev->data->nb_rx_queues;
1703 uint32_t ntxqs = lif->eth_dev->data->nb_tx_queues;
1705 lif->port_id = lif->eth_dev->data->port_id;
1707 IONIC_PRINT(DEBUG, "Configuring LIF on port %u",
1711 nrxqs_per_lif = RTE_MIN(nrxqs_per_lif, nrxqs);
1714 ntxqs_per_lif = RTE_MIN(ntxqs_per_lif, ntxqs);
1716 lif->nrxqcqs = nrxqs_per_lif;
1717 lif->ntxqcqs = ntxqs_per_lif;
1719 /* Update the LIF configuration based on the eth_dev */
1722 * NB: While it is true that RSS_HASH is always enabled on ionic,
1723 * setting this flag unconditionally causes problems in DTS.
1724 * rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1729 if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM ||
1730 rxmode->offloads & DEV_RX_OFFLOAD_UDP_CKSUM ||
1731 rxmode->offloads & DEV_RX_OFFLOAD_TCP_CKSUM)
1732 lif->features |= IONIC_ETH_HW_RX_CSUM;
1734 lif->features &= ~IONIC_ETH_HW_RX_CSUM;
1736 if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER) {
1737 lif->features |= IONIC_ETH_HW_RX_SG;
1738 lif->eth_dev->data->scattered_rx = 1;
1740 lif->features &= ~IONIC_ETH_HW_RX_SG;
1741 lif->eth_dev->data->scattered_rx = 0;
1744 /* Covers VLAN_STRIP */
1745 ionic_lif_configure_vlan_offload(lif, ETH_VLAN_STRIP_MASK);
1749 if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
1750 txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
1751 txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM ||
1752 txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
1753 txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)
1754 lif->features |= IONIC_ETH_HW_TX_CSUM;
1756 lif->features &= ~IONIC_ETH_HW_TX_CSUM;
1758 if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
1759 lif->features |= IONIC_ETH_HW_VLAN_TX_TAG;
1761 lif->features &= ~IONIC_ETH_HW_VLAN_TX_TAG;
1763 if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
1764 lif->features |= IONIC_ETH_HW_TX_SG;
1766 lif->features &= ~IONIC_ETH_HW_TX_SG;
1768 if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
1769 lif->features |= IONIC_ETH_HW_TSO;
1770 lif->features |= IONIC_ETH_HW_TSO_IPV6;
1771 lif->features |= IONIC_ETH_HW_TSO_ECN;
1773 lif->features &= ~IONIC_ETH_HW_TSO;
1774 lif->features &= ~IONIC_ETH_HW_TSO_IPV6;
1775 lif->features &= ~IONIC_ETH_HW_TSO_ECN;
1780 ionic_lif_start(struct ionic_lif *lif)
1786 err = ionic_lif_rss_setup(lif);
1790 if (!lif->rx_mode) {
1791 IONIC_PRINT(DEBUG, "Setting RX mode on %s",
1794 rx_mode = IONIC_RX_MODE_F_UNICAST;
1795 rx_mode |= IONIC_RX_MODE_F_MULTICAST;
1796 rx_mode |= IONIC_RX_MODE_F_BROADCAST;
1798 ionic_set_rx_mode(lif, rx_mode);
1801 IONIC_PRINT(DEBUG, "Starting %u RX queues and %u TX queues "
1803 lif->nrxqcqs, lif->ntxqcqs, lif->port_id);
1805 for (i = 0; i < lif->nrxqcqs; i++) {
1806 struct ionic_rx_qcq *rxq = lif->rxqcqs[i];
1807 if (!(rxq->flags & IONIC_QCQ_F_DEFERRED)) {
1808 err = ionic_dev_rx_queue_start(lif->eth_dev, i);
1815 for (i = 0; i < lif->ntxqcqs; i++) {
1816 struct ionic_tx_qcq *txq = lif->txqcqs[i];
1817 if (!(txq->flags & IONIC_QCQ_F_DEFERRED)) {
1818 err = ionic_dev_tx_queue_start(lif->eth_dev, i);
1825 /* Carrier ON here */
1826 lif->state |= IONIC_LIF_F_UP;
1828 ionic_link_status_check(lif);
1834 ionic_lif_identify(struct ionic_adapter *adapter)
1836 struct ionic_dev *idev = &adapter->idev;
1837 struct ionic_identity *ident = &adapter->ident;
1838 union ionic_lif_config *cfg = &ident->lif.eth.config;
1839 uint32_t lif_words = RTE_DIM(ident->lif.words);
1840 uint32_t cmd_words = RTE_DIM(idev->dev_cmd->data);
1844 ionic_dev_cmd_lif_identify(idev, IONIC_LIF_TYPE_CLASSIC,
1845 IONIC_IDENTITY_VERSION_1);
1846 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
1850 nwords = RTE_MIN(lif_words, cmd_words);
1851 for (i = 0; i < nwords; i++)
1852 ident->lif.words[i] = ioread32(&idev->dev_cmd->data[i]);
1854 IONIC_PRINT(INFO, "capabilities 0x%" PRIx64 " ",
1855 rte_le_to_cpu_64(ident->lif.capabilities));
1857 IONIC_PRINT(INFO, "eth.max_ucast_filters 0x%" PRIx32 " ",
1858 rte_le_to_cpu_32(ident->lif.eth.max_ucast_filters));
1859 IONIC_PRINT(INFO, "eth.max_mcast_filters 0x%" PRIx32 " ",
1860 rte_le_to_cpu_32(ident->lif.eth.max_mcast_filters));
1862 IONIC_PRINT(INFO, "eth.features 0x%" PRIx64 " ",
1863 rte_le_to_cpu_64(cfg->features));
1864 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_ADMINQ] 0x%" PRIx32 " ",
1865 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_ADMINQ]));
1866 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] 0x%" PRIx32 " ",
1867 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_NOTIFYQ]));
1868 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_RXQ] 0x%" PRIx32 " ",
1869 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]));
1870 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_TXQ] 0x%" PRIx32 " ",
1871 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]));
1877 ionic_lifs_size(struct ionic_adapter *adapter)
1879 struct ionic_identity *ident = &adapter->ident;
1880 union ionic_lif_config *cfg = &ident->lif.eth.config;
1881 uint32_t nintrs, dev_nintrs = rte_le_to_cpu_32(ident->dev.nintrs);
1883 adapter->max_ntxqs_per_lif =
1884 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]);
1885 adapter->max_nrxqs_per_lif =
1886 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]);
1888 nintrs = 1 /* notifyq */;
1890 if (nintrs > dev_nintrs) {
1892 "At most %d intr supported, minimum req'd is %u",
1893 dev_nintrs, nintrs);
1897 adapter->nintrs = nintrs;