1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
7 #include <rte_memzone.h>
10 #include "ionic_ethdev.h"
11 #include "ionic_lif.h"
14 ionic_error_to_str(enum ionic_status_code code)
17 case IONIC_RC_SUCCESS:
18 return "IONIC_RC_SUCCESS";
19 case IONIC_RC_EVERSION:
20 return "IONIC_RC_EVERSION";
21 case IONIC_RC_EOPCODE:
22 return "IONIC_RC_EOPCODE";
24 return "IONIC_RC_EIO";
26 return "IONIC_RC_EPERM";
28 return "IONIC_RC_EQID";
30 return "IONIC_RC_EQTYPE";
32 return "IONIC_RC_ENOENT";
34 return "IONIC_RC_EINTR";
36 return "IONIC_RC_EAGAIN";
38 return "IONIC_RC_ENOMEM";
40 return "IONIC_RC_EFAULT";
42 return "IONIC_RC_EBUSY";
44 return "IONIC_RC_EEXIST";
46 return "IONIC_RC_EINVAL";
48 return "IONIC_RC_ENOSPC";
50 return "IONIC_RC_ERANGE";
51 case IONIC_RC_BAD_ADDR:
52 return "IONIC_RC_BAD_ADDR";
53 case IONIC_RC_DEV_CMD:
54 return "IONIC_RC_DEV_CMD";
56 return "IONIC_RC_ERROR";
58 return "IONIC_RC_ERDMA";
60 return "IONIC_RC_UNKNOWN";
65 ionic_opcode_to_str(enum ionic_cmd_opcode opcode)
69 return "IONIC_CMD_NOP";
71 return "IONIC_CMD_INIT";
73 return "IONIC_CMD_RESET";
74 case IONIC_CMD_IDENTIFY:
75 return "IONIC_CMD_IDENTIFY";
76 case IONIC_CMD_GETATTR:
77 return "IONIC_CMD_GETATTR";
78 case IONIC_CMD_SETATTR:
79 return "IONIC_CMD_SETATTR";
80 case IONIC_CMD_PORT_IDENTIFY:
81 return "IONIC_CMD_PORT_IDENTIFY";
82 case IONIC_CMD_PORT_INIT:
83 return "IONIC_CMD_PORT_INIT";
84 case IONIC_CMD_PORT_RESET:
85 return "IONIC_CMD_PORT_RESET";
86 case IONIC_CMD_PORT_GETATTR:
87 return "IONIC_CMD_PORT_GETATTR";
88 case IONIC_CMD_PORT_SETATTR:
89 return "IONIC_CMD_PORT_SETATTR";
90 case IONIC_CMD_LIF_INIT:
91 return "IONIC_CMD_LIF_INIT";
92 case IONIC_CMD_LIF_RESET:
93 return "IONIC_CMD_LIF_RESET";
94 case IONIC_CMD_LIF_IDENTIFY:
95 return "IONIC_CMD_LIF_IDENTIFY";
96 case IONIC_CMD_LIF_SETATTR:
97 return "IONIC_CMD_LIF_SETATTR";
98 case IONIC_CMD_LIF_GETATTR:
99 return "IONIC_CMD_LIF_GETATTR";
100 case IONIC_CMD_RX_MODE_SET:
101 return "IONIC_CMD_RX_MODE_SET";
102 case IONIC_CMD_RX_FILTER_ADD:
103 return "IONIC_CMD_RX_FILTER_ADD";
104 case IONIC_CMD_RX_FILTER_DEL:
105 return "IONIC_CMD_RX_FILTER_DEL";
106 case IONIC_CMD_Q_INIT:
107 return "IONIC_CMD_Q_INIT";
108 case IONIC_CMD_Q_CONTROL:
109 return "IONIC_CMD_Q_CONTROL";
110 case IONIC_CMD_Q_IDENTIFY:
111 return "IONIC_CMD_Q_IDENTIFY";
112 case IONIC_CMD_RDMA_RESET_LIF:
113 return "IONIC_CMD_RDMA_RESET_LIF";
114 case IONIC_CMD_RDMA_CREATE_EQ:
115 return "IONIC_CMD_RDMA_CREATE_EQ";
116 case IONIC_CMD_RDMA_CREATE_CQ:
117 return "IONIC_CMD_RDMA_CREATE_CQ";
118 case IONIC_CMD_RDMA_CREATE_ADMINQ:
119 return "IONIC_CMD_RDMA_CREATE_ADMINQ";
121 return "DEVCMD_UNKNOWN";
126 ionic_adminq_check_err(struct ionic_admin_ctx *ctx, bool timeout)
131 name = ionic_opcode_to_str(ctx->cmd.cmd.opcode);
133 if (ctx->comp.comp.status || timeout) {
134 status = ionic_error_to_str(ctx->comp.comp.status);
135 IONIC_PRINT(ERR, "%s (%d) failed: %s (%d)",
138 timeout ? "TIMEOUT" : status,
139 timeout ? -1 : ctx->comp.comp.status);
143 IONIC_PRINT(DEBUG, "%s (%d) succeeded", name, ctx->cmd.cmd.opcode);
149 ionic_wait_ctx_for_completion(struct ionic_lif *lif, struct ionic_qcq *qcq,
150 struct ionic_admin_ctx *ctx, unsigned long max_wait)
152 unsigned long step_usec = IONIC_DEVCMD_CHECK_PERIOD_US;
153 unsigned long max_wait_usec = max_wait * 1000000L;
154 unsigned long elapsed_usec = 0;
157 while (ctx->pending_work && elapsed_usec < max_wait_usec) {
159 * Locking here as adminq is served inline (this could be called
160 * from multiple places)
162 rte_spinlock_lock(&lif->adminq_service_lock);
164 ionic_qcq_service(qcq, budget, ionic_adminq_service, NULL);
166 rte_spinlock_unlock(&lif->adminq_service_lock);
168 rte_delay_us_block(step_usec);
169 elapsed_usec += step_usec;
172 return (!ctx->pending_work);
176 ionic_adminq_post_wait(struct ionic_lif *lif, struct ionic_admin_ctx *ctx)
178 struct ionic_qcq *qcq = lif->adminqcq;
182 IONIC_PRINT(DEBUG, "Sending %s (%d) via the admin queue",
183 ionic_opcode_to_str(ctx->cmd.cmd.opcode), ctx->cmd.cmd.opcode);
185 err = ionic_adminq_post(lif, ctx);
187 IONIC_PRINT(ERR, "Failure posting %d to the admin queue (%d)",
188 ctx->cmd.cmd.opcode, err);
192 done = ionic_wait_ctx_for_completion(lif, qcq, ctx,
193 IONIC_DEVCMD_TIMEOUT);
195 return ionic_adminq_check_err(ctx, !done /* timed out */);
199 ionic_dev_cmd_wait(struct ionic_dev *idev, unsigned long max_wait)
201 unsigned long step_usec = IONIC_DEVCMD_CHECK_PERIOD_US;
202 unsigned long max_wait_usec = max_wait * 1000000L;
203 unsigned long elapsed_usec = 0;
206 /* Wait for dev cmd to complete.. but no more than max_wait sec */
209 done = ionic_dev_cmd_done(idev);
211 IONIC_PRINT(DEBUG, "DEVCMD %d done took %ld usecs",
212 ioread8(&idev->dev_cmd->cmd.cmd.opcode),
217 rte_delay_us_block(step_usec);
219 elapsed_usec += step_usec;
220 } while (elapsed_usec < max_wait_usec);
222 IONIC_PRINT(ERR, "DEVCMD %d timeout after %ld usecs",
223 ioread8(&idev->dev_cmd->cmd.cmd.opcode),
230 ionic_dev_cmd_check_error(struct ionic_dev *idev)
234 status = ionic_dev_cmd_status(idev);
242 ionic_dev_cmd_wait_check(struct ionic_dev *idev, unsigned long max_wait)
246 err = ionic_dev_cmd_wait(idev, max_wait);
249 err = ionic_dev_cmd_check_error(idev);
251 IONIC_PRINT(DEBUG, "dev_cmd returned %d", err);
256 ionic_setup(struct ionic_adapter *adapter)
258 return ionic_dev_setup(adapter);
262 ionic_identify(struct ionic_adapter *adapter)
264 struct ionic_dev *idev = &adapter->idev;
265 struct ionic_identity *ident = &adapter->ident;
266 uint32_t drv_size = RTE_DIM(ident->drv.words);
267 uint32_t cmd_size = RTE_DIM(idev->dev_cmd->data);
268 uint32_t dev_size = RTE_DIM(ident->dev.words);
272 memset(ident, 0, sizeof(*ident));
274 ident->drv.os_type = IONIC_OS_TYPE_LINUX;
275 ident->drv.os_dist = 0;
276 snprintf(ident->drv.os_dist_str,
277 sizeof(ident->drv.os_dist_str), "Unknown");
278 ident->drv.kernel_ver = 0;
279 snprintf(ident->drv.kernel_ver_str,
280 sizeof(ident->drv.kernel_ver_str), "DPDK");
281 strncpy(ident->drv.driver_ver_str, IONIC_DRV_VERSION,
282 sizeof(ident->drv.driver_ver_str) - 1);
284 nwords = RTE_MIN(drv_size, cmd_size);
285 for (i = 0; i < nwords; i++)
286 iowrite32(ident->drv.words[i], &idev->dev_cmd->data[i]);
288 ionic_dev_cmd_identify(idev, IONIC_IDENTITY_VERSION_1);
289 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
291 nwords = RTE_MIN(dev_size, cmd_size);
292 for (i = 0; i < nwords; i++)
293 ident->dev.words[i] = ioread32(&idev->dev_cmd->data[i]);
300 ionic_init(struct ionic_adapter *adapter)
302 struct ionic_dev *idev = &adapter->idev;
304 ionic_dev_cmd_init(idev);
305 return ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
309 ionic_reset(struct ionic_adapter *adapter)
311 struct ionic_dev *idev = &adapter->idev;
313 ionic_dev_cmd_reset(idev);
314 return ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
318 ionic_port_identify(struct ionic_adapter *adapter)
320 struct ionic_dev *idev = &adapter->idev;
321 struct ionic_identity *ident = &adapter->ident;
322 uint32_t port_words = RTE_DIM(ident->port.words);
323 uint32_t cmd_words = RTE_DIM(idev->dev_cmd->data);
327 ionic_dev_cmd_port_identify(idev);
328 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
330 nwords = RTE_MIN(port_words, cmd_words);
331 for (i = 0; i < nwords; i++)
332 ident->port.words[i] =
333 ioread32(&idev->dev_cmd->data[i]);
336 IONIC_PRINT(INFO, "speed %d",
337 rte_le_to_cpu_32(ident->port.config.speed));
338 IONIC_PRINT(INFO, "mtu %d",
339 rte_le_to_cpu_32(ident->port.config.mtu));
340 IONIC_PRINT(INFO, "state %d", ident->port.config.state);
341 IONIC_PRINT(INFO, "an_enable %d", ident->port.config.an_enable);
342 IONIC_PRINT(INFO, "fec_type %d", ident->port.config.fec_type);
343 IONIC_PRINT(INFO, "pause_type %d", ident->port.config.pause_type);
344 IONIC_PRINT(INFO, "loopback_mode %d",
345 ident->port.config.loopback_mode);
350 static const struct rte_memzone *
351 ionic_memzone_reserve(const char *name, uint32_t len, int socket_id)
353 const struct rte_memzone *mz;
355 mz = rte_memzone_lookup(name);
359 mz = rte_memzone_reserve_aligned(name, len, socket_id,
360 RTE_MEMZONE_IOVA_CONTIG, IONIC_ALIGN);
365 ionic_port_init(struct ionic_adapter *adapter)
367 struct ionic_dev *idev = &adapter->idev;
368 struct ionic_identity *ident = &adapter->ident;
369 char z_name[RTE_MEMZONE_NAMESIZE];
370 uint32_t config_words = RTE_DIM(ident->port.config.words);
371 uint32_t cmd_words = RTE_DIM(idev->dev_cmd->data);
378 idev->port_info_sz = RTE_ALIGN(sizeof(*idev->port_info), PAGE_SIZE);
380 snprintf(z_name, sizeof(z_name), "%s_port_%s_info",
381 IONIC_DRV_NAME, adapter->name);
383 idev->port_info_z = ionic_memzone_reserve(z_name, idev->port_info_sz,
385 if (!idev->port_info_z) {
386 IONIC_PRINT(ERR, "Cannot reserve port info DMA memory");
390 idev->port_info = idev->port_info_z->addr;
391 idev->port_info_pa = idev->port_info_z->iova;
393 nwords = RTE_MIN(config_words, cmd_words);
395 for (i = 0; i < nwords; i++)
396 iowrite32(ident->port.config.words[i], &idev->dev_cmd->data[i]);
398 idev->port_info->config.state = IONIC_PORT_ADMIN_STATE_UP;
399 ionic_dev_cmd_port_init(idev);
400 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
402 IONIC_PRINT(ERR, "Failed to init port");
408 ionic_port_reset(struct ionic_adapter *adapter)
410 struct ionic_dev *idev = &adapter->idev;
413 if (!idev->port_info)
416 ionic_dev_cmd_port_reset(idev);
417 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
419 IONIC_PRINT(ERR, "Failed to reset port");
423 idev->port_info = NULL;
424 idev->port_info_pa = 0;