1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
15 #include <rte_byteorder.h>
16 #include <rte_common.h>
17 #include <rte_cycles.h>
19 #include <rte_debug.h>
20 #include <rte_interrupts.h>
22 #include <rte_memory.h>
23 #include <rte_memzone.h>
24 #include <rte_launch.h>
26 #include <rte_per_lcore.h>
27 #include <rte_lcore.h>
28 #include <rte_atomic.h>
29 #include <rte_branch_prediction.h>
30 #include <rte_mempool.h>
31 #include <rte_malloc.h>
33 #include <rte_ether.h>
34 #include <ethdev_driver.h>
35 #include <rte_prefetch.h>
39 #include <rte_string_fns.h>
40 #include <rte_errno.h>
44 #include "ionic_logs.h"
45 #include "ionic_mac_api.h"
46 #include "ionic_ethdev.h"
47 #include "ionic_lif.h"
48 #include "ionic_rxtx.h"
50 #define IONIC_RX_RING_DOORBELL_STRIDE (32 - 1)
52 /*********************************************************************
56 **********************************************************************/
59 ionic_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
60 struct rte_eth_txq_info *qinfo)
62 struct ionic_qcq *txq = dev->data->tx_queues[queue_id];
63 struct ionic_queue *q = &txq->q;
65 qinfo->nb_desc = q->num_descs;
66 qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads;
67 qinfo->conf.tx_deferred_start = txq->flags & IONIC_QCQ_F_DEFERRED;
70 static __rte_always_inline void
71 ionic_tx_flush(struct ionic_cq *cq)
73 struct ionic_queue *q = cq->bound_q;
74 struct ionic_desc_info *q_desc_info;
75 struct rte_mbuf *txm, *next;
76 struct ionic_txq_comp *cq_desc_base = cq->base;
77 struct ionic_txq_comp *cq_desc;
78 u_int32_t comp_index = (u_int32_t)-1;
80 cq_desc = &cq_desc_base[cq->tail_idx];
81 while (color_match(cq_desc->color, cq->done_color)) {
82 cq->tail_idx = (cq->tail_idx + 1) & (cq->num_descs - 1);
84 /* Prefetch the next 4 descriptors (not really useful here) */
85 if ((cq->tail_idx & 0x3) == 0)
86 rte_prefetch0(&cq_desc_base[cq->tail_idx]);
88 if (cq->tail_idx == 0)
89 cq->done_color = !cq->done_color;
91 comp_index = cq_desc->comp_index;
93 cq_desc = &cq_desc_base[cq->tail_idx];
96 if (comp_index != (u_int32_t)-1) {
97 while (q->tail_idx != comp_index) {
98 q_desc_info = &q->info[q->tail_idx];
100 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1);
102 /* Prefetch the next 4 descriptors */
103 if ((q->tail_idx & 0x3) == 0)
105 rte_prefetch0(&q->info[q->tail_idx]);
108 * Note: you can just use rte_pktmbuf_free,
109 * but this loop is faster
111 txm = q_desc_info->cb_arg;
112 while (txm != NULL) {
114 rte_pktmbuf_free_seg(txm);
122 ionic_dev_tx_queue_release(void *tx_queue)
124 struct ionic_qcq *txq = (struct ionic_qcq *)tx_queue;
128 ionic_lif_txq_deinit(txq);
134 ionic_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
136 struct ionic_qcq *txq;
138 IONIC_PRINT(DEBUG, "Stopping TX queue %u", tx_queue_id);
140 txq = eth_dev->data->tx_queues[tx_queue_id];
142 eth_dev->data->tx_queue_state[tx_queue_id] =
143 RTE_ETH_QUEUE_STATE_STOPPED;
146 * Note: we should better post NOP Tx desc and wait for its completion
147 * before disabling Tx queue
150 ionic_qcq_disable(txq);
152 ionic_tx_flush(&txq->cq);
158 ionic_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id,
159 uint16_t nb_desc, uint32_t socket_id,
160 const struct rte_eth_txconf *tx_conf)
162 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
163 struct ionic_qcq *txq;
167 if (tx_queue_id >= lif->ntxqcqs) {
168 IONIC_PRINT(DEBUG, "Queue index %u not available "
170 tx_queue_id, lif->ntxqcqs);
174 offloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads;
176 "Configuring skt %u TX queue %u with %u buffers, offloads %jx",
177 socket_id, tx_queue_id, nb_desc, offloads);
179 /* Validate number of receive descriptors */
180 if (!rte_is_power_of_2(nb_desc) || nb_desc < IONIC_MIN_RING_DESC)
181 return -EINVAL; /* or use IONIC_DEFAULT_RING_DESC */
183 /* Free memory prior to re-allocation if needed... */
184 if (eth_dev->data->tx_queues[tx_queue_id] != NULL) {
185 void *tx_queue = eth_dev->data->tx_queues[tx_queue_id];
186 ionic_dev_tx_queue_release(tx_queue);
187 eth_dev->data->tx_queues[tx_queue_id] = NULL;
190 eth_dev->data->tx_queue_state[tx_queue_id] =
191 RTE_ETH_QUEUE_STATE_STOPPED;
193 err = ionic_tx_qcq_alloc(lif, tx_queue_id, nb_desc, &txq);
195 IONIC_PRINT(DEBUG, "Queue allocation failure");
199 /* Do not start queue with rte_eth_dev_start() */
200 if (tx_conf->tx_deferred_start)
201 txq->flags |= IONIC_QCQ_F_DEFERRED;
203 /* Convert the offload flags into queue flags */
204 if (offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
205 txq->flags |= IONIC_QCQ_F_CSUM_L3;
206 if (offloads & DEV_TX_OFFLOAD_TCP_CKSUM)
207 txq->flags |= IONIC_QCQ_F_CSUM_TCP;
208 if (offloads & DEV_TX_OFFLOAD_UDP_CKSUM)
209 txq->flags |= IONIC_QCQ_F_CSUM_UDP;
211 eth_dev->data->tx_queues[tx_queue_id] = txq;
217 * Start Transmit Units for specified queue.
220 ionic_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
222 uint8_t *tx_queue_state = eth_dev->data->tx_queue_state;
223 struct ionic_qcq *txq;
226 if (tx_queue_state[tx_queue_id] == RTE_ETH_QUEUE_STATE_STARTED) {
227 IONIC_PRINT(DEBUG, "TX queue %u already started",
232 txq = eth_dev->data->tx_queues[tx_queue_id];
234 IONIC_PRINT(DEBUG, "Starting TX queue %u, %u descs",
235 tx_queue_id, txq->q.num_descs);
237 if (!(txq->flags & IONIC_QCQ_F_INITED)) {
238 err = ionic_lif_txq_init(txq);
242 ionic_qcq_enable(txq);
245 tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
251 ionic_tx_tcp_pseudo_csum(struct rte_mbuf *txm)
253 struct ether_hdr *eth_hdr = rte_pktmbuf_mtod(txm, struct ether_hdr *);
254 char *l3_hdr = ((char *)eth_hdr) + txm->l2_len;
255 struct rte_tcp_hdr *tcp_hdr = (struct rte_tcp_hdr *)
256 (l3_hdr + txm->l3_len);
258 if (txm->ol_flags & PKT_TX_IP_CKSUM) {
259 struct rte_ipv4_hdr *ipv4_hdr = (struct rte_ipv4_hdr *)l3_hdr;
260 ipv4_hdr->hdr_checksum = 0;
262 tcp_hdr->cksum = rte_ipv4_udptcp_cksum(ipv4_hdr, tcp_hdr);
264 struct rte_ipv6_hdr *ipv6_hdr = (struct rte_ipv6_hdr *)l3_hdr;
266 tcp_hdr->cksum = rte_ipv6_udptcp_cksum(ipv6_hdr, tcp_hdr);
271 ionic_tx_tcp_inner_pseudo_csum(struct rte_mbuf *txm)
273 struct ether_hdr *eth_hdr = rte_pktmbuf_mtod(txm, struct ether_hdr *);
274 char *l3_hdr = ((char *)eth_hdr) + txm->outer_l2_len +
275 txm->outer_l3_len + txm->l2_len;
276 struct rte_tcp_hdr *tcp_hdr = (struct rte_tcp_hdr *)
277 (l3_hdr + txm->l3_len);
279 if (txm->ol_flags & PKT_TX_IPV4) {
280 struct rte_ipv4_hdr *ipv4_hdr = (struct rte_ipv4_hdr *)l3_hdr;
281 ipv4_hdr->hdr_checksum = 0;
283 tcp_hdr->cksum = rte_ipv4_udptcp_cksum(ipv4_hdr, tcp_hdr);
285 struct rte_ipv6_hdr *ipv6_hdr = (struct rte_ipv6_hdr *)l3_hdr;
287 tcp_hdr->cksum = rte_ipv6_udptcp_cksum(ipv6_hdr, tcp_hdr);
292 ionic_tx_tso_post(struct ionic_queue *q, struct ionic_txq_desc *desc,
293 struct rte_mbuf *txm,
294 rte_iova_t addr, uint8_t nsge, uint16_t len,
295 uint32_t hdrlen, uint32_t mss,
297 uint16_t vlan_tci, bool has_vlan,
298 bool start, bool done)
301 flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;
302 flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;
303 flags |= start ? IONIC_TXQ_DESC_FLAG_TSO_SOT : 0;
304 flags |= done ? IONIC_TXQ_DESC_FLAG_TSO_EOT : 0;
306 desc->cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_TSO,
309 desc->vlan_tci = vlan_tci;
310 desc->hdr_len = hdrlen;
313 ionic_q_post(q, done, NULL, done ? txm : NULL);
316 static struct ionic_txq_desc *
317 ionic_tx_tso_next(struct ionic_queue *q, struct ionic_txq_sg_elem **elem)
319 struct ionic_txq_desc *desc_base = q->base;
320 struct ionic_txq_sg_desc_v1 *sg_desc_base = q->sg_base;
321 struct ionic_txq_desc *desc = &desc_base[q->head_idx];
322 struct ionic_txq_sg_desc_v1 *sg_desc = &sg_desc_base[q->head_idx];
324 *elem = sg_desc->elems;
329 ionic_tx_tso(struct ionic_qcq *txq, struct rte_mbuf *txm,
332 struct ionic_queue *q = &txq->q;
333 struct ionic_tx_stats *stats = IONIC_Q_TO_TX_STATS(q);
334 struct ionic_txq_desc *desc;
335 struct ionic_txq_sg_elem *elem;
336 struct rte_mbuf *txm_seg;
337 rte_iova_t data_iova;
338 uint64_t desc_addr = 0, next_addr;
339 uint16_t desc_len = 0;
342 uint32_t mss = txm->tso_segsz;
343 uint32_t frag_left = 0;
350 bool has_vlan = !!(txm->ol_flags & PKT_TX_VLAN_PKT);
351 uint16_t vlan_tci = txm->vlan_tci;
352 uint64_t ol_flags = txm->ol_flags;
354 encap = ((ol_flags & PKT_TX_OUTER_IP_CKSUM) ||
355 (ol_flags & PKT_TX_OUTER_UDP_CKSUM)) &&
356 ((ol_flags & PKT_TX_OUTER_IPV4) ||
357 (ol_flags & PKT_TX_OUTER_IPV6));
359 /* Preload inner-most TCP csum field with IP pseudo hdr
360 * calculated with IP length set to zero. HW will later
361 * add in length to each TCP segment resulting from the TSO.
365 ionic_tx_tcp_inner_pseudo_csum(txm);
366 hdrlen = txm->outer_l2_len + txm->outer_l3_len +
367 txm->l2_len + txm->l3_len + txm->l4_len;
369 ionic_tx_tcp_pseudo_csum(txm);
370 hdrlen = txm->l2_len + txm->l3_len + txm->l4_len;
373 seglen = hdrlen + mss;
374 left = txm->data_len;
375 data_iova = rte_mbuf_data_iova(txm);
377 desc = ionic_tx_tso_next(q, &elem);
380 /* Chop data up into desc segments */
383 len = RTE_MIN(seglen, left);
384 frag_left = seglen - len;
385 desc_addr = rte_cpu_to_le_64(data_iova + offset);
390 if (txm->nb_segs > 1 && frag_left > 0)
392 done = (txm->nb_segs == 1 && left == 0);
393 ionic_tx_tso_post(q, desc, txm,
394 desc_addr, desc_nsge, desc_len,
398 start, done && not_xmit_more);
399 desc = ionic_tx_tso_next(q, &elem);
404 /* Chop frags into desc segments */
407 while (txm_seg != NULL) {
409 data_iova = rte_mbuf_data_iova(txm_seg);
410 left = txm_seg->data_len;
414 next_addr = rte_cpu_to_le_64(data_iova + offset);
416 len = RTE_MIN(frag_left, left);
418 elem->addr = next_addr;
423 len = RTE_MIN(mss, left);
424 frag_left = mss - len;
425 desc_addr = next_addr;
431 if (txm_seg->next != NULL && frag_left > 0)
434 done = (txm_seg->next == NULL && left == 0);
435 ionic_tx_tso_post(q, desc, txm_seg,
436 desc_addr, desc_nsge, desc_len,
440 start, done && not_xmit_more);
441 desc = ionic_tx_tso_next(q, &elem);
445 txm_seg = txm_seg->next;
453 static __rte_always_inline int
454 ionic_tx(struct ionic_qcq *txq, struct rte_mbuf *txm,
457 struct ionic_queue *q = &txq->q;
458 struct ionic_txq_desc *desc_base = q->base;
459 struct ionic_txq_sg_desc_v1 *sg_desc_base = q->sg_base;
460 struct ionic_txq_desc *desc = &desc_base[q->head_idx];
461 struct ionic_txq_sg_desc_v1 *sg_desc = &sg_desc_base[q->head_idx];
462 struct ionic_txq_sg_elem *elem = sg_desc->elems;
463 struct ionic_tx_stats *stats = IONIC_Q_TO_TX_STATS(q);
464 struct rte_mbuf *txm_seg;
467 uint64_t ol_flags = txm->ol_flags;
469 uint8_t opcode = IONIC_TXQ_DESC_OPCODE_CSUM_NONE;
472 if ((ol_flags & PKT_TX_IP_CKSUM) &&
473 (txq->flags & IONIC_QCQ_F_CSUM_L3)) {
474 opcode = IONIC_TXQ_DESC_OPCODE_CSUM_HW;
475 flags |= IONIC_TXQ_DESC_FLAG_CSUM_L3;
478 if (((ol_flags & PKT_TX_TCP_CKSUM) &&
479 (txq->flags & IONIC_QCQ_F_CSUM_TCP)) ||
480 ((ol_flags & PKT_TX_UDP_CKSUM) &&
481 (txq->flags & IONIC_QCQ_F_CSUM_UDP))) {
482 opcode = IONIC_TXQ_DESC_OPCODE_CSUM_HW;
483 flags |= IONIC_TXQ_DESC_FLAG_CSUM_L4;
486 if (opcode == IONIC_TXQ_DESC_OPCODE_CSUM_NONE)
489 has_vlan = (ol_flags & PKT_TX_VLAN_PKT);
490 encap = ((ol_flags & PKT_TX_OUTER_IP_CKSUM) ||
491 (ol_flags & PKT_TX_OUTER_UDP_CKSUM)) &&
492 ((ol_flags & PKT_TX_OUTER_IPV4) ||
493 (ol_flags & PKT_TX_OUTER_IPV6));
495 flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;
496 flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;
498 addr = rte_cpu_to_le_64(rte_mbuf_data_iova(txm));
500 desc->cmd = encode_txq_desc_cmd(opcode, flags, txm->nb_segs - 1, addr);
501 desc->len = txm->data_len;
502 desc->vlan_tci = txm->vlan_tci;
505 while (txm_seg != NULL) {
506 elem->len = txm_seg->data_len;
507 elem->addr = rte_cpu_to_le_64(rte_mbuf_data_iova(txm_seg));
510 txm_seg = txm_seg->next;
513 ionic_q_post(q, not_xmit_more, NULL, txm);
519 ionic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
522 struct ionic_qcq *txq = (struct ionic_qcq *)tx_queue;
523 struct ionic_queue *q = &txq->q;
524 struct ionic_cq *cq = &txq->cq;
525 struct ionic_tx_stats *stats = IONIC_Q_TO_TX_STATS(q);
526 uint32_t next_q_head_idx;
527 uint32_t bytes_tx = 0;
532 /* Cleaning old buffers */
535 if (unlikely(ionic_q_space_avail(q) < nb_pkts)) {
536 stats->stop += nb_pkts;
540 while (nb_tx < nb_pkts) {
541 last = (nb_tx == (nb_pkts - 1));
543 next_q_head_idx = (q->head_idx + 1) & (q->num_descs - 1);
544 if ((next_q_head_idx & 0x3) == 0) {
545 struct ionic_txq_desc *desc_base = q->base;
546 rte_prefetch0(&desc_base[next_q_head_idx]);
547 rte_prefetch0(&q->info[next_q_head_idx]);
550 if (tx_pkts[nb_tx]->ol_flags & PKT_TX_TCP_SEG)
551 err = ionic_tx_tso(txq, tx_pkts[nb_tx], last);
553 err = ionic_tx(txq, tx_pkts[nb_tx], last);
555 stats->drop += nb_pkts - nb_tx;
561 bytes_tx += tx_pkts[nb_tx]->pkt_len;
565 stats->packets += nb_tx;
566 stats->bytes += bytes_tx;
571 /*********************************************************************
575 **********************************************************************/
577 #define IONIC_TX_OFFLOAD_MASK ( \
585 #define IONIC_TX_OFFLOAD_NOTSUP_MASK \
586 (PKT_TX_OFFLOAD_MASK ^ IONIC_TX_OFFLOAD_MASK)
589 ionic_prep_pkts(void *tx_queue __rte_unused, struct rte_mbuf **tx_pkts,
592 struct rte_mbuf *txm;
596 for (i = 0; i < nb_pkts; i++) {
599 if (txm->nb_segs > IONIC_TX_MAX_SG_ELEMS) {
604 offloads = txm->ol_flags;
606 if (offloads & IONIC_TX_OFFLOAD_NOTSUP_MASK) {
607 rte_errno = -ENOTSUP;
615 /*********************************************************************
619 **********************************************************************/
621 static void ionic_rx_recycle(struct ionic_queue *q, uint32_t q_desc_index,
622 struct rte_mbuf *mbuf);
625 ionic_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
626 struct rte_eth_rxq_info *qinfo)
628 struct ionic_qcq *rxq = dev->data->rx_queues[queue_id];
629 struct ionic_queue *q = &rxq->q;
631 qinfo->mp = rxq->mb_pool;
632 qinfo->scattered_rx = dev->data->scattered_rx;
633 qinfo->nb_desc = q->num_descs;
634 qinfo->conf.rx_deferred_start = rxq->flags & IONIC_QCQ_F_DEFERRED;
635 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
638 static void __rte_cold
639 ionic_rx_empty(struct ionic_queue *q)
641 struct ionic_qcq *rxq = IONIC_Q_TO_QCQ(q);
642 struct ionic_desc_info *cur;
643 struct rte_mbuf *mbuf;
645 while (q->tail_idx != q->head_idx) {
646 cur = &q->info[q->tail_idx];
648 rte_mempool_put(rxq->mb_pool, mbuf);
650 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1);
655 ionic_dev_rx_queue_release(void *rx_queue)
657 struct ionic_qcq *rxq = (struct ionic_qcq *)rx_queue;
661 ionic_rx_empty(&rxq->q);
663 ionic_lif_rxq_deinit(rxq);
669 ionic_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
670 uint16_t rx_queue_id,
673 const struct rte_eth_rxconf *rx_conf,
674 struct rte_mempool *mp)
676 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
677 struct ionic_qcq *rxq;
681 if (rx_queue_id >= lif->nrxqcqs) {
683 "Queue index %u not available (max %u queues)",
684 rx_queue_id, lif->nrxqcqs);
688 offloads = rx_conf->offloads | eth_dev->data->dev_conf.rxmode.offloads;
690 "Configuring skt %u RX queue %u with %u buffers, offloads %jx",
691 socket_id, rx_queue_id, nb_desc, offloads);
693 if (!rx_conf->rx_drop_en)
694 IONIC_PRINT(WARNING, "No-drop mode is not supported");
696 /* Validate number of receive descriptors */
697 if (!rte_is_power_of_2(nb_desc) ||
698 nb_desc < IONIC_MIN_RING_DESC ||
699 nb_desc > IONIC_MAX_RING_DESC) {
701 "Bad descriptor count (%u) for queue %u (min: %u)",
702 nb_desc, rx_queue_id, IONIC_MIN_RING_DESC);
703 return -EINVAL; /* or use IONIC_DEFAULT_RING_DESC */
706 /* Free memory prior to re-allocation if needed... */
707 if (eth_dev->data->rx_queues[rx_queue_id] != NULL) {
708 void *rx_queue = eth_dev->data->rx_queues[rx_queue_id];
709 ionic_dev_rx_queue_release(rx_queue);
710 eth_dev->data->rx_queues[rx_queue_id] = NULL;
713 eth_dev->data->rx_queue_state[rx_queue_id] =
714 RTE_ETH_QUEUE_STATE_STOPPED;
716 err = ionic_rx_qcq_alloc(lif, rx_queue_id, nb_desc, &rxq);
718 IONIC_PRINT(ERR, "Queue %d allocation failure", rx_queue_id);
725 * Note: the interface does not currently support
726 * DEV_RX_OFFLOAD_KEEP_CRC, please also consider ETHER_CRC_LEN
727 * when the adapter will be able to keep the CRC and subtract
728 * it to the length for all received packets:
729 * if (eth_dev->data->dev_conf.rxmode.offloads &
730 * DEV_RX_OFFLOAD_KEEP_CRC)
731 * rxq->crc_len = ETHER_CRC_LEN;
734 /* Do not start queue with rte_eth_dev_start() */
735 if (rx_conf->rx_deferred_start)
736 rxq->flags |= IONIC_QCQ_F_DEFERRED;
738 eth_dev->data->rx_queues[rx_queue_id] = rxq;
743 static __rte_always_inline void
744 ionic_rx_clean(struct ionic_queue *q,
745 uint32_t q_desc_index, uint32_t cq_desc_index,
746 void *cb_arg, void *service_cb_arg)
748 struct ionic_rxq_comp *cq_desc_base = q->bound_cq->base;
749 struct ionic_rxq_comp *cq_desc = &cq_desc_base[cq_desc_index];
750 struct rte_mbuf *rxm = cb_arg;
751 struct rte_mbuf *rxm_seg;
752 struct ionic_qcq *rxq = IONIC_Q_TO_QCQ(q);
753 uint32_t max_frame_size =
754 rxq->lif->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
755 uint64_t pkt_flags = 0;
757 struct ionic_rx_stats *stats = IONIC_Q_TO_RX_STATS(q);
758 struct ionic_rx_service *recv_args = (struct ionic_rx_service *)
760 uint32_t buf_size = (uint16_t)
761 (rte_pktmbuf_data_room_size(rxq->mb_pool) -
762 RTE_PKTMBUF_HEADROOM);
768 rte_pktmbuf_free(rxm);
770 * Note: rte_mempool_put is faster with no segs
771 * rte_mempool_put(rxq->mb_pool, rxm);
776 if (cq_desc->status) {
777 stats->bad_cq_status++;
778 ionic_rx_recycle(q, q_desc_index, rxm);
782 if (recv_args->nb_rx >= recv_args->nb_pkts) {
784 ionic_rx_recycle(q, q_desc_index, rxm);
788 if (cq_desc->len > max_frame_size ||
791 ionic_rx_recycle(q, q_desc_index, rxm);
795 rxm->data_off = RTE_PKTMBUF_HEADROOM;
796 rte_prefetch1((char *)rxm->buf_addr + rxm->data_off);
797 rxm->nb_segs = 1; /* cq_desc->num_sg_elems */
798 rxm->pkt_len = cq_desc->len;
799 rxm->port = rxq->lif->port_id;
803 rxm->data_len = RTE_MIN(buf_size, left);
804 left -= rxm->data_len;
807 while (rxm_seg && left) {
808 rxm_seg->data_len = RTE_MIN(buf_size, left);
809 left -= rxm_seg->data_len;
811 rxm_seg = rxm_seg->next;
816 pkt_flags |= PKT_RX_RSS_HASH;
817 rxm->hash.rss = cq_desc->rss_hash;
820 if (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_VLAN) {
821 pkt_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
822 rxm->vlan_tci = cq_desc->vlan_tci;
826 if (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_CALC) {
827 if (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_IP_OK)
828 pkt_flags |= PKT_RX_IP_CKSUM_GOOD;
829 else if (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_IP_BAD)
830 pkt_flags |= PKT_RX_IP_CKSUM_BAD;
832 if ((cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_TCP_OK) ||
833 (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_UDP_OK))
834 pkt_flags |= PKT_RX_L4_CKSUM_GOOD;
835 else if ((cq_desc->csum_flags &
836 IONIC_RXQ_COMP_CSUM_F_TCP_BAD) ||
837 (cq_desc->csum_flags &
838 IONIC_RXQ_COMP_CSUM_F_UDP_BAD))
839 pkt_flags |= PKT_RX_L4_CKSUM_BAD;
842 rxm->ol_flags = pkt_flags;
845 switch (cq_desc->pkt_type_color & IONIC_RXQ_COMP_PKT_TYPE_MASK) {
846 case IONIC_PKT_TYPE_IPV4:
847 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4;
849 case IONIC_PKT_TYPE_IPV6:
850 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6;
852 case IONIC_PKT_TYPE_IPV4_TCP:
853 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4 |
856 case IONIC_PKT_TYPE_IPV6_TCP:
857 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6 |
860 case IONIC_PKT_TYPE_IPV4_UDP:
861 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4 |
864 case IONIC_PKT_TYPE_IPV6_UDP:
865 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6 |
870 struct rte_ether_hdr *eth_h = rte_pktmbuf_mtod(rxm,
871 struct rte_ether_hdr *);
872 uint16_t ether_type = eth_h->ether_type;
873 if (ether_type == rte_cpu_to_be_16(RTE_ETHER_TYPE_ARP))
874 pkt_type = RTE_PTYPE_L2_ETHER_ARP;
876 pkt_type = RTE_PTYPE_UNKNOWN;
881 rxm->packet_type = pkt_type;
883 recv_args->rx_pkts[recv_args->nb_rx] = rxm;
887 stats->bytes += rxm->pkt_len;
891 ionic_rx_recycle(struct ionic_queue *q, uint32_t q_desc_index,
892 struct rte_mbuf *mbuf)
894 struct ionic_rxq_desc *desc_base = q->base;
895 struct ionic_rxq_desc *old = &desc_base[q_desc_index];
896 struct ionic_rxq_desc *new = &desc_base[q->head_idx];
898 new->addr = old->addr;
901 ionic_q_post(q, true, ionic_rx_clean, mbuf);
904 static __rte_always_inline int
905 ionic_rx_fill(struct ionic_qcq *rxq, uint32_t len)
907 struct ionic_queue *q = &rxq->q;
908 struct ionic_rxq_desc *desc_base = q->base;
909 struct ionic_rxq_sg_desc *sg_desc_base = q->sg_base;
910 struct ionic_rxq_desc *desc;
911 struct ionic_rxq_sg_desc *sg_desc;
912 struct ionic_rxq_sg_elem *elem;
914 uint32_t i, j, nsegs, buf_size, size;
917 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
918 RTE_PKTMBUF_HEADROOM);
920 /* Initialize software ring entries */
921 for (i = ionic_q_space_avail(q); i; i--) {
922 struct rte_mbuf *rxm = rte_mbuf_raw_alloc(rxq->mb_pool);
923 struct rte_mbuf *prev_rxm_seg;
926 IONIC_PRINT(ERR, "RX mbuf alloc failed");
930 nsegs = (len + buf_size - 1) / buf_size;
932 desc = &desc_base[q->head_idx];
933 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(rxm));
934 desc->addr = dma_addr;
935 desc->len = buf_size;
937 desc->opcode = (nsegs > 1) ? IONIC_RXQ_DESC_OPCODE_SG :
938 IONIC_RXQ_DESC_OPCODE_SIMPLE;
942 sg_desc = &sg_desc_base[q->head_idx];
943 elem = sg_desc->elems;
944 for (j = 0; j < nsegs - 1 && j < IONIC_RX_MAX_SG_ELEMS; j++) {
945 struct rte_mbuf *rxm_seg;
946 rte_iova_t data_iova;
948 rxm_seg = rte_mbuf_raw_alloc(rxq->mb_pool);
949 if (rxm_seg == NULL) {
950 IONIC_PRINT(ERR, "RX mbuf alloc failed");
954 data_iova = rte_mbuf_data_iova(rxm_seg);
955 dma_addr = rte_cpu_to_le_64(data_iova);
956 elem->addr = dma_addr;
957 elem->len = buf_size;
960 rxm_seg->next = NULL;
961 prev_rxm_seg->next = rxm_seg;
962 prev_rxm_seg = rxm_seg;
966 IONIC_PRINT(ERR, "Rx SG size is not sufficient (%d < %d)",
969 ring_doorbell = ((q->head_idx + 1) &
970 IONIC_RX_RING_DOORBELL_STRIDE) == 0;
972 ionic_q_post(q, ring_doorbell, ionic_rx_clean, rxm);
979 * Start Receive Units for specified queue.
982 ionic_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
984 uint32_t frame_size = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
985 uint8_t *rx_queue_state = eth_dev->data->rx_queue_state;
986 struct ionic_qcq *rxq;
989 if (rx_queue_state[rx_queue_id] == RTE_ETH_QUEUE_STATE_STARTED) {
990 IONIC_PRINT(DEBUG, "RX queue %u already started",
995 rxq = eth_dev->data->rx_queues[rx_queue_id];
997 IONIC_PRINT(DEBUG, "Starting RX queue %u, %u descs (size: %u)",
998 rx_queue_id, rxq->q.num_descs, frame_size);
1000 if (!(rxq->flags & IONIC_QCQ_F_INITED)) {
1001 err = ionic_lif_rxq_init(rxq);
1005 ionic_qcq_enable(rxq);
1008 /* Allocate buffers for descriptor rings */
1009 if (ionic_rx_fill(rxq, frame_size) != 0) {
1010 IONIC_PRINT(ERR, "Could not alloc mbuf for queue:%d",
1015 rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1020 static __rte_always_inline void
1021 ionic_rxq_service(struct ionic_cq *cq, uint32_t work_to_do,
1022 void *service_cb_arg)
1024 struct ionic_queue *q = cq->bound_q;
1025 struct ionic_desc_info *q_desc_info;
1026 struct ionic_rxq_comp *cq_desc_base = cq->base;
1027 struct ionic_rxq_comp *cq_desc;
1029 uint32_t curr_q_tail_idx, curr_cq_tail_idx;
1030 uint32_t work_done = 0;
1032 if (work_to_do == 0)
1035 cq_desc = &cq_desc_base[cq->tail_idx];
1036 while (color_match(cq_desc->pkt_type_color, cq->done_color)) {
1037 curr_cq_tail_idx = cq->tail_idx;
1038 cq->tail_idx = (cq->tail_idx + 1) & (cq->num_descs - 1);
1040 if (cq->tail_idx == 0)
1041 cq->done_color = !cq->done_color;
1043 /* Prefetch the next 4 descriptors */
1044 if ((cq->tail_idx & 0x3) == 0)
1045 rte_prefetch0(&cq_desc_base[cq->tail_idx]);
1048 more = (q->tail_idx != cq_desc->comp_index);
1050 q_desc_info = &q->info[q->tail_idx];
1052 curr_q_tail_idx = q->tail_idx;
1053 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1);
1055 /* Prefetch the next 4 descriptors */
1056 if ((q->tail_idx & 0x3) == 0)
1058 rte_prefetch0(&q->info[q->tail_idx]);
1060 ionic_rx_clean(q, curr_q_tail_idx, curr_cq_tail_idx,
1061 q_desc_info->cb_arg, service_cb_arg);
1065 if (++work_done == work_to_do)
1068 cq_desc = &cq_desc_base[cq->tail_idx];
1073 * Stop Receive Units for specified queue.
1076 ionic_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
1078 struct ionic_qcq *rxq;
1080 IONIC_PRINT(DEBUG, "Stopping RX queue %u", rx_queue_id);
1082 rxq = eth_dev->data->rx_queues[rx_queue_id];
1084 eth_dev->data->rx_queue_state[rx_queue_id] =
1085 RTE_ETH_QUEUE_STATE_STOPPED;
1087 ionic_qcq_disable(rxq);
1090 ionic_rxq_service(&rxq->cq, -1, NULL);
1096 ionic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1099 struct ionic_qcq *rxq = (struct ionic_qcq *)rx_queue;
1100 uint32_t frame_size =
1101 rxq->lif->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
1102 struct ionic_cq *cq = &rxq->cq;
1103 struct ionic_rx_service service_cb_arg;
1105 service_cb_arg.rx_pkts = rx_pkts;
1106 service_cb_arg.nb_pkts = nb_pkts;
1107 service_cb_arg.nb_rx = 0;
1109 ionic_rxq_service(cq, nb_pkts, &service_cb_arg);
1111 ionic_rx_fill(rxq, frame_size);
1113 return service_cb_arg.nb_rx;