1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
15 #include <rte_byteorder.h>
16 #include <rte_common.h>
17 #include <rte_cycles.h>
19 #include <rte_debug.h>
20 #include <rte_interrupts.h>
22 #include <rte_memory.h>
23 #include <rte_memzone.h>
24 #include <rte_launch.h>
26 #include <rte_per_lcore.h>
27 #include <rte_lcore.h>
28 #include <rte_atomic.h>
29 #include <rte_branch_prediction.h>
30 #include <rte_mempool.h>
31 #include <rte_malloc.h>
33 #include <rte_ether.h>
34 #include <ethdev_driver.h>
35 #include <rte_prefetch.h>
39 #include <rte_string_fns.h>
40 #include <rte_errno.h>
44 #include "ionic_logs.h"
45 #include "ionic_mac_api.h"
46 #include "ionic_ethdev.h"
47 #include "ionic_lif.h"
48 #include "ionic_rxtx.h"
50 #define IONIC_RX_RING_DOORBELL_STRIDE (32 - 1)
52 /*********************************************************************
56 **********************************************************************/
59 ionic_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
60 struct rte_eth_txq_info *qinfo)
62 struct ionic_qcq *txq = dev->data->tx_queues[queue_id];
63 struct ionic_queue *q = &txq->q;
65 qinfo->nb_desc = q->num_descs;
66 qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads;
67 qinfo->conf.tx_deferred_start = txq->flags & IONIC_QCQ_F_DEFERRED;
70 static __rte_always_inline void
71 ionic_tx_flush(struct ionic_qcq *txq)
73 struct ionic_cq *cq = &txq->cq;
74 struct ionic_queue *q = &txq->q;
75 struct rte_mbuf *txm, *next;
76 struct ionic_txq_comp *cq_desc_base = cq->base;
77 struct ionic_txq_comp *cq_desc;
79 u_int32_t comp_index = (u_int32_t)-1;
81 cq_desc = &cq_desc_base[cq->tail_idx];
82 while (color_match(cq_desc->color, cq->done_color)) {
83 cq->tail_idx = Q_NEXT_TO_SRVC(cq, 1);
85 /* Prefetch the next 4 descriptors (not really useful here) */
86 if ((cq->tail_idx & 0x3) == 0)
87 rte_prefetch0(&cq_desc_base[cq->tail_idx]);
89 if (cq->tail_idx == 0)
90 cq->done_color = !cq->done_color;
92 comp_index = cq_desc->comp_index;
94 cq_desc = &cq_desc_base[cq->tail_idx];
97 if (comp_index != (u_int32_t)-1) {
98 while (q->tail_idx != comp_index) {
99 info = IONIC_INFO_PTR(q, q->tail_idx);
101 q->tail_idx = Q_NEXT_TO_SRVC(q, 1);
103 /* Prefetch the next 4 descriptors */
104 if ((q->tail_idx & 0x3) == 0)
106 rte_prefetch0(&q->info[q->tail_idx]);
109 * Note: you can just use rte_pktmbuf_free,
110 * but this loop is faster
113 while (txm != NULL) {
115 rte_pktmbuf_free_seg(txm);
123 ionic_dev_tx_queue_release(void *tx_queue)
125 struct ionic_qcq *txq = (struct ionic_qcq *)tx_queue;
129 ionic_lif_txq_deinit(txq);
135 ionic_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
137 struct ionic_qcq *txq;
139 IONIC_PRINT(DEBUG, "Stopping TX queue %u", tx_queue_id);
141 txq = eth_dev->data->tx_queues[tx_queue_id];
143 eth_dev->data->tx_queue_state[tx_queue_id] =
144 RTE_ETH_QUEUE_STATE_STOPPED;
147 * Note: we should better post NOP Tx desc and wait for its completion
148 * before disabling Tx queue
151 ionic_qcq_disable(txq);
159 ionic_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id,
160 uint16_t nb_desc, uint32_t socket_id,
161 const struct rte_eth_txconf *tx_conf)
163 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
164 struct ionic_qcq *txq;
168 if (tx_queue_id >= lif->ntxqcqs) {
169 IONIC_PRINT(DEBUG, "Queue index %u not available "
171 tx_queue_id, lif->ntxqcqs);
175 offloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads;
177 "Configuring skt %u TX queue %u with %u buffers, offloads %jx",
178 socket_id, tx_queue_id, nb_desc, offloads);
180 /* Validate number of receive descriptors */
181 if (!rte_is_power_of_2(nb_desc) || nb_desc < IONIC_MIN_RING_DESC)
182 return -EINVAL; /* or use IONIC_DEFAULT_RING_DESC */
184 /* Free memory prior to re-allocation if needed... */
185 if (eth_dev->data->tx_queues[tx_queue_id] != NULL) {
186 void *tx_queue = eth_dev->data->tx_queues[tx_queue_id];
187 ionic_dev_tx_queue_release(tx_queue);
188 eth_dev->data->tx_queues[tx_queue_id] = NULL;
191 eth_dev->data->tx_queue_state[tx_queue_id] =
192 RTE_ETH_QUEUE_STATE_STOPPED;
194 err = ionic_tx_qcq_alloc(lif, tx_queue_id, nb_desc, &txq);
196 IONIC_PRINT(DEBUG, "Queue allocation failure");
200 /* Do not start queue with rte_eth_dev_start() */
201 if (tx_conf->tx_deferred_start)
202 txq->flags |= IONIC_QCQ_F_DEFERRED;
204 /* Convert the offload flags into queue flags */
205 if (offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
206 txq->flags |= IONIC_QCQ_F_CSUM_L3;
207 if (offloads & DEV_TX_OFFLOAD_TCP_CKSUM)
208 txq->flags |= IONIC_QCQ_F_CSUM_TCP;
209 if (offloads & DEV_TX_OFFLOAD_UDP_CKSUM)
210 txq->flags |= IONIC_QCQ_F_CSUM_UDP;
212 eth_dev->data->tx_queues[tx_queue_id] = txq;
218 * Start Transmit Units for specified queue.
221 ionic_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
223 uint8_t *tx_queue_state = eth_dev->data->tx_queue_state;
224 struct ionic_qcq *txq;
227 if (tx_queue_state[tx_queue_id] == RTE_ETH_QUEUE_STATE_STARTED) {
228 IONIC_PRINT(DEBUG, "TX queue %u already started",
233 txq = eth_dev->data->tx_queues[tx_queue_id];
235 IONIC_PRINT(DEBUG, "Starting TX queue %u, %u descs",
236 tx_queue_id, txq->q.num_descs);
238 if (!(txq->flags & IONIC_QCQ_F_INITED)) {
239 err = ionic_lif_txq_init(txq);
243 ionic_qcq_enable(txq);
246 tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
252 ionic_tx_tcp_pseudo_csum(struct rte_mbuf *txm)
254 struct ether_hdr *eth_hdr = rte_pktmbuf_mtod(txm, struct ether_hdr *);
255 char *l3_hdr = ((char *)eth_hdr) + txm->l2_len;
256 struct rte_tcp_hdr *tcp_hdr = (struct rte_tcp_hdr *)
257 (l3_hdr + txm->l3_len);
259 if (txm->ol_flags & PKT_TX_IP_CKSUM) {
260 struct rte_ipv4_hdr *ipv4_hdr = (struct rte_ipv4_hdr *)l3_hdr;
261 ipv4_hdr->hdr_checksum = 0;
263 tcp_hdr->cksum = rte_ipv4_udptcp_cksum(ipv4_hdr, tcp_hdr);
265 struct rte_ipv6_hdr *ipv6_hdr = (struct rte_ipv6_hdr *)l3_hdr;
267 tcp_hdr->cksum = rte_ipv6_udptcp_cksum(ipv6_hdr, tcp_hdr);
272 ionic_tx_tcp_inner_pseudo_csum(struct rte_mbuf *txm)
274 struct ether_hdr *eth_hdr = rte_pktmbuf_mtod(txm, struct ether_hdr *);
275 char *l3_hdr = ((char *)eth_hdr) + txm->outer_l2_len +
276 txm->outer_l3_len + txm->l2_len;
277 struct rte_tcp_hdr *tcp_hdr = (struct rte_tcp_hdr *)
278 (l3_hdr + txm->l3_len);
280 if (txm->ol_flags & PKT_TX_IPV4) {
281 struct rte_ipv4_hdr *ipv4_hdr = (struct rte_ipv4_hdr *)l3_hdr;
282 ipv4_hdr->hdr_checksum = 0;
284 tcp_hdr->cksum = rte_ipv4_udptcp_cksum(ipv4_hdr, tcp_hdr);
286 struct rte_ipv6_hdr *ipv6_hdr = (struct rte_ipv6_hdr *)l3_hdr;
288 tcp_hdr->cksum = rte_ipv6_udptcp_cksum(ipv6_hdr, tcp_hdr);
293 ionic_tx_tso_post(struct ionic_queue *q, struct ionic_txq_desc *desc,
294 struct rte_mbuf *txm,
295 rte_iova_t addr, uint8_t nsge, uint16_t len,
296 uint32_t hdrlen, uint32_t mss,
298 uint16_t vlan_tci, bool has_vlan,
299 bool start, bool done)
302 flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;
303 flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;
304 flags |= start ? IONIC_TXQ_DESC_FLAG_TSO_SOT : 0;
305 flags |= done ? IONIC_TXQ_DESC_FLAG_TSO_EOT : 0;
307 desc->cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_TSO,
310 desc->vlan_tci = vlan_tci;
311 desc->hdr_len = hdrlen;
314 ionic_q_post(q, done, done ? txm : NULL);
317 static struct ionic_txq_desc *
318 ionic_tx_tso_next(struct ionic_queue *q, struct ionic_txq_sg_elem **elem)
320 struct ionic_txq_desc *desc_base = q->base;
321 struct ionic_txq_sg_desc_v1 *sg_desc_base = q->sg_base;
322 struct ionic_txq_desc *desc = &desc_base[q->head_idx];
323 struct ionic_txq_sg_desc_v1 *sg_desc = &sg_desc_base[q->head_idx];
325 *elem = sg_desc->elems;
330 ionic_tx_tso(struct ionic_qcq *txq, struct rte_mbuf *txm,
333 struct ionic_queue *q = &txq->q;
334 struct ionic_tx_stats *stats = IONIC_Q_TO_TX_STATS(q);
335 struct ionic_txq_desc *desc;
336 struct ionic_txq_sg_elem *elem;
337 struct rte_mbuf *txm_seg;
338 rte_iova_t data_iova;
339 uint64_t desc_addr = 0, next_addr;
340 uint16_t desc_len = 0;
343 uint32_t mss = txm->tso_segsz;
344 uint32_t frag_left = 0;
351 bool has_vlan = !!(txm->ol_flags & PKT_TX_VLAN_PKT);
352 uint16_t vlan_tci = txm->vlan_tci;
353 uint64_t ol_flags = txm->ol_flags;
355 encap = ((ol_flags & PKT_TX_OUTER_IP_CKSUM) ||
356 (ol_flags & PKT_TX_OUTER_UDP_CKSUM)) &&
357 ((ol_flags & PKT_TX_OUTER_IPV4) ||
358 (ol_flags & PKT_TX_OUTER_IPV6));
360 /* Preload inner-most TCP csum field with IP pseudo hdr
361 * calculated with IP length set to zero. HW will later
362 * add in length to each TCP segment resulting from the TSO.
366 ionic_tx_tcp_inner_pseudo_csum(txm);
367 hdrlen = txm->outer_l2_len + txm->outer_l3_len +
368 txm->l2_len + txm->l3_len + txm->l4_len;
370 ionic_tx_tcp_pseudo_csum(txm);
371 hdrlen = txm->l2_len + txm->l3_len + txm->l4_len;
374 seglen = hdrlen + mss;
375 left = txm->data_len;
376 data_iova = rte_mbuf_data_iova(txm);
378 desc = ionic_tx_tso_next(q, &elem);
381 /* Chop data up into desc segments */
384 len = RTE_MIN(seglen, left);
385 frag_left = seglen - len;
386 desc_addr = rte_cpu_to_le_64(data_iova + offset);
391 if (txm->nb_segs > 1 && frag_left > 0)
393 done = (txm->nb_segs == 1 && left == 0);
394 ionic_tx_tso_post(q, desc, txm,
395 desc_addr, desc_nsge, desc_len,
399 start, done && not_xmit_more);
400 desc = ionic_tx_tso_next(q, &elem);
405 /* Chop frags into desc segments */
408 while (txm_seg != NULL) {
410 data_iova = rte_mbuf_data_iova(txm_seg);
411 left = txm_seg->data_len;
415 next_addr = rte_cpu_to_le_64(data_iova + offset);
417 len = RTE_MIN(frag_left, left);
419 elem->addr = next_addr;
424 len = RTE_MIN(mss, left);
425 frag_left = mss - len;
426 desc_addr = next_addr;
432 if (txm_seg->next != NULL && frag_left > 0)
435 done = (txm_seg->next == NULL && left == 0);
436 ionic_tx_tso_post(q, desc, txm_seg,
437 desc_addr, desc_nsge, desc_len,
441 start, done && not_xmit_more);
442 desc = ionic_tx_tso_next(q, &elem);
446 txm_seg = txm_seg->next;
454 static __rte_always_inline int
455 ionic_tx(struct ionic_qcq *txq, struct rte_mbuf *txm,
458 struct ionic_queue *q = &txq->q;
459 struct ionic_txq_desc *desc_base = q->base;
460 struct ionic_txq_sg_desc_v1 *sg_desc_base = q->sg_base;
461 struct ionic_txq_desc *desc = &desc_base[q->head_idx];
462 struct ionic_txq_sg_desc_v1 *sg_desc = &sg_desc_base[q->head_idx];
463 struct ionic_txq_sg_elem *elem = sg_desc->elems;
464 struct ionic_tx_stats *stats = IONIC_Q_TO_TX_STATS(q);
465 struct rte_mbuf *txm_seg;
468 uint64_t ol_flags = txm->ol_flags;
470 uint8_t opcode = IONIC_TXQ_DESC_OPCODE_CSUM_NONE;
473 if ((ol_flags & PKT_TX_IP_CKSUM) &&
474 (txq->flags & IONIC_QCQ_F_CSUM_L3)) {
475 opcode = IONIC_TXQ_DESC_OPCODE_CSUM_HW;
476 flags |= IONIC_TXQ_DESC_FLAG_CSUM_L3;
479 if (((ol_flags & PKT_TX_TCP_CKSUM) &&
480 (txq->flags & IONIC_QCQ_F_CSUM_TCP)) ||
481 ((ol_flags & PKT_TX_UDP_CKSUM) &&
482 (txq->flags & IONIC_QCQ_F_CSUM_UDP))) {
483 opcode = IONIC_TXQ_DESC_OPCODE_CSUM_HW;
484 flags |= IONIC_TXQ_DESC_FLAG_CSUM_L4;
487 if (opcode == IONIC_TXQ_DESC_OPCODE_CSUM_NONE)
490 has_vlan = (ol_flags & PKT_TX_VLAN_PKT);
491 encap = ((ol_flags & PKT_TX_OUTER_IP_CKSUM) ||
492 (ol_flags & PKT_TX_OUTER_UDP_CKSUM)) &&
493 ((ol_flags & PKT_TX_OUTER_IPV4) ||
494 (ol_flags & PKT_TX_OUTER_IPV6));
496 flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;
497 flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;
499 addr = rte_cpu_to_le_64(rte_mbuf_data_iova(txm));
501 desc->cmd = encode_txq_desc_cmd(opcode, flags, txm->nb_segs - 1, addr);
502 desc->len = txm->data_len;
503 desc->vlan_tci = txm->vlan_tci;
506 while (txm_seg != NULL) {
507 elem->len = txm_seg->data_len;
508 elem->addr = rte_cpu_to_le_64(rte_mbuf_data_iova(txm_seg));
511 txm_seg = txm_seg->next;
514 ionic_q_post(q, not_xmit_more, txm);
520 ionic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
523 struct ionic_qcq *txq = (struct ionic_qcq *)tx_queue;
524 struct ionic_queue *q = &txq->q;
525 struct ionic_tx_stats *stats = IONIC_Q_TO_TX_STATS(q);
526 uint32_t next_q_head_idx;
527 uint32_t bytes_tx = 0;
532 /* Cleaning old buffers */
535 if (unlikely(ionic_q_space_avail(q) < nb_pkts)) {
536 stats->stop += nb_pkts;
540 while (nb_tx < nb_pkts) {
541 last = (nb_tx == (nb_pkts - 1));
543 next_q_head_idx = Q_NEXT_TO_POST(q, 1);
544 if ((next_q_head_idx & 0x3) == 0) {
545 struct ionic_txq_desc *desc_base = q->base;
546 rte_prefetch0(&desc_base[next_q_head_idx]);
547 rte_prefetch0(&q->info[next_q_head_idx]);
550 if (tx_pkts[nb_tx]->ol_flags & PKT_TX_TCP_SEG)
551 err = ionic_tx_tso(txq, tx_pkts[nb_tx], last);
553 err = ionic_tx(txq, tx_pkts[nb_tx], last);
555 stats->drop += nb_pkts - nb_tx;
561 bytes_tx += tx_pkts[nb_tx]->pkt_len;
565 stats->packets += nb_tx;
566 stats->bytes += bytes_tx;
571 /*********************************************************************
575 **********************************************************************/
577 #define IONIC_TX_OFFLOAD_MASK ( \
585 #define IONIC_TX_OFFLOAD_NOTSUP_MASK \
586 (PKT_TX_OFFLOAD_MASK ^ IONIC_TX_OFFLOAD_MASK)
589 ionic_prep_pkts(void *tx_queue __rte_unused, struct rte_mbuf **tx_pkts,
592 struct rte_mbuf *txm;
596 for (i = 0; i < nb_pkts; i++) {
599 if (txm->nb_segs > IONIC_TX_MAX_SG_ELEMS_V1 + 1) {
604 offloads = txm->ol_flags;
606 if (offloads & IONIC_TX_OFFLOAD_NOTSUP_MASK) {
607 rte_errno = -ENOTSUP;
615 /*********************************************************************
619 **********************************************************************/
621 static void ionic_rx_recycle(struct ionic_queue *q, uint32_t q_desc_index,
622 struct rte_mbuf *mbuf);
625 ionic_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
626 struct rte_eth_rxq_info *qinfo)
628 struct ionic_qcq *rxq = dev->data->rx_queues[queue_id];
629 struct ionic_queue *q = &rxq->q;
631 qinfo->mp = rxq->mb_pool;
632 qinfo->scattered_rx = dev->data->scattered_rx;
633 qinfo->nb_desc = q->num_descs;
634 qinfo->conf.rx_deferred_start = rxq->flags & IONIC_QCQ_F_DEFERRED;
635 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
638 static void __rte_cold
639 ionic_rx_empty(struct ionic_queue *q)
641 struct ionic_qcq *rxq = IONIC_Q_TO_QCQ(q);
642 struct rte_mbuf *mbuf;
645 while (q->tail_idx != q->head_idx) {
646 info = IONIC_INFO_PTR(q, q->tail_idx);
648 rte_mempool_put(rxq->mb_pool, mbuf);
650 q->tail_idx = Q_NEXT_TO_SRVC(q, 1);
655 ionic_dev_rx_queue_release(void *rx_queue)
657 struct ionic_qcq *rxq = (struct ionic_qcq *)rx_queue;
661 ionic_rx_empty(&rxq->q);
663 ionic_lif_rxq_deinit(rxq);
669 ionic_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
670 uint16_t rx_queue_id,
673 const struct rte_eth_rxconf *rx_conf,
674 struct rte_mempool *mp)
676 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
677 struct ionic_qcq *rxq;
681 if (rx_queue_id >= lif->nrxqcqs) {
683 "Queue index %u not available (max %u queues)",
684 rx_queue_id, lif->nrxqcqs);
688 offloads = rx_conf->offloads | eth_dev->data->dev_conf.rxmode.offloads;
690 "Configuring skt %u RX queue %u with %u buffers, offloads %jx",
691 socket_id, rx_queue_id, nb_desc, offloads);
693 if (!rx_conf->rx_drop_en)
694 IONIC_PRINT(WARNING, "No-drop mode is not supported");
696 /* Validate number of receive descriptors */
697 if (!rte_is_power_of_2(nb_desc) ||
698 nb_desc < IONIC_MIN_RING_DESC ||
699 nb_desc > IONIC_MAX_RING_DESC) {
701 "Bad descriptor count (%u) for queue %u (min: %u)",
702 nb_desc, rx_queue_id, IONIC_MIN_RING_DESC);
703 return -EINVAL; /* or use IONIC_DEFAULT_RING_DESC */
706 /* Free memory prior to re-allocation if needed... */
707 if (eth_dev->data->rx_queues[rx_queue_id] != NULL) {
708 void *rx_queue = eth_dev->data->rx_queues[rx_queue_id];
709 ionic_dev_rx_queue_release(rx_queue);
710 eth_dev->data->rx_queues[rx_queue_id] = NULL;
713 eth_dev->data->rx_queue_state[rx_queue_id] =
714 RTE_ETH_QUEUE_STATE_STOPPED;
716 err = ionic_rx_qcq_alloc(lif, rx_queue_id, nb_desc, &rxq);
718 IONIC_PRINT(ERR, "Queue %d allocation failure", rx_queue_id);
725 * Note: the interface does not currently support
726 * DEV_RX_OFFLOAD_KEEP_CRC, please also consider ETHER_CRC_LEN
727 * when the adapter will be able to keep the CRC and subtract
728 * it to the length for all received packets:
729 * if (eth_dev->data->dev_conf.rxmode.offloads &
730 * DEV_RX_OFFLOAD_KEEP_CRC)
731 * rxq->crc_len = ETHER_CRC_LEN;
734 /* Do not start queue with rte_eth_dev_start() */
735 if (rx_conf->rx_deferred_start)
736 rxq->flags |= IONIC_QCQ_F_DEFERRED;
738 eth_dev->data->rx_queues[rx_queue_id] = rxq;
743 static __rte_always_inline void
744 ionic_rx_clean(struct ionic_qcq *rxq,
745 uint32_t q_desc_index, uint32_t cq_desc_index,
746 void *service_cb_arg)
748 struct ionic_queue *q = &rxq->q;
749 struct ionic_cq *cq = &rxq->cq;
750 struct ionic_rxq_comp *cq_desc_base = cq->base;
751 struct ionic_rxq_comp *cq_desc = &cq_desc_base[cq_desc_index];
752 struct rte_mbuf *rxm, *rxm_seg;
753 uint32_t max_frame_size =
754 rxq->lif->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
755 uint64_t pkt_flags = 0;
757 struct ionic_rx_stats *stats = IONIC_Q_TO_RX_STATS(q);
758 struct ionic_rx_service *recv_args = (struct ionic_rx_service *)
760 uint32_t buf_size = (uint16_t)
761 (rte_pktmbuf_data_room_size(rxq->mb_pool) -
762 RTE_PKTMBUF_HEADROOM);
766 assert(q_desc_index == cq_desc->comp_index);
768 info = IONIC_INFO_PTR(q, cq_desc->comp_index);
775 rte_pktmbuf_free(rxm);
777 * Note: rte_mempool_put is faster with no segs
778 * rte_mempool_put(rxq->mb_pool, rxm);
783 if (cq_desc->status) {
784 stats->bad_cq_status++;
785 ionic_rx_recycle(q, q_desc_index, rxm);
789 if (recv_args->nb_rx >= recv_args->nb_pkts) {
791 ionic_rx_recycle(q, q_desc_index, rxm);
795 if (cq_desc->len > max_frame_size ||
798 ionic_rx_recycle(q, q_desc_index, rxm);
802 rxm->data_off = RTE_PKTMBUF_HEADROOM;
803 rte_prefetch1((char *)rxm->buf_addr + rxm->data_off);
804 rxm->nb_segs = 1; /* cq_desc->num_sg_elems */
805 rxm->pkt_len = cq_desc->len;
806 rxm->port = rxq->lif->port_id;
810 rxm->data_len = RTE_MIN(buf_size, left);
811 left -= rxm->data_len;
814 while (rxm_seg && left) {
815 rxm_seg->data_len = RTE_MIN(buf_size, left);
816 left -= rxm_seg->data_len;
818 rxm_seg = rxm_seg->next;
823 pkt_flags |= PKT_RX_RSS_HASH;
824 rxm->hash.rss = cq_desc->rss_hash;
827 if (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_VLAN) {
828 pkt_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
829 rxm->vlan_tci = cq_desc->vlan_tci;
833 if (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_CALC) {
834 if (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_IP_OK)
835 pkt_flags |= PKT_RX_IP_CKSUM_GOOD;
836 else if (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_IP_BAD)
837 pkt_flags |= PKT_RX_IP_CKSUM_BAD;
839 if ((cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_TCP_OK) ||
840 (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_UDP_OK))
841 pkt_flags |= PKT_RX_L4_CKSUM_GOOD;
842 else if ((cq_desc->csum_flags &
843 IONIC_RXQ_COMP_CSUM_F_TCP_BAD) ||
844 (cq_desc->csum_flags &
845 IONIC_RXQ_COMP_CSUM_F_UDP_BAD))
846 pkt_flags |= PKT_RX_L4_CKSUM_BAD;
849 rxm->ol_flags = pkt_flags;
852 switch (cq_desc->pkt_type_color & IONIC_RXQ_COMP_PKT_TYPE_MASK) {
853 case IONIC_PKT_TYPE_IPV4:
854 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4;
856 case IONIC_PKT_TYPE_IPV6:
857 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6;
859 case IONIC_PKT_TYPE_IPV4_TCP:
860 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4 |
863 case IONIC_PKT_TYPE_IPV6_TCP:
864 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6 |
867 case IONIC_PKT_TYPE_IPV4_UDP:
868 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4 |
871 case IONIC_PKT_TYPE_IPV6_UDP:
872 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6 |
877 struct rte_ether_hdr *eth_h = rte_pktmbuf_mtod(rxm,
878 struct rte_ether_hdr *);
879 uint16_t ether_type = eth_h->ether_type;
880 if (ether_type == rte_cpu_to_be_16(RTE_ETHER_TYPE_ARP))
881 pkt_type = RTE_PTYPE_L2_ETHER_ARP;
883 pkt_type = RTE_PTYPE_UNKNOWN;
888 rxm->packet_type = pkt_type;
890 recv_args->rx_pkts[recv_args->nb_rx] = rxm;
894 stats->bytes += rxm->pkt_len;
898 ionic_rx_recycle(struct ionic_queue *q, uint32_t q_desc_index,
899 struct rte_mbuf *mbuf)
901 struct ionic_rxq_desc *desc_base = q->base;
902 struct ionic_rxq_desc *old = &desc_base[q_desc_index];
903 struct ionic_rxq_desc *new = &desc_base[q->head_idx];
905 new->addr = old->addr;
908 ionic_q_post(q, true, mbuf);
911 static __rte_always_inline int
912 ionic_rx_fill(struct ionic_qcq *rxq, uint32_t len)
914 struct ionic_queue *q = &rxq->q;
915 struct ionic_rxq_desc *desc_base = q->base;
916 struct ionic_rxq_sg_desc *sg_desc_base = q->sg_base;
917 struct ionic_rxq_desc *desc;
918 struct ionic_rxq_sg_desc *sg_desc;
919 struct ionic_rxq_sg_elem *elem;
921 uint32_t i, j, nsegs, buf_size, size;
924 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
925 RTE_PKTMBUF_HEADROOM);
927 /* Initialize software ring entries */
928 for (i = ionic_q_space_avail(q); i; i--) {
929 struct rte_mbuf *rxm = rte_mbuf_raw_alloc(rxq->mb_pool);
930 struct rte_mbuf *prev_rxm_seg;
933 IONIC_PRINT(ERR, "RX mbuf alloc failed");
937 nsegs = (len + buf_size - 1) / buf_size;
939 desc = &desc_base[q->head_idx];
940 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(rxm));
941 desc->addr = dma_addr;
942 desc->len = buf_size;
944 desc->opcode = (nsegs > 1) ? IONIC_RXQ_DESC_OPCODE_SG :
945 IONIC_RXQ_DESC_OPCODE_SIMPLE;
949 sg_desc = &sg_desc_base[q->head_idx];
950 elem = sg_desc->elems;
951 for (j = 0; j < nsegs - 1 && j < IONIC_RX_MAX_SG_ELEMS; j++) {
952 struct rte_mbuf *rxm_seg;
953 rte_iova_t data_iova;
955 rxm_seg = rte_mbuf_raw_alloc(rxq->mb_pool);
956 if (rxm_seg == NULL) {
957 IONIC_PRINT(ERR, "RX mbuf alloc failed");
961 data_iova = rte_mbuf_data_iova(rxm_seg);
962 dma_addr = rte_cpu_to_le_64(data_iova);
963 elem->addr = dma_addr;
964 elem->len = buf_size;
967 rxm_seg->next = NULL;
968 prev_rxm_seg->next = rxm_seg;
969 prev_rxm_seg = rxm_seg;
973 IONIC_PRINT(ERR, "Rx SG size is not sufficient (%d < %d)",
976 ring_doorbell = ((q->head_idx + 1) &
977 IONIC_RX_RING_DOORBELL_STRIDE) == 0;
979 ionic_q_post(q, ring_doorbell, rxm);
986 * Start Receive Units for specified queue.
989 ionic_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
991 uint32_t frame_size = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
992 uint8_t *rx_queue_state = eth_dev->data->rx_queue_state;
993 struct ionic_qcq *rxq;
996 if (rx_queue_state[rx_queue_id] == RTE_ETH_QUEUE_STATE_STARTED) {
997 IONIC_PRINT(DEBUG, "RX queue %u already started",
1002 rxq = eth_dev->data->rx_queues[rx_queue_id];
1004 IONIC_PRINT(DEBUG, "Starting RX queue %u, %u descs (size: %u)",
1005 rx_queue_id, rxq->q.num_descs, frame_size);
1007 if (!(rxq->flags & IONIC_QCQ_F_INITED)) {
1008 err = ionic_lif_rxq_init(rxq);
1012 ionic_qcq_enable(rxq);
1015 /* Allocate buffers for descriptor rings */
1016 if (ionic_rx_fill(rxq, frame_size) != 0) {
1017 IONIC_PRINT(ERR, "Could not alloc mbuf for queue:%d",
1022 rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1027 static __rte_always_inline void
1028 ionic_rxq_service(struct ionic_qcq *rxq, uint32_t work_to_do,
1029 void *service_cb_arg)
1031 struct ionic_cq *cq = &rxq->cq;
1032 struct ionic_queue *q = &rxq->q;
1033 struct ionic_rxq_comp *cq_desc_base = cq->base;
1034 struct ionic_rxq_comp *cq_desc;
1036 uint32_t curr_q_tail_idx, curr_cq_tail_idx;
1037 uint32_t work_done = 0;
1039 if (work_to_do == 0)
1042 cq_desc = &cq_desc_base[cq->tail_idx];
1043 while (color_match(cq_desc->pkt_type_color, cq->done_color)) {
1044 curr_cq_tail_idx = cq->tail_idx;
1045 cq->tail_idx = Q_NEXT_TO_SRVC(cq, 1);
1047 if (cq->tail_idx == 0)
1048 cq->done_color = !cq->done_color;
1050 /* Prefetch the next 4 descriptors */
1051 if ((cq->tail_idx & 0x3) == 0)
1052 rte_prefetch0(&cq_desc_base[cq->tail_idx]);
1055 more = (q->tail_idx != cq_desc->comp_index);
1057 curr_q_tail_idx = q->tail_idx;
1058 q->tail_idx = Q_NEXT_TO_SRVC(q, 1);
1060 /* Prefetch the next 4 descriptors */
1061 if ((q->tail_idx & 0x3) == 0)
1063 rte_prefetch0(&q->info[q->tail_idx]);
1065 ionic_rx_clean(rxq, curr_q_tail_idx, curr_cq_tail_idx,
1070 if (++work_done == work_to_do)
1073 cq_desc = &cq_desc_base[cq->tail_idx];
1078 * Stop Receive Units for specified queue.
1081 ionic_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
1083 struct ionic_qcq *rxq;
1085 IONIC_PRINT(DEBUG, "Stopping RX queue %u", rx_queue_id);
1087 rxq = eth_dev->data->rx_queues[rx_queue_id];
1089 eth_dev->data->rx_queue_state[rx_queue_id] =
1090 RTE_ETH_QUEUE_STATE_STOPPED;
1092 ionic_qcq_disable(rxq);
1095 ionic_rxq_service(rxq, -1, NULL);
1101 ionic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1104 struct ionic_qcq *rxq = (struct ionic_qcq *)rx_queue;
1105 uint32_t frame_size =
1106 rxq->lif->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
1107 struct ionic_rx_service service_cb_arg;
1109 service_cb_arg.rx_pkts = rx_pkts;
1110 service_cb_arg.nb_pkts = nb_pkts;
1111 service_cb_arg.nb_rx = 0;
1113 ionic_rxq_service(rxq, nb_pkts, &service_cb_arg);
1115 ionic_rx_fill(rxq, frame_size);
1117 return service_cb_arg.nb_rx;