1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
15 #include <rte_byteorder.h>
16 #include <rte_common.h>
17 #include <rte_cycles.h>
19 #include <rte_debug.h>
20 #include <rte_interrupts.h>
22 #include <rte_memory.h>
23 #include <rte_memzone.h>
24 #include <rte_launch.h>
26 #include <rte_per_lcore.h>
27 #include <rte_lcore.h>
28 #include <rte_atomic.h>
29 #include <rte_branch_prediction.h>
30 #include <rte_mempool.h>
31 #include <rte_malloc.h>
33 #include <rte_ether.h>
34 #include <rte_ethdev_driver.h>
35 #include <rte_prefetch.h>
39 #include <rte_string_fns.h>
40 #include <rte_errno.h>
44 #include "ionic_logs.h"
45 #include "ionic_mac_api.h"
46 #include "ionic_ethdev.h"
47 #include "ionic_lif.h"
48 #include "ionic_rxtx.h"
50 #define IONIC_RX_RING_DOORBELL_STRIDE (32 - 1)
52 /*********************************************************************
56 **********************************************************************/
59 ionic_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
60 struct rte_eth_txq_info *qinfo)
62 struct ionic_qcq *txq = dev->data->tx_queues[queue_id];
63 struct ionic_queue *q = &txq->q;
65 qinfo->nb_desc = q->num_descs;
66 qinfo->conf.offloads = txq->offloads;
67 qinfo->conf.tx_deferred_start = txq->flags & IONIC_QCQ_F_DEFERRED;
70 static inline void __rte_cold
71 ionic_tx_flush(struct ionic_cq *cq)
73 struct ionic_queue *q = cq->bound_q;
74 struct ionic_desc_info *q_desc_info;
75 struct rte_mbuf *txm, *next;
76 struct ionic_txq_comp *cq_desc_base = cq->base;
77 struct ionic_txq_comp *cq_desc;
78 u_int32_t comp_index = (u_int32_t)-1;
80 cq_desc = &cq_desc_base[cq->tail_idx];
81 while (color_match(cq_desc->color, cq->done_color)) {
82 cq->tail_idx = (cq->tail_idx + 1) & (cq->num_descs - 1);
84 /* Prefetch the next 4 descriptors (not really useful here) */
85 if ((cq->tail_idx & 0x3) == 0)
86 rte_prefetch0(&cq_desc_base[cq->tail_idx]);
88 if (cq->tail_idx == 0)
89 cq->done_color = !cq->done_color;
91 comp_index = cq_desc->comp_index;
93 cq_desc = &cq_desc_base[cq->tail_idx];
96 if (comp_index != (u_int32_t)-1) {
97 while (q->tail_idx != comp_index) {
98 q_desc_info = &q->info[q->tail_idx];
100 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1);
102 /* Prefetch the next 4 descriptors */
103 if ((q->tail_idx & 0x3) == 0)
105 rte_prefetch0(&q->info[q->tail_idx]);
108 * Note: you can just use rte_pktmbuf_free,
109 * but this loop is faster
111 txm = q_desc_info->cb_arg;
112 while (txm != NULL) {
114 rte_pktmbuf_free_seg(txm);
122 ionic_dev_tx_queue_release(void *tx_queue)
124 struct ionic_qcq *txq = (struct ionic_qcq *)tx_queue;
132 ionic_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
134 struct ionic_qcq *txq;
136 IONIC_PRINT(DEBUG, "Stopping TX queue %u", tx_queue_id);
138 txq = eth_dev->data->tx_queues[tx_queue_id];
141 * Note: we should better post NOP Tx desc and wait for its completion
142 * before disabling Tx queue
145 ionic_qcq_disable(txq);
147 ionic_tx_flush(&txq->cq);
149 ionic_lif_txq_deinit(txq);
151 eth_dev->data->tx_queue_state[tx_queue_id] =
152 RTE_ETH_QUEUE_STATE_STOPPED;
158 ionic_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id,
159 uint16_t nb_desc, uint32_t socket_id,
160 const struct rte_eth_txconf *tx_conf)
162 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
163 struct ionic_qcq *txq;
167 if (tx_queue_id >= lif->ntxqcqs) {
168 IONIC_PRINT(DEBUG, "Queue index %u not available "
170 tx_queue_id, lif->ntxqcqs);
174 offloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads;
176 "Configuring skt %u TX queue %u with %u buffers, offloads %jx",
177 socket_id, tx_queue_id, nb_desc, offloads);
179 /* Validate number of receive descriptors */
180 if (!rte_is_power_of_2(nb_desc) || nb_desc < IONIC_MIN_RING_DESC)
181 return -EINVAL; /* or use IONIC_DEFAULT_RING_DESC */
183 /* Free memory prior to re-allocation if needed... */
184 if (eth_dev->data->tx_queues[tx_queue_id] != NULL) {
185 void *tx_queue = eth_dev->data->tx_queues[tx_queue_id];
186 ionic_dev_tx_queue_release(tx_queue);
187 eth_dev->data->tx_queues[tx_queue_id] = NULL;
190 err = ionic_tx_qcq_alloc(lif, tx_queue_id, nb_desc, &txq);
192 IONIC_PRINT(DEBUG, "Queue allocation failure");
196 /* Do not start queue with rte_eth_dev_start() */
197 if (tx_conf->tx_deferred_start)
198 txq->flags |= IONIC_QCQ_F_DEFERRED;
200 txq->offloads = offloads;
202 eth_dev->data->tx_queues[tx_queue_id] = txq;
208 * Start Transmit Units for specified queue.
211 ionic_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
213 struct ionic_qcq *txq;
216 txq = eth_dev->data->tx_queues[tx_queue_id];
218 IONIC_PRINT(DEBUG, "Starting TX queue %u, %u descs",
219 tx_queue_id, txq->q.num_descs);
221 err = ionic_lif_txq_init(txq);
225 ionic_qcq_enable(txq);
227 eth_dev->data->tx_queue_state[tx_queue_id] =
228 RTE_ETH_QUEUE_STATE_STARTED;
234 ionic_tx_tcp_pseudo_csum(struct rte_mbuf *txm)
236 struct ether_hdr *eth_hdr = rte_pktmbuf_mtod(txm, struct ether_hdr *);
237 char *l3_hdr = ((char *)eth_hdr) + txm->l2_len;
238 struct rte_tcp_hdr *tcp_hdr = (struct rte_tcp_hdr *)
239 (l3_hdr + txm->l3_len);
241 if (txm->ol_flags & PKT_TX_IP_CKSUM) {
242 struct rte_ipv4_hdr *ipv4_hdr = (struct rte_ipv4_hdr *)l3_hdr;
243 ipv4_hdr->hdr_checksum = 0;
245 tcp_hdr->cksum = rte_ipv4_udptcp_cksum(ipv4_hdr, tcp_hdr);
247 struct rte_ipv6_hdr *ipv6_hdr = (struct rte_ipv6_hdr *)l3_hdr;
249 tcp_hdr->cksum = rte_ipv6_udptcp_cksum(ipv6_hdr, tcp_hdr);
254 ionic_tx_tcp_inner_pseudo_csum(struct rte_mbuf *txm)
256 struct ether_hdr *eth_hdr = rte_pktmbuf_mtod(txm, struct ether_hdr *);
257 char *l3_hdr = ((char *)eth_hdr) + txm->outer_l2_len +
258 txm->outer_l3_len + txm->l2_len;
259 struct rte_tcp_hdr *tcp_hdr = (struct rte_tcp_hdr *)
260 (l3_hdr + txm->l3_len);
262 if (txm->ol_flags & PKT_TX_IPV4) {
263 struct rte_ipv4_hdr *ipv4_hdr = (struct rte_ipv4_hdr *)l3_hdr;
264 ipv4_hdr->hdr_checksum = 0;
266 tcp_hdr->cksum = rte_ipv4_udptcp_cksum(ipv4_hdr, tcp_hdr);
268 struct rte_ipv6_hdr *ipv6_hdr = (struct rte_ipv6_hdr *)l3_hdr;
270 tcp_hdr->cksum = rte_ipv6_udptcp_cksum(ipv6_hdr, tcp_hdr);
275 ionic_tx_tso_post(struct ionic_queue *q, struct ionic_txq_desc *desc,
276 struct rte_mbuf *txm,
277 rte_iova_t addr, uint8_t nsge, uint16_t len,
278 uint32_t hdrlen, uint32_t mss,
280 uint16_t vlan_tci, bool has_vlan,
281 bool start, bool done)
284 flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;
285 flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;
286 flags |= start ? IONIC_TXQ_DESC_FLAG_TSO_SOT : 0;
287 flags |= done ? IONIC_TXQ_DESC_FLAG_TSO_EOT : 0;
289 desc->cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_TSO,
292 desc->vlan_tci = vlan_tci;
293 desc->hdr_len = hdrlen;
296 ionic_q_post(q, done, NULL, done ? txm : NULL);
299 static struct ionic_txq_desc *
300 ionic_tx_tso_next(struct ionic_queue *q, struct ionic_txq_sg_elem **elem)
302 struct ionic_txq_desc *desc_base = q->base;
303 struct ionic_txq_sg_desc *sg_desc_base = q->sg_base;
304 struct ionic_txq_desc *desc = &desc_base[q->head_idx];
305 struct ionic_txq_sg_desc *sg_desc = &sg_desc_base[q->head_idx];
307 *elem = sg_desc->elems;
312 ionic_tx_tso(struct ionic_queue *q, struct rte_mbuf *txm,
313 uint64_t offloads __rte_unused, bool not_xmit_more)
315 struct ionic_tx_stats *stats = IONIC_Q_TO_TX_STATS(q);
316 struct ionic_txq_desc *desc;
317 struct ionic_txq_sg_elem *elem;
318 struct rte_mbuf *txm_seg;
319 uint64_t desc_addr = 0;
320 uint16_t desc_len = 0;
323 uint32_t mss = txm->tso_segsz;
324 uint32_t frag_left = 0;
331 bool has_vlan = !!(txm->ol_flags & PKT_TX_VLAN_PKT);
332 uint16_t vlan_tci = txm->vlan_tci;
333 uint64_t ol_flags = txm->ol_flags;
335 encap = ((ol_flags & PKT_TX_OUTER_IP_CKSUM) ||
336 (ol_flags & PKT_TX_OUTER_UDP_CKSUM)) &&
337 ((ol_flags & PKT_TX_OUTER_IPV4) ||
338 (ol_flags & PKT_TX_OUTER_IPV6));
340 /* Preload inner-most TCP csum field with IP pseudo hdr
341 * calculated with IP length set to zero. HW will later
342 * add in length to each TCP segment resulting from the TSO.
346 ionic_tx_tcp_inner_pseudo_csum(txm);
347 hdrlen = txm->outer_l2_len + txm->outer_l3_len +
348 txm->l2_len + txm->l3_len + txm->l4_len;
350 ionic_tx_tcp_pseudo_csum(txm);
351 hdrlen = txm->l2_len + txm->l3_len + txm->l4_len;
354 seglen = hdrlen + mss;
355 left = txm->data_len;
357 desc = ionic_tx_tso_next(q, &elem);
360 /* Chop data up into desc segments */
363 len = RTE_MIN(seglen, left);
364 frag_left = seglen - len;
365 desc_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(txm));
370 if (txm->nb_segs > 1 && frag_left > 0)
372 done = (txm->nb_segs == 1 && left == 0);
373 ionic_tx_tso_post(q, desc, txm,
374 desc_addr, desc_nsge, desc_len,
378 start, done && not_xmit_more);
379 desc = ionic_tx_tso_next(q, &elem);
384 /* Chop frags into desc segments */
387 while (txm_seg != NULL) {
389 left = txm_seg->data_len;
393 rte_iova_t data_iova;
394 data_iova = rte_mbuf_data_iova(txm_seg);
395 elem->addr = rte_cpu_to_le_64(data_iova) + offset;
397 len = RTE_MIN(frag_left, left);
403 len = RTE_MIN(mss, left);
404 frag_left = mss - len;
405 data_iova = rte_mbuf_data_iova(txm_seg);
406 desc_addr = rte_cpu_to_le_64(data_iova);
412 if (txm_seg->next != NULL && frag_left > 0)
414 done = (txm_seg->next == NULL && left == 0);
415 ionic_tx_tso_post(q, desc, txm_seg,
416 desc_addr, desc_nsge, desc_len,
420 start, done && not_xmit_more);
421 desc = ionic_tx_tso_next(q, &elem);
425 txm_seg = txm_seg->next;
434 ionic_tx(struct ionic_queue *q, struct rte_mbuf *txm,
435 uint64_t offloads, bool not_xmit_more)
437 struct ionic_txq_desc *desc_base = q->base;
438 struct ionic_txq_sg_desc *sg_desc_base = q->sg_base;
439 struct ionic_txq_desc *desc = &desc_base[q->head_idx];
440 struct ionic_txq_sg_desc *sg_desc = &sg_desc_base[q->head_idx];
441 struct ionic_txq_sg_elem *elem = sg_desc->elems;
442 struct ionic_tx_stats *stats = IONIC_Q_TO_TX_STATS(q);
443 struct rte_mbuf *txm_seg;
446 uint64_t ol_flags = txm->ol_flags;
447 uint64_t addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(txm));
448 uint8_t opcode = IONIC_TXQ_DESC_OPCODE_CSUM_NONE;
451 if ((ol_flags & PKT_TX_IP_CKSUM) &&
452 (offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)) {
453 opcode = IONIC_TXQ_DESC_OPCODE_CSUM_HW;
454 flags |= IONIC_TXQ_DESC_FLAG_CSUM_L3;
455 if (((ol_flags & PKT_TX_TCP_CKSUM) &&
456 (offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) ||
457 ((ol_flags & PKT_TX_UDP_CKSUM) &&
458 (offloads & DEV_TX_OFFLOAD_UDP_CKSUM)))
459 flags |= IONIC_TXQ_DESC_FLAG_CSUM_L4;
464 has_vlan = (ol_flags & PKT_TX_VLAN_PKT);
465 encap = ((ol_flags & PKT_TX_OUTER_IP_CKSUM) ||
466 (ol_flags & PKT_TX_OUTER_UDP_CKSUM)) &&
467 ((ol_flags & PKT_TX_OUTER_IPV4) ||
468 (ol_flags & PKT_TX_OUTER_IPV6));
470 flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;
471 flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;
473 desc->cmd = encode_txq_desc_cmd(opcode, flags, txm->nb_segs - 1, addr);
474 desc->len = txm->data_len;
475 desc->vlan_tci = txm->vlan_tci;
478 while (txm_seg != NULL) {
479 elem->len = txm_seg->data_len;
480 elem->addr = rte_cpu_to_le_64(rte_mbuf_data_iova(txm_seg));
483 txm_seg = txm_seg->next;
486 ionic_q_post(q, not_xmit_more, NULL, txm);
492 ionic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
495 struct ionic_qcq *txq = (struct ionic_qcq *)tx_queue;
496 struct ionic_queue *q = &txq->q;
497 struct ionic_cq *cq = &txq->cq;
498 struct ionic_tx_stats *stats = IONIC_Q_TO_TX_STATS(q);
499 uint32_t next_q_head_idx;
500 uint32_t bytes_tx = 0;
505 /* Cleaning old buffers */
508 if (unlikely(ionic_q_space_avail(q) < nb_pkts)) {
509 stats->stop += nb_pkts;
513 while (nb_tx < nb_pkts) {
514 last = (nb_tx == (nb_pkts - 1));
516 next_q_head_idx = (q->head_idx + 1) & (q->num_descs - 1);
517 if ((next_q_head_idx & 0x3) == 0) {
518 struct ionic_txq_desc *desc_base = q->base;
519 rte_prefetch0(&desc_base[next_q_head_idx]);
520 rte_prefetch0(&q->info[next_q_head_idx]);
523 if (tx_pkts[nb_tx]->ol_flags & PKT_TX_TCP_SEG)
524 err = ionic_tx_tso(q, tx_pkts[nb_tx], txq->offloads,
527 err = ionic_tx(q, tx_pkts[nb_tx], txq->offloads, last);
529 stats->drop += nb_pkts - nb_tx;
535 bytes_tx += tx_pkts[nb_tx]->pkt_len;
539 stats->packets += nb_tx;
540 stats->bytes += bytes_tx;
545 /*********************************************************************
549 **********************************************************************/
551 #define IONIC_TX_OFFLOAD_MASK ( \
559 #define IONIC_TX_OFFLOAD_NOTSUP_MASK \
560 (PKT_TX_OFFLOAD_MASK ^ IONIC_TX_OFFLOAD_MASK)
563 ionic_prep_pkts(void *tx_queue __rte_unused, struct rte_mbuf **tx_pkts,
566 struct rte_mbuf *txm;
570 for (i = 0; i < nb_pkts; i++) {
573 if (txm->nb_segs > IONIC_TX_MAX_SG_ELEMS) {
578 offloads = txm->ol_flags;
580 if (offloads & IONIC_TX_OFFLOAD_NOTSUP_MASK) {
581 rte_errno = -ENOTSUP;
589 /*********************************************************************
593 **********************************************************************/
595 static void ionic_rx_recycle(struct ionic_queue *q, uint32_t q_desc_index,
596 struct rte_mbuf *mbuf);
599 ionic_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
600 struct rte_eth_rxq_info *qinfo)
602 struct ionic_qcq *rxq = dev->data->rx_queues[queue_id];
603 struct ionic_queue *q = &rxq->q;
605 qinfo->mp = rxq->mb_pool;
606 qinfo->scattered_rx = dev->data->scattered_rx;
607 qinfo->nb_desc = q->num_descs;
608 qinfo->conf.rx_deferred_start = rxq->flags & IONIC_QCQ_F_DEFERRED;
609 qinfo->conf.offloads = rxq->offloads;
612 static void __rte_cold
613 ionic_rx_empty(struct ionic_queue *q)
615 struct ionic_qcq *rxq = IONIC_Q_TO_QCQ(q);
616 struct ionic_desc_info *cur;
617 struct rte_mbuf *mbuf;
619 while (q->tail_idx != q->head_idx) {
620 cur = &q->info[q->tail_idx];
622 rte_mempool_put(rxq->mb_pool, mbuf);
624 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1);
629 ionic_dev_rx_queue_release(void *rx_queue)
631 struct ionic_qcq *rxq = (struct ionic_qcq *)rx_queue;
635 ionic_rx_empty(&rxq->q);
641 ionic_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
642 uint16_t rx_queue_id,
645 const struct rte_eth_rxconf *rx_conf,
646 struct rte_mempool *mp)
648 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
649 struct ionic_qcq *rxq;
653 if (rx_queue_id >= lif->nrxqcqs) {
655 "Queue index %u not available (max %u queues)",
656 rx_queue_id, lif->nrxqcqs);
660 offloads = rx_conf->offloads | eth_dev->data->dev_conf.rxmode.offloads;
662 "Configuring skt %u RX queue %u with %u buffers, offloads %jx",
663 socket_id, rx_queue_id, nb_desc, offloads);
665 /* Validate number of receive descriptors */
666 if (!rte_is_power_of_2(nb_desc) ||
667 nb_desc < IONIC_MIN_RING_DESC ||
668 nb_desc > IONIC_MAX_RING_DESC) {
670 "Bad descriptor count (%u) for queue %u (min: %u)",
671 nb_desc, rx_queue_id, IONIC_MIN_RING_DESC);
672 return -EINVAL; /* or use IONIC_DEFAULT_RING_DESC */
675 if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER)
676 eth_dev->data->scattered_rx = 1;
678 /* Free memory prior to re-allocation if needed... */
679 if (eth_dev->data->rx_queues[rx_queue_id] != NULL) {
680 void *rx_queue = eth_dev->data->rx_queues[rx_queue_id];
681 ionic_dev_rx_queue_release(rx_queue);
682 eth_dev->data->rx_queues[rx_queue_id] = NULL;
685 err = ionic_rx_qcq_alloc(lif, rx_queue_id, nb_desc, &rxq);
687 IONIC_PRINT(ERR, "Queue %d allocation failure", rx_queue_id);
694 * Note: the interface does not currently support
695 * DEV_RX_OFFLOAD_KEEP_CRC, please also consider ETHER_CRC_LEN
696 * when the adapter will be able to keep the CRC and subtract
697 * it to the length for all received packets:
698 * if (eth_dev->data->dev_conf.rxmode.offloads &
699 * DEV_RX_OFFLOAD_KEEP_CRC)
700 * rxq->crc_len = ETHER_CRC_LEN;
703 /* Do not start queue with rte_eth_dev_start() */
704 if (rx_conf->rx_deferred_start)
705 rxq->flags |= IONIC_QCQ_F_DEFERRED;
707 rxq->offloads = offloads;
709 eth_dev->data->rx_queues[rx_queue_id] = rxq;
715 ionic_rx_clean(struct ionic_queue *q,
716 uint32_t q_desc_index, uint32_t cq_desc_index,
717 void *cb_arg, void *service_cb_arg)
719 struct ionic_rxq_comp *cq_desc_base = q->bound_cq->base;
720 struct ionic_rxq_comp *cq_desc = &cq_desc_base[cq_desc_index];
721 struct rte_mbuf *rxm = cb_arg;
722 struct rte_mbuf *rxm_seg;
723 struct ionic_qcq *rxq = IONIC_Q_TO_QCQ(q);
724 uint32_t max_frame_size =
725 rxq->lif->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
726 uint64_t pkt_flags = 0;
728 struct ionic_rx_stats *stats = IONIC_Q_TO_RX_STATS(q);
729 struct ionic_rx_service *recv_args = (struct ionic_rx_service *)
731 uint32_t buf_size = (uint16_t)
732 (rte_pktmbuf_data_room_size(rxq->mb_pool) -
733 RTE_PKTMBUF_HEADROOM);
739 rte_pktmbuf_free(rxm);
741 * Note: rte_mempool_put is faster with no segs
742 * rte_mempool_put(rxq->mb_pool, rxm);
747 if (cq_desc->status) {
748 stats->bad_cq_status++;
749 ionic_rx_recycle(q, q_desc_index, rxm);
753 if (recv_args->nb_rx >= recv_args->nb_pkts) {
755 ionic_rx_recycle(q, q_desc_index, rxm);
759 if (cq_desc->len > max_frame_size ||
762 ionic_rx_recycle(q, q_desc_index, rxm);
766 rxm->data_off = RTE_PKTMBUF_HEADROOM;
767 rte_prefetch1((char *)rxm->buf_addr + rxm->data_off);
768 rxm->nb_segs = 1; /* cq_desc->num_sg_elems */
769 rxm->pkt_len = cq_desc->len;
770 rxm->port = rxq->lif->port_id;
774 rxm->data_len = RTE_MIN(buf_size, left);
775 left -= rxm->data_len;
778 while (rxm_seg && left) {
779 rxm_seg->data_len = RTE_MIN(buf_size, left);
780 left -= rxm_seg->data_len;
782 rxm_seg = rxm_seg->next;
787 pkt_flags |= PKT_RX_RSS_HASH;
788 rxm->hash.rss = cq_desc->rss_hash;
791 if (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_VLAN) {
792 pkt_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
793 rxm->vlan_tci = cq_desc->vlan_tci;
797 if (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_CALC) {
798 if (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_IP_OK)
799 pkt_flags |= PKT_RX_IP_CKSUM_GOOD;
800 else if (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_IP_BAD)
801 pkt_flags |= PKT_RX_IP_CKSUM_BAD;
803 if ((cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_TCP_OK) ||
804 (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_UDP_OK))
805 pkt_flags |= PKT_RX_L4_CKSUM_GOOD;
806 else if ((cq_desc->csum_flags &
807 IONIC_RXQ_COMP_CSUM_F_TCP_BAD) ||
808 (cq_desc->csum_flags &
809 IONIC_RXQ_COMP_CSUM_F_UDP_BAD))
810 pkt_flags |= PKT_RX_L4_CKSUM_BAD;
813 rxm->ol_flags = pkt_flags;
816 switch (cq_desc->pkt_type_color & IONIC_RXQ_COMP_PKT_TYPE_MASK) {
817 case IONIC_PKT_TYPE_IPV4:
818 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4;
820 case IONIC_PKT_TYPE_IPV6:
821 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6;
823 case IONIC_PKT_TYPE_IPV4_TCP:
824 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4 |
827 case IONIC_PKT_TYPE_IPV6_TCP:
828 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6 |
831 case IONIC_PKT_TYPE_IPV4_UDP:
832 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4 |
835 case IONIC_PKT_TYPE_IPV6_UDP:
836 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6 |
841 struct rte_ether_hdr *eth_h = rte_pktmbuf_mtod(rxm,
842 struct rte_ether_hdr *);
843 uint16_t ether_type = eth_h->ether_type;
844 if (ether_type == rte_cpu_to_be_16(RTE_ETHER_TYPE_ARP))
845 pkt_type = RTE_PTYPE_L2_ETHER_ARP;
847 pkt_type = RTE_PTYPE_UNKNOWN;
852 rxm->packet_type = pkt_type;
854 recv_args->rx_pkts[recv_args->nb_rx] = rxm;
858 stats->bytes += rxm->pkt_len;
862 ionic_rx_recycle(struct ionic_queue *q, uint32_t q_desc_index,
863 struct rte_mbuf *mbuf)
865 struct ionic_rxq_desc *desc_base = q->base;
866 struct ionic_rxq_desc *old = &desc_base[q_desc_index];
867 struct ionic_rxq_desc *new = &desc_base[q->head_idx];
869 new->addr = old->addr;
872 ionic_q_post(q, true, ionic_rx_clean, mbuf);
875 static int __rte_cold
876 ionic_rx_fill(struct ionic_qcq *rxq, uint32_t len)
878 struct ionic_queue *q = &rxq->q;
879 struct ionic_rxq_desc *desc_base = q->base;
880 struct ionic_rxq_sg_desc *sg_desc_base = q->sg_base;
881 struct ionic_rxq_desc *desc;
882 struct ionic_rxq_sg_desc *sg_desc;
883 struct ionic_rxq_sg_elem *elem;
885 uint32_t i, j, nsegs, buf_size, size;
888 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
889 RTE_PKTMBUF_HEADROOM);
891 /* Initialize software ring entries */
892 for (i = ionic_q_space_avail(q); i; i--) {
893 struct rte_mbuf *rxm = rte_mbuf_raw_alloc(rxq->mb_pool);
894 struct rte_mbuf *prev_rxm_seg;
897 IONIC_PRINT(ERR, "RX mbuf alloc failed");
901 nsegs = (len + buf_size - 1) / buf_size;
903 desc = &desc_base[q->head_idx];
904 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(rxm));
905 desc->addr = dma_addr;
906 desc->len = buf_size;
908 desc->opcode = (nsegs > 1) ? IONIC_RXQ_DESC_OPCODE_SG :
909 IONIC_RXQ_DESC_OPCODE_SIMPLE;
913 sg_desc = &sg_desc_base[q->head_idx];
914 elem = sg_desc->elems;
915 for (j = 0; j < nsegs - 1 && j < IONIC_RX_MAX_SG_ELEMS; j++) {
916 struct rte_mbuf *rxm_seg;
917 rte_iova_t data_iova;
919 rxm_seg = rte_mbuf_raw_alloc(rxq->mb_pool);
920 if (rxm_seg == NULL) {
921 IONIC_PRINT(ERR, "RX mbuf alloc failed");
925 data_iova = rte_mbuf_data_iova(rxm_seg);
926 dma_addr = rte_cpu_to_le_64(data_iova);
927 elem->addr = dma_addr;
928 elem->len = buf_size;
931 rxm_seg->next = NULL;
932 prev_rxm_seg->next = rxm_seg;
933 prev_rxm_seg = rxm_seg;
937 IONIC_PRINT(ERR, "Rx SG size is not sufficient (%d < %d)",
940 ring_doorbell = ((q->head_idx + 1) &
941 IONIC_RX_RING_DOORBELL_STRIDE) == 0;
943 ionic_q_post(q, ring_doorbell, ionic_rx_clean, rxm);
950 * Start Receive Units for specified queue.
953 ionic_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
955 uint32_t frame_size = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
956 struct ionic_qcq *rxq;
959 rxq = eth_dev->data->rx_queues[rx_queue_id];
961 IONIC_PRINT(DEBUG, "Starting RX queue %u, %u descs (size: %u)",
962 rx_queue_id, rxq->q.num_descs, frame_size);
964 err = ionic_lif_rxq_init(rxq);
968 /* Allocate buffers for descriptor rings */
969 if (ionic_rx_fill(rxq, frame_size) != 0) {
970 IONIC_PRINT(ERR, "Could not alloc mbuf for queue:%d",
975 ionic_qcq_enable(rxq);
977 eth_dev->data->rx_queue_state[rx_queue_id] =
978 RTE_ETH_QUEUE_STATE_STARTED;
983 static inline void __rte_cold
984 ionic_rxq_service(struct ionic_cq *cq, uint32_t work_to_do,
985 void *service_cb_arg)
987 struct ionic_queue *q = cq->bound_q;
988 struct ionic_desc_info *q_desc_info;
989 struct ionic_rxq_comp *cq_desc_base = cq->base;
990 struct ionic_rxq_comp *cq_desc;
992 uint32_t curr_q_tail_idx, curr_cq_tail_idx;
993 uint32_t work_done = 0;
998 cq_desc = &cq_desc_base[cq->tail_idx];
999 while (color_match(cq_desc->pkt_type_color, cq->done_color)) {
1000 curr_cq_tail_idx = cq->tail_idx;
1001 cq->tail_idx = (cq->tail_idx + 1) & (cq->num_descs - 1);
1003 if (cq->tail_idx == 0)
1004 cq->done_color = !cq->done_color;
1006 /* Prefetch the next 4 descriptors */
1007 if ((cq->tail_idx & 0x3) == 0)
1008 rte_prefetch0(&cq_desc_base[cq->tail_idx]);
1011 more = (q->tail_idx != cq_desc->comp_index);
1013 q_desc_info = &q->info[q->tail_idx];
1015 curr_q_tail_idx = q->tail_idx;
1016 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1);
1018 /* Prefetch the next 4 descriptors */
1019 if ((q->tail_idx & 0x3) == 0)
1021 rte_prefetch0(&q->info[q->tail_idx]);
1023 ionic_rx_clean(q, curr_q_tail_idx, curr_cq_tail_idx,
1024 q_desc_info->cb_arg, service_cb_arg);
1028 if (++work_done == work_to_do)
1031 cq_desc = &cq_desc_base[cq->tail_idx];
1036 * Stop Receive Units for specified queue.
1039 ionic_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
1041 struct ionic_qcq *rxq;
1043 IONIC_PRINT(DEBUG, "Stopping RX queue %u", rx_queue_id);
1045 rxq = eth_dev->data->rx_queues[rx_queue_id];
1047 ionic_qcq_disable(rxq);
1050 ionic_rxq_service(&rxq->cq, -1, NULL);
1052 ionic_lif_rxq_deinit(rxq);
1054 eth_dev->data->rx_queue_state[rx_queue_id] =
1055 RTE_ETH_QUEUE_STATE_STOPPED;
1061 ionic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1064 struct ionic_qcq *rxq = (struct ionic_qcq *)rx_queue;
1065 uint32_t frame_size =
1066 rxq->lif->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
1067 struct ionic_cq *cq = &rxq->cq;
1068 struct ionic_rx_service service_cb_arg;
1070 service_cb_arg.rx_pkts = rx_pkts;
1071 service_cb_arg.nb_pkts = nb_pkts;
1072 service_cb_arg.nb_rx = 0;
1074 ionic_rxq_service(cq, nb_pkts, &service_cb_arg);
1076 ionic_rx_fill(rxq, frame_size);
1078 return service_cb_arg.nb_rx;