1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
15 #include <rte_byteorder.h>
16 #include <rte_common.h>
17 #include <rte_cycles.h>
19 #include <rte_debug.h>
20 #include <rte_interrupts.h>
22 #include <rte_memory.h>
23 #include <rte_memzone.h>
24 #include <rte_launch.h>
26 #include <rte_per_lcore.h>
27 #include <rte_lcore.h>
28 #include <rte_atomic.h>
29 #include <rte_branch_prediction.h>
30 #include <rte_mempool.h>
31 #include <rte_malloc.h>
33 #include <rte_ether.h>
34 #include <rte_ethdev_driver.h>
35 #include <rte_prefetch.h>
39 #include <rte_string_fns.h>
40 #include <rte_errno.h>
44 #include "ionic_logs.h"
45 #include "ionic_mac_api.h"
46 #include "ionic_ethdev.h"
47 #include "ionic_lif.h"
48 #include "ionic_rxtx.h"
50 #define IONIC_RX_RING_DOORBELL_STRIDE (32 - 1)
52 /*********************************************************************
56 **********************************************************************/
59 ionic_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
60 struct rte_eth_txq_info *qinfo)
62 struct ionic_qcq *txq = dev->data->tx_queues[queue_id];
63 struct ionic_queue *q = &txq->q;
65 qinfo->nb_desc = q->num_descs;
66 qinfo->conf.offloads = txq->offloads;
67 qinfo->conf.tx_deferred_start = txq->flags & IONIC_QCQ_F_DEFERRED;
70 static inline void __rte_cold
71 ionic_tx_flush(struct ionic_cq *cq)
73 struct ionic_queue *q = cq->bound_q;
74 struct ionic_desc_info *q_desc_info;
75 struct rte_mbuf *txm, *next;
76 struct ionic_txq_comp *cq_desc_base = cq->base;
77 struct ionic_txq_comp *cq_desc;
78 u_int32_t comp_index = (u_int32_t)-1;
80 cq_desc = &cq_desc_base[cq->tail_idx];
81 while (color_match(cq_desc->color, cq->done_color)) {
82 cq->tail_idx = (cq->tail_idx + 1) & (cq->num_descs - 1);
84 /* Prefetch the next 4 descriptors (not really useful here) */
85 if ((cq->tail_idx & 0x3) == 0)
86 rte_prefetch0(&cq_desc_base[cq->tail_idx]);
88 if (cq->tail_idx == 0)
89 cq->done_color = !cq->done_color;
91 comp_index = cq_desc->comp_index;
93 cq_desc = &cq_desc_base[cq->tail_idx];
96 if (comp_index != (u_int32_t)-1) {
97 while (q->tail_idx != comp_index) {
98 q_desc_info = &q->info[q->tail_idx];
100 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1);
102 /* Prefetch the next 4 descriptors */
103 if ((q->tail_idx & 0x3) == 0)
105 rte_prefetch0(&q->info[q->tail_idx]);
108 * Note: you can just use rte_pktmbuf_free,
109 * but this loop is faster
111 txm = q_desc_info->cb_arg;
112 while (txm != NULL) {
114 rte_pktmbuf_free_seg(txm);
122 ionic_dev_tx_queue_release(void *tx_queue)
124 struct ionic_qcq *txq = (struct ionic_qcq *)tx_queue;
132 ionic_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
134 struct ionic_qcq *txq;
138 txq = eth_dev->data->tx_queues[tx_queue_id];
141 * Note: we should better post NOP Tx desc and wait for its completion
142 * before disabling Tx queue
145 ionic_qcq_disable(txq);
147 ionic_tx_flush(&txq->cq);
149 ionic_lif_txq_deinit(txq);
151 eth_dev->data->tx_queue_state[tx_queue_id] =
152 RTE_ETH_QUEUE_STATE_STOPPED;
158 ionic_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id,
159 uint16_t nb_desc, uint32_t socket_id __rte_unused,
160 const struct rte_eth_txconf *tx_conf)
162 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
163 struct ionic_qcq *txq;
169 IONIC_PRINT(DEBUG, "Configuring TX queue %u with %u buffers",
170 tx_queue_id, nb_desc);
172 if (tx_queue_id >= lif->ntxqcqs) {
173 IONIC_PRINT(DEBUG, "Queue index %u not available "
175 tx_queue_id, lif->ntxqcqs);
179 offloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads;
181 /* Validate number of receive descriptors */
182 if (!rte_is_power_of_2(nb_desc) || nb_desc < IONIC_MIN_RING_DESC)
183 return -EINVAL; /* or use IONIC_DEFAULT_RING_DESC */
185 /* Free memory prior to re-allocation if needed... */
186 if (eth_dev->data->tx_queues[tx_queue_id] != NULL) {
187 void *tx_queue = eth_dev->data->tx_queues[tx_queue_id];
188 ionic_dev_tx_queue_release(tx_queue);
189 eth_dev->data->tx_queues[tx_queue_id] = NULL;
192 err = ionic_tx_qcq_alloc(lif, tx_queue_id, nb_desc, &txq);
194 IONIC_PRINT(DEBUG, "Queue allocation failure");
198 /* Do not start queue with rte_eth_dev_start() */
199 if (tx_conf->tx_deferred_start)
200 txq->flags |= IONIC_QCQ_F_DEFERRED;
202 txq->offloads = offloads;
204 eth_dev->data->tx_queues[tx_queue_id] = txq;
210 * Start Transmit Units for specified queue.
213 ionic_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
215 struct ionic_qcq *txq;
220 txq = eth_dev->data->tx_queues[tx_queue_id];
222 err = ionic_lif_txq_init(txq);
226 ionic_qcq_enable(txq);
228 eth_dev->data->tx_queue_state[tx_queue_id] =
229 RTE_ETH_QUEUE_STATE_STARTED;
235 ionic_tx_tcp_pseudo_csum(struct rte_mbuf *txm)
237 struct ether_hdr *eth_hdr = rte_pktmbuf_mtod(txm, struct ether_hdr *);
238 char *l3_hdr = ((char *)eth_hdr) + txm->l2_len;
239 struct rte_tcp_hdr *tcp_hdr = (struct rte_tcp_hdr *)
240 (l3_hdr + txm->l3_len);
242 if (txm->ol_flags & PKT_TX_IP_CKSUM) {
243 struct rte_ipv4_hdr *ipv4_hdr = (struct rte_ipv4_hdr *)l3_hdr;
244 ipv4_hdr->hdr_checksum = 0;
246 tcp_hdr->cksum = rte_ipv4_udptcp_cksum(ipv4_hdr, tcp_hdr);
248 struct rte_ipv6_hdr *ipv6_hdr = (struct rte_ipv6_hdr *)l3_hdr;
250 tcp_hdr->cksum = rte_ipv6_udptcp_cksum(ipv6_hdr, tcp_hdr);
255 ionic_tx_tcp_inner_pseudo_csum(struct rte_mbuf *txm)
257 struct ether_hdr *eth_hdr = rte_pktmbuf_mtod(txm, struct ether_hdr *);
258 char *l3_hdr = ((char *)eth_hdr) + txm->outer_l2_len +
259 txm->outer_l3_len + txm->l2_len;
260 struct rte_tcp_hdr *tcp_hdr = (struct rte_tcp_hdr *)
261 (l3_hdr + txm->l3_len);
263 if (txm->ol_flags & PKT_TX_IPV4) {
264 struct rte_ipv4_hdr *ipv4_hdr = (struct rte_ipv4_hdr *)l3_hdr;
265 ipv4_hdr->hdr_checksum = 0;
267 tcp_hdr->cksum = rte_ipv4_udptcp_cksum(ipv4_hdr, tcp_hdr);
269 struct rte_ipv6_hdr *ipv6_hdr = (struct rte_ipv6_hdr *)l3_hdr;
271 tcp_hdr->cksum = rte_ipv6_udptcp_cksum(ipv6_hdr, tcp_hdr);
276 ionic_tx_tso_post(struct ionic_queue *q, struct ionic_txq_desc *desc,
277 struct rte_mbuf *txm,
278 rte_iova_t addr, uint8_t nsge, uint16_t len,
279 uint32_t hdrlen, uint32_t mss,
281 uint16_t vlan_tci, bool has_vlan,
282 bool start, bool done)
285 flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;
286 flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;
287 flags |= start ? IONIC_TXQ_DESC_FLAG_TSO_SOT : 0;
288 flags |= done ? IONIC_TXQ_DESC_FLAG_TSO_EOT : 0;
290 desc->cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_TSO,
293 desc->vlan_tci = vlan_tci;
294 desc->hdr_len = hdrlen;
297 ionic_q_post(q, done, NULL, done ? txm : NULL);
300 static struct ionic_txq_desc *
301 ionic_tx_tso_next(struct ionic_queue *q, struct ionic_txq_sg_elem **elem)
303 struct ionic_txq_desc *desc_base = q->base;
304 struct ionic_txq_sg_desc *sg_desc_base = q->sg_base;
305 struct ionic_txq_desc *desc = &desc_base[q->head_idx];
306 struct ionic_txq_sg_desc *sg_desc = &sg_desc_base[q->head_idx];
308 *elem = sg_desc->elems;
313 ionic_tx_tso(struct ionic_queue *q, struct rte_mbuf *txm,
314 uint64_t offloads __rte_unused, bool not_xmit_more)
316 struct ionic_tx_stats *stats = IONIC_Q_TO_TX_STATS(q);
317 struct ionic_txq_desc *desc;
318 struct ionic_txq_sg_elem *elem;
319 struct rte_mbuf *txm_seg;
320 uint64_t desc_addr = 0;
321 uint16_t desc_len = 0;
324 uint32_t mss = txm->tso_segsz;
325 uint32_t frag_left = 0;
332 bool has_vlan = !!(txm->ol_flags & PKT_TX_VLAN_PKT);
333 uint16_t vlan_tci = txm->vlan_tci;
334 uint64_t ol_flags = txm->ol_flags;
336 encap = ((ol_flags & PKT_TX_OUTER_IP_CKSUM) ||
337 (ol_flags & PKT_TX_OUTER_UDP_CKSUM)) &&
338 ((ol_flags & PKT_TX_OUTER_IPV4) ||
339 (ol_flags & PKT_TX_OUTER_IPV6));
341 /* Preload inner-most TCP csum field with IP pseudo hdr
342 * calculated with IP length set to zero. HW will later
343 * add in length to each TCP segment resulting from the TSO.
347 ionic_tx_tcp_inner_pseudo_csum(txm);
348 hdrlen = txm->outer_l2_len + txm->outer_l3_len +
349 txm->l2_len + txm->l3_len + txm->l4_len;
351 ionic_tx_tcp_pseudo_csum(txm);
352 hdrlen = txm->l2_len + txm->l3_len + txm->l4_len;
355 seglen = hdrlen + mss;
356 left = txm->data_len;
358 desc = ionic_tx_tso_next(q, &elem);
361 /* Chop data up into desc segments */
364 len = RTE_MIN(seglen, left);
365 frag_left = seglen - len;
366 desc_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(txm));
371 if (txm->nb_segs > 1 && frag_left > 0)
373 done = (txm->nb_segs == 1 && left == 0);
374 ionic_tx_tso_post(q, desc, txm,
375 desc_addr, desc_nsge, desc_len,
379 start, done && not_xmit_more);
380 desc = ionic_tx_tso_next(q, &elem);
385 /* Chop frags into desc segments */
388 while (txm_seg != NULL) {
390 left = txm_seg->data_len;
394 rte_iova_t data_iova;
395 data_iova = rte_mbuf_data_iova(txm_seg);
396 elem->addr = rte_cpu_to_le_64(data_iova) + offset;
398 len = RTE_MIN(frag_left, left);
404 len = RTE_MIN(mss, left);
405 frag_left = mss - len;
406 data_iova = rte_mbuf_data_iova(txm_seg);
407 desc_addr = rte_cpu_to_le_64(data_iova);
413 if (txm_seg->next != NULL && frag_left > 0)
415 done = (txm_seg->next == NULL && left == 0);
416 ionic_tx_tso_post(q, desc, txm_seg,
417 desc_addr, desc_nsge, desc_len,
421 start, done && not_xmit_more);
422 desc = ionic_tx_tso_next(q, &elem);
426 txm_seg = txm_seg->next;
435 ionic_tx(struct ionic_queue *q, struct rte_mbuf *txm,
436 uint64_t offloads, bool not_xmit_more)
438 struct ionic_txq_desc *desc_base = q->base;
439 struct ionic_txq_sg_desc *sg_desc_base = q->sg_base;
440 struct ionic_txq_desc *desc = &desc_base[q->head_idx];
441 struct ionic_txq_sg_desc *sg_desc = &sg_desc_base[q->head_idx];
442 struct ionic_txq_sg_elem *elem = sg_desc->elems;
443 struct ionic_tx_stats *stats = IONIC_Q_TO_TX_STATS(q);
444 struct rte_mbuf *txm_seg;
447 uint64_t ol_flags = txm->ol_flags;
448 uint64_t addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(txm));
449 uint8_t opcode = IONIC_TXQ_DESC_OPCODE_CSUM_NONE;
452 if ((ol_flags & PKT_TX_IP_CKSUM) &&
453 (offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)) {
454 opcode = IONIC_TXQ_DESC_OPCODE_CSUM_HW;
455 flags |= IONIC_TXQ_DESC_FLAG_CSUM_L3;
456 if (((ol_flags & PKT_TX_TCP_CKSUM) &&
457 (offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) ||
458 ((ol_flags & PKT_TX_UDP_CKSUM) &&
459 (offloads & DEV_TX_OFFLOAD_UDP_CKSUM)))
460 flags |= IONIC_TXQ_DESC_FLAG_CSUM_L4;
465 has_vlan = (ol_flags & PKT_TX_VLAN_PKT);
466 encap = ((ol_flags & PKT_TX_OUTER_IP_CKSUM) ||
467 (ol_flags & PKT_TX_OUTER_UDP_CKSUM)) &&
468 ((ol_flags & PKT_TX_OUTER_IPV4) ||
469 (ol_flags & PKT_TX_OUTER_IPV6));
471 flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;
472 flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;
474 desc->cmd = encode_txq_desc_cmd(opcode, flags, txm->nb_segs - 1, addr);
475 desc->len = txm->data_len;
476 desc->vlan_tci = txm->vlan_tci;
479 while (txm_seg != NULL) {
480 elem->len = txm_seg->data_len;
481 elem->addr = rte_cpu_to_le_64(rte_mbuf_data_iova(txm_seg));
484 txm_seg = txm_seg->next;
487 ionic_q_post(q, not_xmit_more, NULL, txm);
493 ionic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
496 struct ionic_qcq *txq = (struct ionic_qcq *)tx_queue;
497 struct ionic_queue *q = &txq->q;
498 struct ionic_cq *cq = &txq->cq;
499 struct ionic_tx_stats *stats = IONIC_Q_TO_TX_STATS(q);
500 uint32_t next_q_head_idx;
501 uint32_t bytes_tx = 0;
506 /* Cleaning old buffers */
509 if (unlikely(ionic_q_space_avail(q) < nb_pkts)) {
510 stats->stop += nb_pkts;
514 while (nb_tx < nb_pkts) {
515 last = (nb_tx == (nb_pkts - 1));
517 next_q_head_idx = (q->head_idx + 1) & (q->num_descs - 1);
518 if ((next_q_head_idx & 0x3) == 0) {
519 struct ionic_txq_desc *desc_base = q->base;
520 rte_prefetch0(&desc_base[next_q_head_idx]);
521 rte_prefetch0(&q->info[next_q_head_idx]);
524 if (tx_pkts[nb_tx]->ol_flags & PKT_TX_TCP_SEG)
525 err = ionic_tx_tso(q, tx_pkts[nb_tx], txq->offloads,
528 err = ionic_tx(q, tx_pkts[nb_tx], txq->offloads, last);
530 stats->drop += nb_pkts - nb_tx;
536 bytes_tx += tx_pkts[nb_tx]->pkt_len;
540 stats->packets += nb_tx;
541 stats->bytes += bytes_tx;
546 /*********************************************************************
550 **********************************************************************/
552 #define IONIC_TX_OFFLOAD_MASK ( \
560 #define IONIC_TX_OFFLOAD_NOTSUP_MASK \
561 (PKT_TX_OFFLOAD_MASK ^ IONIC_TX_OFFLOAD_MASK)
564 ionic_prep_pkts(void *tx_queue __rte_unused, struct rte_mbuf **tx_pkts,
567 struct rte_mbuf *txm;
571 for (i = 0; i < nb_pkts; i++) {
574 if (txm->nb_segs > IONIC_TX_MAX_SG_ELEMS) {
579 offloads = txm->ol_flags;
581 if (offloads & IONIC_TX_OFFLOAD_NOTSUP_MASK) {
582 rte_errno = -ENOTSUP;
590 /*********************************************************************
594 **********************************************************************/
596 static void ionic_rx_recycle(struct ionic_queue *q, uint32_t q_desc_index,
597 struct rte_mbuf *mbuf);
600 ionic_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
601 struct rte_eth_rxq_info *qinfo)
603 struct ionic_qcq *rxq = dev->data->rx_queues[queue_id];
604 struct ionic_queue *q = &rxq->q;
606 qinfo->mp = rxq->mb_pool;
607 qinfo->scattered_rx = dev->data->scattered_rx;
608 qinfo->nb_desc = q->num_descs;
609 qinfo->conf.rx_deferred_start = rxq->flags & IONIC_QCQ_F_DEFERRED;
610 qinfo->conf.offloads = rxq->offloads;
613 static void __rte_cold
614 ionic_rx_empty(struct ionic_queue *q)
616 struct ionic_qcq *rxq = IONIC_Q_TO_QCQ(q);
617 struct ionic_desc_info *cur;
618 struct rte_mbuf *mbuf;
620 while (q->tail_idx != q->head_idx) {
621 cur = &q->info[q->tail_idx];
623 rte_mempool_put(rxq->mb_pool, mbuf);
625 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1);
630 ionic_dev_rx_queue_release(void *rx_queue)
632 struct ionic_qcq *rxq = (struct ionic_qcq *)rx_queue;
636 ionic_rx_empty(&rxq->q);
642 ionic_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
643 uint16_t rx_queue_id,
645 uint32_t socket_id __rte_unused,
646 const struct rte_eth_rxconf *rx_conf,
647 struct rte_mempool *mp)
649 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
650 struct ionic_qcq *rxq;
656 IONIC_PRINT(DEBUG, "Configuring RX queue %u with %u buffers",
657 rx_queue_id, nb_desc);
659 if (rx_queue_id >= lif->nrxqcqs) {
661 "Queue index %u not available (max %u queues)",
662 rx_queue_id, lif->nrxqcqs);
666 offloads = rx_conf->offloads | eth_dev->data->dev_conf.rxmode.offloads;
668 /* Validate number of receive descriptors */
669 if (!rte_is_power_of_2(nb_desc) ||
670 nb_desc < IONIC_MIN_RING_DESC ||
671 nb_desc > IONIC_MAX_RING_DESC) {
673 "Bad number of descriptors (%u) for queue %u (min: %u)",
674 nb_desc, rx_queue_id, IONIC_MIN_RING_DESC);
675 return -EINVAL; /* or use IONIC_DEFAULT_RING_DESC */
678 if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER)
679 eth_dev->data->scattered_rx = 1;
681 /* Free memory prior to re-allocation if needed... */
682 if (eth_dev->data->rx_queues[rx_queue_id] != NULL) {
683 void *rx_queue = eth_dev->data->rx_queues[rx_queue_id];
684 ionic_dev_rx_queue_release(rx_queue);
685 eth_dev->data->rx_queues[rx_queue_id] = NULL;
688 err = ionic_rx_qcq_alloc(lif, rx_queue_id, nb_desc, &rxq);
690 IONIC_PRINT(ERR, "Queue allocation failure");
697 * Note: the interface does not currently support
698 * DEV_RX_OFFLOAD_KEEP_CRC, please also consider ETHER_CRC_LEN
699 * when the adapter will be able to keep the CRC and subtract
700 * it to the length for all received packets:
701 * if (eth_dev->data->dev_conf.rxmode.offloads &
702 * DEV_RX_OFFLOAD_KEEP_CRC)
703 * rxq->crc_len = ETHER_CRC_LEN;
706 /* Do not start queue with rte_eth_dev_start() */
707 if (rx_conf->rx_deferred_start)
708 rxq->flags |= IONIC_QCQ_F_DEFERRED;
710 rxq->offloads = offloads;
712 eth_dev->data->rx_queues[rx_queue_id] = rxq;
718 ionic_rx_clean(struct ionic_queue *q,
719 uint32_t q_desc_index, uint32_t cq_desc_index,
720 void *cb_arg, void *service_cb_arg)
722 struct ionic_rxq_comp *cq_desc_base = q->bound_cq->base;
723 struct ionic_rxq_comp *cq_desc = &cq_desc_base[cq_desc_index];
724 struct rte_mbuf *rxm = cb_arg;
725 struct rte_mbuf *rxm_seg;
726 struct ionic_qcq *rxq = IONIC_Q_TO_QCQ(q);
727 uint32_t max_frame_size =
728 rxq->lif->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
729 uint64_t pkt_flags = 0;
731 struct ionic_rx_stats *stats = IONIC_Q_TO_RX_STATS(q);
732 struct ionic_rx_service *recv_args = (struct ionic_rx_service *)
734 uint32_t buf_size = (uint16_t)
735 (rte_pktmbuf_data_room_size(rxq->mb_pool) -
736 RTE_PKTMBUF_HEADROOM);
742 rte_pktmbuf_free(rxm);
744 * Note: rte_mempool_put is faster with no segs
745 * rte_mempool_put(rxq->mb_pool, rxm);
750 if (cq_desc->status) {
751 stats->bad_cq_status++;
752 ionic_rx_recycle(q, q_desc_index, rxm);
756 if (recv_args->nb_rx >= recv_args->nb_pkts) {
758 ionic_rx_recycle(q, q_desc_index, rxm);
762 if (cq_desc->len > max_frame_size ||
765 ionic_rx_recycle(q, q_desc_index, rxm);
769 rxm->data_off = RTE_PKTMBUF_HEADROOM;
770 rte_prefetch1((char *)rxm->buf_addr + rxm->data_off);
771 rxm->nb_segs = 1; /* cq_desc->num_sg_elems */
772 rxm->pkt_len = cq_desc->len;
773 rxm->port = rxq->lif->port_id;
777 rxm->data_len = RTE_MIN(buf_size, left);
778 left -= rxm->data_len;
781 while (rxm_seg && left) {
782 rxm_seg->data_len = RTE_MIN(buf_size, left);
783 left -= rxm_seg->data_len;
785 rxm_seg = rxm_seg->next;
790 pkt_flags |= PKT_RX_RSS_HASH;
791 rxm->hash.rss = cq_desc->rss_hash;
794 if (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_VLAN) {
795 pkt_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
796 rxm->vlan_tci = cq_desc->vlan_tci;
800 if (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_CALC) {
801 if (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_IP_OK)
802 pkt_flags |= PKT_RX_IP_CKSUM_GOOD;
803 else if (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_IP_BAD)
804 pkt_flags |= PKT_RX_IP_CKSUM_BAD;
806 if ((cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_TCP_OK) ||
807 (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_UDP_OK))
808 pkt_flags |= PKT_RX_L4_CKSUM_GOOD;
809 else if ((cq_desc->csum_flags &
810 IONIC_RXQ_COMP_CSUM_F_TCP_BAD) ||
811 (cq_desc->csum_flags &
812 IONIC_RXQ_COMP_CSUM_F_UDP_BAD))
813 pkt_flags |= PKT_RX_L4_CKSUM_BAD;
816 rxm->ol_flags = pkt_flags;
819 switch (cq_desc->pkt_type_color & IONIC_RXQ_COMP_PKT_TYPE_MASK) {
820 case IONIC_PKT_TYPE_IPV4:
821 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4;
823 case IONIC_PKT_TYPE_IPV6:
824 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6;
826 case IONIC_PKT_TYPE_IPV4_TCP:
827 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4 |
830 case IONIC_PKT_TYPE_IPV6_TCP:
831 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6 |
834 case IONIC_PKT_TYPE_IPV4_UDP:
835 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4 |
838 case IONIC_PKT_TYPE_IPV6_UDP:
839 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6 |
844 struct rte_ether_hdr *eth_h = rte_pktmbuf_mtod(rxm,
845 struct rte_ether_hdr *);
846 uint16_t ether_type = eth_h->ether_type;
847 if (ether_type == rte_cpu_to_be_16(RTE_ETHER_TYPE_ARP))
848 pkt_type = RTE_PTYPE_L2_ETHER_ARP;
850 pkt_type = RTE_PTYPE_UNKNOWN;
855 rxm->packet_type = pkt_type;
857 recv_args->rx_pkts[recv_args->nb_rx] = rxm;
861 stats->bytes += rxm->pkt_len;
865 ionic_rx_recycle(struct ionic_queue *q, uint32_t q_desc_index,
866 struct rte_mbuf *mbuf)
868 struct ionic_rxq_desc *desc_base = q->base;
869 struct ionic_rxq_desc *old = &desc_base[q_desc_index];
870 struct ionic_rxq_desc *new = &desc_base[q->head_idx];
872 new->addr = old->addr;
875 ionic_q_post(q, true, ionic_rx_clean, mbuf);
878 static int __rte_cold
879 ionic_rx_fill(struct ionic_qcq *rxq, uint32_t len)
881 struct ionic_queue *q = &rxq->q;
882 struct ionic_rxq_desc *desc_base = q->base;
883 struct ionic_rxq_sg_desc *sg_desc_base = q->sg_base;
884 struct ionic_rxq_desc *desc;
885 struct ionic_rxq_sg_desc *sg_desc;
886 struct ionic_rxq_sg_elem *elem;
888 uint32_t i, j, nsegs, buf_size, size;
891 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
892 RTE_PKTMBUF_HEADROOM);
894 /* Initialize software ring entries */
895 for (i = ionic_q_space_avail(q); i; i--) {
896 struct rte_mbuf *rxm = rte_mbuf_raw_alloc(rxq->mb_pool);
897 struct rte_mbuf *prev_rxm_seg;
900 IONIC_PRINT(ERR, "RX mbuf alloc failed");
904 nsegs = (len + buf_size - 1) / buf_size;
906 desc = &desc_base[q->head_idx];
907 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(rxm));
908 desc->addr = dma_addr;
909 desc->len = buf_size;
911 desc->opcode = (nsegs > 1) ? IONIC_RXQ_DESC_OPCODE_SG :
912 IONIC_RXQ_DESC_OPCODE_SIMPLE;
916 sg_desc = &sg_desc_base[q->head_idx];
917 elem = sg_desc->elems;
918 for (j = 0; j < nsegs - 1 && j < IONIC_RX_MAX_SG_ELEMS; j++) {
919 struct rte_mbuf *rxm_seg;
920 rte_iova_t data_iova;
922 rxm_seg = rte_mbuf_raw_alloc(rxq->mb_pool);
923 if (rxm_seg == NULL) {
924 IONIC_PRINT(ERR, "RX mbuf alloc failed");
928 data_iova = rte_mbuf_data_iova(rxm_seg);
929 dma_addr = rte_cpu_to_le_64(data_iova);
930 elem->addr = dma_addr;
931 elem->len = buf_size;
934 rxm_seg->next = NULL;
935 prev_rxm_seg->next = rxm_seg;
936 prev_rxm_seg = rxm_seg;
940 IONIC_PRINT(ERR, "Rx SG size is not sufficient (%d < %d)",
943 ring_doorbell = ((q->head_idx + 1) &
944 IONIC_RX_RING_DOORBELL_STRIDE) == 0;
946 ionic_q_post(q, ring_doorbell, ionic_rx_clean, rxm);
953 * Start Receive Units for specified queue.
956 ionic_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
958 uint32_t frame_size = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
959 struct ionic_qcq *rxq;
964 IONIC_PRINT(DEBUG, "Allocating RX queue buffers (size: %u)",
967 rxq = eth_dev->data->rx_queues[rx_queue_id];
969 err = ionic_lif_rxq_init(rxq);
973 /* Allocate buffers for descriptor rings */
974 if (ionic_rx_fill(rxq, frame_size) != 0) {
975 IONIC_PRINT(ERR, "Could not alloc mbuf for queue:%d",
980 ionic_qcq_enable(rxq);
982 eth_dev->data->rx_queue_state[rx_queue_id] =
983 RTE_ETH_QUEUE_STATE_STARTED;
988 static inline void __rte_cold
989 ionic_rxq_service(struct ionic_cq *cq, uint32_t work_to_do,
990 void *service_cb_arg)
992 struct ionic_queue *q = cq->bound_q;
993 struct ionic_desc_info *q_desc_info;
994 struct ionic_rxq_comp *cq_desc_base = cq->base;
995 struct ionic_rxq_comp *cq_desc;
997 uint32_t curr_q_tail_idx, curr_cq_tail_idx;
998 uint32_t work_done = 0;
1000 if (work_to_do == 0)
1003 cq_desc = &cq_desc_base[cq->tail_idx];
1004 while (color_match(cq_desc->pkt_type_color, cq->done_color)) {
1005 curr_cq_tail_idx = cq->tail_idx;
1006 cq->tail_idx = (cq->tail_idx + 1) & (cq->num_descs - 1);
1008 if (cq->tail_idx == 0)
1009 cq->done_color = !cq->done_color;
1011 /* Prefetch the next 4 descriptors */
1012 if ((cq->tail_idx & 0x3) == 0)
1013 rte_prefetch0(&cq_desc_base[cq->tail_idx]);
1016 more = (q->tail_idx != cq_desc->comp_index);
1018 q_desc_info = &q->info[q->tail_idx];
1020 curr_q_tail_idx = q->tail_idx;
1021 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1);
1023 /* Prefetch the next 4 descriptors */
1024 if ((q->tail_idx & 0x3) == 0)
1026 rte_prefetch0(&q->info[q->tail_idx]);
1028 ionic_rx_clean(q, curr_q_tail_idx, curr_cq_tail_idx,
1029 q_desc_info->cb_arg, service_cb_arg);
1033 if (++work_done == work_to_do)
1036 cq_desc = &cq_desc_base[cq->tail_idx];
1041 * Stop Receive Units for specified queue.
1044 ionic_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
1046 struct ionic_qcq *rxq;
1050 rxq = eth_dev->data->rx_queues[rx_queue_id];
1052 ionic_qcq_disable(rxq);
1055 ionic_rxq_service(&rxq->cq, -1, NULL);
1057 ionic_lif_rxq_deinit(rxq);
1059 eth_dev->data->rx_queue_state[rx_queue_id] =
1060 RTE_ETH_QUEUE_STATE_STOPPED;
1066 ionic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1069 struct ionic_qcq *rxq = (struct ionic_qcq *)rx_queue;
1070 uint32_t frame_size =
1071 rxq->lif->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
1072 struct ionic_cq *cq = &rxq->cq;
1073 struct ionic_rx_service service_cb_arg;
1075 service_cb_arg.rx_pkts = rx_pkts;
1076 service_cb_arg.nb_pkts = nb_pkts;
1077 service_cb_arg.nb_rx = 0;
1079 ionic_rxq_service(cq, nb_pkts, &service_cb_arg);
1081 ionic_rx_fill(rxq, frame_size);
1083 return service_cb_arg.nb_rx;