1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2019 Intel Corporation
7 #include <rte_bus_pci.h>
8 #include <rte_ethdev.h>
10 #include <rte_malloc.h>
13 #include <rte_sched.h>
14 #include <rte_ethdev_driver.h>
17 #include <rte_rawdev.h>
18 #include <rte_rawdev_pmd.h>
19 #include <rte_bus_ifpga.h>
20 #include <ifpga_common.h>
21 #include <ifpga_logs.h>
23 #include "ipn3ke_rawdev_api.h"
24 #include "ipn3ke_flow.h"
25 #include "ipn3ke_logs.h"
26 #include "ipn3ke_ethdev.h"
28 int ipn3ke_afu_logtype;
30 static const struct rte_afu_uuid afu_uuid_ipn3ke_map[] = {
31 { MAP_UUID_10G_LOW, MAP_UUID_10G_HIGH },
32 { IPN3KE_UUID_10G_LOW, IPN3KE_UUID_10G_HIGH },
33 { IPN3KE_UUID_VBNG_LOW, IPN3KE_UUID_VBNG_HIGH},
34 { IPN3KE_UUID_25G_LOW, IPN3KE_UUID_25G_HIGH },
35 { 0, 0 /* sentinel */ },
39 ipn3ke_indirect_read(struct ipn3ke_hw *hw, uint32_t *rd_data,
40 uint32_t addr, uint32_t dev_sel, uint32_t eth_group_sel)
43 uint64_t indirect_value;
44 volatile void *indirect_addrs;
46 uint64_t read_data = 0;
48 if (eth_group_sel != 0 && eth_group_sel != 1)
52 target_addr = addr | dev_sel << 17;
54 indirect_value = RCMD | target_addr << 32;
55 indirect_addrs = hw->eth_group_bar[eth_group_sel] + 0x10;
59 rte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs);
63 indirect_addrs = hw->eth_group_bar[eth_group_sel] +
66 read_data = rte_read64(indirect_addrs);
67 if ((read_data >> 32) == 1)
70 } while (i <= try_cnt);
74 *rd_data = rte_le_to_cpu_32(read_data);
79 ipn3ke_indirect_write(struct ipn3ke_hw *hw, uint32_t wr_data,
80 uint32_t addr, uint32_t dev_sel, uint32_t eth_group_sel)
82 volatile void *indirect_addrs;
83 uint64_t indirect_value;
86 if (eth_group_sel != 0 && eth_group_sel != 1)
90 target_addr = addr | dev_sel << 17;
92 indirect_value = WCMD | target_addr << 32 | wr_data;
93 indirect_addrs = hw->eth_group_bar[eth_group_sel] + 0x10;
95 rte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs);
100 ipn3ke_indirect_mac_read(struct ipn3ke_hw *hw, uint32_t *rd_data,
101 uint32_t addr, uint32_t mac_num, uint32_t eth_group_sel)
105 if (mac_num >= hw->port_num)
109 dev_sel = mac_num * 2 + 3;
111 return ipn3ke_indirect_read(hw, rd_data, addr, dev_sel, eth_group_sel);
115 ipn3ke_indirect_mac_write(struct ipn3ke_hw *hw, uint32_t wr_data,
116 uint32_t addr, uint32_t mac_num, uint32_t eth_group_sel)
120 if (mac_num >= hw->port_num)
124 dev_sel = mac_num * 2 + 3;
126 return ipn3ke_indirect_write(hw, wr_data, addr, dev_sel, eth_group_sel);
130 ipn3ke_hw_cap_init(struct ipn3ke_hw *hw)
132 hw->hw_cap.version_number = IPN3KE_MASK_READ_REG(hw,
133 (IPN3KE_HW_BASE + 0), 0, 0xFFFF);
134 hw->hw_cap.capability_registers_block_offset = IPN3KE_MASK_READ_REG(hw,
135 (IPN3KE_HW_BASE + 0x8), 0, 0xFFFFFFFF);
136 hw->hw_cap.status_registers_block_offset = IPN3KE_MASK_READ_REG(hw,
137 (IPN3KE_HW_BASE + 0x10), 0, 0xFFFFFFFF);
138 hw->hw_cap.control_registers_block_offset = IPN3KE_MASK_READ_REG(hw,
139 (IPN3KE_HW_BASE + 0x18), 0, 0xFFFFFFFF);
140 hw->hw_cap.classify_offset = IPN3KE_MASK_READ_REG(hw,
141 (IPN3KE_HW_BASE + 0x20), 0, 0xFFFFFFFF);
142 hw->hw_cap.classy_size = IPN3KE_MASK_READ_REG(hw,
143 (IPN3KE_HW_BASE + 0x24), 0, 0xFFFF);
144 hw->hw_cap.policer_offset = IPN3KE_MASK_READ_REG(hw,
145 (IPN3KE_HW_BASE + 0x28), 0, 0xFFFFFFFF);
146 hw->hw_cap.policer_entry_size = IPN3KE_MASK_READ_REG(hw,
147 (IPN3KE_HW_BASE + 0x2C), 0, 0xFFFF);
148 hw->hw_cap.rss_key_array_offset = IPN3KE_MASK_READ_REG(hw,
149 (IPN3KE_HW_BASE + 0x30), 0, 0xFFFFFFFF);
150 hw->hw_cap.rss_key_entry_size = IPN3KE_MASK_READ_REG(hw,
151 (IPN3KE_HW_BASE + 0x34), 0, 0xFFFF);
152 hw->hw_cap.rss_indirection_table_array_offset = IPN3KE_MASK_READ_REG(hw,
153 (IPN3KE_HW_BASE + 0x38), 0, 0xFFFFFFFF);
154 hw->hw_cap.rss_indirection_table_entry_size = IPN3KE_MASK_READ_REG(hw,
155 (IPN3KE_HW_BASE + 0x3C), 0, 0xFFFF);
156 hw->hw_cap.dmac_map_offset = IPN3KE_MASK_READ_REG(hw,
157 (IPN3KE_HW_BASE + 0x40), 0, 0xFFFFFFFF);
158 hw->hw_cap.dmac_map_size = IPN3KE_MASK_READ_REG(hw,
159 (IPN3KE_HW_BASE + 0x44), 0, 0xFFFF);
160 hw->hw_cap.qm_offset = IPN3KE_MASK_READ_REG(hw,
161 (IPN3KE_HW_BASE + 0x48), 0, 0xFFFFFFFF);
162 hw->hw_cap.qm_size = IPN3KE_MASK_READ_REG(hw,
163 (IPN3KE_HW_BASE + 0x4C), 0, 0xFFFF);
164 hw->hw_cap.ccb_offset = IPN3KE_MASK_READ_REG(hw,
165 (IPN3KE_HW_BASE + 0x50), 0, 0xFFFFFFFF);
166 hw->hw_cap.ccb_entry_size = IPN3KE_MASK_READ_REG(hw,
167 (IPN3KE_HW_BASE + 0x54), 0, 0xFFFF);
168 hw->hw_cap.qos_offset = IPN3KE_MASK_READ_REG(hw,
169 (IPN3KE_HW_BASE + 0x58), 0, 0xFFFFFFFF);
170 hw->hw_cap.qos_size = IPN3KE_MASK_READ_REG(hw,
171 (IPN3KE_HW_BASE + 0x5C), 0, 0xFFFF);
173 hw->hw_cap.num_rx_flow = IPN3KE_MASK_READ_REG(hw,
174 IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET,
176 hw->hw_cap.num_rss_blocks = IPN3KE_MASK_READ_REG(hw,
177 IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET,
179 hw->hw_cap.num_dmac_map = IPN3KE_MASK_READ_REG(hw,
180 IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET,
182 hw->hw_cap.num_tx_flow = IPN3KE_MASK_READ_REG(hw,
183 IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET,
185 hw->hw_cap.num_smac_map = IPN3KE_MASK_READ_REG(hw,
186 IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET,
189 hw->hw_cap.link_speed_mbps = IPN3KE_MASK_READ_REG(hw,
190 IPN3KE_STATUS_REGISTERS_BLOCK_OFFSET,
195 ipn3ke_vbng_init_done(struct ipn3ke_hw *hw)
197 uint32_t timeout = 10000;
198 while (timeout > 0) {
199 if (IPN3KE_READ_REG(hw, IPN3KE_VBNG_INIT_STS)
200 == IPN3KE_VBNG_INIT_DONE)
207 IPN3KE_AFU_PMD_ERR("IPN3KE vBNG INIT timeout.\n");
215 ipn3ke_hw_init(struct rte_afu_device *afu_dev,
216 struct ipn3ke_hw *hw)
218 struct rte_rawdev *rawdev;
221 uint64_t port_num, mac_type, index;
223 rawdev = afu_dev->rawdev;
225 hw->afu_id.uuid.uuid_low = afu_dev->id.uuid.uuid_low;
226 hw->afu_id.uuid.uuid_high = afu_dev->id.uuid.uuid_high;
227 hw->afu_id.port = afu_dev->id.port;
228 hw->hw_addr = (uint8_t *)(afu_dev->mem_resource[0].addr);
229 hw->f_mac_read = ipn3ke_indirect_mac_read;
230 hw->f_mac_write = ipn3ke_indirect_mac_write;
232 rawdev->dev_ops->attr_get(rawdev,
233 "LineSideBARIndex", &index);
234 hw->eth_group_bar[0] = (uint8_t *)(afu_dev->mem_resource[index].addr);
235 rawdev->dev_ops->attr_get(rawdev,
236 "NICSideBARIndex", &index);
237 hw->eth_group_bar[1] = (uint8_t *)(afu_dev->mem_resource[index].addr);
238 rawdev->dev_ops->attr_get(rawdev,
239 "LineSideLinkPortNum", &port_num);
240 hw->retimer.port_num = (int)port_num;
241 hw->port_num = hw->retimer.port_num;
242 rawdev->dev_ops->attr_get(rawdev,
243 "LineSideMACType", &mac_type);
244 hw->retimer.mac_type = (int)mac_type;
246 IPN3KE_AFU_PMD_DEBUG("UPL_version is 0x%x\n", IPN3KE_READ_REG(hw, 0));
248 if (afu_dev->id.uuid.uuid_low == IPN3KE_UUID_VBNG_LOW &&
249 afu_dev->id.uuid.uuid_high == IPN3KE_UUID_VBNG_HIGH) {
250 /* After power on, wait until init done */
251 if (ipn3ke_vbng_init_done(hw))
254 ipn3ke_hw_cap_init(hw);
257 IPN3KE_WRITE_REG(hw, IPN3KE_CTRL_RESET, 1);
259 IPN3KE_WRITE_REG(hw, IPN3KE_CTRL_RESET, 0);
261 /* After reset, wait until init done */
262 if (ipn3ke_vbng_init_done(hw))
266 if (hw->retimer.mac_type == IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI) {
267 /* Enable inter connect channel */
268 for (i = 0; i < hw->port_num; i++) {
269 /* Enable the TX path */
270 ipn3ke_xmac_tx_enable(hw, i, 1);
272 /* Disables source address override */
273 ipn3ke_xmac_smac_ovd_dis(hw, i, 1);
275 /* Enable the RX path */
276 ipn3ke_xmac_rx_enable(hw, i, 1);
278 /* Clear all TX statistics counters */
279 ipn3ke_xmac_tx_clr_stcs(hw, i, 1);
281 /* Clear all RX statistics counters */
282 ipn3ke_xmac_rx_clr_stcs(hw, i, 1);
286 ret = rte_eth_switch_domain_alloc(&hw->switch_domain_id);
288 IPN3KE_AFU_PMD_WARN("failed to allocate switch domain for device %d",
291 hw->tm_hw_enable = 0;
292 hw->flow_hw_enable = 0;
293 if (afu_dev->id.uuid.uuid_low == IPN3KE_UUID_VBNG_LOW &&
294 afu_dev->id.uuid.uuid_high == IPN3KE_UUID_VBNG_HIGH) {
295 ret = ipn3ke_hw_tm_init(hw);
298 hw->tm_hw_enable = 1;
300 ret = ipn3ke_flow_init(hw);
303 hw->flow_hw_enable = 1;
313 ipn3ke_hw_uninit(struct ipn3ke_hw *hw)
317 if (hw->retimer.mac_type == IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI) {
318 for (i = 0; i < hw->port_num; i++) {
319 /* Disable the TX path */
320 ipn3ke_xmac_tx_disable(hw, i, 1);
322 /* Disable the RX path */
323 ipn3ke_xmac_rx_disable(hw, i, 1);
325 /* Clear all TX statistics counters */
326 ipn3ke_xmac_tx_clr_stcs(hw, i, 1);
328 /* Clear all RX statistics counters */
329 ipn3ke_xmac_rx_clr_stcs(hw, i, 1);
334 static int ipn3ke_vswitch_probe(struct rte_afu_device *afu_dev)
336 char name[RTE_ETH_NAME_MAX_LEN];
337 struct ipn3ke_hw *hw;
340 /* check if the AFU device has been probed already */
341 /* allocate shared mcp_vswitch structure */
342 if (!afu_dev->shared.data) {
343 snprintf(name, sizeof(name), "net_%s_hw",
344 afu_dev->device.name);
345 hw = rte_zmalloc_socket(name,
346 sizeof(struct ipn3ke_hw),
348 afu_dev->device.numa_node);
350 IPN3KE_AFU_PMD_ERR("failed to allocate hardwart data");
354 afu_dev->shared.data = hw;
356 rte_spinlock_init(&afu_dev->shared.lock);
358 hw = afu_dev->shared.data;
361 retval = ipn3ke_hw_init(afu_dev, hw);
365 /* probe representor ports */
366 for (i = 0; i < hw->port_num; i++) {
367 struct ipn3ke_rpst rpst = {
369 .switch_domain_id = hw->switch_domain_id,
373 /* representor port net_bdf_port */
374 snprintf(name, sizeof(name), "net_%s_representor_%d",
375 afu_dev->device.name, i);
377 retval = rte_eth_dev_create(&afu_dev->device, name,
378 sizeof(struct ipn3ke_rpst), NULL, NULL,
379 ipn3ke_rpst_init, &rpst);
382 IPN3KE_AFU_PMD_ERR("failed to create ipn3ke representor %s.",
389 static int ipn3ke_vswitch_remove(struct rte_afu_device *afu_dev)
391 char name[RTE_ETH_NAME_MAX_LEN];
392 struct ipn3ke_hw *hw;
393 struct rte_eth_dev *ethdev;
396 hw = afu_dev->shared.data;
398 /* remove representor ports */
399 for (i = 0; i < hw->port_num; i++) {
400 /* representor port net_bdf_port */
401 snprintf(name, sizeof(name), "net_%s_representor_%d",
402 afu_dev->device.name, i);
404 ethdev = rte_eth_dev_allocated(afu_dev->device.name);
408 rte_eth_dev_destroy(ethdev, ipn3ke_rpst_uninit);
411 ret = rte_eth_switch_domain_free(hw->switch_domain_id);
413 IPN3KE_AFU_PMD_WARN("failed to free switch domain: %d", ret);
416 ipn3ke_hw_uninit(hw);
421 static struct rte_afu_driver afu_ipn3ke_driver = {
422 .id_table = afu_uuid_ipn3ke_map,
423 .probe = ipn3ke_vswitch_probe,
424 .remove = ipn3ke_vswitch_remove,
427 RTE_PMD_REGISTER_AFU(net_ipn3ke_afu, afu_ipn3ke_driver);
429 static const char * const valid_args[] = {
430 #define IPN3KE_AFU_NAME "afu"
432 #define IPN3KE_FPGA_ACCELERATION_LIST "fpga_acc"
433 IPN3KE_FPGA_ACCELERATION_LIST,
434 #define IPN3KE_I40E_PF_LIST "i40e_pf"
440 ipn3ke_cfg_parse_acc_list(const char *afu_name,
441 const char *acc_list_name)
443 struct rte_afu_device *afu_dev;
444 struct ipn3ke_hw *hw;
445 const char *p_source;
447 char name[RTE_ETH_NAME_MAX_LEN];
449 afu_dev = rte_ifpga_find_afu_by_name(afu_name);
452 hw = afu_dev->shared.data;
456 p_source = acc_list_name;
458 while ((*p_source == '{') || (*p_source == '|'))
461 while ((*p_source != '|') && (*p_source != '}'))
462 *p_start++ = *p_source++;
464 if (!strcmp(name, "tm") && hw->tm_hw_enable)
467 if (!strcmp(name, "flow") && hw->flow_hw_enable)
470 if (*p_source == '}')
478 ipn3ke_cfg_parse_i40e_pf_ethdev(const char *afu_name,
481 struct rte_eth_dev *i40e_eth, *rpst_eth;
482 struct rte_afu_device *afu_dev;
483 struct ipn3ke_rpst *rpst;
484 struct ipn3ke_hw *hw;
485 const char *p_source;
487 char name[RTE_ETH_NAME_MAX_LEN];
492 afu_dev = rte_ifpga_find_afu_by_name(afu_name);
495 hw = afu_dev->shared.data;
500 for (i = 0; i < hw->port_num; i++) {
501 snprintf(name, sizeof(name), "net_%s_representor_%d",
503 ret = rte_eth_dev_get_port_by_name(name, &port_id);
506 rpst_eth = &rte_eth_devices[port_id];
507 rpst = IPN3KE_DEV_PRIVATE_TO_RPST(rpst_eth);
509 while ((*p_source == '{') || (*p_source == '|'))
512 while ((*p_source != '|') && (*p_source != '}'))
513 *p_start++ = *p_source++;
516 ret = rte_eth_dev_get_port_by_name(name, &port_id);
519 i40e_eth = &rte_eth_devices[port_id];
521 rpst->i40e_pf_eth = i40e_eth;
522 rpst->i40e_pf_eth_port_id = port_id;
524 if ((*p_source == '}') || !(*p_source))
532 ipn3ke_cfg_probe(struct rte_vdev_device *dev)
534 struct rte_devargs *devargs;
535 struct rte_kvargs *kvlist = NULL;
536 char *afu_name = NULL;
537 char *acc_name = NULL;
538 char *pf_name = NULL;
544 devargs = dev->device.devargs;
546 kvlist = rte_kvargs_parse(devargs->args, valid_args);
548 IPN3KE_AFU_PMD_ERR("error when parsing param");
552 if (rte_kvargs_count(kvlist, IPN3KE_AFU_NAME) == 1) {
553 if (rte_kvargs_process(kvlist, IPN3KE_AFU_NAME,
554 &rte_ifpga_get_string_arg,
556 IPN3KE_AFU_PMD_ERR("error to parse %s",
564 if (rte_kvargs_count(kvlist, IPN3KE_FPGA_ACCELERATION_LIST) == 1) {
565 if (rte_kvargs_process(kvlist, IPN3KE_FPGA_ACCELERATION_LIST,
566 &rte_ifpga_get_string_arg,
568 IPN3KE_AFU_PMD_ERR("error to parse %s",
569 IPN3KE_FPGA_ACCELERATION_LIST);
576 if (rte_kvargs_count(kvlist, IPN3KE_I40E_PF_LIST) == 1) {
577 if (rte_kvargs_process(kvlist, IPN3KE_I40E_PF_LIST,
578 &rte_ifpga_get_string_arg,
580 IPN3KE_AFU_PMD_ERR("error to parse %s",
581 IPN3KE_I40E_PF_LIST);
589 IPN3KE_AFU_PMD_ERR("arg %s is mandatory for ipn3ke",
595 IPN3KE_AFU_PMD_ERR("arg %s is mandatory for ipn3ke",
596 IPN3KE_I40E_PF_LIST);
601 ret = ipn3ke_cfg_parse_acc_list(afu_name, acc_name);
603 IPN3KE_AFU_PMD_ERR("arg %s parse error for ipn3ke",
604 IPN3KE_FPGA_ACCELERATION_LIST);
608 IPN3KE_AFU_PMD_INFO("arg %s is optional for ipn3ke, using i40e acc",
609 IPN3KE_FPGA_ACCELERATION_LIST);
612 ret = ipn3ke_cfg_parse_i40e_pf_ethdev(afu_name, pf_name);
617 rte_kvargs_free(kvlist);
627 ipn3ke_cfg_remove(struct rte_vdev_device *dev)
629 struct rte_devargs *devargs;
630 struct rte_kvargs *kvlist = NULL;
631 char *afu_name = NULL;
632 struct rte_afu_device *afu_dev;
635 devargs = dev->device.devargs;
637 kvlist = rte_kvargs_parse(devargs->args, valid_args);
639 IPN3KE_AFU_PMD_ERR("error when parsing param");
643 if (rte_kvargs_count(kvlist, IPN3KE_AFU_NAME) == 1) {
644 if (rte_kvargs_process(kvlist, IPN3KE_AFU_NAME,
645 &rte_ifpga_get_string_arg,
647 IPN3KE_AFU_PMD_ERR("error to parse %s",
650 afu_dev = rte_ifpga_find_afu_by_name(afu_name);
653 ret = ipn3ke_vswitch_remove(afu_dev);
656 IPN3KE_AFU_PMD_ERR("Remove ipn3ke_cfg %p error", dev);
661 rte_kvargs_free(kvlist);
666 static struct rte_vdev_driver ipn3ke_cfg_driver = {
667 .probe = ipn3ke_cfg_probe,
668 .remove = ipn3ke_cfg_remove,
671 RTE_PMD_REGISTER_VDEV(ipn3ke_cfg, ipn3ke_cfg_driver);
672 RTE_PMD_REGISTER_PARAM_STRING(ipn3ke_cfg,
677 RTE_INIT(ipn3ke_afu_init_log)
679 ipn3ke_afu_logtype = rte_log_register("pmd.afu.ipn3ke");
680 if (ipn3ke_afu_logtype >= 0)
681 rte_log_set_level(ipn3ke_afu_logtype, RTE_LOG_NOTICE);