drivers/net/ipn3ke/ipn3ke_ethdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2019 Intel Corporation
   3  */
   4
   5 #ifndef _IPN3KE_ETHDEV_H_
   6 #define _IPN3KE_ETHDEV_H_
   7
   8 #include <stdbool.h>
   9 #include <stddef.h>
  10 #include <stdint.h>
  11 #include <limits.h>
  12 #include <net/if.h>
  13 #include <netinet/in.h>
  14 #include <sys/queue.h>
  15
  16 #include <rte_mbuf.h>
  17 #include <rte_flow_driver.h>
  18 #include <ethdev_driver.h>
  19 #include <ethdev_vdev.h>
  20 #include <rte_malloc.h>
  21 #include <rte_memcpy.h>
  22 #include <rte_bus_vdev.h>
  23 #include <rte_kvargs.h>
  24 #include <rte_spinlock.h>
  25
  26 #include <rte_cycles.h>
  27 #include <rte_bus_ifpga.h>
  28 #include <rte_tm_driver.h>
  29
  30 #define IPN3KE_TM_SCRATCH_RW 0
  31
  32 /* TM Levels */
  33 enum ipn3ke_tm_node_level {
  34         IPN3KE_TM_NODE_LEVEL_PORT,
  35         IPN3KE_TM_NODE_LEVEL_VT,
  36         IPN3KE_TM_NODE_LEVEL_COS,
  37         IPN3KE_TM_NODE_LEVEL_MAX,
  38 };
  39
  40 /* TM Shaper Profile */
  41 struct ipn3ke_tm_shaper_profile {
  42         uint32_t valid;
  43         uint32_t m;
  44         uint32_t e;
  45         uint64_t rate;
  46         struct rte_tm_shaper_params params;
  47 };
  48
  49 TAILQ_HEAD(ipn3ke_tm_shaper_profile_list, ipn3ke_tm_shaper_profile);
  50
  51
  52 #define IPN3KE_TDROP_TH1_MASK  0x1ffffff
  53 #define IPN3KE_TDROP_TH1_SHIFT (25)
  54 #define IPN3KE_TDROP_TH2_MASK  0x1ffffff
  55
  56 /* TM TDROP Profile */
  57 struct ipn3ke_tm_tdrop_profile {
  58         uint32_t tdrop_profile_id;
  59         uint32_t th1;
  60         uint32_t th2;
  61         uint32_t n_users;
  62         uint32_t valid;
  63         struct rte_tm_wred_params params;
  64 };
  65
  66 /* TM node priority */
  67 enum ipn3ke_tm_node_state {
  68         IPN3KE_TM_NODE_STATE_IDLE = 0,
  69         IPN3KE_TM_NODE_STATE_CONFIGURED_ADD,
  70         IPN3KE_TM_NODE_STATE_CONFIGURED_DEL,
  71         IPN3KE_TM_NODE_STATE_COMMITTED,
  72         IPN3KE_TM_NODE_STATE_MAX,
  73 };
  74
  75 TAILQ_HEAD(ipn3ke_tm_node_list, ipn3ke_tm_node);
  76
  77 /* IPN3KE TM Node */
  78 struct ipn3ke_tm_node {
  79         TAILQ_ENTRY(ipn3ke_tm_node) node;
  80         uint32_t node_index;
  81         uint32_t level;
  82         uint32_t tm_id;
  83         enum ipn3ke_tm_node_state node_state;
  84         uint32_t parent_node_id;
  85         uint32_t priority;
  86         uint32_t weight;
  87         struct ipn3ke_tm_node *parent_node;
  88         struct ipn3ke_tm_shaper_profile shaper_profile;
  89         struct ipn3ke_tm_tdrop_profile *tdrop_profile;
  90         struct rte_tm_node_params params;
  91         struct rte_tm_node_stats stats;
  92         uint32_t n_children;
  93         struct ipn3ke_tm_node_list children_node_list;
  94 };
  95
  96 /* IPN3KE TM Hierarchy Specification */
  97 struct ipn3ke_tm_hierarchy {
  98         struct ipn3ke_tm_node *port_node;
  99         uint32_t n_shaper_profiles;
 100         uint32_t n_tdrop_profiles;
 101         uint32_t n_vt_nodes;
 102         uint32_t n_cos_nodes;
 103         struct ipn3ke_tm_node *port_commit_node;
 104         struct ipn3ke_tm_node_list vt_commit_node_list;
 105         struct ipn3ke_tm_node_list cos_commit_node_list;
 106 };
 107
 108 struct ipn3ke_tm_internals {
 109         /** Hierarchy specification
 110          *
 111          *     -Hierarchy is unfrozen at init and when port is stopped.
 112          *     -Hierarchy is frozen on successful hierarchy commit.
 113          *     -Run-time hierarchy changes are not allowed, therefore it makes
 114          *      sense to keep the hierarchy frozen after the port is started.
 115          */
 116         struct ipn3ke_tm_hierarchy h;
 117         int hierarchy_frozen;
 118         int tm_started;
 119         uint32_t tm_id;
 120 };
 121
 122 #define IPN3KE_TM_COS_NODE_NUM      (64 * 1024)
 123 #define IPN3KE_TM_VT_NODE_NUM       (IPN3KE_TM_COS_NODE_NUM / 8)
 124 #define IPN3KE_TM_10G_PORT_NODE_NUM (8)
 125 #define IPN3KE_TM_25G_PORT_NODE_NUM (4)
 126
 127 #define IPN3KE_TM_NODE_LEVEL_MOD    (100000)
 128 #define IPN3KE_TM_NODE_MOUNT_MAX    (8)
 129
 130 #define IPN3KE_TM_TDROP_PROFILE_NUM (2 * 1024)
 131
 132 /* TM node priority */
 133 enum ipn3ke_tm_node_priority {
 134         IPN3KE_TM_NODE_PRIORITY_NORMAL0 = 0,
 135         IPN3KE_TM_NODE_PRIORITY_LOW,
 136         IPN3KE_TM_NODE_PRIORITY_NORMAL1,
 137         IPN3KE_TM_NODE_PRIORITY_HIGHEST,
 138 };
 139
 140 #define IPN3KE_TM_NODE_WEIGHT_MAX UINT8_MAX
 141
 142 /** Set a bit in the uint32 variable */
 143 #define IPN3KE_BIT_SET(var, pos) \
 144         ((var) |= ((uint32_t)1 << ((pos))))
 145
 146 /** Reset the bit in the variable */
 147 #define IPN3KE_BIT_RESET(var, pos) \
 148         ((var) &= ~((uint32_t)1 << ((pos))))
 149
 150 /** Check the bit is set in the variable */
 151 #define IPN3KE_BIT_ISSET(var, pos) \
 152         (((var) & ((uint32_t)1 << ((pos)))) ? 1 : 0)
 153
 154 struct ipn3ke_hw;
 155
 156 #define IPN3KE_HW_BASE               0x4000000
 157
 158 #define IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET \
 159         (IPN3KE_HW_BASE + hw->hw_cap.capability_registers_block_offset)
 160
 161 #define IPN3KE_STATUS_REGISTERS_BLOCK_OFFSET \
 162         (IPN3KE_HW_BASE + hw->hw_cap.status_registers_block_offset)
 163
 164 #define IPN3KE_CTRL_RESET \
 165         (IPN3KE_HW_BASE + hw->hw_cap.control_registers_block_offset)
 166
 167 #define IPN3KE_CTRL_MTU \
 168         (IPN3KE_HW_BASE + hw->hw_cap.control_registers_block_offset + 4)
 169
 170 #define IPN3KE_CLASSIFY_OFFSET \
 171         (IPN3KE_HW_BASE + hw->hw_cap.classify_offset)
 172
 173 #define IPN3KE_POLICER_OFFSET \
 174         (IPN3KE_HW_BASE + hw->hw_cap.policer_offset)
 175
 176 #define IPN3KE_RSS_KEY_ARRAY_OFFSET \
 177         (IPN3KE_HW_BASE + hw->hw_cap.rss_key_array_offset)
 178
 179 #define IPN3KE_RSS_INDIRECTION_TABLE_ARRAY_OFFSET \
 180         (IPN3KE_HW_BASE + hw->hw_cap.rss_indirection_table_array_offset)
 181
 182 #define IPN3KE_DMAC_MAP_OFFSET \
 183         (IPN3KE_HW_BASE + hw->hw_cap.dmac_map_offset)
 184
 185 #define IPN3KE_QM_OFFSET \
 186         (IPN3KE_HW_BASE + hw->hw_cap.qm_offset)
 187
 188 #define IPN3KE_CCB_OFFSET \
 189         (IPN3KE_HW_BASE + hw->hw_cap.ccb_offset)
 190
 191 #define IPN3KE_QOS_OFFSET \
 192         (IPN3KE_HW_BASE + hw->hw_cap.qos_offset)
 193
 194 struct ipn3ke_hw_cap {
 195         uint32_t version_number;
 196         uint32_t capability_registers_block_offset;
 197         uint32_t status_registers_block_offset;
 198         uint32_t control_registers_block_offset;
 199         uint32_t classify_offset;
 200         uint32_t classy_size;
 201         uint32_t policer_offset;
 202         uint32_t policer_entry_size;
 203         uint32_t rss_key_array_offset;
 204         uint32_t rss_key_entry_size;
 205         uint32_t rss_indirection_table_array_offset;
 206         uint32_t rss_indirection_table_entry_size;
 207         uint32_t dmac_map_offset;
 208         uint32_t dmac_map_size;
 209         uint32_t qm_offset;
 210         uint32_t qm_size;
 211         uint32_t ccb_offset;
 212         uint32_t ccb_entry_size;
 213         uint32_t qos_offset;
 214         uint32_t qos_size;
 215
 216         uint32_t num_rx_flow;    /* Default: 64K */
 217         uint32_t num_rss_blocks; /* Default: 512 */
 218         uint32_t num_dmac_map;   /* Default: 1K */
 219         uint32_t num_tx_flow;    /* Default: 64K */
 220         uint32_t num_smac_map;   /* Default: 1K */
 221
 222         uint32_t link_speed_mbps;
 223 };
 224
 225 /**
 226  * Strucute to store private data for each representor instance
 227  */
 228 struct ipn3ke_rpst {
 229         TAILQ_ENTRY(ipn3ke_rpst) next;       /**< Next in device list. */
 230         uint16_t switch_domain_id;
 231         /**< Switch ID */
 232         uint16_t port_id;
 233         struct rte_eth_dev *ethdev;
 234         /**< Port ID */
 235         struct ipn3ke_hw *hw;
 236         struct rte_eth_dev *i40e_pf_eth;
 237         uint16_t i40e_pf_eth_port_id;
 238         struct rte_eth_link ori_linfo;
 239         struct ipn3ke_tm_internals tm;
 240         /**< Private data store of assocaiated physical function */
 241         struct rte_ether_addr mac_addr;
 242 };
 243
 244 /* UUID IDs */
 245 #define MAP_UUID_10G_LOW                0xffffffffffffffff
 246 #define MAP_UUID_10G_HIGH               0xffffffffffffffff
 247 #define IPN3KE_UUID_10G_LOW             0xc000c9660d824272
 248 #define IPN3KE_UUID_10G_HIGH            0x9aeffe5f84570612
 249 #define IPN3KE_UUID_VBNG_LOW            0x8991165349d23ff9
 250 #define IPN3KE_UUID_VBNG_HIGH           0xb74cf419d15a481f
 251 #define IPN3KE_UUID_25G_LOW             0xb7d9bac566bfbc80
 252 #define IPN3KE_UUID_25G_HIGH            0xb07bac1aeef54d67
 253
 254 #define IPN3KE_AFU_BUF_SIZE_MIN         1024
 255 #define IPN3KE_AFU_FRAME_SIZE_MAX       9728
 256
 257 #define IPN3KE_RAWDEV_ATTR_LEN_MAX      (64)
 258
 259 typedef int (*ipn3ke_indirect_mac_read_t)(struct ipn3ke_hw *hw,
 260         uint32_t *rd_data, uint32_t addr, uint32_t mac_num,
 261         uint32_t eth_wrapper_sel);
 262
 263 typedef int (*ipn3ke_indirect_mac_write_t)(struct ipn3ke_hw *hw,
 264         uint32_t wr_data, uint32_t addr, uint32_t mac_num,
 265         uint32_t eth_wrapper_sel);
 266
 267 struct ipn3ke_hw {
 268         struct rte_eth_dev *eth_dev;
 269
 270         /* afu info */
 271         struct rte_afu_id afu_id;
 272         struct rte_rawdev *rawdev;
 273
 274         struct ipn3ke_hw_cap hw_cap;
 275
 276         struct ifpga_rawdevg_retimer_info retimer;
 277
 278         uint16_t switch_domain_id;
 279         uint16_t port_num;
 280
 281         uint32_t tm_hw_enable;
 282         uint32_t flow_hw_enable;
 283
 284         uint32_t acc_tm;
 285         uint32_t acc_flow;
 286
 287         struct ipn3ke_flow_list flow_list;
 288         uint32_t flow_max_entries;
 289         uint32_t flow_num_entries;
 290
 291         struct ipn3ke_tm_node *nodes;
 292         struct ipn3ke_tm_node *port_nodes;
 293         struct ipn3ke_tm_node *vt_nodes;
 294         struct ipn3ke_tm_node *cos_nodes;
 295
 296         struct ipn3ke_tm_tdrop_profile *tdrop_profile;
 297         uint32_t tdrop_profile_num;
 298
 299         uint32_t ccb_status;
 300         uint32_t ccb_seg_free;
 301         uint32_t ccb_seg_num;
 302         uint32_t ccb_seg_k;
 303
 304         uint8_t *eth_group_bar[2];
 305         /**< MAC Register read */
 306         ipn3ke_indirect_mac_read_t f_mac_read;
 307         /**< MAC Register write */
 308         ipn3ke_indirect_mac_write_t f_mac_write;
 309
 310         uint8_t *hw_addr;
 311 };
 312
 313 /**
 314  * @internal
 315  * Helper macro for drivers that need to convert to struct rte_afu_device.
 316  */
 317 #define RTE_DEV_TO_AFU(ptr) \
 318         container_of(ptr, struct rte_afu_device, device)
 319
 320 #define RTE_DEV_TO_AFU_CONST(ptr) \
 321         container_of(ptr, const struct rte_afu_device, device)
 322
 323 #define RTE_ETH_DEV_TO_AFU(eth_dev) \
 324         RTE_DEV_TO_AFU((eth_dev)->device)
 325
 326 /**
 327  * PCIe MMIO Access
 328  */
 329
 330 #define IPN3KE_PCI_REG(reg)    rte_read32(reg)
 331 #define IPN3KE_PCI_REG_ADDR(a, reg) \
 332         ((volatile uint32_t *)((char *)(a)->hw_addr + (reg)))
 333 static inline uint32_t ipn3ke_read_addr(volatile void *addr)
 334 {
 335         return rte_le_to_cpu_32(IPN3KE_PCI_REG(addr));
 336 }
 337
 338 #define WCMD 0x8000000000000000
 339 #define RCMD 0x4000000000000000
 340 #define INDRCT_CTRL 0x30
 341 #define INDRCT_STS 0x38
 342 static inline uint32_t _ipn3ke_indrct_read(struct ipn3ke_hw *hw,
 343                 uint32_t addr)
 344 {
 345         uint64_t word_offset;
 346         uint64_t read_data = 0;
 347         uint64_t indirect_value;
 348         volatile void *indirect_addrs;
 349
 350         word_offset = (addr & 0x1FFFFFF) >> 2;
 351         indirect_value = RCMD | word_offset << 32;
 352         indirect_addrs = hw->hw_addr + (uint32_t)(INDRCT_CTRL);
 353
 354         rte_delay_us(10);
 355
 356         rte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs);
 357
 358         indirect_addrs = hw->hw_addr + (uint32_t)(INDRCT_STS);
 359         while ((read_data >> 32) != 1)
 360                 read_data = rte_read64(indirect_addrs);
 361
 362         return rte_le_to_cpu_32(read_data);
 363 }
 364
 365 static inline void _ipn3ke_indrct_write(struct ipn3ke_hw *hw,
 366                 uint32_t addr, uint32_t value)
 367 {
 368         uint64_t word_offset;
 369         uint64_t indirect_value;
 370         volatile void *indirect_addrs = 0;
 371
 372         word_offset = (addr & 0x1FFFFFF) >> 2;
 373         indirect_value = WCMD | word_offset << 32 | value;
 374         indirect_addrs = hw->hw_addr + (uint32_t)(INDRCT_CTRL);
 375
 376         rte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs);
 377         rte_delay_us(10);
 378 }
 379
 380 #define IPN3KE_PCI_REG_WRITE(reg, value) \
 381         rte_write32((rte_cpu_to_le_32(value)), reg)
 382
 383 #define IPN3KE_PCI_REG_WRITE_RELAXED(reg, value) \
 384         rte_write32_relaxed((rte_cpu_to_le_32(value)), reg)
 385
 386 #define IPN3KE_READ_REG(hw, reg) \
 387         _ipn3ke_indrct_read((hw), (reg))
 388
 389 #define IPN3KE_WRITE_REG(hw, reg, value) \
 390         _ipn3ke_indrct_write((hw), (reg), (value))
 391
 392 #define IPN3KE_MASK_READ_REG(hw, reg, x, mask) \
 393         ((mask) & IPN3KE_READ_REG((hw), ((reg) + (0x4 * (x)))))
 394
 395 #define IPN3KE_MASK_WRITE_REG(hw, reg, x, value, mask) \
 396         IPN3KE_WRITE_REG((hw), ((reg) + (0x4 * (x))), ((mask) & (value)))
 397
 398 #define IPN3KE_DEV_PRIVATE_TO_HW(dev) \
 399         (((struct ipn3ke_rpst *)(dev)->data->dev_private)->hw)
 400
 401 #define IPN3KE_DEV_PRIVATE_TO_RPST(dev) \
 402         ((struct ipn3ke_rpst *)(dev)->data->dev_private)
 403
 404 #define IPN3KE_DEV_PRIVATE_TO_TM(dev) \
 405         (&(((struct ipn3ke_rpst *)(dev)->data->dev_private)->tm))
 406
 407 #define IPN3KE_VBNG_INIT_DONE                      (0x3)
 408 #define IPN3KE_VBNG_INIT_STS                      (0x204)
 409
 410 /* Byte address of IPN3KE internal module */
 411 #define IPN3KE_TM_VERSION                     (IPN3KE_QM_OFFSET + 0x0000)
 412 #define IPN3KE_TM_SCRATCH                     (IPN3KE_QM_OFFSET + 0x0004)
 413 #define IPN3KE_TM_STATUS                      (IPN3KE_QM_OFFSET + 0x0008)
 414 #define IPN3KE_TM_MISC_STATUS                 (IPN3KE_QM_OFFSET + 0x0010)
 415 #define IPN3KE_TM_MISC_WARNING_0              (IPN3KE_QM_OFFSET + 0x0040)
 416 #define IPN3KE_TM_MISC_MON_0                  (IPN3KE_QM_OFFSET + 0x0048)
 417 #define IPN3KE_TM_MISC_FATAL_0                (IPN3KE_QM_OFFSET + 0x0050)
 418 #define IPN3KE_TM_BW_MON_CTRL_1               (IPN3KE_QM_OFFSET + 0x0080)
 419 #define IPN3KE_TM_BW_MON_CTRL_2               (IPN3KE_QM_OFFSET + 0x0084)
 420 #define IPN3KE_TM_BW_MON_RATE                 (IPN3KE_QM_OFFSET + 0x0088)
 421 #define IPN3KE_TM_STATS_CTRL                  (IPN3KE_QM_OFFSET + 0x0100)
 422 #define IPN3KE_TM_STATS_DATA_0                (IPN3KE_QM_OFFSET + 0x0110)
 423 #define IPN3KE_TM_STATS_DATA_1                (IPN3KE_QM_OFFSET + 0x0114)
 424 #define IPN3KE_QM_UID_CONFIG_CTRL             (IPN3KE_QM_OFFSET + 0x0200)
 425 #define IPN3KE_QM_UID_CONFIG_DATA             (IPN3KE_QM_OFFSET + 0x0204)
 426
 427 #define IPN3KE_BM_VERSION                     (IPN3KE_QM_OFFSET + 0x4000)
 428 #define IPN3KE_BM_STATUS                      (IPN3KE_QM_OFFSET + 0x4008)
 429 #define IPN3KE_BM_STORE_CTRL                  (IPN3KE_QM_OFFSET + 0x4010)
 430 #define IPN3KE_BM_STORE_STATUS                (IPN3KE_QM_OFFSET + 0x4018)
 431 #define IPN3KE_BM_STORE_MON                   (IPN3KE_QM_OFFSET + 0x4028)
 432 #define IPN3KE_BM_WARNING_0                   (IPN3KE_QM_OFFSET + 0x4040)
 433 #define IPN3KE_BM_MON_0                       (IPN3KE_QM_OFFSET + 0x4048)
 434 #define IPN3KE_BM_FATAL_0                     (IPN3KE_QM_OFFSET + 0x4050)
 435 #define IPN3KE_BM_DRAM_ACCESS_CTRL            (IPN3KE_QM_OFFSET + 0x4100)
 436 #define IPN3KE_BM_DRAM_ACCESS_DATA_0          (IPN3KE_QM_OFFSET + 0x4120)
 437 #define IPN3KE_BM_DRAM_ACCESS_DATA_1          (IPN3KE_QM_OFFSET + 0x4124)
 438 #define IPN3KE_BM_DRAM_ACCESS_DATA_2          (IPN3KE_QM_OFFSET + 0x4128)
 439 #define IPN3KE_BM_DRAM_ACCESS_DATA_3          (IPN3KE_QM_OFFSET + 0x412C)
 440 #define IPN3KE_BM_DRAM_ACCESS_DATA_4          (IPN3KE_QM_OFFSET + 0x4130)
 441 #define IPN3KE_BM_DRAM_ACCESS_DATA_5          (IPN3KE_QM_OFFSET + 0x4134)
 442 #define IPN3KE_BM_DRAM_ACCESS_DATA_6          (IPN3KE_QM_OFFSET + 0x4138)
 443
 444 #define IPN3KE_QM_VERSION                     (IPN3KE_QM_OFFSET + 0x8000)
 445 #define IPN3KE_QM_STATUS                      (IPN3KE_QM_OFFSET + 0x8008)
 446 #define IPN3KE_QM_LL_TABLE_MON                (IPN3KE_QM_OFFSET + 0x8018)
 447 #define IPN3KE_QM_WARNING_0                   (IPN3KE_QM_OFFSET + 0x8040)
 448 #define IPN3KE_QM_MON_0                       (IPN3KE_QM_OFFSET + 0x8048)
 449 #define IPN3KE_QM_FATAL_0                     (IPN3KE_QM_OFFSET + 0x8050)
 450 #define IPN3KE_QM_FATAL_1                     (IPN3KE_QM_OFFSET + 0x8054)
 451 #define IPN3KE_LL_TABLE_ACCESS_CTRL           (IPN3KE_QM_OFFSET + 0x8100)
 452 #define IPN3KE_LL_TABLE_ACCESS_DATA_0         (IPN3KE_QM_OFFSET + 0x8110)
 453 #define IPN3KE_LL_TABLE_ACCESS_DATA_1         (IPN3KE_QM_OFFSET + 0x8114)
 454
 455 #define IPN3KE_CCB_ERROR                      (IPN3KE_CCB_OFFSET + 0x0008)
 456 #define IPN3KE_CCB_NSEGFREE                   (IPN3KE_CCB_OFFSET + 0x200000)
 457 #define IPN3KE_CCB_NSEGFREE_MASK               0x3FFFFF
 458 #define IPN3KE_CCB_PSEGMAX_COEF               (IPN3KE_CCB_OFFSET + 0x200008)
 459 #define IPN3KE_CCB_PSEGMAX_COEF_MASK           0xFFFFF
 460 #define IPN3KE_CCB_NSEG_P                     (IPN3KE_CCB_OFFSET + 0x200080)
 461 #define IPN3KE_CCB_NSEG_MASK                   0x3FFFFF
 462 #define IPN3KE_CCB_QPROFILE_Q                 (IPN3KE_CCB_OFFSET + 0x240000)
 463 #define IPN3KE_CCB_QPROFILE_MASK               0x7FF
 464 #define IPN3KE_CCB_PROFILE_P                  (IPN3KE_CCB_OFFSET + 0x280000)
 465 #define IPN3KE_CCB_PROFILE_MASK                0x1FFFFFF
 466 #define IPN3KE_CCB_PROFILE_MS                 (IPN3KE_CCB_OFFSET + 0xC)
 467 #define IPN3KE_CCB_PROFILE_MS_MASK             0x1FFFFFF
 468 #define IPN3KE_CCB_LR_LB_DBG_CTRL             (IPN3KE_CCB_OFFSET + 0x2C0000)
 469 #define IPN3KE_CCB_LR_LB_DBG_DONE             (IPN3KE_CCB_OFFSET + 0x2C0004)
 470 #define IPN3KE_CCB_LR_LB_DBG_RDATA            (IPN3KE_CCB_OFFSET + 0x2C000C)
 471
 472 #define IPN3KE_QOS_MAP_L1_X                   (IPN3KE_QOS_OFFSET + 0x000000)
 473 #define IPN3KE_QOS_MAP_L1_MASK                 0x1FFF
 474 #define IPN3KE_QOS_MAP_L2_X                   (IPN3KE_QOS_OFFSET + 0x040000)
 475 #define IPN3KE_QOS_MAP_L2_MASK                 0x7
 476 #define IPN3KE_QOS_TYPE_MASK                   0x3
 477 #define IPN3KE_QOS_TYPE_L1_X                  (IPN3KE_QOS_OFFSET + 0x200000)
 478 #define IPN3KE_QOS_TYPE_L2_X                  (IPN3KE_QOS_OFFSET + 0x240000)
 479 #define IPN3KE_QOS_TYPE_L3_X                  (IPN3KE_QOS_OFFSET + 0x280000)
 480 #define IPN3KE_QOS_SCH_WT_MASK                 0xFF
 481 #define IPN3KE_QOS_SCH_WT_L1_X                (IPN3KE_QOS_OFFSET + 0x400000)
 482 #define IPN3KE_QOS_SCH_WT_L2_X                (IPN3KE_QOS_OFFSET + 0x440000)
 483 #define IPN3KE_QOS_SCH_WT_L3_X                (IPN3KE_QOS_OFFSET + 0x480000)
 484 #define IPN3KE_QOS_SHAP_WT_MASK                0x3FFF
 485 #define IPN3KE_QOS_SHAP_WT_L1_X               (IPN3KE_QOS_OFFSET + 0x600000)
 486 #define IPN3KE_QOS_SHAP_WT_L2_X               (IPN3KE_QOS_OFFSET + 0x640000)
 487 #define IPN3KE_QOS_SHAP_WT_L3_X               (IPN3KE_QOS_OFFSET + 0x680000)
 488
 489 #define IPN3KE_CLF_BASE_DST_MAC_ADDR_HI       (IPN3KE_CLASSIFY_OFFSET + 0x0000)
 490 #define IPN3KE_CLF_BASE_DST_MAC_ADDR_LOW      (IPN3KE_CLASSIFY_OFFSET + 0x0004)
 491 #define IPN3KE_CLF_QINQ_STAG                  (IPN3KE_CLASSIFY_OFFSET + 0x0008)
 492 #define IPN3KE_CLF_LKUP_ENABLE                (IPN3KE_CLASSIFY_OFFSET + 0x000C)
 493 #define IPN3KE_CLF_DFT_FLOW_ID                (IPN3KE_CLASSIFY_OFFSET + 0x0040)
 494 #define IPN3KE_CLF_RX_PARSE_CFG               (IPN3KE_CLASSIFY_OFFSET + 0x0080)
 495 #define IPN3KE_CLF_RX_STATS_CFG               (IPN3KE_CLASSIFY_OFFSET + 0x00C0)
 496 #define IPN3KE_CLF_RX_STATS_RPT               (IPN3KE_CLASSIFY_OFFSET + 0x00C4)
 497 #define IPN3KE_CLF_RX_TEST                    (IPN3KE_CLASSIFY_OFFSET + 0x0400)
 498
 499 #define IPN3KE_CLF_EM_VERSION       (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0000)
 500 #define IPN3KE_CLF_EM_NUM           (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0008)
 501 #define IPN3KE_CLF_EM_KEY_WDTH      (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x000C)
 502 #define IPN3KE_CLF_EM_RES_WDTH      (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0010)
 503 #define IPN3KE_CLF_EM_ALARMS        (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0014)
 504 #define IPN3KE_CLF_EM_DRC_RLAT      (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0018)
 505
 506 #define IPN3KE_CLF_MHL_VERSION      (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x0000)
 507 #define IPN3KE_CLF_MHL_GEN_CTRL     (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x0018)
 508 #define IPN3KE_CLF_MHL_MGMT_CTRL    (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x0020)
 509 #define IPN3KE_CLF_MHL_MGMT_CTRL_BIT_BUSY      31
 510 #define IPN3KE_CLF_MHL_MGMT_CTRL_FLUSH         0x0
 511 #define IPN3KE_CLF_MHL_MGMT_CTRL_INSERT        0x1
 512 #define IPN3KE_CLF_MHL_MGMT_CTRL_DELETE        0x2
 513 #define IPN3KE_CLF_MHL_MGMT_CTRL_SEARCH        0x3
 514 #define IPN3KE_CLF_MHL_FATAL_0     (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x0050)
 515 #define IPN3KE_CLF_MHL_MON_0       (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x0060)
 516 #define IPN3KE_CLF_MHL_TOTAL_ENTRIES   (IPN3KE_CLASSIFY_OFFSET + \
 517                                         0x50000 + 0x0080)
 518 #define IPN3KE_CLF_MHL_ONEHIT_BUCKETS  (IPN3KE_CLASSIFY_OFFSET + \
 519                                         0x50000 + 0x0084)
 520 #define IPN3KE_CLF_MHL_KEY_MASK         0xFFFFFFFF
 521 #define IPN3KE_CLF_MHL_KEY_0       (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x1000)
 522 #define IPN3KE_CLF_MHL_KEY_1       (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x1004)
 523 #define IPN3KE_CLF_MHL_KEY_2       (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x1008)
 524 #define IPN3KE_CLF_MHL_KEY_3       (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x100C)
 525 #define IPN3KE_CLF_MHL_RES_MASK    0xFFFFFFFF
 526 #define IPN3KE_CLF_MHL_RES         (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x2000)
 527
 528 int
 529 ipn3ke_rpst_dev_set_link_up(struct rte_eth_dev *dev);
 530 int
 531 ipn3ke_rpst_dev_set_link_down(struct rte_eth_dev *dev);
 532 int
 533 ipn3ke_rpst_link_update(struct rte_eth_dev *ethdev,
 534         __rte_unused int wait_to_complete);
 535 int
 536 ipn3ke_rpst_promiscuous_enable(struct rte_eth_dev *ethdev);
 537 int
 538 ipn3ke_rpst_promiscuous_disable(struct rte_eth_dev *ethdev);
 539 int
 540 ipn3ke_rpst_allmulticast_enable(struct rte_eth_dev *ethdev);
 541 int
 542 ipn3ke_rpst_allmulticast_disable(struct rte_eth_dev *ethdev);
 543 int
 544 ipn3ke_rpst_mac_addr_set(struct rte_eth_dev *ethdev,
 545                 struct rte_ether_addr *mac_addr);
 546 int
 547 ipn3ke_rpst_mtu_set(struct rte_eth_dev *ethdev, uint16_t mtu);
 548
 549 int
 550 ipn3ke_rpst_init(struct rte_eth_dev *ethdev, void *init_params);
 551 int
 552 ipn3ke_rpst_uninit(struct rte_eth_dev *ethdev);
 553 int
 554 ipn3ke_hw_tm_init(struct ipn3ke_hw *hw);
 555 void
 556 ipn3ke_tm_init(struct ipn3ke_rpst *rpst);
 557 int
 558 ipn3ke_tm_ops_get(struct rte_eth_dev *ethdev,
 559                 void *arg);
 560
 561
 562 /* IPN3KE_MASK is a macro used on 32 bit registers */
 563 #define IPN3KE_MASK(mask, shift) ((mask) << (shift))
 564
 565 #define IPN3KE_MAC_CTRL_BASE_0    0x00000000
 566 #define IPN3KE_MAC_CTRL_BASE_1    0x00008000
 567
 568 #define IPN3KE_MAC_STATS_MASK    0xFFFFFFFFF
 569
 570 /* All the address are in 4Bytes*/
 571 #define IPN3KE_MAC_PRIMARY_MAC_ADDR0    0x0010
 572 #define IPN3KE_MAC_PRIMARY_MAC_ADDR1    0x0011
 573
 574 #define IPN3KE_MAC_MAC_RESET_CONTROL    0x001F
 575 #define IPN3KE_MAC_MAC_RESET_CONTROL_TX_SHIFT    0
 576 #define IPN3KE_MAC_MAC_RESET_CONTROL_TX_MASK \
 577         IPN3KE_MASK(0x1, IPN3KE_MAC_MAC_RESET_CONTROL_TX_SHIFT)
 578
 579 #define IPN3KE_MAC_MAC_RESET_CONTROL_RX_SHIFT    8
 580 #define IPN3KE_MAC_MAC_RESET_CONTROL_RX_MASK \
 581         IPN3KE_MASK(0x1, IPN3KE_MAC_MAC_RESET_CONTROL_RX_SHIFT)
 582
 583 #define IPN3KE_MAC_TX_PACKET_CONTROL    0x0020
 584 #define IPN3KE_MAC_TX_PACKET_CONTROL_SHIFT    0
 585 #define IPN3KE_MAC_TX_PACKET_CONTROL_MASK \
 586         IPN3KE_MASK(0x1, IPN3KE_MAC_TX_PACKET_CONTROL_SHIFT)
 587
 588 #define IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE    0x002A
 589 #define IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE_SHIFT    0
 590 #define IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE_MASK \
 591         IPN3KE_MASK(0x1, IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE_SHIFT)
 592
 593 #define IPN3KE_MAC_TX_FRAME_MAXLENGTH    0x002C
 594 #define IPN3KE_MAC_TX_FRAME_MAXLENGTH_SHIFT    0
 595 #define IPN3KE_MAC_TX_FRAME_MAXLENGTH_MASK \
 596         IPN3KE_MASK(0xFFFF, IPN3KE_MAC_TX_FRAME_MAXLENGTH_SHIFT)
 597
 598 #define IPN3KE_MAC_TX_PAUSEFRAME_CONTROL    0x0040
 599 #define IPN3KE_MAC_TX_PAUSEFRAME_CONTROL_SHIFT    0
 600 #define IPN3KE_MAC_TX_PAUSEFRAME_CONTROL_MASK \
 601         IPN3KE_MASK(0x3, IPN3KE_MAC_TX_PAUSEFRAME_CONTROL_SHIFT)
 602
 603 #define IPN3KE_MAC_TX_PAUSEFRAME_QUANTA    0x0042
 604 #define IPN3KE_MAC_TX_PAUSEFRAME_QUANTA_SHIFT    0
 605 #define IPN3KE_MAC_TX_PAUSEFRAME_QUANTA_MASK \
 606         IPN3KE_MASK(0xFFFF, IPN3KE_MAC_TX_PAUSEFRAME_QUANTA_SHIFT)
 607
 608 #define IPN3KE_MAC_TX_PAUSEFRAME_HOLDOFF_QUANTA    0x0043
 609 #define IPN3KE_MAC_TX_PAUSEFRAME_HOLDOFF_QUANTA_SHIFT    0
 610 #define IPN3KE_MAC_TX_PAUSEFRAME_HOLDOFF_QUANTA_MASK \
 611         IPN3KE_MASK(0xFFFF, IPN3KE_MAC_TX_PAUSEFRAME_HOLDOFF_QUANTA_SHIFT)
 612
 613 #define IPN3KE_MAC_TX_PAUSEFRAME_ENABLE    0x0044
 614 #define IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_CFG_SHIFT    0
 615 #define IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_CFG_MASK \
 616         IPN3KE_MASK(0x1, IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_CFG_SHIFT)
 617
 618 #define IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_TYPE_SHIFT    1
 619 #define IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_TYPE_MASK \
 620         IPN3KE_MASK(0x3, IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_TYPE_SHIFT)
 621
 622 #define IPN3KE_MAC_RX_TRANSFER_CONTROL    0x00A0
 623 #define IPN3KE_MAC_RX_TRANSFER_CONTROL_SHIFT    0x0
 624 #define IPN3KE_MAC_RX_TRANSFER_CONTROL_MASK \
 625         IPN3KE_MASK(0x1, IPN3KE_MAC_RX_TRANSFER_CONTROL_SHIFT)
 626
 627 #define IPN3KE_MAC_RX_FRAME_CONTROL    0x00AC
 628 #define IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLUCAST_SHIFT    0x0
 629 #define IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLUCAST_MASK \
 630         IPN3KE_MASK(0x1, IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLUCAST_SHIFT)
 631
 632 #define IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLMCAST_SHIFT    0x1
 633 #define IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLMCAST_MASK \
 634         IPN3KE_MASK(0x1, IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLMCAST_SHIFT)
 635
 636 #define IPN3KE_VLAN_TAG_SIZE    4
 637 /**
 638  * The overhead from MTU to max frame size.
 639  * Considering QinQ packet, the VLAN tag needs to be counted twice.
 640  */
 641 #define IPN3KE_ETH_OVERHEAD \
 642         (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + IPN3KE_VLAN_TAG_SIZE * 2)
 643 #define IPN3KE_ETH_MAX_LEN (RTE_ETHER_MTU + IPN3KE_ETH_OVERHEAD)
 644
 645 #define IPN3KE_MAC_FRAME_SIZE_MAX    9728
 646 #define IPN3KE_MAC_RX_FRAME_MAXLENGTH    0x00AE
 647 #define IPN3KE_MAC_RX_FRAME_MAXLENGTH_SHIFT    0
 648 #define IPN3KE_MAC_RX_FRAME_MAXLENGTH_MASK \
 649         IPN3KE_MASK(0xFFFF, IPN3KE_MAC_RX_FRAME_MAXLENGTH_SHIFT)
 650
 651 #define IPN3KE_25G_MAX_TX_SIZE_CONFIG                                0x407
 652 #define IPN3KE_25G_MAX_RX_SIZE_CONFIG                                0x506
 653
 654 #define IPN3KE_10G_TX_FRAME_MAXLENGTH                                0x002C
 655 #define IPN3KE_10G_RX_FRAME_MAXLENGTH                                0x00AE
 656
 657 #define IPN3KE_REGISTER_WIDTH                                        32
 658
 659 /*Bits[2:0]: Configuration of TX statistics counters:
 660  *Bit[2]: Shadow request (active high): When set to the value of 1,
 661  *TX statistics collection is paused. The underlying counters
 662  *continue to operate, but the readable values reflect a snapshot at
 663  *the time the pause flag was activated. Write a 0 to release.
 664  *Bit[1]: Parity-error clear. When software sets this bit, the IP core
 665  *clears the parity bit CNTR_TX_STATUS[0]. This bit
 666  *(CNTR_TX_CONFIG[1]) is self-clearing.
 667  *Bit[0]: Software can set this bit to the value of 1 to reset all of
 668  *the TX statistics registers at the same time. This bit is selfclearing.
 669  *Bits[31:3] are Reserved
 670  */
 671 #define IPN3KE_25G_TX_STATISTICS_CONFIG                              0x845
 672 #define IPN3KE_25G_TX_STATISTICS_CONFIG_SHADOW_REQUEST_MASK          0x00000004
 673
 674 /*Bit[1]: Indicates that the TX statistics registers are paused (while
 675  *CNTR_TX_CONFIG[2] is asserted).
 676  *Bit[0]: Indicates the presence of at least one parity error in the
 677  *TX statistics counters.
 678  *Bits[31:2] are Reserved.
 679  */
 680 #define IPN3KE_25G_TX_STATISTICS_STATUS                              0x846
 681 #define IPN3KE_25G_TX_STATISTICS_STATUS_SHADOW_REQUEST_MASK          0x00000002
 682
 683 #define IPN3KE_25G_CNTR_TX_FRAGMENTS_LO                              0x800
 684 #define IPN3KE_25G_CNTR_TX_FRAGMENTS_HI                              0x801
 685 #define IPN3KE_25G_CNTR_TX_JABBERS_LO                                0x802
 686 #define IPN3KE_25G_CNTR_TX_JABBERS_HI                                0x803
 687 #define IPN3KE_25G_CNTR_TX_FCS_LO                                    0x804
 688 #define IPN3KE_25G_CNTR_TX_FCS_HI                                    0x805
 689 #define IPN3KE_25G_CNTR_TX_CRCERR_LO                                 0x806
 690 #define IPN3KE_25G_CNTR_TX_CRCERR_HI                                 0x807
 691 #define IPN3KE_25G_CNTR_TX_MCAST_DATA_ERR_LO                         0x808
 692 #define IPN3KE_25G_CNTR_TX_MCAST_DATA_ERR_HI                         0x809
 693 #define IPN3KE_25G_CNTR_TX_BCAST_DATA_ERR_LO                         0x80A
 694 #define IPN3KE_25G_CNTR_TX_BCAST_DATA_ERR_HI                         0x80B
 695 #define IPN3KE_25G_CNTR_TX_UCAST_DATA_ERR_LO                         0x80C
 696 #define IPN3KE_25G_CNTR_TX_UCAST_DATA_ERR_HI                         0x80D
 697 #define IPN3KE_25G_CNTR_TX_MCAST_CTRL_ERR_LO                         0x80E
 698 #define IPN3KE_25G_CNTR_TX_MCAST_CTRL_ERR_HI                         0x80F
 699 #define IPN3KE_25G_CNTR_TX_BCAST_CTRL_ERR_LO                         0x810
 700 #define IPN3KE_25G_CNTR_TX_BCAST_CTRL_ERR_HI                         0x811
 701 #define IPN3KE_25G_CNTR_TX_UCAST_CTRL_ERR_LO                         0x812
 702 #define IPN3KE_25G_CNTR_TX_UCAST_CTRL_ERR_HI                         0x813
 703 #define IPN3KE_25G_CNTR_TX_PAUSE_ERR_LO                              0x814
 704 #define IPN3KE_25G_CNTR_TX_PAUSE_ERR_HI                              0x815
 705 #define IPN3KE_25G_CNTR_TX_64B_LO                                    0x816
 706 #define IPN3KE_25G_CNTR_TX_64B_HI                                    0x817
 707 #define IPN3KE_25G_CNTR_TX_65_127B_LO                                0x818
 708 #define IPN3KE_25G_CNTR_TX_65_127B_HI                                0x819
 709 #define IPN3KE_25G_CNTR_TX_128_255B_LO                               0x81A
 710 #define IPN3KE_25G_CNTR_TX_128_255B_HI                               0x81B
 711 #define IPN3KE_25G_CNTR_TX_256_511B_LO                               0x81C
 712 #define IPN3KE_25G_CNTR_TX_256_511B_HI                               0x81D
 713 #define IPN3KE_25G_CNTR_TX_512_1023B_LO                              0x81E
 714 #define IPN3KE_25G_CNTR_TX_512_1023B_HI                              0x81F
 715 #define IPN3KE_25G_CNTR_TX_1024_1518B_LO                             0x820
 716 #define IPN3KE_25G_CNTR_TX_1024_1518B_HI                             0x821
 717 #define IPN3KE_25G_CNTR_TX_1519_MAXB_LO                              0x822
 718 #define IPN3KE_25G_CNTR_TX_1519_MAXB_HI                              0x823
 719 #define IPN3KE_25G_CNTR_TX_OVERSIZE_LO                               0x824
 720 #define IPN3KE_25G_CNTR_TX_OVERSIZE_HI                               0x825
 721 #define IPN3KE_25G_CNTR_TX_MCAST_DATA_OK_LO                          0x826
 722 #define IPN3KE_25G_CNTR_TX_MCAST_DATA_OK_HI                          0x827
 723 #define IPN3KE_25G_CNTR_TX_BCAST_DATA_OK_LO                          0x828
 724 #define IPN3KE_25G_CNTR_TX_BCAST_DATA_OK_HI                          0x829
 725 #define IPN3KE_25G_CNTR_TX_UCAST_DATA_OK_LO                          0x82A
 726 #define IPN3KE_25G_CNTR_TX_UCAST_DATA_OK_HI                          0x82B
 727 #define IPN3KE_25G_CNTR_TX_MCAST_CTRL_LO                             0x82C
 728 #define IPN3KE_25G_CNTR_TX_MCAST_CTRL_HI                             0x82D
 729 #define IPN3KE_25G_CNTR_TX_BCAST_CTRL_LO                             0x82E
 730 #define IPN3KE_25G_CNTR_TX_BCAST_CTRL_HI                             0x82F
 731 #define IPN3KE_25G_CNTR_TX_UCAST_CTRL_LO                             0x830
 732 #define IPN3KE_25G_CNTR_TX_UCAST_CTRL_HI                             0x831
 733 #define IPN3KE_25G_CNTR_TX_PAUSE_LO                                  0x832
 734 #define IPN3KE_25G_CNTR_TX_PAUSE_HI                                  0x833
 735 #define IPN3KE_25G_CNTR_TX_RUNT_LO                                   0x834
 736 #define IPN3KE_25G_CNTR_TX_RUNT_HI                                   0x835
 737 #define IPN3KE_25G_TX_PAYLOAD_OCTETS_OK_LO                           0x860
 738 #define IPN3KE_25G_TX_PAYLOAD_OCTETS_OK_HI                           0x861
 739 #define IPN3KE_25G_TX_FRAME_OCTETS_OK_LO                             0x862
 740 #define IPN3KE_25G_TX_FRAME_OCTETS_OK_HI                             0x863
 741
 742 /*Bits[2:0]: Configuration of RX statistics counters:
 743  *Bit[2]: Shadow request (active high): When set to the value of 1,
 744  *RX statistics collection is paused. The underlying counters
 745  *continue to operate, but the readable values reflect a snapshot
 746  *at the time the pause flag was activated. Write a 0 to release.
 747  *Bit[1]: Parity-error clear. When software sets this bit, the IP
 748  *core clears the parity bit CNTR_RX_STATUS[0]. This bit
 749  *(CNTR_RX_CONFIG[1]) is self-clearing.
 750  *Bit[0]: Software can set this bit to the value of 1 to reset all of
 751  *the RX statistics registers at the same time. This bit is selfclearing.
 752  *Bits[31:3] are Reserved.
 753  */
 754 #define IPN3KE_25G_RX_STATISTICS_CONFIG                              0x945
 755 #define IPN3KE_25G_RX_STATISTICS_CONFIG_SHADOW_REQUEST_MASK          0x00000004
 756
 757 /*Bit[1]: Indicates that the RX statistics registers are paused
 758  *(while CNTR_RX_CONFIG[2] is asserted).
 759  *Bit[0]: Indicates the presence of at least one parity error in the
 760  *RX statistics counters.
 761  *Bits [31:2] are Reserved
 762  */
 763 #define IPN3KE_25G_RX_STATISTICS_STATUS                              0x946
 764 #define IPN3KE_25G_RX_STATISTICS_STATUS_SHADOW_REQUEST_MASK          0x00000002
 765
 766 #define IPN3KE_25G_CNTR_RX_FRAGMENTS_LO                              0x900
 767 #define IPN3KE_25G_CNTR_RX_FRAGMENTS_HI                              0x901
 768 #define IPN3KE_25G_CNTR_RX_JABBERS_LO                                0x902
 769 #define IPN3KE_25G_CNTR_RX_JABBERS_HI                                0x903
 770 #define IPN3KE_25G_CNTR_RX_FCS_LO                                    0x904
 771 #define IPN3KE_25G_CNTR_RX_FCS_HI                                    0x905
 772 #define IPN3KE_25G_CNTR_RX_CRCERR_LO                                 0x906
 773 #define IPN3KE_25G_CNTR_RX_CRCERR_HI                                 0x907
 774 #define IPN3KE_25G_CNTR_RX_MCAST_DATA_ERR_LO                         0x908
 775 #define IPN3KE_25G_CNTR_RX_MCAST_DATA_ERR_HI                         0x909
 776 #define IPN3KE_25G_CNTR_RX_BCAST_DATA_ERR_LO                         0x90A
 777 #define IPN3KE_25G_CNTR_RX_BCAST_DATA_ERR_HI                         0x90B
 778 #define IPN3KE_25G_CNTR_RX_UCAST_DATA_ERR_LO                         0x90C
 779 #define IPN3KE_25G_CNTR_RX_UCAST_DATA_ERR_HI                         0x90D
 780 #define IPN3KE_25G_CNTR_RX_MCAST_CTRL_ERR_LO                         0x90E
 781 #define IPN3KE_25G_CNTR_RX_MCAST_CTRL_ERR_HI                         0x90F
 782 #define IPN3KE_25G_CNTR_RX_BCAST_CTRL_ERR_LO                         0x910
 783 #define IPN3KE_25G_CNTR_RX_BCAST_CTRL_ERR_HI                         0x911
 784 #define IPN3KE_25G_CNTR_RX_UCAST_CTRL_ERR_LO                         0x912
 785 #define IPN3KE_25G_CNTR_RX_UCAST_CTRL_ERR_HI                         0x913
 786 #define IPN3KE_25G_CNTR_RX_PAUSE_ERR_LO                              0x914
 787 #define IPN3KE_25G_CNTR_RX_PAUSE_ERR_HI                              0x915
 788 #define IPN3KE_25G_CNTR_RX_64B_LO                                    0x916
 789 #define IPN3KE_25G_CNTR_RX_64B_HI                                    0x917
 790 #define IPN3KE_25G_CNTR_RX_65_127B_LO                                0x918
 791 #define IPN3KE_25G_CNTR_RX_65_127B_HI                                0x919
 792 #define IPN3KE_25G_CNTR_RX_128_255B_LO                               0x91A
 793 #define IPN3KE_25G_CNTR_RX_128_255B_HI                               0x91B
 794 #define IPN3KE_25G_CNTR_RX_256_511B_LO                               0x91C
 795 #define IPN3KE_25G_CNTR_RX_256_511B_HI                               0x91D
 796 #define IPN3KE_25G_CNTR_RX_512_1023B_LO                              0x91E
 797 #define IPN3KE_25G_CNTR_RX_512_1023B_HI                              0x91F
 798 #define IPN3KE_25G_CNTR_RX_1024_1518B_LO                             0x920
 799 #define IPN3KE_25G_CNTR_RX_1024_1518B_HI                             0x921
 800 #define IPN3KE_25G_CNTR_RX_1519_MAXB_LO                              0x922
 801 #define IPN3KE_25G_CNTR_RX_1519_MAXB_HI                              0x923
 802 #define IPN3KE_25G_CNTR_RX_OVERSIZE_LO                               0x924
 803 #define IPN3KE_25G_CNTR_RX_OVERSIZE_HI                               0x925
 804 #define IPN3KE_25G_CNTR_RX_MCAST_DATA_OK_LO                          0x926
 805 #define IPN3KE_25G_CNTR_RX_MCAST_DATA_OK_HI                          0x927
 806 #define IPN3KE_25G_CNTR_RX_BCAST_DATA_OK_LO                          0x928
 807 #define IPN3KE_25G_CNTR_RX_BCAST_DATA_OK_HI                          0x929
 808 #define IPN3KE_25G_CNTR_RX_UCAST_DATA_OK_LO                          0x92A
 809 #define IPN3KE_25G_CNTR_RX_UCAST_DATA_OK_HI                          0x92B
 810 #define IPN3KE_25G_CNTR_RX_MCAST_CTRL_LO                             0x92C
 811 #define IPN3KE_25G_CNTR_RX_MCAST_CTRL_HI                             0x92D
 812 #define IPN3KE_25G_CNTR_RX_BCAST_CTRL_LO                             0x92E
 813 #define IPN3KE_25G_CNTR_RX_BCAST_CTRL_HI                             0x92F
 814 #define IPN3KE_25G_CNTR_RX_UCAST_CTRL_LO                             0x930
 815 #define IPN3KE_25G_CNTR_RX_UCAST_CTRL_HI                             0x931
 816 #define IPN3KE_25G_CNTR_RX_PAUSE_LO                                  0x932
 817 #define IPN3KE_25G_CNTR_RX_PAUSE_HI                                  0x933
 818 #define IPN3KE_25G_CNTR_RX_RUNT_LO                                   0x934
 819 #define IPN3KE_25G_CNTR_RX_RUNT_HI                                   0x935
 820 #define IPN3KE_25G_RX_PAYLOAD_OCTETS_OK_LO                           0x960
 821 #define IPN3KE_25G_RX_PAYLOAD_OCTETS_OK_HI                           0x961
 822 #define IPN3KE_25G_RX_FRAME_OCTETS_OK_LO                             0x962
 823 #define IPN3KE_25G_RX_FRAME_OCTETS_OK_HI                             0x963
 824
 825 #define IPN3KE_10G_STATS_HI_VALID_MASK                               0x0000000F
 826
 827 #define IPN3KE_10G_TX_STATS_CLR                                      0x0140
 828 #define IPN3KE_10G_TX_STATS_CLR_CLEAR_SHIFT    0
 829 #define IPN3KE_10G_TX_STATS_CLR_CLEAR_MASK \
 830         IPN3KE_MASK(0x1, IPN3KE_10G_TX_STATS_CLR_CLEAR_SHIFT)
 831
 832 #define IPN3KE_10G_RX_STATS_CLR                                      0x01C0
 833 #define IPN3KE_10G_RX_STATS_CLR_CLEAR_SHIFT    0
 834 #define IPN3KE_10G_RX_STATS_CLR_CLEAR_MASK \
 835         IPN3KE_MASK(0x1, IPN3KE_10G_RX_STATS_CLR_CLEAR_SHIFT)
 836
 837 #define IPN3KE_10G_TX_STATS_FRAME_OK_LO                              0x0142
 838 #define IPN3KE_10G_TX_STATS_FRAME_OK_HI                              0x0143
 839 #define IPN3KE_10G_RX_STATS_FRAME_OK_LO                              0x01C2
 840 #define IPN3KE_10G_RX_STATS_FRAME_OK_HI                              0x01C3
 841 #define IPN3KE_10G_TX_STATS_FRAME_ERR_LO                             0x0144
 842 #define IPN3KE_10G_TX_STATS_FRAME_ERR_HI                             0x0145
 843 #define IPN3KE_10G_RX_STATS_FRAME_ERR_LO                             0x01C4
 844 #define IPN3KE_10G_RX_STATS_FRAME_ERR_HI                             0x01C5
 845 #define IPN3KE_10G_RX_STATS_FRAME_CRC_ERR_LO                         0x01C6
 846 #define IPN3KE_10G_RX_STATS_FRAME_CRC_ERR_HI                         0x01C7
 847 #define IPN3KE_10G_TX_STATS_OCTETS_OK_LO                             0x0148
 848 #define IPN3KE_10G_TX_STATS_OCTETS_OK_HI                             0x0149
 849 #define IPN3KE_10G_RX_STATS_OCTETS_OK_LO                             0x01C8
 850 #define IPN3KE_10G_RX_STATS_OCTETS_OK_HI                             0x01C9
 851 #define IPN3KE_10G_TX_STATS_PAUSE_MAC_CTRL_FRAMES_LO                 0x014A
 852 #define IPN3KE_10G_TX_STATS_PAUSE_MAC_CTRL_FRAMES_HI                 0x014B
 853 #define IPN3KE_10G_RX_STATS_PAUSE_MAC_CTRL_FRAMES_LO                 0x01CA
 854 #define IPN3KE_10G_RX_STATS_PAUSE_MAC_CTRL_FRAMES_HI                 0x01CB
 855 #define IPN3KE_10G_TX_STATS_IF_ERRORS_LO                             0x014C
 856 #define IPN3KE_10G_TX_STATS_IF_ERRORS_HI                             0x014D
 857 #define IPN3KE_10G_RX_STATS_IF_ERRORS_LO                             0x01CC
 858 #define IPN3KE_10G_RX_STATS_IF_ERRORS_HI                             0x01CD
 859 #define IPN3KE_10G_TX_STATS_UNICAST_FRAME_OK_LO                      0x014E
 860 #define IPN3KE_10G_TX_STATS_UNICAST_FRAME_OK_HI                      0x014F
 861 #define IPN3KE_10G_RX_STATS_UNICAST_FRAME_OK_LO                      0x01CE
 862 #define IPN3KE_10G_RX_STATS_UNICAST_FRAME_OK_HI                      0x01CF
 863 #define IPN3KE_10G_TX_STATS_UNICAST_FRAME_ERR_LO                     0x0150
 864 #define IPN3KE_10G_TX_STATS_UNICAST_FRAME_ERR_HI                     0x0151
 865 #define IPN3KE_10G_RX_STATS_UNICAST_FRAME_ERR_LO                     0x01D0
 866 #define IPN3KE_10G_RX_STATS_UNICAST_FRAME_ERR_HI                     0x01D1
 867 #define IPN3KE_10G_TX_STATS_MULTICAST_FRAME_OK_LO                    0x0152
 868 #define IPN3KE_10G_TX_STATS_MULTICAST_FRAME_OK_HI                    0x0153
 869 #define IPN3KE_10G_RX_STATS_MULTICAST_FRAME_OK_LO                    0x01D2
 870 #define IPN3KE_10G_RX_STATS_MULTICAST_FRAME_OK_HI                    0x01D3
 871 #define IPN3KE_10G_TX_STATS_MULTICAST_FRAME_ERR_LO                   0x0154
 872 #define IPN3KE_10G_TX_STATS_MULTICAST_FRAME_ERR_HI                   0x0155
 873 #define IPN3KE_10G_RX_STATS_MULTICAST_FRAME_ERR_LO                   0x01D4
 874 #define IPN3KE_10G_RX_STATS_MULTICAST_FRAME_ERR_HI                   0x01D5
 875 #define IPN3KE_10G_TX_STATS_BROADCAST_FRAME_OK_LO                    0x0156
 876 #define IPN3KE_10G_TX_STATS_BROADCAST_FRAME_OK_HI                    0x0157
 877 #define IPN3KE_10G_RX_STATS_BROADCAST_FRAME_OK_LO                    0x01D6
 878 #define IPN3KE_10G_RX_STATS_BROADCAST_FRAME_OK_HI                    0x01D7
 879 #define IPN3KE_10G_TX_STATS_BROADCAST_FRAME_ERR_LO                   0x0158
 880 #define IPN3KE_10G_TX_STATS_BROADCAST_FRAME_ERR_HI                   0x0159
 881 #define IPN3KE_10G_RX_STATS_BROADCAST_FRAME_ERR_LO                   0x01D8
 882 #define IPN3KE_10G_RX_STATS_BROADCAST_FRAME_ERR_HI                   0x01D9
 883 #define IPN3KE_10G_TX_STATS_ETHER_STATS_OCTETS_LO                    0x015A
 884 #define IPN3KE_10G_TX_STATS_ETHER_STATS_OCTETS_HI                    0x015B
 885 #define IPN3KE_10G_RX_STATS_ETHER_STATS_OCTETS_LO                    0x01DA
 886 #define IPN3KE_10G_RX_STATS_ETHER_STATS_OCTETS_HI                    0x01DB
 887 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_LO                      0x015C
 888 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_HI                      0x015D
 889 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_LO                      0x01DC
 890 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_HI                      0x01DD
 891 #define IPN3KE_10G_TX_STATS_ETHER_STATS_UNDER_SIZE_PKTS_LO           0x015E
 892 #define IPN3KE_10G_TX_STATS_ETHER_STATS_UNDER_SIZE_PKTS_HI           0x015F
 893 #define IPN3KE_10G_RX_STATS_ETHER_STATS_UNDER_SIZE_PKTS_LO           0x01DE
 894 #define IPN3KE_10G_RX_STATS_ETHER_STATS_UNDER_SIZE_PKTS_HI           0x01DF
 895 #define IPN3KE_10G_TX_STATS_ETHER_STATS_OVER_SIZE_PKTS_LO            0x0160
 896 #define IPN3KE_10G_TX_STATS_ETHER_STATS_OVER_SIZE_PKTS_HI            0x0161
 897 #define IPN3KE_10G_RX_STATS_ETHER_STATS_OVER_SIZE_PKTS_LO            0x01E0
 898 #define IPN3KE_10G_RX_STATS_ETHER_STATS_OVER_SIZE_PKTS_HI            0x01E1
 899 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_64_OCTETS_LO            0x0162
 900 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_64_OCTETS_HI            0x0163
 901 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_64_OCTETS_LO            0x01E2
 902 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_64_OCTETS_HI            0x01E3
 903 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_65_127_OCTETS_LO        0x0164
 904 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_65_127_OCTETS_HI        0x0165
 905 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_65_127_OCTETS_LO        0x01E4
 906 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_65_127_OCTETS_HI        0x01E5
 907 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_128_255_OCTETS_LO       0x0166
 908 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_128_255_OCTETS_HI       0x0167
 909 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_128_255_OCTETS_LO       0x01E6
 910 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_128_255_OCTETS_HI       0x01E7
 911 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_256_511_OCTETS_LO       0x0168
 912 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_256_511_OCTETS_HI       0x0169
 913 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_256_511_OCTETS_LO       0x01E8
 914 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_256_511_OCTETS_HI       0x01E9
 915 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_512_1023_OCTETS_LO      0x016A
 916 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_512_1023_OCTETS_HI      0x016B
 917 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_512_1023_OCTETS_LO      0x01EA
 918 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_512_1023_OCTETS_HI      0x01EB
 919 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_1024_1518_OCTETS_LO     0x016C
 920 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_1024_1518_OCTETS_HI     0x016D
 921 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_1024_1518_OCTETS_LO     0x01EC
 922 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_1024_1518_OCTETS_HI     0x01ED
 923 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_1519_X_OCTETS_LO        0x016E
 924 #define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_1519_X_OCTETS_HI        0x016F
 925 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_1519_X_OCTETS_LO        0x01EE
 926 #define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_1519_X_OCTETS_HI        0x01EF
 927 #define IPN3KE_10G_RX_STATS_ETHER_STATS_FRAGMENTS_LO                 0x01E0
 928 #define IPN3KE_10G_RX_STATS_ETHER_STATS_FRAGMENTS_HI                 0x01F1
 929 #define IPN3KE_10G_RX_STATS_ETHER_STATS_JABBERS_LO                   0x01E2
 930 #define IPN3KE_10G_RX_STATS_ETHER_STATS_JABBERS_HI                   0x01F3
 931 #define IPN3KE_10G_RX_STATS_ETHER_STATS_CRC_ERR_LO                   0x01E4
 932 #define IPN3KE_10G_RX_STATS_ETHER_STATS_CRC_ERR_HI                   0x01F5
 933 #define IPN3KE_10G_TX_STATS_UNICAST_MAC_CTRL_FRAMES_LO               0x0176
 934 #define IPN3KE_10G_TX_STATS_UNICAST_MAC_CTRL_FRAMES_HI               0x0177
 935 #define IPN3KE_10G_RX_STATS_UNICAST_MAC_CTRL_FRAMES_LO               0x01F6
 936 #define IPN3KE_10G_RX_STATS_UNICAST_MAC_CTRL_FRAMES_HI               0x01F7
 937 #define IPN3KE_10G_TX_STATS_MULTICAST_MAC_CTRL_FRAMES_LO             0x0178
 938 #define IPN3KE_10G_TX_STATS_MULTICAST_MAC_CTRL_FRAMES_HI             0x0179
 939 #define IPN3KE_10G_RX_STATS_MULTICAST_MAC_CTRL_FRAMES_LO             0x01F8
 940 #define IPN3KE_10G_RX_STATS_MULTICAST_MAC_CTRL_FRAMES_HI             0x01F9
 941 #define IPN3KE_10G_TX_STATS_BROADCAST_MAC_CTRL_FRAMES_LO             0x017A
 942 #define IPN3KE_10G_TX_STATS_BROADCAST_MAC_CTRL_FRAMES_HI             0x017B
 943 #define IPN3KE_10G_RX_STATS_BROADCAST_MAC_CTRL_FRAMES_LO             0x01FA
 944 #define IPN3KE_10G_RX_STATS_BROADCAST_MAC_CTRL_FRAMES_HI             0x01FB
 945 #define IPN3KE_10G_TX_STATS_PFC_MAC_CTRL_FRAMES_LO                   0x017C
 946 #define IPN3KE_10G_TX_STATS_PFC_MAC_CTRL_FRAMES_HI                   0x017D
 947 #define IPN3KE_10G_RX_STATS_PFC_MAC_CTRL_FRAMES_LO                   0x01FC
 948 #define IPN3KE_10G_RX_STATS_PFC_MAC_CTRL_FRAMES_HI                   0x01FD
 949
 950 static inline void ipn3ke_xmac_tx_enable(struct ipn3ke_hw *hw,
 951                 uint32_t mac_num, uint32_t eth_group_sel)
 952 {
 953 #define IPN3KE_XMAC_TX_ENABLE (0 & (IPN3KE_MAC_TX_PACKET_CONTROL_MASK))
 954
 955         (*hw->f_mac_write)(hw,
 956                                         IPN3KE_XMAC_TX_ENABLE,
 957                                         IPN3KE_MAC_TX_PACKET_CONTROL,
 958                                         mac_num,
 959                                         eth_group_sel);
 960 }
 961
 962 static inline void ipn3ke_xmac_tx_disable(struct ipn3ke_hw *hw,
 963                 uint32_t mac_num, uint32_t eth_group_sel)
 964 {
 965 #define IPN3KE_XMAC_TX_DISABLE (1 & (IPN3KE_MAC_TX_PACKET_CONTROL_MASK))
 966
 967         (*hw->f_mac_write)(hw,
 968                                         IPN3KE_XMAC_TX_DISABLE,
 969                                         IPN3KE_MAC_TX_PACKET_CONTROL,
 970                                         mac_num,
 971                                         eth_group_sel);
 972 }
 973
 974 static inline void ipn3ke_xmac_rx_enable(struct ipn3ke_hw *hw,
 975                 uint32_t mac_num, uint32_t eth_group_sel)
 976 {
 977 #define IPN3KE_XMAC_RX_ENABLE (0 & (IPN3KE_MAC_RX_TRANSFER_CONTROL_MASK))
 978
 979         (*hw->f_mac_write)(hw,
 980                                         IPN3KE_XMAC_RX_ENABLE,
 981                                         IPN3KE_MAC_RX_TRANSFER_CONTROL,
 982                                         mac_num,
 983                                         eth_group_sel);
 984 }
 985
 986 static inline void ipn3ke_xmac_rx_disable(struct ipn3ke_hw *hw,
 987                 uint32_t mac_num, uint32_t eth_group_sel)
 988 {
 989 #define IPN3KE_XMAC_RX_DISABLE (1 & (IPN3KE_MAC_RX_TRANSFER_CONTROL_MASK))
 990
 991         (*hw->f_mac_write)(hw,
 992                                         IPN3KE_XMAC_RX_DISABLE,
 993                                         IPN3KE_MAC_RX_TRANSFER_CONTROL,
 994                                         mac_num,
 995                                         eth_group_sel);
 996 }
 997
 998 static inline void ipn3ke_xmac_smac_ovd_dis(struct ipn3ke_hw *hw,
 999         uint32_t mac_num, uint32_t eth_group_sel)
1000 {
1001 #define IPN3KE_XMAC_SMAC_OVERRIDE_DISABLE (0 & \
1002         (IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE_MASK))
1003
1004         (*hw->f_mac_write)(hw,
1005                                         IPN3KE_XMAC_SMAC_OVERRIDE_DISABLE,
1006                                         IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE,
1007                                         mac_num,
1008                                         eth_group_sel);
1009 }
1010
1011 static inline void ipn3ke_xmac_tx_clr_10G_stcs
1012 (struct ipn3ke_hw *hw, uint32_t mac_num, uint32_t eth_group_sel)
1013 {
1014         uint32_t tmp;
1015         tmp = 0x00000000;
1016         (*hw->f_mac_read)(hw,
1017                                         &tmp,
1018                                         IPN3KE_10G_TX_STATS_CLR,
1019                                         mac_num,
1020                                         eth_group_sel);
1021         tmp |= 0x00000001;
1022         (*hw->f_mac_write)(hw,
1023                                         tmp,
1024                                         IPN3KE_10G_TX_STATS_CLR,
1025                                         mac_num,
1026                                         eth_group_sel);
1027 }
1028
1029 static inline void ipn3ke_xmac_rx_clr_10G_stcs
1030 (struct ipn3ke_hw *hw, uint32_t mac_num, uint32_t eth_group_sel)
1031 {
1032         uint32_t tmp;
1033         tmp = 0x00000000;
1034         (*hw->f_mac_read)(hw,
1035                                         &tmp,
1036                                         IPN3KE_10G_RX_STATS_CLR,
1037                                         mac_num,
1038                                         eth_group_sel);
1039         tmp |= 0x00000001;
1040         (*hw->f_mac_write)(hw,
1041                                         tmp,
1042                                         IPN3KE_10G_RX_STATS_CLR,
1043                                         mac_num,
1044                                         eth_group_sel);
1045 }
1046
1047 static inline void ipn3ke_xmac_tx_clr_25G_stcs
1048 (struct ipn3ke_hw *hw, uint32_t mac_num, uint32_t eth_group_sel)
1049 {
1050         uint32_t tmp = 0x00000001;
1051
1052         /* Bit[0]: Software can set this bit to the value of 1
1053          * to reset all of the TX statistics registers at the same time.
1054          * This bit is selfclearing.
1055          */
1056         (*hw->f_mac_write)(hw,
1057                                         tmp,
1058                                         IPN3KE_25G_TX_STATISTICS_CONFIG,
1059                                         mac_num,
1060                                         eth_group_sel);
1061 }
1062
1063 static inline void ipn3ke_xmac_rx_clr_25G_stcs
1064 (struct ipn3ke_hw *hw, uint32_t mac_num, uint32_t eth_group_sel)
1065 {
1066         uint32_t tmp = 0x00000001;
1067
1068         /* Bit[0]: Software can set this bit to the value of 1
1069          * to reset all of the RX statistics registers at the same time.
1070          * This bit is selfclearing.
1071          */
1072         (*hw->f_mac_write)(hw,
1073                                         tmp,
1074                                         IPN3KE_25G_RX_STATISTICS_CONFIG,
1075                                         mac_num,
1076                                         eth_group_sel);
1077 }
1078
1079 #endif /* _IPN3KE_ETHDEV_H_ */