1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2018
5 #include "ixgbe_type.h"
6 #include "ixgbe_82599.h"
8 #include "ixgbe_common.h"
11 #define IXGBE_82599_MAX_TX_QUEUES 128
12 #define IXGBE_82599_MAX_RX_QUEUES 128
13 #define IXGBE_82599_RAR_ENTRIES 128
14 #define IXGBE_82599_MC_TBL_SIZE 128
15 #define IXGBE_82599_VFT_TBL_SIZE 128
16 #define IXGBE_82599_RX_PB_SIZE 512
18 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
19 ixgbe_link_speed speed,
20 bool autoneg_wait_to_complete);
21 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
22 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
23 u16 offset, u16 *data);
24 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
25 u16 words, u16 *data);
26 STATIC s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
27 u8 dev_addr, u8 *data);
28 STATIC s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
29 u8 dev_addr, u8 data);
31 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
33 struct ixgbe_mac_info *mac = &hw->mac;
35 DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
38 * enable the laser control functions for SFP+ fiber
41 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
42 !ixgbe_mng_enabled(hw)) {
43 mac->ops.disable_tx_laser =
44 ixgbe_disable_tx_laser_multispeed_fiber;
45 mac->ops.enable_tx_laser =
46 ixgbe_enable_tx_laser_multispeed_fiber;
47 mac->ops.flap_tx_laser = ixgbe_flap_tx_laser_multispeed_fiber;
50 mac->ops.disable_tx_laser = NULL;
51 mac->ops.enable_tx_laser = NULL;
52 mac->ops.flap_tx_laser = NULL;
55 if (hw->phy.multispeed_fiber) {
56 /* Set up dual speed SFP+ support */
57 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
58 mac->ops.setup_mac_link = ixgbe_setup_mac_link_82599;
59 mac->ops.set_rate_select_speed =
60 ixgbe_set_hard_rate_select_speed;
61 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber_fixed)
62 mac->ops.set_rate_select_speed =
63 ixgbe_set_soft_rate_select_speed;
65 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
66 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
67 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
68 !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
69 mac->ops.setup_link = ixgbe_setup_mac_link_smartspeed;
71 mac->ops.setup_link = ixgbe_setup_mac_link_82599;
77 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
78 * @hw: pointer to hardware structure
80 * Initialize any function pointers that were not able to be
81 * set during init_shared_code because the PHY/SFP type was
82 * not known. Perform the SFP init if necessary.
85 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
87 struct ixgbe_mac_info *mac = &hw->mac;
88 struct ixgbe_phy_info *phy = &hw->phy;
89 s32 ret_val = IXGBE_SUCCESS;
92 DEBUGFUNC("ixgbe_init_phy_ops_82599");
94 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) {
95 /* Store flag indicating I2C bus access control unit. */
96 hw->phy.qsfp_shared_i2c_bus = TRUE;
98 /* Initialize access to QSFP+ I2C bus */
99 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
100 esdp |= IXGBE_ESDP_SDP0_DIR;
101 esdp &= ~IXGBE_ESDP_SDP1_DIR;
102 esdp &= ~IXGBE_ESDP_SDP0;
103 esdp &= ~IXGBE_ESDP_SDP0_NATIVE;
104 esdp &= ~IXGBE_ESDP_SDP1_NATIVE;
105 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
106 IXGBE_WRITE_FLUSH(hw);
108 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_82599;
109 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_82599;
111 /* Identify the PHY or SFP module */
112 ret_val = phy->ops.identify(hw);
113 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
114 goto init_phy_ops_out;
116 /* Setup function pointers based on detected SFP module and speeds */
117 ixgbe_init_mac_link_ops_82599(hw);
118 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
119 hw->phy.ops.reset = NULL;
121 /* If copper media, overwrite with copper function pointers */
122 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
123 mac->ops.setup_link = ixgbe_setup_copper_link_82599;
124 mac->ops.get_link_capabilities =
125 ixgbe_get_copper_link_capabilities_generic;
128 /* Set necessary function pointers based on PHY type */
129 switch (hw->phy.type) {
131 phy->ops.setup_link = ixgbe_setup_phy_link_tnx;
132 phy->ops.check_link = ixgbe_check_phy_link_tnx;
133 phy->ops.get_firmware_version =
134 ixgbe_get_phy_firmware_version_tnx;
143 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
145 s32 ret_val = IXGBE_SUCCESS;
146 u16 list_offset, data_offset, data_value;
148 DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
150 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
151 ixgbe_init_mac_link_ops_82599(hw);
153 hw->phy.ops.reset = NULL;
155 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
157 if (ret_val != IXGBE_SUCCESS)
160 /* PHY config will finish before releasing the semaphore */
161 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
162 IXGBE_GSSR_MAC_CSR_SM);
163 if (ret_val != IXGBE_SUCCESS) {
164 ret_val = IXGBE_ERR_SWFW_SYNC;
168 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
170 while (data_value != 0xffff) {
171 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
172 IXGBE_WRITE_FLUSH(hw);
173 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
177 /* Release the semaphore */
178 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
179 /* Delay obtaining semaphore again to allow FW access
180 * prot_autoc_write uses the semaphore too.
182 msec_delay(hw->eeprom.semaphore_delay);
184 /* Restart DSP and set SFI mode */
185 ret_val = hw->mac.ops.prot_autoc_write(hw,
186 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL,
190 DEBUGOUT("sfp module setup not complete\n");
191 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
201 /* Release the semaphore */
202 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
203 /* Delay obtaining semaphore again to allow FW access */
204 msec_delay(hw->eeprom.semaphore_delay);
205 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
206 "eeprom read at offset %d failed", data_offset);
207 return IXGBE_ERR_PHY;
211 * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read
212 * @hw: pointer to hardware structure
213 * @locked: Return the if we locked for this read.
214 * @reg_val: Value we read from AUTOC
216 * For this part (82599) we need to wrap read-modify-writes with a possible
217 * FW/SW lock. It is assumed this lock will be freed with the next
218 * prot_autoc_write_82599().
220 s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
225 /* If LESM is on then we need to hold the SW/FW semaphore. */
226 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
227 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
228 IXGBE_GSSR_MAC_CSR_SM);
229 if (ret_val != IXGBE_SUCCESS)
230 return IXGBE_ERR_SWFW_SYNC;
235 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
236 return IXGBE_SUCCESS;
240 * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write
241 * @hw: pointer to hardware structure
242 * @autoc: value to write to AUTOC
243 * @locked: bool to indicate whether the SW/FW lock was already taken by
244 * previous proc_autoc_read_82599.
246 * This part (82599) may need to hold the SW/FW lock around all writes to
247 * AUTOC. Likewise after a write we need to do a pipeline reset.
249 s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)
251 s32 ret_val = IXGBE_SUCCESS;
253 /* Blocked by MNG FW so bail */
254 if (ixgbe_check_reset_blocked(hw))
257 /* We only need to get the lock if:
258 * - We didn't do it already (in the read part of a read-modify-write)
261 if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) {
262 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
263 IXGBE_GSSR_MAC_CSR_SM);
264 if (ret_val != IXGBE_SUCCESS)
265 return IXGBE_ERR_SWFW_SYNC;
270 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
271 ret_val = ixgbe_reset_pipeline_82599(hw);
274 /* Free the SW/FW semaphore as we either grabbed it here or
275 * already had it when this function was called.
278 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
284 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
285 * @hw: pointer to hardware structure
287 * Initialize the function pointers and assign the MAC type for 82599.
288 * Does not touch the hardware.
291 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
293 struct ixgbe_mac_info *mac = &hw->mac;
294 struct ixgbe_phy_info *phy = &hw->phy;
295 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
298 DEBUGFUNC("ixgbe_init_ops_82599");
300 ixgbe_init_phy_ops_generic(hw);
301 ret_val = ixgbe_init_ops_generic(hw);
304 phy->ops.identify = ixgbe_identify_phy_82599;
305 phy->ops.init = ixgbe_init_phy_ops_82599;
308 mac->ops.reset_hw = ixgbe_reset_hw_82599;
309 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2;
310 mac->ops.get_media_type = ixgbe_get_media_type_82599;
311 mac->ops.get_supported_physical_layer =
312 ixgbe_get_supported_physical_layer_82599;
313 mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic;
314 mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic;
315 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82599;
316 mac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82599;
317 mac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82599;
318 mac->ops.start_hw = ixgbe_start_hw_82599;
319 mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic;
320 mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic;
321 mac->ops.get_device_caps = ixgbe_get_device_caps_generic;
322 mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic;
323 mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic;
324 mac->ops.prot_autoc_read = prot_autoc_read_82599;
325 mac->ops.prot_autoc_write = prot_autoc_write_82599;
327 /* RAR, Multicast, VLAN */
328 mac->ops.set_vmdq = ixgbe_set_vmdq_generic;
329 mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic;
330 mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic;
331 mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic;
332 mac->rar_highwater = 1;
333 mac->ops.set_vfta = ixgbe_set_vfta_generic;
334 mac->ops.set_vlvf = ixgbe_set_vlvf_generic;
335 mac->ops.clear_vfta = ixgbe_clear_vfta_generic;
336 mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic;
337 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_82599;
338 mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing;
339 mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing;
342 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82599;
343 mac->ops.check_link = ixgbe_check_mac_link_generic;
344 mac->ops.setup_rxpba = ixgbe_set_rxpba_generic;
345 ixgbe_init_mac_link_ops_82599(hw);
347 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
348 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
349 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
350 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE;
351 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
352 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
353 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
355 mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw))
356 & IXGBE_FWSM_MODE_MASK);
358 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
361 eeprom->ops.read = ixgbe_read_eeprom_82599;
362 eeprom->ops.read_buffer = ixgbe_read_eeprom_buffer_82599;
364 /* Manageability interface */
365 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic;
367 mac->ops.get_thermal_sensor_data =
368 ixgbe_get_thermal_sensor_data_generic;
369 mac->ops.init_thermal_sensor_thresh =
370 ixgbe_init_thermal_sensor_thresh_generic;
372 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
378 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
379 * @hw: pointer to hardware structure
380 * @speed: pointer to link speed
381 * @autoneg: true when autoneg or autotry is enabled
383 * Determines the link capabilities by reading the AUTOC register.
385 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
386 ixgbe_link_speed *speed,
389 s32 status = IXGBE_SUCCESS;
392 DEBUGFUNC("ixgbe_get_link_capabilities_82599");
395 /* Check if 1G SFP module. */
396 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
397 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
398 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
399 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
400 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
401 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
402 *speed = IXGBE_LINK_SPEED_1GB_FULL;
408 * Determine link capabilities based on the stored value of AUTOC,
409 * which represents EEPROM defaults. If AUTOC value has not
410 * been stored, use the current register values.
412 if (hw->mac.orig_link_settings_stored)
413 autoc = hw->mac.orig_autoc;
415 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
417 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
418 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
419 *speed = IXGBE_LINK_SPEED_1GB_FULL;
423 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
424 *speed = IXGBE_LINK_SPEED_10GB_FULL;
428 case IXGBE_AUTOC_LMS_1G_AN:
429 *speed = IXGBE_LINK_SPEED_1GB_FULL;
433 case IXGBE_AUTOC_LMS_10G_SERIAL:
434 *speed = IXGBE_LINK_SPEED_10GB_FULL;
438 case IXGBE_AUTOC_LMS_KX4_KX_KR:
439 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
440 *speed = IXGBE_LINK_SPEED_UNKNOWN;
441 if (autoc & IXGBE_AUTOC_KR_SUPP)
442 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
443 if (autoc & IXGBE_AUTOC_KX4_SUPP)
444 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
445 if (autoc & IXGBE_AUTOC_KX_SUPP)
446 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
450 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
451 *speed = IXGBE_LINK_SPEED_100_FULL;
452 if (autoc & IXGBE_AUTOC_KR_SUPP)
453 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
454 if (autoc & IXGBE_AUTOC_KX4_SUPP)
455 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
456 if (autoc & IXGBE_AUTOC_KX_SUPP)
457 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
461 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
462 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
467 status = IXGBE_ERR_LINK_SETUP;
472 if (hw->phy.multispeed_fiber) {
473 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
474 IXGBE_LINK_SPEED_1GB_FULL;
476 /* QSFP must not enable full auto-negotiation
477 * Limited autoneg is enabled at 1G
479 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp)
490 * ixgbe_get_media_type_82599 - Get media type
491 * @hw: pointer to hardware structure
493 * Returns the media type (fiber, copper, backplane)
495 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
497 enum ixgbe_media_type media_type;
499 DEBUGFUNC("ixgbe_get_media_type_82599");
501 /* Detect if there is a copper PHY attached. */
502 switch (hw->phy.type) {
503 case ixgbe_phy_cu_unknown:
505 media_type = ixgbe_media_type_copper;
511 switch (hw->device_id) {
512 case IXGBE_DEV_ID_82599_KX4:
513 case IXGBE_DEV_ID_82599_KX4_MEZZ:
514 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
515 case IXGBE_DEV_ID_82599_KR:
516 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
517 case IXGBE_DEV_ID_82599_XAUI_LOM:
518 /* Default device ID is mezzanine card KX/KX4 */
519 media_type = ixgbe_media_type_backplane;
521 case IXGBE_DEV_ID_82599_SFP:
522 case IXGBE_DEV_ID_82599_SFP_FCOE:
523 case IXGBE_DEV_ID_82599_SFP_EM:
524 case IXGBE_DEV_ID_82599_SFP_SF2:
525 case IXGBE_DEV_ID_82599_SFP_SF_QP:
526 case IXGBE_DEV_ID_82599EN_SFP:
527 media_type = ixgbe_media_type_fiber;
529 case IXGBE_DEV_ID_82599_CX4:
530 media_type = ixgbe_media_type_cx4;
532 case IXGBE_DEV_ID_82599_T3_LOM:
533 media_type = ixgbe_media_type_copper;
535 case IXGBE_DEV_ID_82599_LS:
536 media_type = ixgbe_media_type_fiber_lco;
538 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
539 media_type = ixgbe_media_type_fiber_qsfp;
541 case IXGBE_DEV_ID_82599_BYPASS:
542 media_type = ixgbe_media_type_fiber_fixed;
543 hw->phy.multispeed_fiber = true;
546 media_type = ixgbe_media_type_unknown;
554 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
555 * @hw: pointer to hardware structure
557 * Disables link during D3 power down sequence.
560 void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
565 DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599");
566 ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);
568 if (!ixgbe_mng_present(hw) && !hw->wol_enabled &&
569 ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) {
570 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
571 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;
572 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
577 * ixgbe_start_mac_link_82599 - Setup MAC link settings
578 * @hw: pointer to hardware structure
579 * @autoneg_wait_to_complete: true when waiting for completion is needed
581 * Configures link settings based on values in the ixgbe_hw struct.
582 * Restarts the link. Performs autonegotiation if needed.
584 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
585 bool autoneg_wait_to_complete)
590 s32 status = IXGBE_SUCCESS;
591 bool got_lock = false;
593 DEBUGFUNC("ixgbe_start_mac_link_82599");
596 /* reset_pipeline requires us to hold this lock as it writes to
599 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
600 status = hw->mac.ops.acquire_swfw_sync(hw,
601 IXGBE_GSSR_MAC_CSR_SM);
602 if (status != IXGBE_SUCCESS)
609 ixgbe_reset_pipeline_82599(hw);
612 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
614 /* Only poll for autoneg to complete if specified to do so */
615 if (autoneg_wait_to_complete) {
616 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
617 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
618 IXGBE_AUTOC_LMS_KX4_KX_KR ||
619 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
620 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
621 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
622 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
623 links_reg = 0; /* Just in case Autoneg time = 0 */
624 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
625 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
626 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
630 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
631 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
632 DEBUGOUT("Autoneg did not complete.\n");
637 /* Add delay to filter out noises during initial link setup */
645 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
646 * @hw: pointer to hardware structure
648 * The base drivers may require better control over SFP+ module
649 * PHY states. This includes selectively shutting down the Tx
650 * laser on the PHY, effectively halting physical link.
652 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
654 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
656 /* Blocked by MNG FW so bail */
657 if (ixgbe_check_reset_blocked(hw))
660 /* Disable Tx laser; allow 100us to go dark per spec */
661 esdp_reg |= IXGBE_ESDP_SDP3;
662 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
663 IXGBE_WRITE_FLUSH(hw);
668 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
669 * @hw: pointer to hardware structure
671 * The base drivers may require better control over SFP+ module
672 * PHY states. This includes selectively turning on the Tx
673 * laser on the PHY, effectively starting physical link.
675 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
677 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
679 /* Enable Tx laser; allow 100ms to light up */
680 esdp_reg &= ~IXGBE_ESDP_SDP3;
681 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
682 IXGBE_WRITE_FLUSH(hw);
687 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
688 * @hw: pointer to hardware structure
690 * When the driver changes the link speeds that it can support,
691 * it sets autotry_restart to true to indicate that we need to
692 * initiate a new autotry session with the link partner. To do
693 * so, we set the speed then disable and re-enable the Tx laser, to
694 * alert the link partner that it also needs to restart autotry on its
695 * end. This is consistent with true clause 37 autoneg, which also
696 * involves a loss of signal.
698 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
700 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
702 /* Blocked by MNG FW so bail */
703 if (ixgbe_check_reset_blocked(hw))
706 if (hw->mac.autotry_restart) {
707 ixgbe_disable_tx_laser_multispeed_fiber(hw);
708 ixgbe_enable_tx_laser_multispeed_fiber(hw);
709 hw->mac.autotry_restart = false;
714 * ixgbe_set_hard_rate_select_speed - Set module link speed
715 * @hw: pointer to hardware structure
716 * @speed: link speed to set
718 * Set module link speed via RS0/RS1 rate select pins.
720 void ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw,
721 ixgbe_link_speed speed)
723 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
726 case IXGBE_LINK_SPEED_10GB_FULL:
727 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
729 case IXGBE_LINK_SPEED_1GB_FULL:
730 esdp_reg &= ~IXGBE_ESDP_SDP5;
731 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
734 DEBUGOUT("Invalid fixed module speed\n");
738 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
739 IXGBE_WRITE_FLUSH(hw);
743 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
744 * @hw: pointer to hardware structure
745 * @speed: new link speed
746 * @autoneg_wait_to_complete: true when waiting for completion is needed
748 * Implements the Intel SmartSpeed algorithm.
750 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
751 ixgbe_link_speed speed,
752 bool autoneg_wait_to_complete)
754 s32 status = IXGBE_SUCCESS;
755 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
757 bool link_up = false;
758 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
760 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
762 /* Set autoneg_advertised value based on input link speed */
763 hw->phy.autoneg_advertised = 0;
765 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
766 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
768 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
769 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
771 if (speed & IXGBE_LINK_SPEED_100_FULL)
772 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
775 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
776 * autoneg advertisement if link is unable to be established at the
777 * highest negotiated rate. This can sometimes happen due to integrity
778 * issues with the physical media connection.
781 /* First, try to get link with full advertisement */
782 hw->phy.smart_speed_active = false;
783 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
784 status = ixgbe_setup_mac_link_82599(hw, speed,
785 autoneg_wait_to_complete);
786 if (status != IXGBE_SUCCESS)
790 * Wait for the controller to acquire link. Per IEEE 802.3ap,
791 * Section 73.10.2, we may have to wait up to 500ms if KR is
792 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
793 * Table 9 in the AN MAS.
795 for (i = 0; i < 5; i++) {
798 /* If we have link, just jump out */
799 status = ixgbe_check_link(hw, &link_speed, &link_up,
801 if (status != IXGBE_SUCCESS)
810 * We didn't get link. If we advertised KR plus one of KX4/KX
811 * (or BX4/BX), then disable KR and try again.
813 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
814 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
817 /* Turn SmartSpeed on to disable KR support */
818 hw->phy.smart_speed_active = true;
819 status = ixgbe_setup_mac_link_82599(hw, speed,
820 autoneg_wait_to_complete);
821 if (status != IXGBE_SUCCESS)
825 * Wait for the controller to acquire link. 600ms will allow for
826 * the AN link_fail_inhibit_timer as well for multiple cycles of
827 * parallel detect, both 10g and 1g. This allows for the maximum
828 * connect attempts as defined in the AN MAS table 73-7.
830 for (i = 0; i < 6; i++) {
833 /* If we have link, just jump out */
834 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
835 if (status != IXGBE_SUCCESS)
842 /* We didn't get link. Turn SmartSpeed back off. */
843 hw->phy.smart_speed_active = false;
844 status = ixgbe_setup_mac_link_82599(hw, speed,
845 autoneg_wait_to_complete);
848 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
849 DEBUGOUT("Smartspeed has downgraded the link speed "
850 "from the maximum advertised\n");
855 * ixgbe_setup_mac_link_82599 - Set MAC link speed
856 * @hw: pointer to hardware structure
857 * @speed: new link speed
858 * @autoneg_wait_to_complete: true when waiting for completion is needed
860 * Set the link speed in the AUTOC register and restarts link.
862 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
863 ixgbe_link_speed speed,
864 bool autoneg_wait_to_complete)
866 bool autoneg = false;
867 s32 status = IXGBE_SUCCESS;
868 u32 pma_pmd_1g, link_mode;
869 u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); /* holds the value of AUTOC register at this current point in time */
870 u32 orig_autoc = 0; /* holds the cached value of AUTOC register */
871 u32 autoc = current_autoc; /* Temporary variable used for comparison purposes */
872 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
873 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
876 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
878 DEBUGFUNC("ixgbe_setup_mac_link_82599");
880 /* Check to see if speed passed in is supported. */
881 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
885 speed &= link_capabilities;
887 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
888 status = IXGBE_ERR_LINK_SETUP;
892 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
893 if (hw->mac.orig_link_settings_stored)
894 orig_autoc = hw->mac.orig_autoc;
898 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
899 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
901 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
902 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
903 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
904 /* Set KX4/KX/KR support according to speed requested */
905 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
906 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
907 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
908 autoc |= IXGBE_AUTOC_KX4_SUPP;
909 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
910 (hw->phy.smart_speed_active == false))
911 autoc |= IXGBE_AUTOC_KR_SUPP;
913 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
914 autoc |= IXGBE_AUTOC_KX_SUPP;
915 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
916 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
917 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
918 /* Switch from 1G SFI to 10G SFI if requested */
919 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
920 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
921 autoc &= ~IXGBE_AUTOC_LMS_MASK;
922 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
924 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
925 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
926 /* Switch from 10G SFI to 1G SFI if requested */
927 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
928 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
929 autoc &= ~IXGBE_AUTOC_LMS_MASK;
930 if (autoneg || hw->phy.type == ixgbe_phy_qsfp_intel)
931 autoc |= IXGBE_AUTOC_LMS_1G_AN;
933 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
937 if (autoc != current_autoc) {
939 status = hw->mac.ops.prot_autoc_write(hw, autoc, false);
940 if (status != IXGBE_SUCCESS)
943 /* Only poll for autoneg to complete if specified to do so */
944 if (autoneg_wait_to_complete) {
945 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
946 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
947 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
948 links_reg = 0; /*Just in case Autoneg time=0*/
949 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
951 IXGBE_READ_REG(hw, IXGBE_LINKS);
952 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
956 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
958 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
959 DEBUGOUT("Autoneg did not complete.\n");
964 /* Add delay to filter out noises during initial link setup */
973 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
974 * @hw: pointer to hardware structure
975 * @speed: new link speed
976 * @autoneg_wait_to_complete: true if waiting is needed to complete
978 * Restarts link on PHY and MAC based on settings passed in.
980 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
981 ixgbe_link_speed speed,
982 bool autoneg_wait_to_complete)
986 DEBUGFUNC("ixgbe_setup_copper_link_82599");
988 /* Setup the PHY according to input speed */
989 status = hw->phy.ops.setup_link_speed(hw, speed,
990 autoneg_wait_to_complete);
992 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
998 * ixgbe_reset_hw_82599 - Perform hardware reset
999 * @hw: pointer to hardware structure
1001 * Resets the hardware by resetting the transmit and receive units, masks
1002 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1005 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
1007 ixgbe_link_speed link_speed;
1010 u32 i, autoc, autoc2;
1012 bool link_up = false;
1014 DEBUGFUNC("ixgbe_reset_hw_82599");
1016 /* Call adapter stop to disable tx/rx and clear interrupts */
1017 status = hw->mac.ops.stop_adapter(hw);
1018 if (status != IXGBE_SUCCESS)
1021 /* flush pending Tx transactions */
1022 ixgbe_clear_tx_pending(hw);
1024 /* PHY ops must be identified and initialized prior to reset */
1026 /* Identify PHY and related function pointers */
1027 status = hw->phy.ops.init(hw);
1029 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1032 /* Setup SFP module if there is one present. */
1033 if (hw->phy.sfp_setup_needed) {
1034 status = hw->mac.ops.setup_sfp(hw);
1035 hw->phy.sfp_setup_needed = false;
1038 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1042 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
1043 hw->phy.ops.reset(hw);
1045 /* remember AUTOC from before we reset */
1046 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK;
1050 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1051 * If link reset is used when link is up, it might reset the PHY when
1052 * mng is using it. If link is down or the flag to force full link
1053 * reset is set, then perform link reset.
1055 ctrl = IXGBE_CTRL_LNK_RST;
1056 if (!hw->force_full_reset) {
1057 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1059 ctrl = IXGBE_CTRL_RST;
1062 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1063 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1064 IXGBE_WRITE_FLUSH(hw);
1066 /* Poll for reset bit to self-clear meaning reset is complete */
1067 for (i = 0; i < 10; i++) {
1069 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1070 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1074 if (ctrl & IXGBE_CTRL_RST_MASK) {
1075 status = IXGBE_ERR_RESET_FAILED;
1076 DEBUGOUT("Reset polling failed to complete.\n");
1082 * Double resets are required for recovery from certain error
1083 * conditions. Between resets, it is necessary to stall to
1084 * allow time for any pending HW events to complete.
1086 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1087 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1092 * Store the original AUTOC/AUTOC2 values if they have not been
1093 * stored off yet. Otherwise restore the stored original
1094 * values since the reset operation sets back to defaults.
1096 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1097 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1099 /* Enable link if disabled in NVM */
1100 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
1101 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
1102 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1103 IXGBE_WRITE_FLUSH(hw);
1106 if (hw->mac.orig_link_settings_stored == false) {
1107 hw->mac.orig_autoc = autoc;
1108 hw->mac.orig_autoc2 = autoc2;
1109 hw->mac.orig_link_settings_stored = true;
1112 /* If MNG FW is running on a multi-speed device that
1113 * doesn't autoneg with out driver support we need to
1114 * leave LMS in the state it was before we MAC reset.
1115 * Likewise if we support WoL we don't want change the
1118 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) ||
1120 hw->mac.orig_autoc =
1121 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
1124 if (autoc != hw->mac.orig_autoc) {
1125 status = hw->mac.ops.prot_autoc_write(hw,
1128 if (status != IXGBE_SUCCESS)
1132 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1133 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1134 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1135 autoc2 |= (hw->mac.orig_autoc2 &
1136 IXGBE_AUTOC2_UPPER_MASK);
1137 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1141 /* Store the permanent mac address */
1142 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1145 * Store MAC address from RAR0, clear receive address registers, and
1146 * clear the multicast table. Also reset num_rar_entries to 128,
1147 * since we modify this value when programming the SAN MAC address.
1149 hw->mac.num_rar_entries = 128;
1150 hw->mac.ops.init_rx_addrs(hw);
1152 /* Store the permanent SAN mac address */
1153 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1155 /* Add the SAN MAC address to the RAR only if it's a valid address */
1156 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1157 /* Save the SAN MAC RAR index */
1158 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1160 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
1161 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1163 /* clear VMDq pool/queue selection for this RAR */
1164 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
1165 IXGBE_CLEAR_VMDQ_ALL);
1167 /* Reserve the last RAR for the SAN MAC address */
1168 hw->mac.num_rar_entries--;
1171 /* Store the alternative WWNN/WWPN prefix */
1172 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1173 &hw->mac.wwpn_prefix);
1180 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
1181 * @hw: pointer to hardware structure
1182 * @fdircmd: current value of FDIRCMD register
1184 STATIC s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd)
1188 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1189 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1190 if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1191 return IXGBE_SUCCESS;
1195 return IXGBE_ERR_FDIR_CMD_INCOMPLETE;
1199 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1200 * @hw: pointer to hardware structure
1202 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1206 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1208 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1210 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599");
1213 * Before starting reinitialization process,
1214 * FDIRCMD.CMD must be zero.
1216 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1218 DEBUGOUT("Flow Director previous command did not complete, aborting table re-initialization.\n");
1222 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1223 IXGBE_WRITE_FLUSH(hw);
1225 * 82599 adapters flow director init flow cannot be restarted,
1226 * Workaround 82599 silicon errata by performing the following steps
1227 * before re-writing the FDIRCTRL control register with the same value.
1228 * - write 1 to bit 8 of FDIRCMD register &
1229 * - write 0 to bit 8 of FDIRCMD register
1231 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1232 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1233 IXGBE_FDIRCMD_CLEARHT));
1234 IXGBE_WRITE_FLUSH(hw);
1235 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1236 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1237 ~IXGBE_FDIRCMD_CLEARHT));
1238 IXGBE_WRITE_FLUSH(hw);
1240 * Clear FDIR Hash register to clear any leftover hashes
1241 * waiting to be programmed.
1243 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1244 IXGBE_WRITE_FLUSH(hw);
1246 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1247 IXGBE_WRITE_FLUSH(hw);
1249 /* Poll init-done after we write FDIRCTRL register */
1250 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1251 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1252 IXGBE_FDIRCTRL_INIT_DONE)
1256 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1257 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
1258 return IXGBE_ERR_FDIR_REINIT_FAILED;
1261 /* Clear FDIR statistics registers (read to clear) */
1262 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1263 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1264 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1265 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1266 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1268 return IXGBE_SUCCESS;
1272 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1273 * @hw: pointer to hardware structure
1274 * @fdirctrl: value to write to flow director control register
1276 STATIC void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1280 DEBUGFUNC("ixgbe_fdir_enable_82599");
1282 /* Prime the keys for hashing */
1283 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1284 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1287 * Poll init-done after we write the register. Estimated times:
1288 * 10G: PBALLOC = 11b, timing is 60us
1289 * 1G: PBALLOC = 11b, timing is 600us
1290 * 100M: PBALLOC = 11b, timing is 6ms
1292 * Multiple these timings by 4 if under full Rx load
1294 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1295 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1296 * this might not finish in our poll time, but we can live with that
1299 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1300 IXGBE_WRITE_FLUSH(hw);
1301 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1302 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1303 IXGBE_FDIRCTRL_INIT_DONE)
1308 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1309 DEBUGOUT("Flow Director poll time exceeded!\n");
1313 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1314 * @hw: pointer to hardware structure
1315 * @fdirctrl: value to write to flow director control register, initially
1316 * contains just the value of the Rx packet buffer allocation
1318 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1320 DEBUGFUNC("ixgbe_init_fdir_signature_82599");
1323 * Continue setup of fdirctrl register bits:
1324 * Move the flexible bytes to use the ethertype - shift 6 words
1325 * Set the maximum length per hash bucket to 0xA filters
1326 * Send interrupt when 64 filters are left
1328 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1329 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1330 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1332 /* write hashes and fdirctrl register, poll for completion */
1333 ixgbe_fdir_enable_82599(hw, fdirctrl);
1335 return IXGBE_SUCCESS;
1339 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1340 * @hw: pointer to hardware structure
1341 * @fdirctrl: value to write to flow director control register, initially
1342 * contains just the value of the Rx packet buffer allocation
1343 * @cloud_mode: true - cloud mode, false - other mode
1345 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
1348 UNREFERENCED_1PARAMETER(cloud_mode);
1349 DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
1352 * Continue setup of fdirctrl register bits:
1353 * Turn perfect match filtering on
1354 * Report hash in RSS field of Rx wb descriptor
1355 * Initialize the drop queue to queue 127
1356 * Move the flexible bytes to use the ethertype - shift 6 words
1357 * Set the maximum length per hash bucket to 0xA filters
1358 * Send interrupt when 64 (0x4 * 16) filters are left
1360 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1361 IXGBE_FDIRCTRL_REPORT_STATUS |
1362 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1363 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1364 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1365 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1368 fdirctrl |=(IXGBE_FDIRCTRL_FILTERMODE_CLOUD <<
1369 IXGBE_FDIRCTRL_FILTERMODE_SHIFT);
1371 /* write hashes and fdirctrl register, poll for completion */
1372 ixgbe_fdir_enable_82599(hw, fdirctrl);
1374 return IXGBE_SUCCESS;
1378 * ixgbe_set_fdir_drop_queue_82599 - Set Flow Director drop queue
1379 * @hw: pointer to hardware structure
1380 * @dropqueue: Rx queue index used for the dropped packets
1382 void ixgbe_set_fdir_drop_queue_82599(struct ixgbe_hw *hw, u8 dropqueue)
1386 DEBUGFUNC("ixgbe_set_fdir_drop_queue_82599");
1387 /* Clear init done bit and drop queue field */
1388 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1389 fdirctrl &= ~(IXGBE_FDIRCTRL_DROP_Q_MASK | IXGBE_FDIRCTRL_INIT_DONE);
1391 /* Set drop queue */
1392 fdirctrl |= (dropqueue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
1393 if ((hw->mac.type == ixgbe_mac_X550) ||
1394 (hw->mac.type == ixgbe_mac_X550EM_x) ||
1395 (hw->mac.type == ixgbe_mac_X550EM_a))
1396 fdirctrl |= IXGBE_FDIRCTRL_DROP_NO_MATCH;
1398 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1399 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1400 IXGBE_FDIRCMD_CLEARHT));
1401 IXGBE_WRITE_FLUSH(hw);
1402 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1403 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1404 ~IXGBE_FDIRCMD_CLEARHT));
1405 IXGBE_WRITE_FLUSH(hw);
1407 /* write hashes and fdirctrl register, poll for completion */
1408 ixgbe_fdir_enable_82599(hw, fdirctrl);
1412 * These defines allow us to quickly generate all of the necessary instructions
1413 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1414 * for values 0 through 15
1416 #define IXGBE_ATR_COMMON_HASH_KEY \
1417 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1418 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1421 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1422 common_hash ^= lo_hash_dword >> n; \
1423 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1424 bucket_hash ^= lo_hash_dword >> n; \
1425 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1426 sig_hash ^= lo_hash_dword << (16 - n); \
1427 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1428 common_hash ^= hi_hash_dword >> n; \
1429 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1430 bucket_hash ^= hi_hash_dword >> n; \
1431 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1432 sig_hash ^= hi_hash_dword << (16 - n); \
1436 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1437 * @input: input bitstream to compute the hash on
1438 * @common: compressed common input dword
1440 * This function is almost identical to the function above but contains
1441 * several optimizations such as unwinding all of the loops, letting the
1442 * compiler work out all of the conditional ifs since the keys are static
1443 * defines, and computing two keys at once since the hashed dword stream
1444 * will be the same for both keys.
1446 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1447 union ixgbe_atr_hash_dword common)
1449 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1450 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1452 /* record the flow_vm_vlan bits as they are a key part to the hash */
1453 flow_vm_vlan = IXGBE_NTOHL(input.dword);
1455 /* generate common hash dword */
1456 hi_hash_dword = IXGBE_NTOHL(common.dword);
1458 /* low dword is word swapped version of common */
1459 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1461 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1462 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1464 /* Process bits 0 and 16 */
1465 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1468 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1469 * delay this because bit 0 of the stream should not be processed
1470 * so we do not add the VLAN until after bit 0 was processed
1472 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1474 /* Process remaining 30 bit of the key */
1475 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1476 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1477 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1478 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1479 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1480 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1481 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1482 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1483 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1484 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1485 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1486 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1487 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1488 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1489 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1491 /* combine common_hash result with signature and bucket hashes */
1492 bucket_hash ^= common_hash;
1493 bucket_hash &= IXGBE_ATR_HASH_MASK;
1495 sig_hash ^= common_hash << 16;
1496 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1498 /* return completed signature hash */
1499 return sig_hash ^ bucket_hash;
1503 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1504 * @hw: pointer to hardware structure
1505 * @input: unique input dword
1506 * @common: compressed common input dword
1507 * @queue: queue index to direct traffic to
1509 * Note that the tunnel bit in input must not be set when the hardware
1510 * tunneling support does not exist.
1512 void ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1513 union ixgbe_atr_hash_dword input,
1514 union ixgbe_atr_hash_dword common,
1522 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
1525 * Get the flow_type in order to program FDIRCMD properly
1526 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1527 * fifth is FDIRCMD.TUNNEL_FILTER
1529 tunnel = !!(input.formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK);
1530 flow_type = input.formatted.flow_type &
1531 (IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1);
1532 switch (flow_type) {
1533 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1534 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1535 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1536 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1537 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1538 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1541 DEBUGOUT(" Error on flow type input\n");
1545 /* configure FDIRCMD register */
1546 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1547 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1548 fdircmd |= (u32)flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1549 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1551 fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER;
1554 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1555 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1557 fdirhashcmd = (u64)fdircmd << 32;
1558 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1559 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1561 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1566 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1569 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1570 bucket_hash ^= lo_hash_dword >> n; \
1571 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1572 bucket_hash ^= hi_hash_dword >> n; \
1576 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1577 * @input: input bitstream to compute the hash on
1578 * @input_mask: mask for the input bitstream
1580 * This function serves two main purposes. First it applies the input_mask
1581 * to the atr_input resulting in a cleaned up atr_input data stream.
1582 * Secondly it computes the hash and stores it in the bkt_hash field at
1583 * the end of the input byte stream. This way it will be available for
1584 * future use without needing to recompute the hash.
1586 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1587 union ixgbe_atr_input *input_mask)
1590 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1591 u32 bucket_hash = 0;
1595 /* Apply masks to input data */
1596 for (i = 0; i < 14; i++)
1597 input->dword_stream[i] &= input_mask->dword_stream[i];
1599 /* record the flow_vm_vlan bits as they are a key part to the hash */
1600 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
1602 /* generate common hash dword */
1603 for (i = 1; i <= 13; i++)
1604 hi_dword ^= input->dword_stream[i];
1605 hi_hash_dword = IXGBE_NTOHL(hi_dword);
1607 /* low dword is word swapped version of common */
1608 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1610 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1611 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1613 /* Process bits 0 and 16 */
1614 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1617 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1618 * delay this because bit 0 of the stream should not be processed
1619 * so we do not add the VLAN until after bit 0 was processed
1621 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1623 /* Process remaining 30 bit of the key */
1624 for (i = 1; i <= 15; i++)
1625 IXGBE_COMPUTE_BKT_HASH_ITERATION(i);
1628 * Limit hash to 13 bits since max bucket count is 8K.
1629 * Store result at the end of the input stream.
1631 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1635 * ixgbe_get_fdirtcpm_82599 - generate a TCP port from atr_input_masks
1636 * @input_mask: mask to be bit swapped
1638 * The source and destination port masks for flow director are bit swapped
1639 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1640 * generate a correctly swapped value we need to bit swap the mask and that
1641 * is what is accomplished by this function.
1643 STATIC u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1645 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
1646 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1647 mask |= IXGBE_NTOHS(input_mask->formatted.src_port);
1648 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1649 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1650 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1651 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1655 * These two macros are meant to address the fact that we have registers
1656 * that are either all or in part big-endian. As a result on big-endian
1657 * systems we will end up byte swapping the value to little-endian before
1658 * it is byte swapped again and written to the hardware in the original
1659 * big-endian format.
1661 #define IXGBE_STORE_AS_BE32(_value) \
1662 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1663 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1665 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1666 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
1668 #define IXGBE_STORE_AS_BE16(_value) \
1669 IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1671 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1672 union ixgbe_atr_input *input_mask, bool cloud_mode)
1674 /* mask IPv6 since it is currently not supported */
1675 u32 fdirm = IXGBE_FDIRM_DIPv6;
1678 UNREFERENCED_1PARAMETER(cloud_mode);
1679 DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
1682 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1683 * are zero, then assume a full mask for that field. Also assume that
1684 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1685 * cannot be masked out in this implementation.
1687 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1691 /* verify bucket hash is cleared on hash generation */
1692 if (input_mask->formatted.bkt_hash)
1693 DEBUGOUT(" bucket hash should always be 0 in mask\n");
1695 /* Program FDIRM and verify partial masks */
1696 switch (input_mask->formatted.vm_pool & 0x7F) {
1698 fdirm |= IXGBE_FDIRM_POOL;
1702 DEBUGOUT(" Error on vm pool mask\n");
1703 return IXGBE_ERR_CONFIG;
1706 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1708 fdirm |= IXGBE_FDIRM_L4P;
1709 if (input_mask->formatted.dst_port ||
1710 input_mask->formatted.src_port) {
1711 DEBUGOUT(" Error on src/dst port mask\n");
1712 return IXGBE_ERR_CONFIG;
1714 case IXGBE_ATR_L4TYPE_MASK:
1717 DEBUGOUT(" Error on flow type mask\n");
1718 return IXGBE_ERR_CONFIG;
1721 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
1724 fdirm |= IXGBE_FDIRM_VLANID;
1727 /* mask VLAN priority */
1728 fdirm |= IXGBE_FDIRM_VLANP;
1731 /* mask VLAN ID only */
1732 fdirm |= IXGBE_FDIRM_VLANID;
1735 /* no VLAN fields masked */
1738 DEBUGOUT(" Error on VLAN mask\n");
1739 return IXGBE_ERR_CONFIG;
1742 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1744 /* Mask Flex Bytes */
1745 fdirm |= IXGBE_FDIRM_FLEX;
1750 DEBUGOUT(" Error on flexible byte mask\n");
1751 return IXGBE_ERR_CONFIG;
1755 fdirm |= IXGBE_FDIRM_L3P;
1756 fdirip6m = ((u32) 0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT);
1757 fdirip6m |= IXGBE_FDIRIP6M_ALWAYS_MASK;
1759 switch (input_mask->formatted.inner_mac[0] & 0xFF) {
1761 /* Mask inner MAC, fall through */
1762 fdirip6m |= IXGBE_FDIRIP6M_INNER_MAC;
1766 DEBUGOUT(" Error on inner_mac byte mask\n");
1767 return IXGBE_ERR_CONFIG;
1770 switch (input_mask->formatted.tni_vni & 0xFFFFFFFF) {
1773 fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI;
1776 fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI_24;
1781 DEBUGOUT(" Error on TNI/VNI byte mask\n");
1782 return IXGBE_ERR_CONFIG;
1785 switch (input_mask->formatted.tunnel_type & 0xFFFF) {
1787 /* Mask turnnel type, fall through */
1788 fdirip6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE;
1792 DEBUGOUT(" Error on tunnel type byte mask\n");
1793 return IXGBE_ERR_CONFIG;
1795 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m);
1797 /* Set all bits in FDIRTCPM, FDIRUDPM, FDIRSCTPM,
1798 * FDIRSIP4M and FDIRDIP4M in cloud mode to allow
1799 * L3/L3 packets to tunnel.
1801 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF);
1802 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF);
1803 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF);
1804 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF);
1805 switch (hw->mac.type) {
1806 case ixgbe_mac_X550:
1807 case ixgbe_mac_X550EM_x:
1808 case ixgbe_mac_X550EM_a:
1809 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, 0xFFFFFFFF);
1816 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1817 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1820 /* store the TCP/UDP port masks, bit reversed from port
1822 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1824 /* write both the same so that UDP and TCP use the same mask */
1825 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1826 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1827 /* also use it for SCTP */
1828 switch (hw->mac.type) {
1829 case ixgbe_mac_X550:
1830 case ixgbe_mac_X550EM_x:
1831 case ixgbe_mac_X550EM_a:
1832 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);
1838 /* store source and destination IP masks (big-enian) */
1839 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1840 ~input_mask->formatted.src_ip[0]);
1841 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1842 ~input_mask->formatted.dst_ip[0]);
1844 return IXGBE_SUCCESS;
1847 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1848 union ixgbe_atr_input *input,
1849 u16 soft_id, u8 queue, bool cloud_mode)
1851 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1852 u32 addr_low, addr_high;
1855 UNREFERENCED_1PARAMETER(cloud_mode);
1857 DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
1859 /* currently IPv6 is not supported, must be programmed with 0 */
1860 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1861 input->formatted.src_ip[0]);
1862 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1863 input->formatted.src_ip[1]);
1864 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1865 input->formatted.src_ip[2]);
1867 /* record the source address (big-endian) */
1868 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA,
1869 input->formatted.src_ip[0]);
1871 /* record the first 32 bits of the destination address
1873 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA,
1874 input->formatted.dst_ip[0]);
1876 /* record source and destination port (little-endian)*/
1877 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
1878 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1879 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
1880 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1883 /* record VLAN (little-endian) and flex_bytes(big-endian) */
1884 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1885 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1886 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1887 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1890 if (input->formatted.tunnel_type != 0)
1891 cloud_type = 0x80000000;
1893 addr_low = ((u32)input->formatted.inner_mac[0] |
1894 ((u32)input->formatted.inner_mac[1] << 8) |
1895 ((u32)input->formatted.inner_mac[2] << 16) |
1896 ((u32)input->formatted.inner_mac[3] << 24));
1897 addr_high = ((u32)input->formatted.inner_mac[4] |
1898 ((u32)input->formatted.inner_mac[5] << 8));
1899 cloud_type |= addr_high;
1900 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), addr_low);
1901 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), cloud_type);
1902 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), input->formatted.tni_vni);
1905 /* configure FDIRHASH register */
1906 fdirhash = input->formatted.bkt_hash;
1907 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1908 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1911 * flush all previous writes to make certain registers are
1912 * programmed prior to issuing the command
1914 IXGBE_WRITE_FLUSH(hw);
1916 /* configure FDIRCMD register */
1917 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1918 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1919 if (queue == IXGBE_FDIR_DROP_QUEUE)
1920 fdircmd |= IXGBE_FDIRCMD_DROP;
1921 if (input->formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK)
1922 fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER;
1923 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1924 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1925 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1927 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1928 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1930 DEBUGOUT("Flow Director command did not complete!\n");
1934 return IXGBE_SUCCESS;
1937 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1938 union ixgbe_atr_input *input,
1945 /* configure FDIRHASH register */
1946 fdirhash = input->formatted.bkt_hash;
1947 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1948 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1950 /* flush hash to HW */
1951 IXGBE_WRITE_FLUSH(hw);
1953 /* Query if filter is present */
1954 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1956 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1958 DEBUGOUT("Flow Director command did not complete!\n");
1962 /* if filter exists in hardware then remove it */
1963 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1964 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1965 IXGBE_WRITE_FLUSH(hw);
1966 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1967 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1970 return IXGBE_SUCCESS;
1974 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1975 * @hw: pointer to hardware structure
1976 * @input: input bitstream
1977 * @input_mask: mask for the input bitstream
1978 * @soft_id: software index for the filters
1979 * @queue: queue index to direct traffic to
1980 * @cloud_mode: unused
1982 * Note that the caller to this function must lock before calling, since the
1983 * hardware writes must be protected from one another.
1985 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1986 union ixgbe_atr_input *input,
1987 union ixgbe_atr_input *input_mask,
1988 u16 soft_id, u8 queue, bool cloud_mode)
1990 s32 err = IXGBE_ERR_CONFIG;
1991 UNREFERENCED_1PARAMETER(cloud_mode);
1993 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
1996 * Check flow_type formatting, and bail out before we touch the hardware
1997 * if there's a configuration issue
1999 switch (input->formatted.flow_type) {
2000 case IXGBE_ATR_FLOW_TYPE_IPV4:
2001 case IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4:
2002 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
2003 if (input->formatted.dst_port || input->formatted.src_port) {
2004 DEBUGOUT(" Error on src/dst port\n");
2005 return IXGBE_ERR_CONFIG;
2008 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2009 case IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4:
2010 if (input->formatted.dst_port || input->formatted.src_port) {
2011 DEBUGOUT(" Error on src/dst port\n");
2012 return IXGBE_ERR_CONFIG;
2015 case IXGBE_ATR_FLOW_TYPE_TCPV4:
2016 case IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4:
2017 case IXGBE_ATR_FLOW_TYPE_UDPV4:
2018 case IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4:
2019 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2020 IXGBE_ATR_L4TYPE_MASK;
2023 DEBUGOUT(" Error on flow type input\n");
2027 /* program input mask into the HW */
2028 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask, cloud_mode);
2032 /* apply mask and compute/store hash */
2033 ixgbe_atr_compute_perfect_hash_82599(input, input_mask);
2035 /* program filters to filter memory */
2036 return ixgbe_fdir_write_perfect_filter_82599(hw, input,
2037 soft_id, queue, cloud_mode);
2041 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
2042 * @hw: pointer to hardware structure
2043 * @reg: analog register to read
2046 * Performs read operation to Omer analog register specified.
2048 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
2052 DEBUGFUNC("ixgbe_read_analog_reg8_82599");
2054 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2056 IXGBE_WRITE_FLUSH(hw);
2058 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2059 *val = (u8)core_ctl;
2061 return IXGBE_SUCCESS;
2065 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2066 * @hw: pointer to hardware structure
2067 * @reg: atlas register to write
2068 * @val: value to write
2070 * Performs write operation to Omer analog register specified.
2072 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
2076 DEBUGFUNC("ixgbe_write_analog_reg8_82599");
2078 core_ctl = (reg << 8) | val;
2079 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2080 IXGBE_WRITE_FLUSH(hw);
2083 return IXGBE_SUCCESS;
2087 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2088 * @hw: pointer to hardware structure
2090 * Starts the hardware using the generic start_hw function
2091 * and the generation start_hw function.
2092 * Then performs revision-specific operations, if any.
2094 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
2096 s32 ret_val = IXGBE_SUCCESS;
2098 DEBUGFUNC("ixgbe_start_hw_82599");
2100 ret_val = ixgbe_start_hw_generic(hw);
2101 if (ret_val != IXGBE_SUCCESS)
2104 ret_val = ixgbe_start_hw_gen2(hw);
2105 if (ret_val != IXGBE_SUCCESS)
2108 /* We need to run link autotry after the driver loads */
2109 hw->mac.autotry_restart = true;
2111 if (ret_val == IXGBE_SUCCESS)
2112 ret_val = ixgbe_verify_fw_version_82599(hw);
2118 * ixgbe_identify_phy_82599 - Get physical layer module
2119 * @hw: pointer to hardware structure
2121 * Determines the physical layer module found on the current adapter.
2122 * If PHY already detected, maintains current PHY type in hw struct,
2123 * otherwise executes the PHY detection routine.
2125 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
2129 DEBUGFUNC("ixgbe_identify_phy_82599");
2131 /* Detect PHY if not unknown - returns success if already detected. */
2132 status = ixgbe_identify_phy_generic(hw);
2133 if (status != IXGBE_SUCCESS) {
2134 /* 82599 10GBASE-T requires an external PHY */
2135 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
2138 status = ixgbe_identify_module_generic(hw);
2141 /* Set PHY type none if no PHY detected */
2142 if (hw->phy.type == ixgbe_phy_unknown) {
2143 hw->phy.type = ixgbe_phy_none;
2144 return IXGBE_SUCCESS;
2147 /* Return error if SFP module has been detected but is not supported */
2148 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
2149 return IXGBE_ERR_SFP_NOT_SUPPORTED;
2155 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2156 * @hw: pointer to hardware structure
2158 * Determines physical layer capabilities of the current configuration.
2160 u64 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2162 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2163 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2164 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2165 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2166 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2167 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2168 u16 ext_ability = 0;
2170 DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
2172 hw->phy.ops.identify(hw);
2174 switch (hw->phy.type) {
2176 case ixgbe_phy_cu_unknown:
2177 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2178 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
2179 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2180 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2181 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2182 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2183 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
2184 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2190 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2191 case IXGBE_AUTOC_LMS_1G_AN:
2192 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2193 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2194 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2195 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2198 /* SFI mode so read SFP module */
2201 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2202 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2203 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2204 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2205 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2206 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2207 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2210 case IXGBE_AUTOC_LMS_10G_SERIAL:
2211 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2212 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2214 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2217 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2218 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2219 if (autoc & IXGBE_AUTOC_KX_SUPP)
2220 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2221 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2222 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2223 if (autoc & IXGBE_AUTOC_KR_SUPP)
2224 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2233 /* SFP check must be done last since DA modules are sometimes used to
2234 * test KR mode - we need to id KR mode correctly before SFP module.
2235 * Call identify_sfp because the pluggable module may have changed */
2236 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2238 return physical_layer;
2242 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2243 * @hw: pointer to hardware structure
2244 * @regval: register value to write to RXCTRL
2246 * Enables the Rx DMA unit for 82599
2248 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2251 DEBUGFUNC("ixgbe_enable_rx_dma_82599");
2254 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2255 * If traffic is incoming before we enable the Rx unit, it could hang
2256 * the Rx DMA unit. Therefore, make sure the security engine is
2257 * completely disabled prior to enabling the Rx unit.
2260 hw->mac.ops.disable_sec_rx_path(hw);
2262 if (regval & IXGBE_RXCTRL_RXEN)
2263 ixgbe_enable_rx(hw);
2265 ixgbe_disable_rx(hw);
2267 hw->mac.ops.enable_sec_rx_path(hw);
2269 return IXGBE_SUCCESS;
2273 * ixgbe_verify_fw_version_82599 - verify FW version for 82599
2274 * @hw: pointer to hardware structure
2276 * Verifies that installed the firmware version is 0.6 or higher
2277 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2279 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2280 * if the FW version is not supported.
2282 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2284 s32 status = IXGBE_ERR_EEPROM_VERSION;
2285 u16 fw_offset, fw_ptp_cfg_offset;
2288 DEBUGFUNC("ixgbe_verify_fw_version_82599");
2290 /* firmware check is only necessary for SFI devices */
2291 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2292 status = IXGBE_SUCCESS;
2293 goto fw_version_out;
2296 /* get the offset to the Firmware Module block */
2297 if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) {
2298 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2299 "eeprom read at offset %d failed", IXGBE_FW_PTR);
2300 return IXGBE_ERR_EEPROM_VERSION;
2303 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2304 goto fw_version_out;
2306 /* get the offset to the Pass Through Patch Configuration block */
2307 if (hw->eeprom.ops.read(hw, (fw_offset +
2308 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2309 &fw_ptp_cfg_offset)) {
2310 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2311 "eeprom read at offset %d failed",
2313 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR);
2314 return IXGBE_ERR_EEPROM_VERSION;
2317 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2318 goto fw_version_out;
2320 /* get the firmware version */
2321 if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2322 IXGBE_FW_PATCH_VERSION_4), &fw_version)) {
2323 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2324 "eeprom read at offset %d failed",
2325 fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4);
2326 return IXGBE_ERR_EEPROM_VERSION;
2329 if (fw_version > 0x5)
2330 status = IXGBE_SUCCESS;
2337 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2338 * @hw: pointer to hardware structure
2340 * Returns true if the LESM FW module is present and enabled. Otherwise
2341 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2343 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2345 bool lesm_enabled = false;
2346 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2349 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599");
2351 /* get the offset to the Firmware Module block */
2352 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2354 if ((status != IXGBE_SUCCESS) ||
2355 (fw_offset == 0) || (fw_offset == 0xFFFF))
2358 /* get the offset to the LESM Parameters block */
2359 status = hw->eeprom.ops.read(hw, (fw_offset +
2360 IXGBE_FW_LESM_PARAMETERS_PTR),
2361 &fw_lesm_param_offset);
2363 if ((status != IXGBE_SUCCESS) ||
2364 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2367 /* get the LESM state word */
2368 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2369 IXGBE_FW_LESM_STATE_1),
2372 if ((status == IXGBE_SUCCESS) &&
2373 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2374 lesm_enabled = true;
2377 return lesm_enabled;
2381 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2382 * fastest available method
2384 * @hw: pointer to hardware structure
2385 * @offset: offset of word in EEPROM to read
2386 * @words: number of words
2387 * @data: word(s) read from the EEPROM
2389 * Retrieves 16 bit word(s) read from EEPROM
2391 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2392 u16 words, u16 *data)
2394 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2395 s32 ret_val = IXGBE_ERR_CONFIG;
2397 DEBUGFUNC("ixgbe_read_eeprom_buffer_82599");
2400 * If EEPROM is detected and can be addressed using 14 bits,
2401 * use EERD otherwise use bit bang
2403 if ((eeprom->type == ixgbe_eeprom_spi) &&
2404 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2405 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2408 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2416 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2417 * fastest available method
2419 * @hw: pointer to hardware structure
2420 * @offset: offset of word in the EEPROM to read
2421 * @data: word read from the EEPROM
2423 * Reads a 16 bit word from the EEPROM
2425 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2426 u16 offset, u16 *data)
2428 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2429 s32 ret_val = IXGBE_ERR_CONFIG;
2431 DEBUGFUNC("ixgbe_read_eeprom_82599");
2434 * If EEPROM is detected and can be addressed using 14 bits,
2435 * use EERD otherwise use bit bang
2437 if ((eeprom->type == ixgbe_eeprom_spi) &&
2438 (offset <= IXGBE_EERD_MAX_ADDR))
2439 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2441 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2447 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2449 * @hw: pointer to hardware structure
2451 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2452 * full pipeline reset. This function assumes the SW/FW lock is held.
2454 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2458 u32 i, autoc_reg, autoc2_reg;
2460 /* Enable link if disabled in NVM */
2461 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2462 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
2463 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
2464 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
2465 IXGBE_WRITE_FLUSH(hw);
2468 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2469 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2470 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2471 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
2472 autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT));
2473 /* Wait for AN to leave state 0 */
2474 for (i = 0; i < 10; i++) {
2476 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2477 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2481 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2482 DEBUGOUT("auto negotiation not completed\n");
2483 ret_val = IXGBE_ERR_RESET_FAILED;
2484 goto reset_pipeline_out;
2487 ret_val = IXGBE_SUCCESS;
2490 /* Write AUTOC register with original LMS field and Restart_AN */
2491 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2492 IXGBE_WRITE_FLUSH(hw);
2498 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
2499 * @hw: pointer to hardware structure
2500 * @byte_offset: byte offset to read
2501 * @dev_addr: address to read from
2504 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2505 * a specified device address.
2507 STATIC s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2508 u8 dev_addr, u8 *data)
2514 DEBUGFUNC("ixgbe_read_i2c_byte_82599");
2516 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2517 /* Acquire I2C bus ownership. */
2518 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2519 esdp |= IXGBE_ESDP_SDP0;
2520 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2521 IXGBE_WRITE_FLUSH(hw);
2524 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2525 if (esdp & IXGBE_ESDP_SDP1)
2533 DEBUGOUT("Driver can't access resource,"
2534 " acquiring I2C bus timeout.\n");
2535 status = IXGBE_ERR_I2C;
2536 goto release_i2c_access;
2540 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2544 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2545 /* Release I2C bus ownership. */
2546 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2547 esdp &= ~IXGBE_ESDP_SDP0;
2548 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2549 IXGBE_WRITE_FLUSH(hw);
2556 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
2557 * @hw: pointer to hardware structure
2558 * @byte_offset: byte offset to write
2559 * @dev_addr: address to read from
2560 * @data: value to write
2562 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2563 * a specified device address.
2565 STATIC s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2566 u8 dev_addr, u8 data)
2572 DEBUGFUNC("ixgbe_write_i2c_byte_82599");
2574 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2575 /* Acquire I2C bus ownership. */
2576 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2577 esdp |= IXGBE_ESDP_SDP0;
2578 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2579 IXGBE_WRITE_FLUSH(hw);
2582 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2583 if (esdp & IXGBE_ESDP_SDP1)
2591 DEBUGOUT("Driver can't access resource,"
2592 " acquiring I2C bus timeout.\n");
2593 status = IXGBE_ERR_I2C;
2594 goto release_i2c_access;
2598 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2602 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2603 /* Release I2C bus ownership. */
2604 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2605 esdp &= ~IXGBE_ESDP_SDP0;
2606 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2607 IXGBE_WRITE_FLUSH(hw);