1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_type.h"
35 #include "ixgbe_82599.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
40 #define IXGBE_82599_MAX_TX_QUEUES 128
41 #define IXGBE_82599_MAX_RX_QUEUES 128
42 #define IXGBE_82599_RAR_ENTRIES 128
43 #define IXGBE_82599_MC_TBL_SIZE 128
44 #define IXGBE_82599_VFT_TBL_SIZE 128
45 #define IXGBE_82599_RX_PB_SIZE 512
47 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
48 ixgbe_link_speed speed,
49 bool autoneg_wait_to_complete);
50 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
51 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
52 u16 offset, u16 *data);
53 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
54 u16 words, u16 *data);
55 STATIC s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
56 u8 dev_addr, u8 *data);
57 STATIC s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
58 u8 dev_addr, u8 data);
60 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
62 struct ixgbe_mac_info *mac = &hw->mac;
64 DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
67 * enable the laser control functions for SFP+ fiber
70 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
71 !ixgbe_mng_enabled(hw)) {
72 mac->ops.disable_tx_laser =
73 ixgbe_disable_tx_laser_multispeed_fiber;
74 mac->ops.enable_tx_laser =
75 ixgbe_enable_tx_laser_multispeed_fiber;
76 mac->ops.flap_tx_laser = ixgbe_flap_tx_laser_multispeed_fiber;
79 mac->ops.disable_tx_laser = NULL;
80 mac->ops.enable_tx_laser = NULL;
81 mac->ops.flap_tx_laser = NULL;
84 if (hw->phy.multispeed_fiber) {
85 /* Set up dual speed SFP+ support */
86 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
87 mac->ops.setup_mac_link = ixgbe_setup_mac_link_82599;
88 mac->ops.set_rate_select_speed =
89 ixgbe_set_hard_rate_select_speed;
91 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
92 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
93 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
94 !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
95 mac->ops.setup_link = ixgbe_setup_mac_link_smartspeed;
97 mac->ops.setup_link = ixgbe_setup_mac_link_82599;
103 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
104 * @hw: pointer to hardware structure
106 * Initialize any function pointers that were not able to be
107 * set during init_shared_code because the PHY/SFP type was
108 * not known. Perform the SFP init if necessary.
111 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
113 struct ixgbe_mac_info *mac = &hw->mac;
114 struct ixgbe_phy_info *phy = &hw->phy;
115 s32 ret_val = IXGBE_SUCCESS;
118 DEBUGFUNC("ixgbe_init_phy_ops_82599");
120 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) {
121 /* Store flag indicating I2C bus access control unit. */
122 hw->phy.qsfp_shared_i2c_bus = TRUE;
124 /* Initialize access to QSFP+ I2C bus */
125 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
126 esdp |= IXGBE_ESDP_SDP0_DIR;
127 esdp &= ~IXGBE_ESDP_SDP1_DIR;
128 esdp &= ~IXGBE_ESDP_SDP0;
129 esdp &= ~IXGBE_ESDP_SDP0_NATIVE;
130 esdp &= ~IXGBE_ESDP_SDP1_NATIVE;
131 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
132 IXGBE_WRITE_FLUSH(hw);
134 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_82599;
135 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_82599;
137 /* Identify the PHY or SFP module */
138 ret_val = phy->ops.identify(hw);
139 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
140 goto init_phy_ops_out;
142 /* Setup function pointers based on detected SFP module and speeds */
143 ixgbe_init_mac_link_ops_82599(hw);
144 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
145 hw->phy.ops.reset = NULL;
147 /* If copper media, overwrite with copper function pointers */
148 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
149 mac->ops.setup_link = ixgbe_setup_copper_link_82599;
150 mac->ops.get_link_capabilities =
151 ixgbe_get_copper_link_capabilities_generic;
154 /* Set necessary function pointers based on PHY type */
155 switch (hw->phy.type) {
157 phy->ops.setup_link = ixgbe_setup_phy_link_tnx;
158 phy->ops.check_link = ixgbe_check_phy_link_tnx;
159 phy->ops.get_firmware_version =
160 ixgbe_get_phy_firmware_version_tnx;
169 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
171 s32 ret_val = IXGBE_SUCCESS;
172 u16 list_offset, data_offset, data_value;
174 DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
176 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
177 ixgbe_init_mac_link_ops_82599(hw);
179 hw->phy.ops.reset = NULL;
181 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
183 if (ret_val != IXGBE_SUCCESS)
186 /* PHY config will finish before releasing the semaphore */
187 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
188 IXGBE_GSSR_MAC_CSR_SM);
189 if (ret_val != IXGBE_SUCCESS) {
190 ret_val = IXGBE_ERR_SWFW_SYNC;
194 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
196 while (data_value != 0xffff) {
197 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
198 IXGBE_WRITE_FLUSH(hw);
199 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
203 /* Release the semaphore */
204 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
205 /* Delay obtaining semaphore again to allow FW access
206 * prot_autoc_write uses the semaphore too.
208 msec_delay(hw->eeprom.semaphore_delay);
210 /* Restart DSP and set SFI mode */
211 ret_val = hw->mac.ops.prot_autoc_write(hw,
212 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL,
216 DEBUGOUT("sfp module setup not complete\n");
217 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
227 /* Release the semaphore */
228 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
229 /* Delay obtaining semaphore again to allow FW access */
230 msec_delay(hw->eeprom.semaphore_delay);
231 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
232 "eeprom read at offset %d failed", data_offset);
233 return IXGBE_ERR_PHY;
237 * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read
238 * @hw: pointer to hardware structure
239 * @locked: Return the if we locked for this read.
240 * @reg_val: Value we read from AUTOC
242 * For this part (82599) we need to wrap read-modify-writes with a possible
243 * FW/SW lock. It is assumed this lock will be freed with the next
244 * prot_autoc_write_82599().
246 s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
251 /* If LESM is on then we need to hold the SW/FW semaphore. */
252 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
253 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
254 IXGBE_GSSR_MAC_CSR_SM);
255 if (ret_val != IXGBE_SUCCESS)
256 return IXGBE_ERR_SWFW_SYNC;
261 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
262 return IXGBE_SUCCESS;
266 * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write
267 * @hw: pointer to hardware structure
268 * @reg_val: value to write to AUTOC
269 * @locked: bool to indicate whether the SW/FW lock was already taken by
270 * previous proc_autoc_read_82599.
272 * This part (82599) may need to hold the SW/FW lock around all writes to
273 * AUTOC. Likewise after a write we need to do a pipeline reset.
275 s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)
277 s32 ret_val = IXGBE_SUCCESS;
279 /* Blocked by MNG FW so bail */
280 if (ixgbe_check_reset_blocked(hw))
283 /* We only need to get the lock if:
284 * - We didn't do it already (in the read part of a read-modify-write)
287 if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) {
288 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
289 IXGBE_GSSR_MAC_CSR_SM);
290 if (ret_val != IXGBE_SUCCESS)
291 return IXGBE_ERR_SWFW_SYNC;
296 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
297 ret_val = ixgbe_reset_pipeline_82599(hw);
300 /* Free the SW/FW semaphore as we either grabbed it here or
301 * already had it when this function was called.
304 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
310 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
311 * @hw: pointer to hardware structure
313 * Initialize the function pointers and assign the MAC type for 82599.
314 * Does not touch the hardware.
317 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
319 struct ixgbe_mac_info *mac = &hw->mac;
320 struct ixgbe_phy_info *phy = &hw->phy;
321 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
324 DEBUGFUNC("ixgbe_init_ops_82599");
326 ixgbe_init_phy_ops_generic(hw);
327 ret_val = ixgbe_init_ops_generic(hw);
330 phy->ops.identify = ixgbe_identify_phy_82599;
331 phy->ops.init = ixgbe_init_phy_ops_82599;
334 mac->ops.reset_hw = ixgbe_reset_hw_82599;
335 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2;
336 mac->ops.get_media_type = ixgbe_get_media_type_82599;
337 mac->ops.get_supported_physical_layer =
338 ixgbe_get_supported_physical_layer_82599;
339 mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic;
340 mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic;
341 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82599;
342 mac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82599;
343 mac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82599;
344 mac->ops.start_hw = ixgbe_start_hw_82599;
345 mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic;
346 mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic;
347 mac->ops.get_device_caps = ixgbe_get_device_caps_generic;
348 mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic;
349 mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic;
350 mac->ops.prot_autoc_read = prot_autoc_read_82599;
351 mac->ops.prot_autoc_write = prot_autoc_write_82599;
353 /* RAR, Multicast, VLAN */
354 mac->ops.set_vmdq = ixgbe_set_vmdq_generic;
355 mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic;
356 mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic;
357 mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic;
358 mac->rar_highwater = 1;
359 mac->ops.set_vfta = ixgbe_set_vfta_generic;
360 mac->ops.set_vlvf = ixgbe_set_vlvf_generic;
361 mac->ops.clear_vfta = ixgbe_clear_vfta_generic;
362 mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic;
363 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_82599;
364 mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing;
365 mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing;
368 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82599;
369 mac->ops.check_link = ixgbe_check_mac_link_generic;
370 mac->ops.setup_rxpba = ixgbe_set_rxpba_generic;
371 ixgbe_init_mac_link_ops_82599(hw);
373 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
374 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
375 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
376 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE;
377 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
378 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
379 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
381 mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw))
382 & IXGBE_FWSM_MODE_MASK);
384 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
387 eeprom->ops.read = ixgbe_read_eeprom_82599;
388 eeprom->ops.read_buffer = ixgbe_read_eeprom_buffer_82599;
390 /* Manageability interface */
391 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic;
393 mac->ops.get_thermal_sensor_data =
394 ixgbe_get_thermal_sensor_data_generic;
395 mac->ops.init_thermal_sensor_thresh =
396 ixgbe_init_thermal_sensor_thresh_generic;
398 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
404 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
405 * @hw: pointer to hardware structure
406 * @speed: pointer to link speed
407 * @autoneg: true when autoneg or autotry is enabled
409 * Determines the link capabilities by reading the AUTOC register.
411 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
412 ixgbe_link_speed *speed,
415 s32 status = IXGBE_SUCCESS;
418 DEBUGFUNC("ixgbe_get_link_capabilities_82599");
421 /* Check if 1G SFP module. */
422 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
423 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
424 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
425 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
426 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
427 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
428 *speed = IXGBE_LINK_SPEED_1GB_FULL;
434 * Determine link capabilities based on the stored value of AUTOC,
435 * which represents EEPROM defaults. If AUTOC value has not
436 * been stored, use the current register values.
438 if (hw->mac.orig_link_settings_stored)
439 autoc = hw->mac.orig_autoc;
441 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
443 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
444 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
445 *speed = IXGBE_LINK_SPEED_1GB_FULL;
449 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
450 *speed = IXGBE_LINK_SPEED_10GB_FULL;
454 case IXGBE_AUTOC_LMS_1G_AN:
455 *speed = IXGBE_LINK_SPEED_1GB_FULL;
459 case IXGBE_AUTOC_LMS_10G_SERIAL:
460 *speed = IXGBE_LINK_SPEED_10GB_FULL;
464 case IXGBE_AUTOC_LMS_KX4_KX_KR:
465 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
466 *speed = IXGBE_LINK_SPEED_UNKNOWN;
467 if (autoc & IXGBE_AUTOC_KR_SUPP)
468 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
469 if (autoc & IXGBE_AUTOC_KX4_SUPP)
470 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
471 if (autoc & IXGBE_AUTOC_KX_SUPP)
472 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
476 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
477 *speed = IXGBE_LINK_SPEED_100_FULL;
478 if (autoc & IXGBE_AUTOC_KR_SUPP)
479 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
480 if (autoc & IXGBE_AUTOC_KX4_SUPP)
481 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
482 if (autoc & IXGBE_AUTOC_KX_SUPP)
483 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
487 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
488 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
493 status = IXGBE_ERR_LINK_SETUP;
498 if (hw->phy.multispeed_fiber) {
499 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
500 IXGBE_LINK_SPEED_1GB_FULL;
502 /* QSFP must not enable full auto-negotiation
503 * Limited autoneg is enabled at 1G
505 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp)
516 * ixgbe_get_media_type_82599 - Get media type
517 * @hw: pointer to hardware structure
519 * Returns the media type (fiber, copper, backplane)
521 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
523 enum ixgbe_media_type media_type;
525 DEBUGFUNC("ixgbe_get_media_type_82599");
527 /* Detect if there is a copper PHY attached. */
528 switch (hw->phy.type) {
529 case ixgbe_phy_cu_unknown:
531 media_type = ixgbe_media_type_copper;
537 switch (hw->device_id) {
538 case IXGBE_DEV_ID_82599_KX4:
539 case IXGBE_DEV_ID_82599_KX4_MEZZ:
540 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
541 case IXGBE_DEV_ID_82599_KR:
542 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
543 case IXGBE_DEV_ID_82599_XAUI_LOM:
544 /* Default device ID is mezzanine card KX/KX4 */
545 media_type = ixgbe_media_type_backplane;
547 case IXGBE_DEV_ID_82599_SFP:
548 case IXGBE_DEV_ID_82599_SFP_FCOE:
549 case IXGBE_DEV_ID_82599_SFP_EM:
550 case IXGBE_DEV_ID_82599_SFP_SF2:
551 case IXGBE_DEV_ID_82599_SFP_SF_QP:
552 case IXGBE_DEV_ID_82599EN_SFP:
553 media_type = ixgbe_media_type_fiber;
555 case IXGBE_DEV_ID_82599_CX4:
556 media_type = ixgbe_media_type_cx4;
558 case IXGBE_DEV_ID_82599_T3_LOM:
559 media_type = ixgbe_media_type_copper;
561 case IXGBE_DEV_ID_82599_LS:
562 media_type = ixgbe_media_type_fiber_lco;
564 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
565 media_type = ixgbe_media_type_fiber_qsfp;
568 media_type = ixgbe_media_type_unknown;
576 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
577 * @hw: pointer to hardware structure
579 * Disables link during D3 power down sequence.
582 void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
587 DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599");
588 ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);
590 if (!ixgbe_mng_present(hw) && !hw->wol_enabled &&
591 ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) {
592 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
593 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;
594 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
599 * ixgbe_start_mac_link_82599 - Setup MAC link settings
600 * @hw: pointer to hardware structure
601 * @autoneg_wait_to_complete: true when waiting for completion is needed
603 * Configures link settings based on values in the ixgbe_hw struct.
604 * Restarts the link. Performs autonegotiation if needed.
606 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
607 bool autoneg_wait_to_complete)
612 s32 status = IXGBE_SUCCESS;
613 bool got_lock = false;
615 DEBUGFUNC("ixgbe_start_mac_link_82599");
618 /* reset_pipeline requires us to hold this lock as it writes to
621 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
622 status = hw->mac.ops.acquire_swfw_sync(hw,
623 IXGBE_GSSR_MAC_CSR_SM);
624 if (status != IXGBE_SUCCESS)
631 ixgbe_reset_pipeline_82599(hw);
634 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
636 /* Only poll for autoneg to complete if specified to do so */
637 if (autoneg_wait_to_complete) {
638 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
639 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
640 IXGBE_AUTOC_LMS_KX4_KX_KR ||
641 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
642 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
643 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
644 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
645 links_reg = 0; /* Just in case Autoneg time = 0 */
646 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
647 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
648 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
652 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
653 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
654 DEBUGOUT("Autoneg did not complete.\n");
659 /* Add delay to filter out noises during initial link setup */
667 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
668 * @hw: pointer to hardware structure
670 * The base drivers may require better control over SFP+ module
671 * PHY states. This includes selectively shutting down the Tx
672 * laser on the PHY, effectively halting physical link.
674 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
676 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
678 /* Blocked by MNG FW so bail */
679 if (ixgbe_check_reset_blocked(hw))
682 /* Disable Tx laser; allow 100us to go dark per spec */
683 esdp_reg |= IXGBE_ESDP_SDP3;
684 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
685 IXGBE_WRITE_FLUSH(hw);
690 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
691 * @hw: pointer to hardware structure
693 * The base drivers may require better control over SFP+ module
694 * PHY states. This includes selectively turning on the Tx
695 * laser on the PHY, effectively starting physical link.
697 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
699 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
701 /* Enable Tx laser; allow 100ms to light up */
702 esdp_reg &= ~IXGBE_ESDP_SDP3;
703 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
704 IXGBE_WRITE_FLUSH(hw);
709 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
710 * @hw: pointer to hardware structure
712 * When the driver changes the link speeds that it can support,
713 * it sets autotry_restart to true to indicate that we need to
714 * initiate a new autotry session with the link partner. To do
715 * so, we set the speed then disable and re-enable the Tx laser, to
716 * alert the link partner that it also needs to restart autotry on its
717 * end. This is consistent with true clause 37 autoneg, which also
718 * involves a loss of signal.
720 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
722 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
724 /* Blocked by MNG FW so bail */
725 if (ixgbe_check_reset_blocked(hw))
728 if (hw->mac.autotry_restart) {
729 ixgbe_disable_tx_laser_multispeed_fiber(hw);
730 ixgbe_enable_tx_laser_multispeed_fiber(hw);
731 hw->mac.autotry_restart = false;
736 * ixgbe_set_hard_rate_select_speed - Set module link speed
737 * @hw: pointer to hardware structure
738 * @speed: link speed to set
740 * Set module link speed via RS0/RS1 rate select pins.
742 void ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw,
743 ixgbe_link_speed speed)
745 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
748 case IXGBE_LINK_SPEED_10GB_FULL:
749 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
751 case IXGBE_LINK_SPEED_1GB_FULL:
752 esdp_reg &= ~IXGBE_ESDP_SDP5;
753 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
756 DEBUGOUT("Invalid fixed module speed\n");
760 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
761 IXGBE_WRITE_FLUSH(hw);
765 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
766 * @hw: pointer to hardware structure
767 * @speed: new link speed
768 * @autoneg_wait_to_complete: true when waiting for completion is needed
770 * Implements the Intel SmartSpeed algorithm.
772 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
773 ixgbe_link_speed speed,
774 bool autoneg_wait_to_complete)
776 s32 status = IXGBE_SUCCESS;
777 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
779 bool link_up = false;
780 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
782 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
784 /* Set autoneg_advertised value based on input link speed */
785 hw->phy.autoneg_advertised = 0;
787 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
788 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
790 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
791 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
793 if (speed & IXGBE_LINK_SPEED_100_FULL)
794 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
797 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
798 * autoneg advertisement if link is unable to be established at the
799 * highest negotiated rate. This can sometimes happen due to integrity
800 * issues with the physical media connection.
803 /* First, try to get link with full advertisement */
804 hw->phy.smart_speed_active = false;
805 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
806 status = ixgbe_setup_mac_link_82599(hw, speed,
807 autoneg_wait_to_complete);
808 if (status != IXGBE_SUCCESS)
812 * Wait for the controller to acquire link. Per IEEE 802.3ap,
813 * Section 73.10.2, we may have to wait up to 500ms if KR is
814 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
815 * Table 9 in the AN MAS.
817 for (i = 0; i < 5; i++) {
820 /* If we have link, just jump out */
821 status = ixgbe_check_link(hw, &link_speed, &link_up,
823 if (status != IXGBE_SUCCESS)
832 * We didn't get link. If we advertised KR plus one of KX4/KX
833 * (or BX4/BX), then disable KR and try again.
835 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
836 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
839 /* Turn SmartSpeed on to disable KR support */
840 hw->phy.smart_speed_active = true;
841 status = ixgbe_setup_mac_link_82599(hw, speed,
842 autoneg_wait_to_complete);
843 if (status != IXGBE_SUCCESS)
847 * Wait for the controller to acquire link. 600ms will allow for
848 * the AN link_fail_inhibit_timer as well for multiple cycles of
849 * parallel detect, both 10g and 1g. This allows for the maximum
850 * connect attempts as defined in the AN MAS table 73-7.
852 for (i = 0; i < 6; i++) {
855 /* If we have link, just jump out */
856 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
857 if (status != IXGBE_SUCCESS)
864 /* We didn't get link. Turn SmartSpeed back off. */
865 hw->phy.smart_speed_active = false;
866 status = ixgbe_setup_mac_link_82599(hw, speed,
867 autoneg_wait_to_complete);
870 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
871 DEBUGOUT("Smartspeed has downgraded the link speed "
872 "from the maximum advertised\n");
877 * ixgbe_setup_mac_link_82599 - Set MAC link speed
878 * @hw: pointer to hardware structure
879 * @speed: new link speed
880 * @autoneg_wait_to_complete: true when waiting for completion is needed
882 * Set the link speed in the AUTOC register and restarts link.
884 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
885 ixgbe_link_speed speed,
886 bool autoneg_wait_to_complete)
888 bool autoneg = false;
889 s32 status = IXGBE_SUCCESS;
890 u32 pma_pmd_1g, link_mode;
891 u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); /* holds the value of AUTOC register at this current point in time */
892 u32 orig_autoc = 0; /* holds the cached value of AUTOC register */
893 u32 autoc = current_autoc; /* Temporary variable used for comparison purposes */
894 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
895 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
898 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
900 DEBUGFUNC("ixgbe_setup_mac_link_82599");
902 /* Check to see if speed passed in is supported. */
903 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
907 speed &= link_capabilities;
909 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
910 status = IXGBE_ERR_LINK_SETUP;
914 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
915 if (hw->mac.orig_link_settings_stored)
916 orig_autoc = hw->mac.orig_autoc;
920 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
921 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
923 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
924 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
925 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
926 /* Set KX4/KX/KR support according to speed requested */
927 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
928 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
929 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
930 autoc |= IXGBE_AUTOC_KX4_SUPP;
931 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
932 (hw->phy.smart_speed_active == false))
933 autoc |= IXGBE_AUTOC_KR_SUPP;
935 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
936 autoc |= IXGBE_AUTOC_KX_SUPP;
937 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
938 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
939 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
940 /* Switch from 1G SFI to 10G SFI if requested */
941 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
942 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
943 autoc &= ~IXGBE_AUTOC_LMS_MASK;
944 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
946 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
947 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
948 /* Switch from 10G SFI to 1G SFI if requested */
949 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
950 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
951 autoc &= ~IXGBE_AUTOC_LMS_MASK;
952 if (autoneg || hw->phy.type == ixgbe_phy_qsfp_intel)
953 autoc |= IXGBE_AUTOC_LMS_1G_AN;
955 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
959 if (autoc != current_autoc) {
961 status = hw->mac.ops.prot_autoc_write(hw, autoc, false);
962 if (status != IXGBE_SUCCESS)
965 /* Only poll for autoneg to complete if specified to do so */
966 if (autoneg_wait_to_complete) {
967 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
968 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
969 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
970 links_reg = 0; /*Just in case Autoneg time=0*/
971 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
973 IXGBE_READ_REG(hw, IXGBE_LINKS);
974 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
978 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
980 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
981 DEBUGOUT("Autoneg did not complete.\n");
986 /* Add delay to filter out noises during initial link setup */
995 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
996 * @hw: pointer to hardware structure
997 * @speed: new link speed
998 * @autoneg_wait_to_complete: true if waiting is needed to complete
1000 * Restarts link on PHY and MAC based on settings passed in.
1002 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
1003 ixgbe_link_speed speed,
1004 bool autoneg_wait_to_complete)
1008 DEBUGFUNC("ixgbe_setup_copper_link_82599");
1010 /* Setup the PHY according to input speed */
1011 status = hw->phy.ops.setup_link_speed(hw, speed,
1012 autoneg_wait_to_complete);
1014 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
1020 * ixgbe_reset_hw_82599 - Perform hardware reset
1021 * @hw: pointer to hardware structure
1023 * Resets the hardware by resetting the transmit and receive units, masks
1024 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1027 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
1029 ixgbe_link_speed link_speed;
1032 u32 i, autoc, autoc2;
1034 bool link_up = false;
1036 DEBUGFUNC("ixgbe_reset_hw_82599");
1038 /* Call adapter stop to disable tx/rx and clear interrupts */
1039 status = hw->mac.ops.stop_adapter(hw);
1040 if (status != IXGBE_SUCCESS)
1043 /* flush pending Tx transactions */
1044 ixgbe_clear_tx_pending(hw);
1046 /* PHY ops must be identified and initialized prior to reset */
1048 /* Identify PHY and related function pointers */
1049 status = hw->phy.ops.init(hw);
1051 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1054 /* Setup SFP module if there is one present. */
1055 if (hw->phy.sfp_setup_needed) {
1056 status = hw->mac.ops.setup_sfp(hw);
1057 hw->phy.sfp_setup_needed = false;
1060 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1064 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
1065 hw->phy.ops.reset(hw);
1067 /* remember AUTOC from before we reset */
1068 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK;
1072 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1073 * If link reset is used when link is up, it might reset the PHY when
1074 * mng is using it. If link is down or the flag to force full link
1075 * reset is set, then perform link reset.
1077 ctrl = IXGBE_CTRL_LNK_RST;
1078 if (!hw->force_full_reset) {
1079 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1081 ctrl = IXGBE_CTRL_RST;
1084 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1085 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1086 IXGBE_WRITE_FLUSH(hw);
1088 /* Poll for reset bit to self-clear meaning reset is complete */
1089 for (i = 0; i < 10; i++) {
1091 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1092 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1096 if (ctrl & IXGBE_CTRL_RST_MASK) {
1097 status = IXGBE_ERR_RESET_FAILED;
1098 DEBUGOUT("Reset polling failed to complete.\n");
1104 * Double resets are required for recovery from certain error
1105 * conditions. Between resets, it is necessary to stall to
1106 * allow time for any pending HW events to complete.
1108 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1109 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1114 * Store the original AUTOC/AUTOC2 values if they have not been
1115 * stored off yet. Otherwise restore the stored original
1116 * values since the reset operation sets back to defaults.
1118 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1119 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1121 /* Enable link if disabled in NVM */
1122 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
1123 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
1124 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1125 IXGBE_WRITE_FLUSH(hw);
1128 if (hw->mac.orig_link_settings_stored == false) {
1129 hw->mac.orig_autoc = autoc;
1130 hw->mac.orig_autoc2 = autoc2;
1131 hw->mac.orig_link_settings_stored = true;
1134 /* If MNG FW is running on a multi-speed device that
1135 * doesn't autoneg with out driver support we need to
1136 * leave LMS in the state it was before we MAC reset.
1137 * Likewise if we support WoL we don't want change the
1140 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) ||
1142 hw->mac.orig_autoc =
1143 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
1146 if (autoc != hw->mac.orig_autoc) {
1147 status = hw->mac.ops.prot_autoc_write(hw,
1150 if (status != IXGBE_SUCCESS)
1154 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1155 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1156 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1157 autoc2 |= (hw->mac.orig_autoc2 &
1158 IXGBE_AUTOC2_UPPER_MASK);
1159 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1163 /* Store the permanent mac address */
1164 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1167 * Store MAC address from RAR0, clear receive address registers, and
1168 * clear the multicast table. Also reset num_rar_entries to 128,
1169 * since we modify this value when programming the SAN MAC address.
1171 hw->mac.num_rar_entries = 128;
1172 hw->mac.ops.init_rx_addrs(hw);
1174 /* Store the permanent SAN mac address */
1175 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1177 /* Add the SAN MAC address to the RAR only if it's a valid address */
1178 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1179 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1180 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1182 /* Save the SAN MAC RAR index */
1183 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1185 /* Reserve the last RAR for the SAN MAC address */
1186 hw->mac.num_rar_entries--;
1189 /* Store the alternative WWNN/WWPN prefix */
1190 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1191 &hw->mac.wwpn_prefix);
1198 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
1199 * @hw: pointer to hardware structure
1200 * @fdircmd: current value of FDIRCMD register
1202 STATIC s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd)
1206 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1207 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1208 if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1209 return IXGBE_SUCCESS;
1213 return IXGBE_ERR_FDIR_CMD_INCOMPLETE;
1217 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1218 * @hw: pointer to hardware structure
1220 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1224 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1226 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1228 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599");
1231 * Before starting reinitialization process,
1232 * FDIRCMD.CMD must be zero.
1234 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1236 DEBUGOUT("Flow Director previous command did not complete, aborting table re-initialization.\n");
1240 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1241 IXGBE_WRITE_FLUSH(hw);
1243 * 82599 adapters flow director init flow cannot be restarted,
1244 * Workaround 82599 silicon errata by performing the following steps
1245 * before re-writing the FDIRCTRL control register with the same value.
1246 * - write 1 to bit 8 of FDIRCMD register &
1247 * - write 0 to bit 8 of FDIRCMD register
1249 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1250 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1251 IXGBE_FDIRCMD_CLEARHT));
1252 IXGBE_WRITE_FLUSH(hw);
1253 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1254 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1255 ~IXGBE_FDIRCMD_CLEARHT));
1256 IXGBE_WRITE_FLUSH(hw);
1258 * Clear FDIR Hash register to clear any leftover hashes
1259 * waiting to be programmed.
1261 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1262 IXGBE_WRITE_FLUSH(hw);
1264 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1265 IXGBE_WRITE_FLUSH(hw);
1267 /* Poll init-done after we write FDIRCTRL register */
1268 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1269 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1270 IXGBE_FDIRCTRL_INIT_DONE)
1274 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1275 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
1276 return IXGBE_ERR_FDIR_REINIT_FAILED;
1279 /* Clear FDIR statistics registers (read to clear) */
1280 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1281 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1282 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1283 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1284 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1286 return IXGBE_SUCCESS;
1290 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1291 * @hw: pointer to hardware structure
1292 * @fdirctrl: value to write to flow director control register
1294 STATIC void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1298 DEBUGFUNC("ixgbe_fdir_enable_82599");
1300 /* Prime the keys for hashing */
1301 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1302 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1305 * Poll init-done after we write the register. Estimated times:
1306 * 10G: PBALLOC = 11b, timing is 60us
1307 * 1G: PBALLOC = 11b, timing is 600us
1308 * 100M: PBALLOC = 11b, timing is 6ms
1310 * Multiple these timings by 4 if under full Rx load
1312 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1313 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1314 * this might not finish in our poll time, but we can live with that
1317 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1318 IXGBE_WRITE_FLUSH(hw);
1319 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1320 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1321 IXGBE_FDIRCTRL_INIT_DONE)
1326 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1327 DEBUGOUT("Flow Director poll time exceeded!\n");
1331 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1332 * @hw: pointer to hardware structure
1333 * @fdirctrl: value to write to flow director control register, initially
1334 * contains just the value of the Rx packet buffer allocation
1336 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1338 DEBUGFUNC("ixgbe_init_fdir_signature_82599");
1341 * Continue setup of fdirctrl register bits:
1342 * Move the flexible bytes to use the ethertype - shift 6 words
1343 * Set the maximum length per hash bucket to 0xA filters
1344 * Send interrupt when 64 filters are left
1346 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1347 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1348 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1350 /* write hashes and fdirctrl register, poll for completion */
1351 ixgbe_fdir_enable_82599(hw, fdirctrl);
1353 return IXGBE_SUCCESS;
1357 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1358 * @hw: pointer to hardware structure
1359 * @fdirctrl: value to write to flow director control register, initially
1360 * contains just the value of the Rx packet buffer allocation
1361 * @cloud_mode: true - cloud mode, false - other mode
1363 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
1366 DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
1369 * Continue setup of fdirctrl register bits:
1370 * Turn perfect match filtering on
1371 * Report hash in RSS field of Rx wb descriptor
1372 * Initialize the drop queue to queue 127
1373 * Move the flexible bytes to use the ethertype - shift 6 words
1374 * Set the maximum length per hash bucket to 0xA filters
1375 * Send interrupt when 64 (0x4 * 16) filters are left
1377 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1378 IXGBE_FDIRCTRL_REPORT_STATUS |
1379 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1380 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1381 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1382 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1383 if ((hw->mac.type == ixgbe_mac_X550) ||
1384 (hw->mac.type == ixgbe_mac_X550EM_x))
1385 fdirctrl |= IXGBE_FDIRCTRL_DROP_NO_MATCH;
1388 fdirctrl |=(IXGBE_FDIRCTRL_FILTERMODE_CLOUD <<
1389 IXGBE_FDIRCTRL_FILTERMODE_SHIFT);
1391 /* write hashes and fdirctrl register, poll for completion */
1392 ixgbe_fdir_enable_82599(hw, fdirctrl);
1394 return IXGBE_SUCCESS;
1398 * ixgbe_set_fdir_drop_queue_82599 - Set Flow Director drop queue
1399 * @hw: pointer to hardware structure
1400 * @dropqueue: Rx queue index used for the dropped packets
1402 void ixgbe_set_fdir_drop_queue_82599(struct ixgbe_hw *hw, u8 dropqueue)
1406 DEBUGFUNC("ixgbe_set_fdir_drop_queue_82599");
1407 /* Clear init done bit and drop queue field */
1408 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1409 fdirctrl &= ~(IXGBE_FDIRCTRL_DROP_Q_MASK | IXGBE_FDIRCTRL_INIT_DONE);
1411 /* Set drop queue */
1412 fdirctrl |= (dropqueue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
1413 if ((hw->mac.type == ixgbe_mac_X550) ||
1414 (hw->mac.type == ixgbe_mac_X550EM_x) ||
1415 (hw->mac.type == ixgbe_mac_X550EM_a))
1416 fdirctrl |= IXGBE_FDIRCTRL_DROP_NO_MATCH;
1418 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1419 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1420 IXGBE_FDIRCMD_CLEARHT));
1421 IXGBE_WRITE_FLUSH(hw);
1422 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1423 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1424 ~IXGBE_FDIRCMD_CLEARHT));
1425 IXGBE_WRITE_FLUSH(hw);
1427 /* write hashes and fdirctrl register, poll for completion */
1428 ixgbe_fdir_enable_82599(hw, fdirctrl);
1432 * These defines allow us to quickly generate all of the necessary instructions
1433 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1434 * for values 0 through 15
1436 #define IXGBE_ATR_COMMON_HASH_KEY \
1437 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1438 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1441 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1442 common_hash ^= lo_hash_dword >> n; \
1443 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1444 bucket_hash ^= lo_hash_dword >> n; \
1445 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1446 sig_hash ^= lo_hash_dword << (16 - n); \
1447 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1448 common_hash ^= hi_hash_dword >> n; \
1449 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1450 bucket_hash ^= hi_hash_dword >> n; \
1451 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1452 sig_hash ^= hi_hash_dword << (16 - n); \
1456 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1457 * @stream: input bitstream to compute the hash on
1459 * This function is almost identical to the function above but contains
1460 * several optimizations such as unwinding all of the loops, letting the
1461 * compiler work out all of the conditional ifs since the keys are static
1462 * defines, and computing two keys at once since the hashed dword stream
1463 * will be the same for both keys.
1465 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1466 union ixgbe_atr_hash_dword common)
1468 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1469 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1471 /* record the flow_vm_vlan bits as they are a key part to the hash */
1472 flow_vm_vlan = IXGBE_NTOHL(input.dword);
1474 /* generate common hash dword */
1475 hi_hash_dword = IXGBE_NTOHL(common.dword);
1477 /* low dword is word swapped version of common */
1478 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1480 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1481 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1483 /* Process bits 0 and 16 */
1484 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1487 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1488 * delay this because bit 0 of the stream should not be processed
1489 * so we do not add the VLAN until after bit 0 was processed
1491 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1493 /* Process remaining 30 bit of the key */
1494 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1495 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1496 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1497 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1498 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1499 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1500 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1501 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1502 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1503 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1504 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1505 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1506 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1507 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1508 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1510 /* combine common_hash result with signature and bucket hashes */
1511 bucket_hash ^= common_hash;
1512 bucket_hash &= IXGBE_ATR_HASH_MASK;
1514 sig_hash ^= common_hash << 16;
1515 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1517 /* return completed signature hash */
1518 return sig_hash ^ bucket_hash;
1522 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1523 * @hw: pointer to hardware structure
1524 * @input: unique input dword
1525 * @common: compressed common input dword
1526 * @queue: queue index to direct traffic to
1528 * Note that the tunnel bit in input must not be set when the hardware
1529 * tunneling support does not exist.
1531 void ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1532 union ixgbe_atr_hash_dword input,
1533 union ixgbe_atr_hash_dword common,
1541 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
1544 * Get the flow_type in order to program FDIRCMD properly
1545 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1546 * fifth is FDIRCMD.TUNNEL_FILTER
1548 tunnel = !!(input.formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK);
1549 flow_type = input.formatted.flow_type &
1550 (IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1);
1551 switch (flow_type) {
1552 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1553 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1554 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1555 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1556 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1557 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1560 DEBUGOUT(" Error on flow type input\n");
1564 /* configure FDIRCMD register */
1565 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1566 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1567 fdircmd |= (u32)flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1568 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1570 fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER;
1573 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1574 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1576 fdirhashcmd = (u64)fdircmd << 32;
1577 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1578 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1580 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1585 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1588 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1589 bucket_hash ^= lo_hash_dword >> n; \
1590 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1591 bucket_hash ^= hi_hash_dword >> n; \
1595 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1596 * @atr_input: input bitstream to compute the hash on
1597 * @input_mask: mask for the input bitstream
1599 * This function serves two main purposes. First it applies the input_mask
1600 * to the atr_input resulting in a cleaned up atr_input data stream.
1601 * Secondly it computes the hash and stores it in the bkt_hash field at
1602 * the end of the input byte stream. This way it will be available for
1603 * future use without needing to recompute the hash.
1605 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1606 union ixgbe_atr_input *input_mask)
1609 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1610 u32 bucket_hash = 0;
1614 /* Apply masks to input data */
1615 for (i = 0; i < 14; i++)
1616 input->dword_stream[i] &= input_mask->dword_stream[i];
1618 /* record the flow_vm_vlan bits as they are a key part to the hash */
1619 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
1621 /* generate common hash dword */
1622 for (i = 1; i <= 13; i++)
1623 hi_dword ^= input->dword_stream[i];
1624 hi_hash_dword = IXGBE_NTOHL(hi_dword);
1626 /* low dword is word swapped version of common */
1627 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1629 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1630 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1632 /* Process bits 0 and 16 */
1633 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1636 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1637 * delay this because bit 0 of the stream should not be processed
1638 * so we do not add the VLAN until after bit 0 was processed
1640 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1642 /* Process remaining 30 bit of the key */
1643 for (i = 1; i <= 15; i++)
1644 IXGBE_COMPUTE_BKT_HASH_ITERATION(i);
1647 * Limit hash to 13 bits since max bucket count is 8K.
1648 * Store result at the end of the input stream.
1650 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1654 * ixgbe_get_fdirtcpm_82599 - generate a TCP port from atr_input_masks
1655 * @input_mask: mask to be bit swapped
1657 * The source and destination port masks for flow director are bit swapped
1658 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1659 * generate a correctly swapped value we need to bit swap the mask and that
1660 * is what is accomplished by this function.
1662 STATIC u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1664 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
1665 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1666 mask |= IXGBE_NTOHS(input_mask->formatted.src_port);
1667 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1668 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1669 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1670 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1674 * These two macros are meant to address the fact that we have registers
1675 * that are either all or in part big-endian. As a result on big-endian
1676 * systems we will end up byte swapping the value to little-endian before
1677 * it is byte swapped again and written to the hardware in the original
1678 * big-endian format.
1680 #define IXGBE_STORE_AS_BE32(_value) \
1681 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1682 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1684 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1685 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
1687 #define IXGBE_STORE_AS_BE16(_value) \
1688 IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1690 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1691 union ixgbe_atr_input *input_mask, bool cloud_mode)
1693 /* mask IPv6 since it is currently not supported */
1694 u32 fdirm = IXGBE_FDIRM_DIPv6;
1697 DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
1700 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1701 * are zero, then assume a full mask for that field. Also assume that
1702 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1703 * cannot be masked out in this implementation.
1705 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1709 /* verify bucket hash is cleared on hash generation */
1710 if (input_mask->formatted.bkt_hash)
1711 DEBUGOUT(" bucket hash should always be 0 in mask\n");
1713 /* Program FDIRM and verify partial masks */
1714 switch (input_mask->formatted.vm_pool & 0x7F) {
1716 fdirm |= IXGBE_FDIRM_POOL;
1720 DEBUGOUT(" Error on vm pool mask\n");
1721 return IXGBE_ERR_CONFIG;
1724 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1726 fdirm |= IXGBE_FDIRM_L4P;
1727 if (input_mask->formatted.dst_port ||
1728 input_mask->formatted.src_port) {
1729 DEBUGOUT(" Error on src/dst port mask\n");
1730 return IXGBE_ERR_CONFIG;
1732 case IXGBE_ATR_L4TYPE_MASK:
1735 DEBUGOUT(" Error on flow type mask\n");
1736 return IXGBE_ERR_CONFIG;
1739 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
1741 /* mask VLAN ID, fall through to mask VLAN priority */
1742 fdirm |= IXGBE_FDIRM_VLANID;
1744 /* mask VLAN priority */
1745 fdirm |= IXGBE_FDIRM_VLANP;
1748 /* mask VLAN ID only, fall through */
1749 fdirm |= IXGBE_FDIRM_VLANID;
1751 /* no VLAN fields masked */
1754 DEBUGOUT(" Error on VLAN mask\n");
1755 return IXGBE_ERR_CONFIG;
1758 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1760 /* Mask Flex Bytes, fall through */
1761 fdirm |= IXGBE_FDIRM_FLEX;
1765 DEBUGOUT(" Error on flexible byte mask\n");
1766 return IXGBE_ERR_CONFIG;
1770 fdirm |= IXGBE_FDIRM_L3P;
1771 fdirip6m = ((u32) 0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT);
1772 fdirip6m |= IXGBE_FDIRIP6M_ALWAYS_MASK;
1774 switch (input_mask->formatted.inner_mac[0] & 0xFF) {
1776 /* Mask inner MAC, fall through */
1777 fdirip6m |= IXGBE_FDIRIP6M_INNER_MAC;
1781 DEBUGOUT(" Error on inner_mac byte mask\n");
1782 return IXGBE_ERR_CONFIG;
1785 switch (input_mask->formatted.tni_vni & 0xFFFFFFFF) {
1788 fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI;
1791 fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI_24;
1796 DEBUGOUT(" Error on TNI/VNI byte mask\n");
1797 return IXGBE_ERR_CONFIG;
1800 switch (input_mask->formatted.tunnel_type & 0xFFFF) {
1802 /* Mask turnnel type, fall through */
1803 fdirip6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE;
1807 DEBUGOUT(" Error on tunnel type byte mask\n");
1808 return IXGBE_ERR_CONFIG;
1810 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m);
1812 /* Set all bits in FDIRTCPM, FDIRUDPM, FDIRSIP4M and
1813 * FDIRDIP4M in cloud mode to allow L3/L3 packets to
1816 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF);
1817 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF);
1818 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF);
1819 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF);
1822 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1823 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1826 /* store the TCP/UDP port masks, bit reversed from port
1828 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1830 /* write both the same so that UDP and TCP use the same mask */
1831 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1832 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1833 /* also use it for SCTP */
1834 switch (hw->mac.type) {
1835 case ixgbe_mac_X550:
1836 case ixgbe_mac_X550EM_x:
1837 case ixgbe_mac_X550EM_a:
1838 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);
1844 /* store source and destination IP masks (big-enian) */
1845 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1846 ~input_mask->formatted.src_ip[0]);
1847 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1848 ~input_mask->formatted.dst_ip[0]);
1850 return IXGBE_SUCCESS;
1853 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1854 union ixgbe_atr_input *input,
1855 u16 soft_id, u8 queue, bool cloud_mode)
1857 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1858 u32 addr_low, addr_high;
1862 DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
1864 /* currently IPv6 is not supported, must be programmed with 0 */
1865 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1866 input->formatted.src_ip[0]);
1867 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1868 input->formatted.src_ip[1]);
1869 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1870 input->formatted.src_ip[2]);
1872 /* record the source address (big-endian) */
1873 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA,
1874 input->formatted.src_ip[0]);
1876 /* record the first 32 bits of the destination address
1878 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA,
1879 input->formatted.dst_ip[0]);
1881 /* record source and destination port (little-endian)*/
1882 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
1883 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1884 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
1885 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1888 /* record VLAN (little-endian) and flex_bytes(big-endian) */
1889 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1890 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1891 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1892 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1895 if (input->formatted.tunnel_type != 0)
1896 cloud_type = 0x80000000;
1898 addr_low = ((u32)input->formatted.inner_mac[0] |
1899 ((u32)input->formatted.inner_mac[1] << 8) |
1900 ((u32)input->formatted.inner_mac[2] << 16) |
1901 ((u32)input->formatted.inner_mac[3] << 24));
1902 addr_high = ((u32)input->formatted.inner_mac[4] |
1903 ((u32)input->formatted.inner_mac[5] << 8));
1904 cloud_type |= addr_high;
1905 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), addr_low);
1906 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), cloud_type);
1907 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), input->formatted.tni_vni);
1910 /* configure FDIRHASH register */
1911 fdirhash = input->formatted.bkt_hash;
1912 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1913 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1916 * flush all previous writes to make certain registers are
1917 * programmed prior to issuing the command
1919 IXGBE_WRITE_FLUSH(hw);
1921 /* configure FDIRCMD register */
1922 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1923 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1924 if (queue == IXGBE_FDIR_DROP_QUEUE)
1925 fdircmd |= IXGBE_FDIRCMD_DROP;
1926 if (input->formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK)
1927 fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER;
1928 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1929 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1930 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1932 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1933 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1935 DEBUGOUT("Flow Director command did not complete!\n");
1939 return IXGBE_SUCCESS;
1942 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1943 union ixgbe_atr_input *input,
1950 /* configure FDIRHASH register */
1951 fdirhash = input->formatted.bkt_hash;
1952 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1953 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1955 /* flush hash to HW */
1956 IXGBE_WRITE_FLUSH(hw);
1958 /* Query if filter is present */
1959 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1961 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1963 DEBUGOUT("Flow Director command did not complete!\n");
1967 /* if filter exists in hardware then remove it */
1968 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1969 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1970 IXGBE_WRITE_FLUSH(hw);
1971 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1972 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1975 return IXGBE_SUCCESS;
1979 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1980 * @hw: pointer to hardware structure
1981 * @input: input bitstream
1982 * @input_mask: mask for the input bitstream
1983 * @soft_id: software index for the filters
1984 * @queue: queue index to direct traffic to
1986 * Note that the caller to this function must lock before calling, since the
1987 * hardware writes must be protected from one another.
1989 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1990 union ixgbe_atr_input *input,
1991 union ixgbe_atr_input *input_mask,
1992 u16 soft_id, u8 queue, bool cloud_mode)
1994 s32 err = IXGBE_ERR_CONFIG;
1996 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
1999 * Check flow_type formatting, and bail out before we touch the hardware
2000 * if there's a configuration issue
2002 switch (input->formatted.flow_type) {
2003 case IXGBE_ATR_FLOW_TYPE_IPV4:
2004 case IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4:
2005 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
2006 if (input->formatted.dst_port || input->formatted.src_port) {
2007 DEBUGOUT(" Error on src/dst port\n");
2008 return IXGBE_ERR_CONFIG;
2011 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2012 case IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4:
2013 if (input->formatted.dst_port || input->formatted.src_port) {
2014 DEBUGOUT(" Error on src/dst port\n");
2015 return IXGBE_ERR_CONFIG;
2017 case IXGBE_ATR_FLOW_TYPE_TCPV4:
2018 case IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4:
2019 case IXGBE_ATR_FLOW_TYPE_UDPV4:
2020 case IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4:
2021 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2022 IXGBE_ATR_L4TYPE_MASK;
2025 DEBUGOUT(" Error on flow type input\n");
2029 /* program input mask into the HW */
2030 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask, cloud_mode);
2034 /* apply mask and compute/store hash */
2035 ixgbe_atr_compute_perfect_hash_82599(input, input_mask);
2037 /* program filters to filter memory */
2038 return ixgbe_fdir_write_perfect_filter_82599(hw, input,
2039 soft_id, queue, cloud_mode);
2043 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
2044 * @hw: pointer to hardware structure
2045 * @reg: analog register to read
2048 * Performs read operation to Omer analog register specified.
2050 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
2054 DEBUGFUNC("ixgbe_read_analog_reg8_82599");
2056 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2058 IXGBE_WRITE_FLUSH(hw);
2060 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2061 *val = (u8)core_ctl;
2063 return IXGBE_SUCCESS;
2067 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2068 * @hw: pointer to hardware structure
2069 * @reg: atlas register to write
2070 * @val: value to write
2072 * Performs write operation to Omer analog register specified.
2074 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
2078 DEBUGFUNC("ixgbe_write_analog_reg8_82599");
2080 core_ctl = (reg << 8) | val;
2081 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2082 IXGBE_WRITE_FLUSH(hw);
2085 return IXGBE_SUCCESS;
2089 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2090 * @hw: pointer to hardware structure
2092 * Starts the hardware using the generic start_hw function
2093 * and the generation start_hw function.
2094 * Then performs revision-specific operations, if any.
2096 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
2098 s32 ret_val = IXGBE_SUCCESS;
2100 DEBUGFUNC("ixgbe_start_hw_82599");
2102 ret_val = ixgbe_start_hw_generic(hw);
2103 if (ret_val != IXGBE_SUCCESS)
2106 ret_val = ixgbe_start_hw_gen2(hw);
2107 if (ret_val != IXGBE_SUCCESS)
2110 /* We need to run link autotry after the driver loads */
2111 hw->mac.autotry_restart = true;
2113 if (ret_val == IXGBE_SUCCESS)
2114 ret_val = ixgbe_verify_fw_version_82599(hw);
2120 * ixgbe_identify_phy_82599 - Get physical layer module
2121 * @hw: pointer to hardware structure
2123 * Determines the physical layer module found on the current adapter.
2124 * If PHY already detected, maintains current PHY type in hw struct,
2125 * otherwise executes the PHY detection routine.
2127 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
2131 DEBUGFUNC("ixgbe_identify_phy_82599");
2133 /* Detect PHY if not unknown - returns success if already detected. */
2134 status = ixgbe_identify_phy_generic(hw);
2135 if (status != IXGBE_SUCCESS) {
2136 /* 82599 10GBASE-T requires an external PHY */
2137 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
2140 status = ixgbe_identify_module_generic(hw);
2143 /* Set PHY type none if no PHY detected */
2144 if (hw->phy.type == ixgbe_phy_unknown) {
2145 hw->phy.type = ixgbe_phy_none;
2146 return IXGBE_SUCCESS;
2149 /* Return error if SFP module has been detected but is not supported */
2150 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
2151 return IXGBE_ERR_SFP_NOT_SUPPORTED;
2157 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2158 * @hw: pointer to hardware structure
2160 * Determines physical layer capabilities of the current configuration.
2162 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2164 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2165 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2166 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2167 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2168 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2169 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2170 u16 ext_ability = 0;
2172 DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
2174 hw->phy.ops.identify(hw);
2176 switch (hw->phy.type) {
2178 case ixgbe_phy_cu_unknown:
2179 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2180 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
2181 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2182 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2183 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2184 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2185 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
2186 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2192 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2193 case IXGBE_AUTOC_LMS_1G_AN:
2194 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2195 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2196 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2197 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2200 /* SFI mode so read SFP module */
2203 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2204 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2205 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2206 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2207 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2208 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2209 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2212 case IXGBE_AUTOC_LMS_10G_SERIAL:
2213 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2214 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2216 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2219 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2220 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2221 if (autoc & IXGBE_AUTOC_KX_SUPP)
2222 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2223 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2224 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2225 if (autoc & IXGBE_AUTOC_KR_SUPP)
2226 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2235 /* SFP check must be done last since DA modules are sometimes used to
2236 * test KR mode - we need to id KR mode correctly before SFP module.
2237 * Call identify_sfp because the pluggable module may have changed */
2238 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2240 return physical_layer;
2244 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2245 * @hw: pointer to hardware structure
2246 * @regval: register value to write to RXCTRL
2248 * Enables the Rx DMA unit for 82599
2250 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2253 DEBUGFUNC("ixgbe_enable_rx_dma_82599");
2256 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2257 * If traffic is incoming before we enable the Rx unit, it could hang
2258 * the Rx DMA unit. Therefore, make sure the security engine is
2259 * completely disabled prior to enabling the Rx unit.
2262 hw->mac.ops.disable_sec_rx_path(hw);
2264 if (regval & IXGBE_RXCTRL_RXEN)
2265 ixgbe_enable_rx(hw);
2267 ixgbe_disable_rx(hw);
2269 hw->mac.ops.enable_sec_rx_path(hw);
2271 return IXGBE_SUCCESS;
2275 * ixgbe_verify_fw_version_82599 - verify FW version for 82599
2276 * @hw: pointer to hardware structure
2278 * Verifies that installed the firmware version is 0.6 or higher
2279 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2281 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2282 * if the FW version is not supported.
2284 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2286 s32 status = IXGBE_ERR_EEPROM_VERSION;
2287 u16 fw_offset, fw_ptp_cfg_offset;
2290 DEBUGFUNC("ixgbe_verify_fw_version_82599");
2292 /* firmware check is only necessary for SFI devices */
2293 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2294 status = IXGBE_SUCCESS;
2295 goto fw_version_out;
2298 /* get the offset to the Firmware Module block */
2299 if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) {
2300 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2301 "eeprom read at offset %d failed", IXGBE_FW_PTR);
2302 return IXGBE_ERR_EEPROM_VERSION;
2305 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2306 goto fw_version_out;
2308 /* get the offset to the Pass Through Patch Configuration block */
2309 if (hw->eeprom.ops.read(hw, (fw_offset +
2310 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2311 &fw_ptp_cfg_offset)) {
2312 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2313 "eeprom read at offset %d failed",
2315 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR);
2316 return IXGBE_ERR_EEPROM_VERSION;
2319 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2320 goto fw_version_out;
2322 /* get the firmware version */
2323 if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2324 IXGBE_FW_PATCH_VERSION_4), &fw_version)) {
2325 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2326 "eeprom read at offset %d failed",
2327 fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4);
2328 return IXGBE_ERR_EEPROM_VERSION;
2331 if (fw_version > 0x5)
2332 status = IXGBE_SUCCESS;
2339 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2340 * @hw: pointer to hardware structure
2342 * Returns true if the LESM FW module is present and enabled. Otherwise
2343 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2345 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2347 bool lesm_enabled = false;
2348 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2351 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599");
2353 /* get the offset to the Firmware Module block */
2354 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2356 if ((status != IXGBE_SUCCESS) ||
2357 (fw_offset == 0) || (fw_offset == 0xFFFF))
2360 /* get the offset to the LESM Parameters block */
2361 status = hw->eeprom.ops.read(hw, (fw_offset +
2362 IXGBE_FW_LESM_PARAMETERS_PTR),
2363 &fw_lesm_param_offset);
2365 if ((status != IXGBE_SUCCESS) ||
2366 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2369 /* get the LESM state word */
2370 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2371 IXGBE_FW_LESM_STATE_1),
2374 if ((status == IXGBE_SUCCESS) &&
2375 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2376 lesm_enabled = true;
2379 return lesm_enabled;
2383 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2384 * fastest available method
2386 * @hw: pointer to hardware structure
2387 * @offset: offset of word in EEPROM to read
2388 * @words: number of words
2389 * @data: word(s) read from the EEPROM
2391 * Retrieves 16 bit word(s) read from EEPROM
2393 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2394 u16 words, u16 *data)
2396 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2397 s32 ret_val = IXGBE_ERR_CONFIG;
2399 DEBUGFUNC("ixgbe_read_eeprom_buffer_82599");
2402 * If EEPROM is detected and can be addressed using 14 bits,
2403 * use EERD otherwise use bit bang
2405 if ((eeprom->type == ixgbe_eeprom_spi) &&
2406 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2407 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2410 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2418 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2419 * fastest available method
2421 * @hw: pointer to hardware structure
2422 * @offset: offset of word in the EEPROM to read
2423 * @data: word read from the EEPROM
2425 * Reads a 16 bit word from the EEPROM
2427 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2428 u16 offset, u16 *data)
2430 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2431 s32 ret_val = IXGBE_ERR_CONFIG;
2433 DEBUGFUNC("ixgbe_read_eeprom_82599");
2436 * If EEPROM is detected and can be addressed using 14 bits,
2437 * use EERD otherwise use bit bang
2439 if ((eeprom->type == ixgbe_eeprom_spi) &&
2440 (offset <= IXGBE_EERD_MAX_ADDR))
2441 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2443 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2449 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2451 * @hw: pointer to hardware structure
2453 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2454 * full pipeline reset. This function assumes the SW/FW lock is held.
2456 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2460 u32 i, autoc_reg, autoc2_reg;
2462 /* Enable link if disabled in NVM */
2463 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2464 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
2465 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
2466 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
2467 IXGBE_WRITE_FLUSH(hw);
2470 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2471 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2472 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2473 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
2474 autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT));
2475 /* Wait for AN to leave state 0 */
2476 for (i = 0; i < 10; i++) {
2478 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2479 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2483 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2484 DEBUGOUT("auto negotiation not completed\n");
2485 ret_val = IXGBE_ERR_RESET_FAILED;
2486 goto reset_pipeline_out;
2489 ret_val = IXGBE_SUCCESS;
2492 /* Write AUTOC register with original LMS field and Restart_AN */
2493 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2494 IXGBE_WRITE_FLUSH(hw);
2500 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
2501 * @hw: pointer to hardware structure
2502 * @byte_offset: byte offset to read
2505 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2506 * a specified device address.
2508 STATIC s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2509 u8 dev_addr, u8 *data)
2515 DEBUGFUNC("ixgbe_read_i2c_byte_82599");
2517 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2518 /* Acquire I2C bus ownership. */
2519 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2520 esdp |= IXGBE_ESDP_SDP0;
2521 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2522 IXGBE_WRITE_FLUSH(hw);
2525 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2526 if (esdp & IXGBE_ESDP_SDP1)
2534 DEBUGOUT("Driver can't access resource,"
2535 " acquiring I2C bus timeout.\n");
2536 status = IXGBE_ERR_I2C;
2537 goto release_i2c_access;
2541 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2545 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2546 /* Release I2C bus ownership. */
2547 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2548 esdp &= ~IXGBE_ESDP_SDP0;
2549 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2550 IXGBE_WRITE_FLUSH(hw);
2557 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
2558 * @hw: pointer to hardware structure
2559 * @byte_offset: byte offset to write
2560 * @data: value to write
2562 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2563 * a specified device address.
2565 STATIC s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2566 u8 dev_addr, u8 data)
2572 DEBUGFUNC("ixgbe_write_i2c_byte_82599");
2574 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2575 /* Acquire I2C bus ownership. */
2576 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2577 esdp |= IXGBE_ESDP_SDP0;
2578 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2579 IXGBE_WRITE_FLUSH(hw);
2582 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2583 if (esdp & IXGBE_ESDP_SDP1)
2591 DEBUGOUT("Driver can't access resource,"
2592 " acquiring I2C bus timeout.\n");
2593 status = IXGBE_ERR_I2C;
2594 goto release_i2c_access;
2598 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2602 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2603 /* Release I2C bus ownership. */
2604 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2605 esdp &= ~IXGBE_ESDP_SDP0;
2606 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2607 IXGBE_WRITE_FLUSH(hw);