1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_type.h"
35 #include "ixgbe_82599.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
40 #define IXGBE_82599_MAX_TX_QUEUES 128
41 #define IXGBE_82599_MAX_RX_QUEUES 128
42 #define IXGBE_82599_RAR_ENTRIES 128
43 #define IXGBE_82599_MC_TBL_SIZE 128
44 #define IXGBE_82599_VFT_TBL_SIZE 128
45 #define IXGBE_82599_RX_PB_SIZE 512
47 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
48 ixgbe_link_speed speed,
49 bool autoneg_wait_to_complete);
50 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
51 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
52 u16 offset, u16 *data);
53 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
54 u16 words, u16 *data);
55 STATIC s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
56 u8 dev_addr, u8 *data);
57 STATIC s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
58 u8 dev_addr, u8 data);
60 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
62 struct ixgbe_mac_info *mac = &hw->mac;
64 DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
67 * enable the laser control functions for SFP+ fiber
70 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
71 !ixgbe_mng_enabled(hw)) {
72 mac->ops.disable_tx_laser =
73 ixgbe_disable_tx_laser_multispeed_fiber;
74 mac->ops.enable_tx_laser =
75 ixgbe_enable_tx_laser_multispeed_fiber;
76 mac->ops.flap_tx_laser = ixgbe_flap_tx_laser_multispeed_fiber;
79 mac->ops.disable_tx_laser = NULL;
80 mac->ops.enable_tx_laser = NULL;
81 mac->ops.flap_tx_laser = NULL;
84 if (hw->phy.multispeed_fiber) {
85 /* Set up dual speed SFP+ support */
86 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
88 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
89 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
90 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
91 !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
92 mac->ops.setup_link = ixgbe_setup_mac_link_smartspeed;
94 mac->ops.setup_link = ixgbe_setup_mac_link_82599;
100 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
101 * @hw: pointer to hardware structure
103 * Initialize any function pointers that were not able to be
104 * set during init_shared_code because the PHY/SFP type was
105 * not known. Perform the SFP init if necessary.
108 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
110 struct ixgbe_mac_info *mac = &hw->mac;
111 struct ixgbe_phy_info *phy = &hw->phy;
112 s32 ret_val = IXGBE_SUCCESS;
115 DEBUGFUNC("ixgbe_init_phy_ops_82599");
117 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) {
118 /* Store flag indicating I2C bus access control unit. */
119 hw->phy.qsfp_shared_i2c_bus = TRUE;
121 /* Initialize access to QSFP+ I2C bus */
122 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
123 esdp |= IXGBE_ESDP_SDP0_DIR;
124 esdp &= ~IXGBE_ESDP_SDP1_DIR;
125 esdp &= ~IXGBE_ESDP_SDP0;
126 esdp &= ~IXGBE_ESDP_SDP0_NATIVE;
127 esdp &= ~IXGBE_ESDP_SDP1_NATIVE;
128 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
129 IXGBE_WRITE_FLUSH(hw);
131 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_82599;
132 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_82599;
134 /* Identify the PHY or SFP module */
135 ret_val = phy->ops.identify(hw);
136 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
137 goto init_phy_ops_out;
139 /* Setup function pointers based on detected SFP module and speeds */
140 ixgbe_init_mac_link_ops_82599(hw);
141 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
142 hw->phy.ops.reset = NULL;
144 /* If copper media, overwrite with copper function pointers */
145 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
146 mac->ops.setup_link = ixgbe_setup_copper_link_82599;
147 mac->ops.get_link_capabilities =
148 ixgbe_get_copper_link_capabilities_generic;
151 /* Set necessary function pointers based on PHY type */
152 switch (hw->phy.type) {
154 phy->ops.setup_link = ixgbe_setup_phy_link_tnx;
155 phy->ops.check_link = ixgbe_check_phy_link_tnx;
156 phy->ops.get_firmware_version =
157 ixgbe_get_phy_firmware_version_tnx;
166 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
168 s32 ret_val = IXGBE_SUCCESS;
169 u16 list_offset, data_offset, data_value;
171 DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
173 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
174 ixgbe_init_mac_link_ops_82599(hw);
176 hw->phy.ops.reset = NULL;
178 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
180 if (ret_val != IXGBE_SUCCESS)
183 /* PHY config will finish before releasing the semaphore */
184 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
185 IXGBE_GSSR_MAC_CSR_SM);
186 if (ret_val != IXGBE_SUCCESS) {
187 ret_val = IXGBE_ERR_SWFW_SYNC;
191 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
193 while (data_value != 0xffff) {
194 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
195 IXGBE_WRITE_FLUSH(hw);
196 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
200 /* Release the semaphore */
201 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
202 /* Delay obtaining semaphore again to allow FW access
203 * prot_autoc_write uses the semaphore too.
205 msec_delay(hw->eeprom.semaphore_delay);
207 /* Restart DSP and set SFI mode */
208 ret_val = hw->mac.ops.prot_autoc_write(hw,
209 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL,
213 DEBUGOUT("sfp module setup not complete\n");
214 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
224 /* Release the semaphore */
225 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
226 /* Delay obtaining semaphore again to allow FW access */
227 msec_delay(hw->eeprom.semaphore_delay);
228 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
229 "eeprom read at offset %d failed", data_offset);
230 return IXGBE_ERR_PHY;
234 * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read
235 * @hw: pointer to hardware structure
236 * @locked: Return the if we locked for this read.
237 * @reg_val: Value we read from AUTOC
239 * For this part (82599) we need to wrap read-modify-writes with a possible
240 * FW/SW lock. It is assumed this lock will be freed with the next
241 * prot_autoc_write_82599().
243 s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
248 /* If LESM is on then we need to hold the SW/FW semaphore. */
249 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
250 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
251 IXGBE_GSSR_MAC_CSR_SM);
252 if (ret_val != IXGBE_SUCCESS)
253 return IXGBE_ERR_SWFW_SYNC;
258 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
259 return IXGBE_SUCCESS;
263 * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write
264 * @hw: pointer to hardware structure
265 * @reg_val: value to write to AUTOC
266 * @locked: bool to indicate whether the SW/FW lock was already taken by
267 * previous proc_autoc_read_82599.
269 * This part (82599) may need to hold the SW/FW lock around all writes to
270 * AUTOC. Likewise after a write we need to do a pipeline reset.
272 s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)
274 s32 ret_val = IXGBE_SUCCESS;
276 /* Blocked by MNG FW so bail */
277 if (ixgbe_check_reset_blocked(hw))
280 /* We only need to get the lock if:
281 * - We didn't do it already (in the read part of a read-modify-write)
284 if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) {
285 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
286 IXGBE_GSSR_MAC_CSR_SM);
287 if (ret_val != IXGBE_SUCCESS)
288 return IXGBE_ERR_SWFW_SYNC;
293 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
294 ret_val = ixgbe_reset_pipeline_82599(hw);
297 /* Free the SW/FW semaphore as we either grabbed it here or
298 * already had it when this function was called.
301 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
307 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
308 * @hw: pointer to hardware structure
310 * Initialize the function pointers and assign the MAC type for 82599.
311 * Does not touch the hardware.
314 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
316 struct ixgbe_mac_info *mac = &hw->mac;
317 struct ixgbe_phy_info *phy = &hw->phy;
318 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
321 DEBUGFUNC("ixgbe_init_ops_82599");
323 ixgbe_init_phy_ops_generic(hw);
324 ret_val = ixgbe_init_ops_generic(hw);
327 phy->ops.identify = ixgbe_identify_phy_82599;
328 phy->ops.init = ixgbe_init_phy_ops_82599;
331 mac->ops.reset_hw = ixgbe_reset_hw_82599;
332 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2;
333 mac->ops.get_media_type = ixgbe_get_media_type_82599;
334 mac->ops.get_supported_physical_layer =
335 ixgbe_get_supported_physical_layer_82599;
336 mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic;
337 mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic;
338 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82599;
339 mac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82599;
340 mac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82599;
341 mac->ops.start_hw = ixgbe_start_hw_82599;
342 mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic;
343 mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic;
344 mac->ops.get_device_caps = ixgbe_get_device_caps_generic;
345 mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic;
346 mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic;
347 mac->ops.prot_autoc_read = prot_autoc_read_82599;
348 mac->ops.prot_autoc_write = prot_autoc_write_82599;
350 /* RAR, Multicast, VLAN */
351 mac->ops.set_vmdq = ixgbe_set_vmdq_generic;
352 mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic;
353 mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic;
354 mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic;
355 mac->rar_highwater = 1;
356 mac->ops.set_vfta = ixgbe_set_vfta_generic;
357 mac->ops.set_vlvf = ixgbe_set_vlvf_generic;
358 mac->ops.clear_vfta = ixgbe_clear_vfta_generic;
359 mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic;
360 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_82599;
361 mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing;
362 mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing;
365 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82599;
366 mac->ops.check_link = ixgbe_check_mac_link_generic;
367 mac->ops.setup_rxpba = ixgbe_set_rxpba_generic;
368 ixgbe_init_mac_link_ops_82599(hw);
370 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
371 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
372 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
373 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE;
374 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
375 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
376 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
378 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
379 IXGBE_FWSM_MODE_MASK) ? true : false;
381 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
384 eeprom->ops.read = ixgbe_read_eeprom_82599;
385 eeprom->ops.read_buffer = ixgbe_read_eeprom_buffer_82599;
387 /* Manageability interface */
388 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic;
390 mac->ops.get_thermal_sensor_data =
391 ixgbe_get_thermal_sensor_data_generic;
392 mac->ops.init_thermal_sensor_thresh =
393 ixgbe_init_thermal_sensor_thresh_generic;
395 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
401 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
402 * @hw: pointer to hardware structure
403 * @speed: pointer to link speed
404 * @autoneg: true when autoneg or autotry is enabled
406 * Determines the link capabilities by reading the AUTOC register.
408 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
409 ixgbe_link_speed *speed,
412 s32 status = IXGBE_SUCCESS;
415 DEBUGFUNC("ixgbe_get_link_capabilities_82599");
418 /* Check if 1G SFP module. */
419 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
420 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
421 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
422 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
423 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
424 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
425 *speed = IXGBE_LINK_SPEED_1GB_FULL;
431 * Determine link capabilities based on the stored value of AUTOC,
432 * which represents EEPROM defaults. If AUTOC value has not
433 * been stored, use the current register values.
435 if (hw->mac.orig_link_settings_stored)
436 autoc = hw->mac.orig_autoc;
438 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
440 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
441 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
442 *speed = IXGBE_LINK_SPEED_1GB_FULL;
446 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
447 *speed = IXGBE_LINK_SPEED_10GB_FULL;
451 case IXGBE_AUTOC_LMS_1G_AN:
452 *speed = IXGBE_LINK_SPEED_1GB_FULL;
456 case IXGBE_AUTOC_LMS_10G_SERIAL:
457 *speed = IXGBE_LINK_SPEED_10GB_FULL;
461 case IXGBE_AUTOC_LMS_KX4_KX_KR:
462 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
463 *speed = IXGBE_LINK_SPEED_UNKNOWN;
464 if (autoc & IXGBE_AUTOC_KR_SUPP)
465 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
466 if (autoc & IXGBE_AUTOC_KX4_SUPP)
467 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
468 if (autoc & IXGBE_AUTOC_KX_SUPP)
469 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
473 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
474 *speed = IXGBE_LINK_SPEED_100_FULL;
475 if (autoc & IXGBE_AUTOC_KR_SUPP)
476 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
477 if (autoc & IXGBE_AUTOC_KX4_SUPP)
478 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
479 if (autoc & IXGBE_AUTOC_KX_SUPP)
480 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
484 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
485 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
490 status = IXGBE_ERR_LINK_SETUP;
495 if (hw->phy.multispeed_fiber) {
496 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
497 IXGBE_LINK_SPEED_1GB_FULL;
499 /* QSFP must not enable full auto-negotiation
500 * Limited autoneg is enabled at 1G
502 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp)
513 * ixgbe_get_media_type_82599 - Get media type
514 * @hw: pointer to hardware structure
516 * Returns the media type (fiber, copper, backplane)
518 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
520 enum ixgbe_media_type media_type;
522 DEBUGFUNC("ixgbe_get_media_type_82599");
524 /* Detect if there is a copper PHY attached. */
525 switch (hw->phy.type) {
526 case ixgbe_phy_cu_unknown:
528 media_type = ixgbe_media_type_copper;
534 switch (hw->device_id) {
535 case IXGBE_DEV_ID_82599_KX4:
536 case IXGBE_DEV_ID_82599_KX4_MEZZ:
537 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
538 case IXGBE_DEV_ID_82599_KR:
539 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
540 case IXGBE_DEV_ID_82599_XAUI_LOM:
541 /* Default device ID is mezzanine card KX/KX4 */
542 media_type = ixgbe_media_type_backplane;
544 case IXGBE_DEV_ID_82599_SFP:
545 case IXGBE_DEV_ID_82599_SFP_FCOE:
546 case IXGBE_DEV_ID_82599_SFP_EM:
547 case IXGBE_DEV_ID_82599_SFP_SF2:
548 case IXGBE_DEV_ID_82599_SFP_SF_QP:
549 case IXGBE_DEV_ID_82599EN_SFP:
550 media_type = ixgbe_media_type_fiber;
552 case IXGBE_DEV_ID_82599_CX4:
553 media_type = ixgbe_media_type_cx4;
555 case IXGBE_DEV_ID_82599_T3_LOM:
556 media_type = ixgbe_media_type_copper;
558 case IXGBE_DEV_ID_82599_LS:
559 media_type = ixgbe_media_type_fiber_lco;
561 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
562 media_type = ixgbe_media_type_fiber_qsfp;
565 media_type = ixgbe_media_type_unknown;
573 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
574 * @hw: pointer to hardware structure
576 * Disables link during D3 power down sequence.
579 void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
584 DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599");
585 ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);
587 if (!ixgbe_mng_present(hw) && !hw->wol_enabled &&
588 ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) {
589 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
590 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;
591 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
596 * ixgbe_start_mac_link_82599 - Setup MAC link settings
597 * @hw: pointer to hardware structure
598 * @autoneg_wait_to_complete: true when waiting for completion is needed
600 * Configures link settings based on values in the ixgbe_hw struct.
601 * Restarts the link. Performs autonegotiation if needed.
603 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
604 bool autoneg_wait_to_complete)
609 s32 status = IXGBE_SUCCESS;
610 bool got_lock = false;
612 DEBUGFUNC("ixgbe_start_mac_link_82599");
615 /* reset_pipeline requires us to hold this lock as it writes to
618 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
619 status = hw->mac.ops.acquire_swfw_sync(hw,
620 IXGBE_GSSR_MAC_CSR_SM);
621 if (status != IXGBE_SUCCESS)
628 ixgbe_reset_pipeline_82599(hw);
631 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
633 /* Only poll for autoneg to complete if specified to do so */
634 if (autoneg_wait_to_complete) {
635 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
636 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
637 IXGBE_AUTOC_LMS_KX4_KX_KR ||
638 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
639 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
640 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
641 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
642 links_reg = 0; /* Just in case Autoneg time = 0 */
643 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
644 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
645 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
649 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
650 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
651 DEBUGOUT("Autoneg did not complete.\n");
656 /* Add delay to filter out noises during initial link setup */
664 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
665 * @hw: pointer to hardware structure
667 * The base drivers may require better control over SFP+ module
668 * PHY states. This includes selectively shutting down the Tx
669 * laser on the PHY, effectively halting physical link.
671 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
673 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
675 /* Blocked by MNG FW so bail */
676 if (ixgbe_check_reset_blocked(hw))
679 /* Disable Tx laser; allow 100us to go dark per spec */
680 esdp_reg |= IXGBE_ESDP_SDP3;
681 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
682 IXGBE_WRITE_FLUSH(hw);
687 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
688 * @hw: pointer to hardware structure
690 * The base drivers may require better control over SFP+ module
691 * PHY states. This includes selectively turning on the Tx
692 * laser on the PHY, effectively starting physical link.
694 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
696 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
698 /* Enable Tx laser; allow 100ms to light up */
699 esdp_reg &= ~IXGBE_ESDP_SDP3;
700 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
701 IXGBE_WRITE_FLUSH(hw);
706 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
707 * @hw: pointer to hardware structure
709 * When the driver changes the link speeds that it can support,
710 * it sets autotry_restart to true to indicate that we need to
711 * initiate a new autotry session with the link partner. To do
712 * so, we set the speed then disable and re-enable the Tx laser, to
713 * alert the link partner that it also needs to restart autotry on its
714 * end. This is consistent with true clause 37 autoneg, which also
715 * involves a loss of signal.
717 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
719 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
721 /* Blocked by MNG FW so bail */
722 if (ixgbe_check_reset_blocked(hw))
725 if (hw->mac.autotry_restart) {
726 ixgbe_disable_tx_laser_multispeed_fiber(hw);
727 ixgbe_enable_tx_laser_multispeed_fiber(hw);
728 hw->mac.autotry_restart = false;
734 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
735 * @hw: pointer to hardware structure
736 * @speed: new link speed
737 * @autoneg_wait_to_complete: true when waiting for completion is needed
739 * Set the link speed in the AUTOC register and restarts link.
741 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
742 ixgbe_link_speed speed,
743 bool autoneg_wait_to_complete)
745 s32 status = IXGBE_SUCCESS;
746 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
747 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
749 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
751 bool autoneg, link_up = false;
753 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
755 /* Mask off requested but non-supported speeds */
756 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
757 if (status != IXGBE_SUCCESS)
763 * Try each speed one by one, highest priority first. We do this in
764 * software because 10gb fiber doesn't support speed autonegotiation.
766 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
768 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
770 /* If we already have link at this speed, just jump out */
771 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
772 if (status != IXGBE_SUCCESS)
775 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
778 /* Set the module link speed */
779 switch (hw->phy.media_type) {
780 case ixgbe_media_type_fiber:
781 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
782 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
783 IXGBE_WRITE_FLUSH(hw);
785 case ixgbe_media_type_fiber_qsfp:
786 /* QSFP module automatically detects MAC link speed */
789 DEBUGOUT("Unexpected media type.\n");
793 /* Allow module to change analog characteristics (1G->10G) */
796 status = ixgbe_setup_mac_link_82599(hw,
797 IXGBE_LINK_SPEED_10GB_FULL,
798 autoneg_wait_to_complete);
799 if (status != IXGBE_SUCCESS)
802 /* Flap the tx laser if it has not already been done */
803 ixgbe_flap_tx_laser(hw);
806 * Wait for the controller to acquire link. Per IEEE 802.3ap,
807 * Section 73.10.2, we may have to wait up to 500ms if KR is
808 * attempted. 82599 uses the same timing for 10g SFI.
810 for (i = 0; i < 5; i++) {
811 /* Wait for the link partner to also set speed */
814 /* If we have link, just jump out */
815 status = ixgbe_check_link(hw, &link_speed,
817 if (status != IXGBE_SUCCESS)
825 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
827 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
828 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
830 /* If we already have link at this speed, just jump out */
831 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
832 if (status != IXGBE_SUCCESS)
835 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
838 /* Set the module link speed */
839 switch (hw->phy.media_type) {
840 case ixgbe_media_type_fiber:
841 esdp_reg &= ~IXGBE_ESDP_SDP5;
842 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
843 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
844 IXGBE_WRITE_FLUSH(hw);
846 case ixgbe_media_type_fiber_qsfp:
847 /* QSFP module automatically detects link speed */
850 DEBUGOUT("Unexpected media type.\n");
854 /* Allow module to change analog characteristics (10G->1G) */
857 status = ixgbe_setup_mac_link_82599(hw,
858 IXGBE_LINK_SPEED_1GB_FULL,
859 autoneg_wait_to_complete);
860 if (status != IXGBE_SUCCESS)
863 /* Flap the Tx laser if it has not already been done */
864 ixgbe_flap_tx_laser(hw);
866 /* Wait for the link partner to also set speed */
869 /* If we have link, just jump out */
870 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
871 if (status != IXGBE_SUCCESS)
879 * We didn't get link. Configure back to the highest speed we tried,
880 * (if there was more than one). We call ourselves back with just the
881 * single highest speed that the user requested.
884 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
885 highest_link_speed, autoneg_wait_to_complete);
888 /* Set autoneg_advertised value based on input link speed */
889 hw->phy.autoneg_advertised = 0;
891 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
892 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
894 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
895 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
901 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
902 * @hw: pointer to hardware structure
903 * @speed: new link speed
904 * @autoneg_wait_to_complete: true when waiting for completion is needed
906 * Implements the Intel SmartSpeed algorithm.
908 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
909 ixgbe_link_speed speed,
910 bool autoneg_wait_to_complete)
912 s32 status = IXGBE_SUCCESS;
913 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
915 bool link_up = false;
916 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
918 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
920 /* Set autoneg_advertised value based on input link speed */
921 hw->phy.autoneg_advertised = 0;
923 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
924 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
926 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
927 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
929 if (speed & IXGBE_LINK_SPEED_100_FULL)
930 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
933 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
934 * autoneg advertisement if link is unable to be established at the
935 * highest negotiated rate. This can sometimes happen due to integrity
936 * issues with the physical media connection.
939 /* First, try to get link with full advertisement */
940 hw->phy.smart_speed_active = false;
941 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
942 status = ixgbe_setup_mac_link_82599(hw, speed,
943 autoneg_wait_to_complete);
944 if (status != IXGBE_SUCCESS)
948 * Wait for the controller to acquire link. Per IEEE 802.3ap,
949 * Section 73.10.2, we may have to wait up to 500ms if KR is
950 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
951 * Table 9 in the AN MAS.
953 for (i = 0; i < 5; i++) {
956 /* If we have link, just jump out */
957 status = ixgbe_check_link(hw, &link_speed, &link_up,
959 if (status != IXGBE_SUCCESS)
968 * We didn't get link. If we advertised KR plus one of KX4/KX
969 * (or BX4/BX), then disable KR and try again.
971 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
972 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
975 /* Turn SmartSpeed on to disable KR support */
976 hw->phy.smart_speed_active = true;
977 status = ixgbe_setup_mac_link_82599(hw, speed,
978 autoneg_wait_to_complete);
979 if (status != IXGBE_SUCCESS)
983 * Wait for the controller to acquire link. 600ms will allow for
984 * the AN link_fail_inhibit_timer as well for multiple cycles of
985 * parallel detect, both 10g and 1g. This allows for the maximum
986 * connect attempts as defined in the AN MAS table 73-7.
988 for (i = 0; i < 6; i++) {
991 /* If we have link, just jump out */
992 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
993 if (status != IXGBE_SUCCESS)
1000 /* We didn't get link. Turn SmartSpeed back off. */
1001 hw->phy.smart_speed_active = false;
1002 status = ixgbe_setup_mac_link_82599(hw, speed,
1003 autoneg_wait_to_complete);
1006 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
1007 DEBUGOUT("Smartspeed has downgraded the link speed "
1008 "from the maximum advertised\n");
1013 * ixgbe_setup_mac_link_82599 - Set MAC link speed
1014 * @hw: pointer to hardware structure
1015 * @speed: new link speed
1016 * @autoneg_wait_to_complete: true when waiting for completion is needed
1018 * Set the link speed in the AUTOC register and restarts link.
1020 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
1021 ixgbe_link_speed speed,
1022 bool autoneg_wait_to_complete)
1024 bool autoneg = false;
1025 s32 status = IXGBE_SUCCESS;
1026 u32 pma_pmd_1g, link_mode;
1027 u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); /* holds the value of AUTOC register at this current point in time */
1028 u32 orig_autoc = 0; /* holds the cached value of AUTOC register */
1029 u32 autoc = current_autoc; /* Temporary variable used for comparison purposes */
1030 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1031 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1034 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
1036 DEBUGFUNC("ixgbe_setup_mac_link_82599");
1038 /* Check to see if speed passed in is supported. */
1039 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
1043 speed &= link_capabilities;
1045 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
1046 status = IXGBE_ERR_LINK_SETUP;
1050 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
1051 if (hw->mac.orig_link_settings_stored)
1052 orig_autoc = hw->mac.orig_autoc;
1056 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
1057 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1059 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
1060 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
1061 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
1062 /* Set KX4/KX/KR support according to speed requested */
1063 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
1064 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1065 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
1066 autoc |= IXGBE_AUTOC_KX4_SUPP;
1067 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
1068 (hw->phy.smart_speed_active == false))
1069 autoc |= IXGBE_AUTOC_KR_SUPP;
1071 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1072 autoc |= IXGBE_AUTOC_KX_SUPP;
1073 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
1074 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
1075 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
1076 /* Switch from 1G SFI to 10G SFI if requested */
1077 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
1078 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
1079 autoc &= ~IXGBE_AUTOC_LMS_MASK;
1080 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
1082 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
1083 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
1084 /* Switch from 10G SFI to 1G SFI if requested */
1085 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
1086 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
1087 autoc &= ~IXGBE_AUTOC_LMS_MASK;
1088 if (autoneg || hw->phy.type == ixgbe_phy_qsfp_intel)
1089 autoc |= IXGBE_AUTOC_LMS_1G_AN;
1091 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
1095 if (autoc != current_autoc) {
1097 status = hw->mac.ops.prot_autoc_write(hw, autoc, false);
1098 if (status != IXGBE_SUCCESS)
1101 /* Only poll for autoneg to complete if specified to do so */
1102 if (autoneg_wait_to_complete) {
1103 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
1104 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
1105 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
1106 links_reg = 0; /*Just in case Autoneg time=0*/
1107 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
1109 IXGBE_READ_REG(hw, IXGBE_LINKS);
1110 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
1114 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
1116 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
1117 DEBUGOUT("Autoneg did not complete.\n");
1122 /* Add delay to filter out noises during initial link setup */
1131 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
1132 * @hw: pointer to hardware structure
1133 * @speed: new link speed
1134 * @autoneg_wait_to_complete: true if waiting is needed to complete
1136 * Restarts link on PHY and MAC based on settings passed in.
1138 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
1139 ixgbe_link_speed speed,
1140 bool autoneg_wait_to_complete)
1144 DEBUGFUNC("ixgbe_setup_copper_link_82599");
1146 /* Setup the PHY according to input speed */
1147 status = hw->phy.ops.setup_link_speed(hw, speed,
1148 autoneg_wait_to_complete);
1150 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
1156 * ixgbe_reset_hw_82599 - Perform hardware reset
1157 * @hw: pointer to hardware structure
1159 * Resets the hardware by resetting the transmit and receive units, masks
1160 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1163 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
1165 ixgbe_link_speed link_speed;
1168 u32 i, autoc, autoc2;
1170 bool link_up = false;
1172 DEBUGFUNC("ixgbe_reset_hw_82599");
1174 /* Call adapter stop to disable tx/rx and clear interrupts */
1175 status = hw->mac.ops.stop_adapter(hw);
1176 if (status != IXGBE_SUCCESS)
1179 /* flush pending Tx transactions */
1180 ixgbe_clear_tx_pending(hw);
1182 /* PHY ops must be identified and initialized prior to reset */
1184 /* Identify PHY and related function pointers */
1185 status = hw->phy.ops.init(hw);
1187 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1190 /* Setup SFP module if there is one present. */
1191 if (hw->phy.sfp_setup_needed) {
1192 status = hw->mac.ops.setup_sfp(hw);
1193 hw->phy.sfp_setup_needed = false;
1196 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1200 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
1201 hw->phy.ops.reset(hw);
1203 /* remember AUTOC from before we reset */
1204 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK;
1208 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1209 * If link reset is used when link is up, it might reset the PHY when
1210 * mng is using it. If link is down or the flag to force full link
1211 * reset is set, then perform link reset.
1213 ctrl = IXGBE_CTRL_LNK_RST;
1214 if (!hw->force_full_reset) {
1215 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1217 ctrl = IXGBE_CTRL_RST;
1220 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1221 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1222 IXGBE_WRITE_FLUSH(hw);
1224 /* Poll for reset bit to self-clear meaning reset is complete */
1225 for (i = 0; i < 10; i++) {
1227 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1228 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1232 if (ctrl & IXGBE_CTRL_RST_MASK) {
1233 status = IXGBE_ERR_RESET_FAILED;
1234 DEBUGOUT("Reset polling failed to complete.\n");
1240 * Double resets are required for recovery from certain error
1241 * conditions. Between resets, it is necessary to stall to
1242 * allow time for any pending HW events to complete.
1244 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1245 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1250 * Store the original AUTOC/AUTOC2 values if they have not been
1251 * stored off yet. Otherwise restore the stored original
1252 * values since the reset operation sets back to defaults.
1254 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1255 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1257 /* Enable link if disabled in NVM */
1258 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
1259 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
1260 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1261 IXGBE_WRITE_FLUSH(hw);
1264 if (hw->mac.orig_link_settings_stored == false) {
1265 hw->mac.orig_autoc = autoc;
1266 hw->mac.orig_autoc2 = autoc2;
1267 hw->mac.orig_link_settings_stored = true;
1270 /* If MNG FW is running on a multi-speed device that
1271 * doesn't autoneg with out driver support we need to
1272 * leave LMS in the state it was before we MAC reset.
1273 * Likewise if we support WoL we don't want change the
1276 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) ||
1278 hw->mac.orig_autoc =
1279 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
1282 if (autoc != hw->mac.orig_autoc) {
1283 status = hw->mac.ops.prot_autoc_write(hw,
1286 if (status != IXGBE_SUCCESS)
1290 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1291 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1292 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1293 autoc2 |= (hw->mac.orig_autoc2 &
1294 IXGBE_AUTOC2_UPPER_MASK);
1295 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1299 /* Store the permanent mac address */
1300 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1303 * Store MAC address from RAR0, clear receive address registers, and
1304 * clear the multicast table. Also reset num_rar_entries to 128,
1305 * since we modify this value when programming the SAN MAC address.
1307 hw->mac.num_rar_entries = 128;
1308 hw->mac.ops.init_rx_addrs(hw);
1310 /* Store the permanent SAN mac address */
1311 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1313 /* Add the SAN MAC address to the RAR only if it's a valid address */
1314 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1315 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1316 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1318 /* Save the SAN MAC RAR index */
1319 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1321 /* Reserve the last RAR for the SAN MAC address */
1322 hw->mac.num_rar_entries--;
1325 /* Store the alternative WWNN/WWPN prefix */
1326 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1327 &hw->mac.wwpn_prefix);
1334 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
1335 * @hw: pointer to hardware structure
1336 * @fdircmd: current value of FDIRCMD register
1338 STATIC s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd)
1342 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1343 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1344 if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1345 return IXGBE_SUCCESS;
1349 return IXGBE_ERR_FDIR_CMD_INCOMPLETE;
1353 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1354 * @hw: pointer to hardware structure
1356 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1360 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1362 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1364 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599");
1367 * Before starting reinitialization process,
1368 * FDIRCMD.CMD must be zero.
1370 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1372 DEBUGOUT("Flow Director previous command did not complete, aborting table re-initialization.\n");
1376 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1377 IXGBE_WRITE_FLUSH(hw);
1379 * 82599 adapters flow director init flow cannot be restarted,
1380 * Workaround 82599 silicon errata by performing the following steps
1381 * before re-writing the FDIRCTRL control register with the same value.
1382 * - write 1 to bit 8 of FDIRCMD register &
1383 * - write 0 to bit 8 of FDIRCMD register
1385 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1386 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1387 IXGBE_FDIRCMD_CLEARHT));
1388 IXGBE_WRITE_FLUSH(hw);
1389 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1390 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1391 ~IXGBE_FDIRCMD_CLEARHT));
1392 IXGBE_WRITE_FLUSH(hw);
1394 * Clear FDIR Hash register to clear any leftover hashes
1395 * waiting to be programmed.
1397 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1398 IXGBE_WRITE_FLUSH(hw);
1400 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1401 IXGBE_WRITE_FLUSH(hw);
1403 /* Poll init-done after we write FDIRCTRL register */
1404 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1405 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1406 IXGBE_FDIRCTRL_INIT_DONE)
1410 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1411 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
1412 return IXGBE_ERR_FDIR_REINIT_FAILED;
1415 /* Clear FDIR statistics registers (read to clear) */
1416 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1417 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1418 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1419 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1420 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1422 return IXGBE_SUCCESS;
1426 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1427 * @hw: pointer to hardware structure
1428 * @fdirctrl: value to write to flow director control register
1430 STATIC void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1434 DEBUGFUNC("ixgbe_fdir_enable_82599");
1436 /* Prime the keys for hashing */
1437 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1438 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1441 * Poll init-done after we write the register. Estimated times:
1442 * 10G: PBALLOC = 11b, timing is 60us
1443 * 1G: PBALLOC = 11b, timing is 600us
1444 * 100M: PBALLOC = 11b, timing is 6ms
1446 * Multiple these timings by 4 if under full Rx load
1448 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1449 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1450 * this might not finish in our poll time, but we can live with that
1453 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1454 IXGBE_WRITE_FLUSH(hw);
1455 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1456 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1457 IXGBE_FDIRCTRL_INIT_DONE)
1462 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1463 DEBUGOUT("Flow Director poll time exceeded!\n");
1467 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1468 * @hw: pointer to hardware structure
1469 * @fdirctrl: value to write to flow director control register, initially
1470 * contains just the value of the Rx packet buffer allocation
1472 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1474 DEBUGFUNC("ixgbe_init_fdir_signature_82599");
1477 * Continue setup of fdirctrl register bits:
1478 * Move the flexible bytes to use the ethertype - shift 6 words
1479 * Set the maximum length per hash bucket to 0xA filters
1480 * Send interrupt when 64 filters are left
1482 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1483 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1484 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1486 /* write hashes and fdirctrl register, poll for completion */
1487 ixgbe_fdir_enable_82599(hw, fdirctrl);
1489 return IXGBE_SUCCESS;
1493 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1494 * @hw: pointer to hardware structure
1495 * @fdirctrl: value to write to flow director control register, initially
1496 * contains just the value of the Rx packet buffer allocation
1497 * @cloud_mode: true - cloud mode, false - other mode
1499 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
1502 DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
1505 * Continue setup of fdirctrl register bits:
1506 * Turn perfect match filtering on
1507 * Report hash in RSS field of Rx wb descriptor
1508 * Initialize the drop queue
1509 * Move the flexible bytes to use the ethertype - shift 6 words
1510 * Set the maximum length per hash bucket to 0xA filters
1511 * Send interrupt when 64 (0x4 * 16) filters are left
1513 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1514 IXGBE_FDIRCTRL_REPORT_STATUS |
1515 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1516 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1517 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1518 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1521 fdirctrl |=(IXGBE_FDIRCTRL_FILTERMODE_CLOUD <<
1522 IXGBE_FDIRCTRL_FILTERMODE_SHIFT);
1524 /* write hashes and fdirctrl register, poll for completion */
1525 ixgbe_fdir_enable_82599(hw, fdirctrl);
1527 return IXGBE_SUCCESS;
1531 * These defines allow us to quickly generate all of the necessary instructions
1532 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1533 * for values 0 through 15
1535 #define IXGBE_ATR_COMMON_HASH_KEY \
1536 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1537 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1540 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1541 common_hash ^= lo_hash_dword >> n; \
1542 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1543 bucket_hash ^= lo_hash_dword >> n; \
1544 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1545 sig_hash ^= lo_hash_dword << (16 - n); \
1546 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1547 common_hash ^= hi_hash_dword >> n; \
1548 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1549 bucket_hash ^= hi_hash_dword >> n; \
1550 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1551 sig_hash ^= hi_hash_dword << (16 - n); \
1555 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1556 * @stream: input bitstream to compute the hash on
1558 * This function is almost identical to the function above but contains
1559 * several optimizations such as unwinding all of the loops, letting the
1560 * compiler work out all of the conditional ifs since the keys are static
1561 * defines, and computing two keys at once since the hashed dword stream
1562 * will be the same for both keys.
1564 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1565 union ixgbe_atr_hash_dword common)
1567 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1568 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1570 /* record the flow_vm_vlan bits as they are a key part to the hash */
1571 flow_vm_vlan = IXGBE_NTOHL(input.dword);
1573 /* generate common hash dword */
1574 hi_hash_dword = IXGBE_NTOHL(common.dword);
1576 /* low dword is word swapped version of common */
1577 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1579 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1580 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1582 /* Process bits 0 and 16 */
1583 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1586 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1587 * delay this because bit 0 of the stream should not be processed
1588 * so we do not add the VLAN until after bit 0 was processed
1590 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1592 /* Process remaining 30 bit of the key */
1593 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1594 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1595 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1596 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1597 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1598 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1599 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1600 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1601 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1602 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1603 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1604 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1605 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1606 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1607 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1609 /* combine common_hash result with signature and bucket hashes */
1610 bucket_hash ^= common_hash;
1611 bucket_hash &= IXGBE_ATR_HASH_MASK;
1613 sig_hash ^= common_hash << 16;
1614 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1616 /* return completed signature hash */
1617 return sig_hash ^ bucket_hash;
1621 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1622 * @hw: pointer to hardware structure
1623 * @input: unique input dword
1624 * @common: compressed common input dword
1625 * @queue: queue index to direct traffic to
1627 * Note that the tunnel bit in input must not be set when the hardware
1628 * tunneling support does not exist.
1630 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1631 union ixgbe_atr_hash_dword input,
1632 union ixgbe_atr_hash_dword common,
1641 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
1644 * Get the flow_type in order to program FDIRCMD properly
1645 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1646 * fifth is FDIRCMD.TUNNEL_FILTER
1648 tunnel = !!(input.formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK);
1649 flow_type = input.formatted.flow_type &
1650 (IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1);
1651 switch (flow_type) {
1652 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1653 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1654 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1655 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1656 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1657 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1660 DEBUGOUT(" Error on flow type input\n");
1661 return IXGBE_ERR_CONFIG;
1664 /* configure FDIRCMD register */
1665 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1666 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1667 fdircmd |= (u32)flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1668 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1670 fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER;
1673 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1674 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1676 fdirhashcmd = (u64)fdircmd << 32;
1677 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1678 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1680 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1682 DEBUGOUT("Flow Director command did not complete!\n");
1686 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1688 return IXGBE_SUCCESS;
1691 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1694 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1695 bucket_hash ^= lo_hash_dword >> n; \
1696 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1697 bucket_hash ^= hi_hash_dword >> n; \
1701 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1702 * @atr_input: input bitstream to compute the hash on
1703 * @input_mask: mask for the input bitstream
1705 * This function serves two main purposes. First it applies the input_mask
1706 * to the atr_input resulting in a cleaned up atr_input data stream.
1707 * Secondly it computes the hash and stores it in the bkt_hash field at
1708 * the end of the input byte stream. This way it will be available for
1709 * future use without needing to recompute the hash.
1711 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1712 union ixgbe_atr_input *input_mask)
1715 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1716 u32 bucket_hash = 0;
1720 /* Apply masks to input data */
1721 for (i = 0; i < 14; i++)
1722 input->dword_stream[i] &= input_mask->dword_stream[i];
1724 /* record the flow_vm_vlan bits as they are a key part to the hash */
1725 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
1727 /* generate common hash dword */
1728 for (i = 1; i <= 13; i++)
1729 hi_dword ^= input->dword_stream[i];
1730 hi_hash_dword = IXGBE_NTOHL(hi_dword);
1732 /* low dword is word swapped version of common */
1733 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1735 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1736 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1738 /* Process bits 0 and 16 */
1739 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1742 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1743 * delay this because bit 0 of the stream should not be processed
1744 * so we do not add the VLAN until after bit 0 was processed
1746 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1748 /* Process remaining 30 bit of the key */
1749 for (i = 1; i <= 15; i++)
1750 IXGBE_COMPUTE_BKT_HASH_ITERATION(i);
1753 * Limit hash to 13 bits since max bucket count is 8K.
1754 * Store result at the end of the input stream.
1756 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1760 * ixgbe_get_fdirtcpm_82599 - generate a TCP port from atr_input_masks
1761 * @input_mask: mask to be bit swapped
1763 * The source and destination port masks for flow director are bit swapped
1764 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1765 * generate a correctly swapped value we need to bit swap the mask and that
1766 * is what is accomplished by this function.
1768 STATIC u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1770 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
1771 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1772 mask |= IXGBE_NTOHS(input_mask->formatted.src_port);
1773 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1774 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1775 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1776 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1780 * These two macros are meant to address the fact that we have registers
1781 * that are either all or in part big-endian. As a result on big-endian
1782 * systems we will end up byte swapping the value to little-endian before
1783 * it is byte swapped again and written to the hardware in the original
1784 * big-endian format.
1786 #define IXGBE_STORE_AS_BE32(_value) \
1787 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1788 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1790 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1791 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
1793 #define IXGBE_STORE_AS_BE16(_value) \
1794 IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1796 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1797 union ixgbe_atr_input *input_mask, bool cloud_mode)
1799 /* mask IPv6 since it is currently not supported */
1800 u32 fdirm = IXGBE_FDIRM_DIPv6;
1803 DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
1806 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1807 * are zero, then assume a full mask for that field. Also assume that
1808 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1809 * cannot be masked out in this implementation.
1811 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1815 /* verify bucket hash is cleared on hash generation */
1816 if (input_mask->formatted.bkt_hash)
1817 DEBUGOUT(" bucket hash should always be 0 in mask\n");
1819 /* Program FDIRM and verify partial masks */
1820 switch (input_mask->formatted.vm_pool & 0x7F) {
1822 fdirm |= IXGBE_FDIRM_POOL;
1826 DEBUGOUT(" Error on vm pool mask\n");
1827 return IXGBE_ERR_CONFIG;
1830 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1832 fdirm |= IXGBE_FDIRM_L4P;
1833 if (input_mask->formatted.dst_port ||
1834 input_mask->formatted.src_port) {
1835 DEBUGOUT(" Error on src/dst port mask\n");
1836 return IXGBE_ERR_CONFIG;
1838 case IXGBE_ATR_L4TYPE_MASK:
1841 DEBUGOUT(" Error on flow type mask\n");
1842 return IXGBE_ERR_CONFIG;
1845 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
1847 /* mask VLAN ID, fall through to mask VLAN priority */
1848 fdirm |= IXGBE_FDIRM_VLANID;
1850 /* mask VLAN priority */
1851 fdirm |= IXGBE_FDIRM_VLANP;
1854 /* mask VLAN ID only, fall through */
1855 fdirm |= IXGBE_FDIRM_VLANID;
1857 /* no VLAN fields masked */
1860 DEBUGOUT(" Error on VLAN mask\n");
1861 return IXGBE_ERR_CONFIG;
1864 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1866 /* Mask Flex Bytes, fall through */
1867 fdirm |= IXGBE_FDIRM_FLEX;
1871 DEBUGOUT(" Error on flexible byte mask\n");
1872 return IXGBE_ERR_CONFIG;
1876 fdirm |= IXGBE_FDIRM_L3P;
1877 fdirip6m = ((u32) 0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT);
1878 fdirip6m |= IXGBE_FDIRIP6M_ALWAYS_MASK;
1880 switch (input_mask->formatted.inner_mac[0] & 0xFF) {
1882 /* Mask inner MAC, fall through */
1883 fdirip6m |= IXGBE_FDIRIP6M_INNER_MAC;
1887 DEBUGOUT(" Error on inner_mac byte mask\n");
1888 return IXGBE_ERR_CONFIG;
1891 switch (input_mask->formatted.tni_vni & 0xFFFFFFFF) {
1894 fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI;
1897 fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI_24;
1902 DEBUGOUT(" Error on TNI/VNI byte mask\n");
1903 return IXGBE_ERR_CONFIG;
1906 switch (input_mask->formatted.tunnel_type & 0xFFFF) {
1908 /* Mask turnnel type, fall through */
1909 fdirip6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE;
1913 DEBUGOUT(" Error on tunnel type byte mask\n");
1914 return IXGBE_ERR_CONFIG;
1916 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m);
1918 /* Set all bits in FDIRTCPM, FDIRUDPM, FDIRSIP4M and
1919 * FDIRDIP4M in cloud mode to allow L3/L3 packets to
1922 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF);
1923 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF);
1924 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF);
1925 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF);
1928 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1929 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1932 /* store the TCP/UDP port masks, bit reversed from port
1934 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1936 /* write both the same so that UDP and TCP use the same mask */
1937 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1938 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1939 /* also use it for SCTP */
1940 switch (hw->mac.type) {
1941 case ixgbe_mac_X550:
1942 case ixgbe_mac_X550EM_x:
1943 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);
1949 /* store source and destination IP masks (big-enian) */
1950 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1951 ~input_mask->formatted.src_ip[0]);
1952 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1953 ~input_mask->formatted.dst_ip[0]);
1955 return IXGBE_SUCCESS;
1958 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1959 union ixgbe_atr_input *input,
1960 u16 soft_id, u8 queue, bool cloud_mode)
1962 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1963 u32 addr_low, addr_high;
1967 DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
1969 /* currently IPv6 is not supported, must be programmed with 0 */
1970 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1971 input->formatted.src_ip[0]);
1972 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1973 input->formatted.src_ip[1]);
1974 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1975 input->formatted.src_ip[2]);
1977 /* record the source address (big-endian) */
1978 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA,
1979 input->formatted.src_ip[0]);
1981 /* record the first 32 bits of the destination address
1983 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA,
1984 input->formatted.dst_ip[0]);
1986 /* record source and destination port (little-endian)*/
1987 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
1988 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1989 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
1990 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1993 /* record VLAN (little-endian) and flex_bytes(big-endian) */
1994 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1995 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1996 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1997 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
2000 if (input->formatted.tunnel_type != 0)
2001 cloud_type = 0x80000000;
2003 addr_low = ((u32)input->formatted.inner_mac[0] |
2004 ((u32)input->formatted.inner_mac[1] << 8) |
2005 ((u32)input->formatted.inner_mac[2] << 16) |
2006 ((u32)input->formatted.inner_mac[3] << 24));
2007 addr_high = ((u32)input->formatted.inner_mac[4] |
2008 ((u32)input->formatted.inner_mac[5] << 8));
2009 cloud_type |= addr_high;
2010 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), addr_low);
2011 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), cloud_type);
2012 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), input->formatted.tni_vni);
2015 /* configure FDIRHASH register */
2016 fdirhash = input->formatted.bkt_hash;
2017 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
2018 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
2021 * flush all previous writes to make certain registers are
2022 * programmed prior to issuing the command
2024 IXGBE_WRITE_FLUSH(hw);
2026 /* configure FDIRCMD register */
2027 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
2028 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
2029 if (queue == IXGBE_FDIR_DROP_QUEUE)
2030 fdircmd |= IXGBE_FDIRCMD_DROP;
2031 if (input->formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK)
2032 fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER;
2033 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
2034 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
2035 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
2037 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
2038 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
2040 DEBUGOUT("Flow Director command did not complete!\n");
2044 return IXGBE_SUCCESS;
2047 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
2048 union ixgbe_atr_input *input,
2055 /* configure FDIRHASH register */
2056 fdirhash = input->formatted.bkt_hash;
2057 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
2058 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
2060 /* flush hash to HW */
2061 IXGBE_WRITE_FLUSH(hw);
2063 /* Query if filter is present */
2064 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
2066 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
2068 DEBUGOUT("Flow Director command did not complete!\n");
2072 /* if filter exists in hardware then remove it */
2073 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
2074 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
2075 IXGBE_WRITE_FLUSH(hw);
2076 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
2077 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
2080 return IXGBE_SUCCESS;
2084 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
2085 * @hw: pointer to hardware structure
2086 * @input: input bitstream
2087 * @input_mask: mask for the input bitstream
2088 * @soft_id: software index for the filters
2089 * @queue: queue index to direct traffic to
2091 * Note that the caller to this function must lock before calling, since the
2092 * hardware writes must be protected from one another.
2094 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
2095 union ixgbe_atr_input *input,
2096 union ixgbe_atr_input *input_mask,
2097 u16 soft_id, u8 queue, bool cloud_mode)
2099 s32 err = IXGBE_ERR_CONFIG;
2101 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
2104 * Check flow_type formatting, and bail out before we touch the hardware
2105 * if there's a configuration issue
2107 switch (input->formatted.flow_type) {
2108 case IXGBE_ATR_FLOW_TYPE_IPV4:
2109 case IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4:
2110 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
2111 if (input->formatted.dst_port || input->formatted.src_port) {
2112 DEBUGOUT(" Error on src/dst port\n");
2113 return IXGBE_ERR_CONFIG;
2116 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2117 case IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4:
2118 if (input->formatted.dst_port || input->formatted.src_port) {
2119 DEBUGOUT(" Error on src/dst port\n");
2120 return IXGBE_ERR_CONFIG;
2122 case IXGBE_ATR_FLOW_TYPE_TCPV4:
2123 case IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4:
2124 case IXGBE_ATR_FLOW_TYPE_UDPV4:
2125 case IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4:
2126 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2127 IXGBE_ATR_L4TYPE_MASK;
2130 DEBUGOUT(" Error on flow type input\n");
2134 /* program input mask into the HW */
2135 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask, cloud_mode);
2139 /* apply mask and compute/store hash */
2140 ixgbe_atr_compute_perfect_hash_82599(input, input_mask);
2142 /* program filters to filter memory */
2143 return ixgbe_fdir_write_perfect_filter_82599(hw, input,
2144 soft_id, queue, cloud_mode);
2148 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
2149 * @hw: pointer to hardware structure
2150 * @reg: analog register to read
2153 * Performs read operation to Omer analog register specified.
2155 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
2159 DEBUGFUNC("ixgbe_read_analog_reg8_82599");
2161 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2163 IXGBE_WRITE_FLUSH(hw);
2165 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2166 *val = (u8)core_ctl;
2168 return IXGBE_SUCCESS;
2172 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2173 * @hw: pointer to hardware structure
2174 * @reg: atlas register to write
2175 * @val: value to write
2177 * Performs write operation to Omer analog register specified.
2179 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
2183 DEBUGFUNC("ixgbe_write_analog_reg8_82599");
2185 core_ctl = (reg << 8) | val;
2186 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2187 IXGBE_WRITE_FLUSH(hw);
2190 return IXGBE_SUCCESS;
2194 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2195 * @hw: pointer to hardware structure
2197 * Starts the hardware using the generic start_hw function
2198 * and the generation start_hw function.
2199 * Then performs revision-specific operations, if any.
2201 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
2203 s32 ret_val = IXGBE_SUCCESS;
2205 DEBUGFUNC("ixgbe_start_hw_82599");
2207 ret_val = ixgbe_start_hw_generic(hw);
2208 if (ret_val != IXGBE_SUCCESS)
2211 ret_val = ixgbe_start_hw_gen2(hw);
2212 if (ret_val != IXGBE_SUCCESS)
2215 /* We need to run link autotry after the driver loads */
2216 hw->mac.autotry_restart = true;
2218 if (ret_val == IXGBE_SUCCESS)
2219 ret_val = ixgbe_verify_fw_version_82599(hw);
2225 * ixgbe_identify_phy_82599 - Get physical layer module
2226 * @hw: pointer to hardware structure
2228 * Determines the physical layer module found on the current adapter.
2229 * If PHY already detected, maintains current PHY type in hw struct,
2230 * otherwise executes the PHY detection routine.
2232 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
2236 DEBUGFUNC("ixgbe_identify_phy_82599");
2238 /* Detect PHY if not unknown - returns success if already detected. */
2239 status = ixgbe_identify_phy_generic(hw);
2240 if (status != IXGBE_SUCCESS) {
2241 /* 82599 10GBASE-T requires an external PHY */
2242 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
2245 status = ixgbe_identify_module_generic(hw);
2248 /* Set PHY type none if no PHY detected */
2249 if (hw->phy.type == ixgbe_phy_unknown) {
2250 hw->phy.type = ixgbe_phy_none;
2251 return IXGBE_SUCCESS;
2254 /* Return error if SFP module has been detected but is not supported */
2255 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
2256 return IXGBE_ERR_SFP_NOT_SUPPORTED;
2262 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2263 * @hw: pointer to hardware structure
2265 * Determines physical layer capabilities of the current configuration.
2267 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2269 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2270 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2271 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2272 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2273 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2274 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2275 u16 ext_ability = 0;
2277 DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
2279 hw->phy.ops.identify(hw);
2281 switch (hw->phy.type) {
2283 case ixgbe_phy_cu_unknown:
2284 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2285 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
2286 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2287 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2288 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2289 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2290 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
2291 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2297 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2298 case IXGBE_AUTOC_LMS_1G_AN:
2299 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2300 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2301 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2302 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2305 /* SFI mode so read SFP module */
2308 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2309 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2310 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2311 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2312 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2313 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2314 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2317 case IXGBE_AUTOC_LMS_10G_SERIAL:
2318 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2319 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2321 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2324 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2325 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2326 if (autoc & IXGBE_AUTOC_KX_SUPP)
2327 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2328 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2329 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2330 if (autoc & IXGBE_AUTOC_KR_SUPP)
2331 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2340 /* SFP check must be done last since DA modules are sometimes used to
2341 * test KR mode - we need to id KR mode correctly before SFP module.
2342 * Call identify_sfp because the pluggable module may have changed */
2343 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2345 return physical_layer;
2349 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2350 * @hw: pointer to hardware structure
2351 * @regval: register value to write to RXCTRL
2353 * Enables the Rx DMA unit for 82599
2355 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2358 DEBUGFUNC("ixgbe_enable_rx_dma_82599");
2361 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2362 * If traffic is incoming before we enable the Rx unit, it could hang
2363 * the Rx DMA unit. Therefore, make sure the security engine is
2364 * completely disabled prior to enabling the Rx unit.
2367 hw->mac.ops.disable_sec_rx_path(hw);
2369 if (regval & IXGBE_RXCTRL_RXEN)
2370 ixgbe_enable_rx(hw);
2372 ixgbe_disable_rx(hw);
2374 hw->mac.ops.enable_sec_rx_path(hw);
2376 return IXGBE_SUCCESS;
2380 * ixgbe_verify_fw_version_82599 - verify FW version for 82599
2381 * @hw: pointer to hardware structure
2383 * Verifies that installed the firmware version is 0.6 or higher
2384 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2386 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2387 * if the FW version is not supported.
2389 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2391 s32 status = IXGBE_ERR_EEPROM_VERSION;
2392 u16 fw_offset, fw_ptp_cfg_offset;
2395 DEBUGFUNC("ixgbe_verify_fw_version_82599");
2397 /* firmware check is only necessary for SFI devices */
2398 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2399 status = IXGBE_SUCCESS;
2400 goto fw_version_out;
2403 /* get the offset to the Firmware Module block */
2404 if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) {
2405 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2406 "eeprom read at offset %d failed", IXGBE_FW_PTR);
2407 return IXGBE_ERR_EEPROM_VERSION;
2410 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2411 goto fw_version_out;
2413 /* get the offset to the Pass Through Patch Configuration block */
2414 if (hw->eeprom.ops.read(hw, (fw_offset +
2415 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2416 &fw_ptp_cfg_offset)) {
2417 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2418 "eeprom read at offset %d failed",
2420 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR);
2421 return IXGBE_ERR_EEPROM_VERSION;
2424 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2425 goto fw_version_out;
2427 /* get the firmware version */
2428 if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2429 IXGBE_FW_PATCH_VERSION_4), &fw_version)) {
2430 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2431 "eeprom read at offset %d failed",
2432 fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4);
2433 return IXGBE_ERR_EEPROM_VERSION;
2436 if (fw_version > 0x5)
2437 status = IXGBE_SUCCESS;
2444 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2445 * @hw: pointer to hardware structure
2447 * Returns true if the LESM FW module is present and enabled. Otherwise
2448 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2450 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2452 bool lesm_enabled = false;
2453 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2456 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599");
2458 /* get the offset to the Firmware Module block */
2459 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2461 if ((status != IXGBE_SUCCESS) ||
2462 (fw_offset == 0) || (fw_offset == 0xFFFF))
2465 /* get the offset to the LESM Parameters block */
2466 status = hw->eeprom.ops.read(hw, (fw_offset +
2467 IXGBE_FW_LESM_PARAMETERS_PTR),
2468 &fw_lesm_param_offset);
2470 if ((status != IXGBE_SUCCESS) ||
2471 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2474 /* get the LESM state word */
2475 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2476 IXGBE_FW_LESM_STATE_1),
2479 if ((status == IXGBE_SUCCESS) &&
2480 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2481 lesm_enabled = true;
2484 return lesm_enabled;
2488 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2489 * fastest available method
2491 * @hw: pointer to hardware structure
2492 * @offset: offset of word in EEPROM to read
2493 * @words: number of words
2494 * @data: word(s) read from the EEPROM
2496 * Retrieves 16 bit word(s) read from EEPROM
2498 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2499 u16 words, u16 *data)
2501 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2502 s32 ret_val = IXGBE_ERR_CONFIG;
2504 DEBUGFUNC("ixgbe_read_eeprom_buffer_82599");
2507 * If EEPROM is detected and can be addressed using 14 bits,
2508 * use EERD otherwise use bit bang
2510 if ((eeprom->type == ixgbe_eeprom_spi) &&
2511 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2512 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2515 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2523 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2524 * fastest available method
2526 * @hw: pointer to hardware structure
2527 * @offset: offset of word in the EEPROM to read
2528 * @data: word read from the EEPROM
2530 * Reads a 16 bit word from the EEPROM
2532 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2533 u16 offset, u16 *data)
2535 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2536 s32 ret_val = IXGBE_ERR_CONFIG;
2538 DEBUGFUNC("ixgbe_read_eeprom_82599");
2541 * If EEPROM is detected and can be addressed using 14 bits,
2542 * use EERD otherwise use bit bang
2544 if ((eeprom->type == ixgbe_eeprom_spi) &&
2545 (offset <= IXGBE_EERD_MAX_ADDR))
2546 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2548 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2554 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2556 * @hw: pointer to hardware structure
2558 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2559 * full pipeline reset. This function assumes the SW/FW lock is held.
2561 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2565 u32 i, autoc_reg, autoc2_reg;
2567 /* Enable link if disabled in NVM */
2568 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2569 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
2570 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
2571 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
2572 IXGBE_WRITE_FLUSH(hw);
2575 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2576 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2577 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2578 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
2579 autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT));
2580 /* Wait for AN to leave state 0 */
2581 for (i = 0; i < 10; i++) {
2583 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2584 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2588 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2589 DEBUGOUT("auto negotiation not completed\n");
2590 ret_val = IXGBE_ERR_RESET_FAILED;
2591 goto reset_pipeline_out;
2594 ret_val = IXGBE_SUCCESS;
2597 /* Write AUTOC register with original LMS field and Restart_AN */
2598 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2599 IXGBE_WRITE_FLUSH(hw);
2606 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
2607 * @hw: pointer to hardware structure
2608 * @byte_offset: byte offset to read
2611 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2612 * a specified device address.
2614 STATIC s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2615 u8 dev_addr, u8 *data)
2621 DEBUGFUNC("ixgbe_read_i2c_byte_82599");
2623 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2624 /* Acquire I2C bus ownership. */
2625 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2626 esdp |= IXGBE_ESDP_SDP0;
2627 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2628 IXGBE_WRITE_FLUSH(hw);
2631 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2632 if (esdp & IXGBE_ESDP_SDP1)
2640 DEBUGOUT("Driver can't access resource,"
2641 " acquiring I2C bus timeout.\n");
2642 status = IXGBE_ERR_I2C;
2643 goto release_i2c_access;
2647 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2651 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2652 /* Release I2C bus ownership. */
2653 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2654 esdp &= ~IXGBE_ESDP_SDP0;
2655 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2656 IXGBE_WRITE_FLUSH(hw);
2663 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
2664 * @hw: pointer to hardware structure
2665 * @byte_offset: byte offset to write
2666 * @data: value to write
2668 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2669 * a specified device address.
2671 STATIC s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2672 u8 dev_addr, u8 data)
2678 DEBUGFUNC("ixgbe_write_i2c_byte_82599");
2680 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2681 /* Acquire I2C bus ownership. */
2682 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2683 esdp |= IXGBE_ESDP_SDP0;
2684 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2685 IXGBE_WRITE_FLUSH(hw);
2688 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2689 if (esdp & IXGBE_ESDP_SDP1)
2697 DEBUGOUT("Driver can't access resource,"
2698 " acquiring I2C bus timeout.\n");
2699 status = IXGBE_ERR_I2C;
2700 goto release_i2c_access;
2704 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2708 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2709 /* Release I2C bus ownership. */
2710 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2711 esdp &= ~IXGBE_ESDP_SDP0;
2712 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2713 IXGBE_WRITE_FLUSH(hw);