1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
36 #include "ixgbe_dcb.h"
37 #include "ixgbe_dcb_82599.h"
38 #include "ixgbe_api.h"
40 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
41 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
42 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
43 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
44 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
45 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
47 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
48 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
49 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
50 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw);
52 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
53 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
55 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
56 u16 words, u16 *data);
57 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
58 u16 words, u16 *data);
59 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
63 * ixgbe_init_ops_generic - Inits function ptrs
64 * @hw: pointer to the hardware structure
66 * Initialize the function pointers.
68 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
70 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
71 struct ixgbe_mac_info *mac = &hw->mac;
72 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
74 DEBUGFUNC("ixgbe_init_ops_generic");
77 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic;
78 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
79 if (eec & IXGBE_EEC_PRES) {
80 eeprom->ops.read = ixgbe_read_eerd_generic;
81 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic;
83 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic;
84 eeprom->ops.read_buffer =
85 ixgbe_read_eeprom_buffer_bit_bang_generic;
87 eeprom->ops.write = ixgbe_write_eeprom_generic;
88 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic;
89 eeprom->ops.validate_checksum =
90 ixgbe_validate_eeprom_checksum_generic;
91 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic;
92 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic;
95 mac->ops.init_hw = ixgbe_init_hw_generic;
96 mac->ops.reset_hw = NULL;
97 mac->ops.start_hw = ixgbe_start_hw_generic;
98 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic;
99 mac->ops.get_media_type = NULL;
100 mac->ops.get_supported_physical_layer = NULL;
101 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic;
102 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic;
103 mac->ops.stop_adapter = ixgbe_stop_adapter_generic;
104 mac->ops.get_bus_info = ixgbe_get_bus_info_generic;
105 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie;
106 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync;
107 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync;
108 mac->ops.prot_autoc_read = prot_autoc_read_generic;
109 mac->ops.prot_autoc_write = prot_autoc_write_generic;
112 mac->ops.led_on = ixgbe_led_on_generic;
113 mac->ops.led_off = ixgbe_led_off_generic;
114 mac->ops.blink_led_start = ixgbe_blink_led_start_generic;
115 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic;
117 /* RAR, Multicast, VLAN */
118 mac->ops.set_rar = ixgbe_set_rar_generic;
119 mac->ops.clear_rar = ixgbe_clear_rar_generic;
120 mac->ops.insert_mac_addr = NULL;
121 mac->ops.set_vmdq = NULL;
122 mac->ops.clear_vmdq = NULL;
123 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic;
124 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic;
125 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic;
126 mac->ops.enable_mc = ixgbe_enable_mc_generic;
127 mac->ops.disable_mc = ixgbe_disable_mc_generic;
128 mac->ops.clear_vfta = NULL;
129 mac->ops.set_vfta = NULL;
130 mac->ops.set_vlvf = NULL;
131 mac->ops.init_uta_tables = NULL;
132 mac->ops.enable_rx = ixgbe_enable_rx_generic;
133 mac->ops.disable_rx = ixgbe_disable_rx_generic;
136 mac->ops.fc_enable = ixgbe_fc_enable_generic;
137 mac->ops.setup_fc = ixgbe_setup_fc_generic;
138 mac->ops.fc_autoneg = ixgbe_fc_autoneg;
141 mac->ops.get_link_capabilities = NULL;
142 mac->ops.setup_link = NULL;
143 mac->ops.check_link = NULL;
144 mac->ops.dmac_config = NULL;
145 mac->ops.dmac_update_tcs = NULL;
146 mac->ops.dmac_config_tcs = NULL;
148 return IXGBE_SUCCESS;
152 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
154 * @hw: pointer to hardware structure
156 * This function returns true if the device supports flow control
157 * autonegotiation, and false if it does not.
160 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
162 bool supported = false;
163 ixgbe_link_speed speed;
166 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
168 switch (hw->phy.media_type) {
169 case ixgbe_media_type_fiber_qsfp:
170 case ixgbe_media_type_fiber:
171 hw->mac.ops.check_link(hw, &speed, &link_up, false);
172 /* if link is down, assume supported */
174 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
179 case ixgbe_media_type_backplane:
182 case ixgbe_media_type_copper:
183 /* only some copper devices support flow control autoneg */
184 switch (hw->device_id) {
185 case IXGBE_DEV_ID_82599_T3_LOM:
186 case IXGBE_DEV_ID_X540T:
187 case IXGBE_DEV_ID_X540T1:
188 case IXGBE_DEV_ID_X550T:
189 case IXGBE_DEV_ID_X550T1:
190 case IXGBE_DEV_ID_X550EM_X_10G_T:
191 case IXGBE_DEV_ID_X550EM_A_10G_T:
192 case IXGBE_DEV_ID_X550EM_A_1G_T:
193 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
203 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
204 "Device %x does not support flow control autoneg",
210 * ixgbe_setup_fc_generic - Set up flow control
211 * @hw: pointer to hardware structure
213 * Called at init time to set up flow control.
215 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
217 s32 ret_val = IXGBE_SUCCESS;
218 u32 reg = 0, reg_bp = 0;
222 DEBUGFUNC("ixgbe_setup_fc_generic");
224 /* Validate the requested mode */
225 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
226 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
227 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
228 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
233 * 10gig parts do not have a word in the EEPROM to determine the
234 * default flow control setting, so we explicitly set it to full.
236 if (hw->fc.requested_mode == ixgbe_fc_default)
237 hw->fc.requested_mode = ixgbe_fc_full;
240 * Set up the 1G and 10G flow control advertisement registers so the
241 * HW will be able to do fc autoneg once the cable is plugged in. If
242 * we link at 10G, the 1G advertisement is harmless and vice versa.
244 switch (hw->phy.media_type) {
245 case ixgbe_media_type_backplane:
246 /* some MAC's need RMW protection on AUTOC */
247 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
248 if (ret_val != IXGBE_SUCCESS)
251 /* only backplane uses autoc so fall though */
252 case ixgbe_media_type_fiber_qsfp:
253 case ixgbe_media_type_fiber:
254 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
257 case ixgbe_media_type_copper:
258 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
259 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
266 * The possible values of fc.requested_mode are:
267 * 0: Flow control is completely disabled
268 * 1: Rx flow control is enabled (we can receive pause frames,
269 * but not send pause frames).
270 * 2: Tx flow control is enabled (we can send pause frames but
271 * we do not support receiving pause frames).
272 * 3: Both Rx and Tx flow control (symmetric) are enabled.
275 switch (hw->fc.requested_mode) {
277 /* Flow control completely disabled by software override. */
278 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
279 if (hw->phy.media_type == ixgbe_media_type_backplane)
280 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
281 IXGBE_AUTOC_ASM_PAUSE);
282 else if (hw->phy.media_type == ixgbe_media_type_copper)
283 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
285 case ixgbe_fc_tx_pause:
287 * Tx Flow control is enabled, and Rx Flow control is
288 * disabled by software override.
290 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
291 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
292 if (hw->phy.media_type == ixgbe_media_type_backplane) {
293 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
294 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
295 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
296 reg_cu |= IXGBE_TAF_ASM_PAUSE;
297 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
300 case ixgbe_fc_rx_pause:
302 * Rx Flow control is enabled and Tx Flow control is
303 * disabled by software override. Since there really
304 * isn't a way to advertise that we are capable of RX
305 * Pause ONLY, we will advertise that we support both
306 * symmetric and asymmetric Rx PAUSE, as such we fall
307 * through to the fc_full statement. Later, we will
308 * disable the adapter's ability to send PAUSE frames.
311 /* Flow control (both Rx and Tx) is enabled by SW override. */
312 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
313 if (hw->phy.media_type == ixgbe_media_type_backplane)
314 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
315 IXGBE_AUTOC_ASM_PAUSE;
316 else if (hw->phy.media_type == ixgbe_media_type_copper)
317 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
320 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
321 "Flow control param set incorrectly\n");
322 ret_val = IXGBE_ERR_CONFIG;
327 if (hw->mac.type < ixgbe_mac_X540) {
329 * Enable auto-negotiation between the MAC & PHY;
330 * the MAC will advertise clause 37 flow control.
332 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
333 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
335 /* Disable AN timeout */
336 if (hw->fc.strict_ieee)
337 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
339 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
340 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
344 * AUTOC restart handles negotiation of 1G and 10G on backplane
345 * and copper. There is no need to set the PCS1GCTL register.
348 if (hw->phy.media_type == ixgbe_media_type_backplane) {
349 reg_bp |= IXGBE_AUTOC_AN_RESTART;
350 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
353 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
354 (ixgbe_device_supports_autoneg_fc(hw))) {
355 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
356 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
359 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
365 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
366 * @hw: pointer to hardware structure
368 * Starts the hardware by filling the bus info structure and media type, clears
369 * all on chip counters, initializes receive address registers, multicast
370 * table, VLAN filter table, calls routine to set up link and flow control
371 * settings, and leaves transmit and receive units disabled and uninitialized
373 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
379 DEBUGFUNC("ixgbe_start_hw_generic");
381 /* Set the media type */
382 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
384 /* PHY ops initialization must be done in reset_hw() */
386 /* Clear the VLAN filter table */
387 hw->mac.ops.clear_vfta(hw);
389 /* Clear statistics registers */
390 hw->mac.ops.clear_hw_cntrs(hw);
392 /* Set No Snoop Disable */
393 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
394 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
395 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
396 IXGBE_WRITE_FLUSH(hw);
398 /* Setup flow control */
399 ret_val = ixgbe_setup_fc(hw);
400 if (ret_val != IXGBE_SUCCESS)
403 /* Cache bit indicating need for crosstalk fix */
404 switch (hw->mac.type) {
405 case ixgbe_mac_82599EB:
406 case ixgbe_mac_X550EM_x:
407 case ixgbe_mac_X550EM_a:
408 hw->mac.ops.get_device_caps(hw, &device_caps);
409 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
410 hw->need_crosstalk_fix = false;
412 hw->need_crosstalk_fix = true;
415 hw->need_crosstalk_fix = false;
419 /* Clear adapter stopped flag */
420 hw->adapter_stopped = false;
427 * ixgbe_start_hw_gen2 - Init sequence for common device family
428 * @hw: pointer to hw structure
430 * Performs the init sequence common to the second generation
432 * Devices in the second generation:
436 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
441 /* Clear the rate limiters */
442 for (i = 0; i < hw->mac.max_tx_queues; i++) {
443 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
444 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
446 IXGBE_WRITE_FLUSH(hw);
448 /* Disable relaxed ordering */
449 for (i = 0; i < hw->mac.max_tx_queues; i++) {
450 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
451 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
452 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
455 for (i = 0; i < hw->mac.max_rx_queues; i++) {
456 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
457 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
458 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
459 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
462 return IXGBE_SUCCESS;
466 * ixgbe_init_hw_generic - Generic hardware initialization
467 * @hw: pointer to hardware structure
469 * Initialize the hardware by resetting the hardware, filling the bus info
470 * structure and media type, clears all on chip counters, initializes receive
471 * address registers, multicast table, VLAN filter table, calls routine to set
472 * up link and flow control settings, and leaves transmit and receive units
473 * disabled and uninitialized
475 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
479 DEBUGFUNC("ixgbe_init_hw_generic");
481 /* Reset the hardware */
482 status = hw->mac.ops.reset_hw(hw);
484 if (status == IXGBE_SUCCESS) {
486 status = hw->mac.ops.start_hw(hw);
493 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
494 * @hw: pointer to hardware structure
496 * Clears all hardware statistics counters by reading them from the hardware
497 * Statistics counters are clear on read.
499 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
503 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
505 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
506 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
507 IXGBE_READ_REG(hw, IXGBE_ERRBC);
508 IXGBE_READ_REG(hw, IXGBE_MSPDC);
509 for (i = 0; i < 8; i++)
510 IXGBE_READ_REG(hw, IXGBE_MPC(i));
512 IXGBE_READ_REG(hw, IXGBE_MLFC);
513 IXGBE_READ_REG(hw, IXGBE_MRFC);
514 IXGBE_READ_REG(hw, IXGBE_RLEC);
515 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
516 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
517 if (hw->mac.type >= ixgbe_mac_82599EB) {
518 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
519 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
521 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
522 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
525 for (i = 0; i < 8; i++) {
526 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
527 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
528 if (hw->mac.type >= ixgbe_mac_82599EB) {
529 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
530 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
532 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
533 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
536 if (hw->mac.type >= ixgbe_mac_82599EB)
537 for (i = 0; i < 8; i++)
538 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
539 IXGBE_READ_REG(hw, IXGBE_PRC64);
540 IXGBE_READ_REG(hw, IXGBE_PRC127);
541 IXGBE_READ_REG(hw, IXGBE_PRC255);
542 IXGBE_READ_REG(hw, IXGBE_PRC511);
543 IXGBE_READ_REG(hw, IXGBE_PRC1023);
544 IXGBE_READ_REG(hw, IXGBE_PRC1522);
545 IXGBE_READ_REG(hw, IXGBE_GPRC);
546 IXGBE_READ_REG(hw, IXGBE_BPRC);
547 IXGBE_READ_REG(hw, IXGBE_MPRC);
548 IXGBE_READ_REG(hw, IXGBE_GPTC);
549 IXGBE_READ_REG(hw, IXGBE_GORCL);
550 IXGBE_READ_REG(hw, IXGBE_GORCH);
551 IXGBE_READ_REG(hw, IXGBE_GOTCL);
552 IXGBE_READ_REG(hw, IXGBE_GOTCH);
553 if (hw->mac.type == ixgbe_mac_82598EB)
554 for (i = 0; i < 8; i++)
555 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
556 IXGBE_READ_REG(hw, IXGBE_RUC);
557 IXGBE_READ_REG(hw, IXGBE_RFC);
558 IXGBE_READ_REG(hw, IXGBE_ROC);
559 IXGBE_READ_REG(hw, IXGBE_RJC);
560 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
561 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
562 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
563 IXGBE_READ_REG(hw, IXGBE_TORL);
564 IXGBE_READ_REG(hw, IXGBE_TORH);
565 IXGBE_READ_REG(hw, IXGBE_TPR);
566 IXGBE_READ_REG(hw, IXGBE_TPT);
567 IXGBE_READ_REG(hw, IXGBE_PTC64);
568 IXGBE_READ_REG(hw, IXGBE_PTC127);
569 IXGBE_READ_REG(hw, IXGBE_PTC255);
570 IXGBE_READ_REG(hw, IXGBE_PTC511);
571 IXGBE_READ_REG(hw, IXGBE_PTC1023);
572 IXGBE_READ_REG(hw, IXGBE_PTC1522);
573 IXGBE_READ_REG(hw, IXGBE_MPTC);
574 IXGBE_READ_REG(hw, IXGBE_BPTC);
575 for (i = 0; i < 16; i++) {
576 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
577 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
578 if (hw->mac.type >= ixgbe_mac_82599EB) {
579 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
580 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
581 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
582 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
583 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
585 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
586 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
590 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
592 ixgbe_identify_phy(hw);
593 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
594 IXGBE_MDIO_PCS_DEV_TYPE, &i);
595 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
596 IXGBE_MDIO_PCS_DEV_TYPE, &i);
597 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
598 IXGBE_MDIO_PCS_DEV_TYPE, &i);
599 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
600 IXGBE_MDIO_PCS_DEV_TYPE, &i);
603 return IXGBE_SUCCESS;
607 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
608 * @hw: pointer to hardware structure
609 * @pba_num: stores the part number string from the EEPROM
610 * @pba_num_size: part number string buffer length
612 * Reads the part number string from the EEPROM.
614 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
623 DEBUGFUNC("ixgbe_read_pba_string_generic");
625 if (pba_num == NULL) {
626 DEBUGOUT("PBA string buffer was null\n");
627 return IXGBE_ERR_INVALID_ARGUMENT;
630 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
632 DEBUGOUT("NVM Read Error\n");
636 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
638 DEBUGOUT("NVM Read Error\n");
643 * if data is not ptr guard the PBA must be in legacy format which
644 * means pba_ptr is actually our second data word for the PBA number
645 * and we can decode it into an ascii string
647 if (data != IXGBE_PBANUM_PTR_GUARD) {
648 DEBUGOUT("NVM PBA number is not stored as string\n");
650 /* we will need 11 characters to store the PBA */
651 if (pba_num_size < 11) {
652 DEBUGOUT("PBA string buffer too small\n");
653 return IXGBE_ERR_NO_SPACE;
656 /* extract hex string from data and pba_ptr */
657 pba_num[0] = (data >> 12) & 0xF;
658 pba_num[1] = (data >> 8) & 0xF;
659 pba_num[2] = (data >> 4) & 0xF;
660 pba_num[3] = data & 0xF;
661 pba_num[4] = (pba_ptr >> 12) & 0xF;
662 pba_num[5] = (pba_ptr >> 8) & 0xF;
665 pba_num[8] = (pba_ptr >> 4) & 0xF;
666 pba_num[9] = pba_ptr & 0xF;
668 /* put a null character on the end of our string */
671 /* switch all the data but the '-' to hex char */
672 for (offset = 0; offset < 10; offset++) {
673 if (pba_num[offset] < 0xA)
674 pba_num[offset] += '0';
675 else if (pba_num[offset] < 0x10)
676 pba_num[offset] += 'A' - 0xA;
679 return IXGBE_SUCCESS;
682 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
684 DEBUGOUT("NVM Read Error\n");
688 if (length == 0xFFFF || length == 0) {
689 DEBUGOUT("NVM PBA number section invalid length\n");
690 return IXGBE_ERR_PBA_SECTION;
693 /* check if pba_num buffer is big enough */
694 if (pba_num_size < (((u32)length * 2) - 1)) {
695 DEBUGOUT("PBA string buffer too small\n");
696 return IXGBE_ERR_NO_SPACE;
699 /* trim pba length from start of string */
703 for (offset = 0; offset < length; offset++) {
704 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
706 DEBUGOUT("NVM Read Error\n");
709 pba_num[offset * 2] = (u8)(data >> 8);
710 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
712 pba_num[offset * 2] = '\0';
714 return IXGBE_SUCCESS;
718 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
719 * @hw: pointer to hardware structure
720 * @pba_num: stores the part number from the EEPROM
722 * Reads the part number from the EEPROM.
724 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
729 DEBUGFUNC("ixgbe_read_pba_num_generic");
731 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
733 DEBUGOUT("NVM Read Error\n");
735 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
736 DEBUGOUT("NVM Not supported\n");
737 return IXGBE_NOT_IMPLEMENTED;
739 *pba_num = (u32)(data << 16);
741 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
743 DEBUGOUT("NVM Read Error\n");
748 return IXGBE_SUCCESS;
753 * @hw: pointer to the HW structure
754 * @eeprom_buf: optional pointer to EEPROM image
755 * @eeprom_buf_size: size of EEPROM image in words
756 * @max_pba_block_size: PBA block size limit
757 * @pba: pointer to output PBA structure
759 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
760 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
763 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
764 u32 eeprom_buf_size, u16 max_pba_block_size,
765 struct ixgbe_pba *pba)
771 return IXGBE_ERR_PARAM;
773 if (eeprom_buf == NULL) {
774 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
779 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
780 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
781 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
783 return IXGBE_ERR_PARAM;
787 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
788 if (pba->pba_block == NULL)
789 return IXGBE_ERR_PARAM;
791 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
797 if (pba_block_size > max_pba_block_size)
798 return IXGBE_ERR_PARAM;
800 if (eeprom_buf == NULL) {
801 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
807 if (eeprom_buf_size > (u32)(pba->word[1] +
809 memcpy(pba->pba_block,
810 &eeprom_buf[pba->word[1]],
811 pba_block_size * sizeof(u16));
813 return IXGBE_ERR_PARAM;
818 return IXGBE_SUCCESS;
822 * ixgbe_write_pba_raw
823 * @hw: pointer to the HW structure
824 * @eeprom_buf: optional pointer to EEPROM image
825 * @eeprom_buf_size: size of EEPROM image in words
826 * @pba: pointer to PBA structure
828 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
829 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
832 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
833 u32 eeprom_buf_size, struct ixgbe_pba *pba)
838 return IXGBE_ERR_PARAM;
840 if (eeprom_buf == NULL) {
841 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
846 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
847 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
848 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
850 return IXGBE_ERR_PARAM;
854 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
855 if (pba->pba_block == NULL)
856 return IXGBE_ERR_PARAM;
858 if (eeprom_buf == NULL) {
859 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
865 if (eeprom_buf_size > (u32)(pba->word[1] +
866 pba->pba_block[0])) {
867 memcpy(&eeprom_buf[pba->word[1]],
869 pba->pba_block[0] * sizeof(u16));
871 return IXGBE_ERR_PARAM;
876 return IXGBE_SUCCESS;
880 * ixgbe_get_pba_block_size
881 * @hw: pointer to the HW structure
882 * @eeprom_buf: optional pointer to EEPROM image
883 * @eeprom_buf_size: size of EEPROM image in words
884 * @pba_data_size: pointer to output variable
886 * Returns the size of the PBA block in words. Function operates on EEPROM
887 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
891 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
892 u32 eeprom_buf_size, u16 *pba_block_size)
898 DEBUGFUNC("ixgbe_get_pba_block_size");
900 if (eeprom_buf == NULL) {
901 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
906 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
907 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
908 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
910 return IXGBE_ERR_PARAM;
914 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
915 if (eeprom_buf == NULL) {
916 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
921 if (eeprom_buf_size > pba_word[1])
922 length = eeprom_buf[pba_word[1] + 0];
924 return IXGBE_ERR_PARAM;
927 if (length == 0xFFFF || length == 0)
928 return IXGBE_ERR_PBA_SECTION;
930 /* PBA number in legacy format, there is no PBA Block. */
934 if (pba_block_size != NULL)
935 *pba_block_size = length;
937 return IXGBE_SUCCESS;
941 * ixgbe_get_mac_addr_generic - Generic get MAC address
942 * @hw: pointer to hardware structure
943 * @mac_addr: Adapter MAC address
945 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
946 * A reset of the adapter must be performed prior to calling this function
947 * in order for the MAC address to have been loaded from the EEPROM into RAR0
949 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
955 DEBUGFUNC("ixgbe_get_mac_addr_generic");
957 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
958 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
960 for (i = 0; i < 4; i++)
961 mac_addr[i] = (u8)(rar_low >> (i*8));
963 for (i = 0; i < 2; i++)
964 mac_addr[i+4] = (u8)(rar_high >> (i*8));
966 return IXGBE_SUCCESS;
970 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
971 * @hw: pointer to hardware structure
972 * @link_status: the link status returned by the PCI config space
974 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
976 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
978 struct ixgbe_mac_info *mac = &hw->mac;
980 if (hw->bus.type == ixgbe_bus_type_unknown)
981 hw->bus.type = ixgbe_bus_type_pci_express;
983 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
984 case IXGBE_PCI_LINK_WIDTH_1:
985 hw->bus.width = ixgbe_bus_width_pcie_x1;
987 case IXGBE_PCI_LINK_WIDTH_2:
988 hw->bus.width = ixgbe_bus_width_pcie_x2;
990 case IXGBE_PCI_LINK_WIDTH_4:
991 hw->bus.width = ixgbe_bus_width_pcie_x4;
993 case IXGBE_PCI_LINK_WIDTH_8:
994 hw->bus.width = ixgbe_bus_width_pcie_x8;
997 hw->bus.width = ixgbe_bus_width_unknown;
1001 switch (link_status & IXGBE_PCI_LINK_SPEED) {
1002 case IXGBE_PCI_LINK_SPEED_2500:
1003 hw->bus.speed = ixgbe_bus_speed_2500;
1005 case IXGBE_PCI_LINK_SPEED_5000:
1006 hw->bus.speed = ixgbe_bus_speed_5000;
1008 case IXGBE_PCI_LINK_SPEED_8000:
1009 hw->bus.speed = ixgbe_bus_speed_8000;
1012 hw->bus.speed = ixgbe_bus_speed_unknown;
1016 mac->ops.set_lan_id(hw);
1020 * ixgbe_get_bus_info_generic - Generic set PCI bus info
1021 * @hw: pointer to hardware structure
1023 * Gets the PCI bus info (speed, width, type) then calls helper function to
1024 * store this data within the ixgbe_hw structure.
1026 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
1030 DEBUGFUNC("ixgbe_get_bus_info_generic");
1032 /* Get the negotiated link width and speed from PCI config space */
1033 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
1035 ixgbe_set_pci_config_data_generic(hw, link_status);
1037 return IXGBE_SUCCESS;
1041 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
1042 * @hw: pointer to the HW structure
1044 * Determines the LAN function id by reading memory-mapped registers and swaps
1045 * the port value if requested, and set MAC instance for devices that share
1048 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
1050 struct ixgbe_bus_info *bus = &hw->bus;
1054 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
1056 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
1057 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
1058 bus->lan_id = (u8)bus->func;
1060 /* check for a port swap */
1061 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
1062 if (reg & IXGBE_FACTPS_LFS)
1065 /* Get MAC instance from EEPROM for configuring CS4227 */
1066 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) {
1067 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4);
1068 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >>
1069 IXGBE_EE_CTRL_4_INST_ID_SHIFT;
1074 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1075 * @hw: pointer to hardware structure
1077 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
1078 * disables transmit and receive units. The adapter_stopped flag is used by
1079 * the shared code and drivers to determine if the adapter is in a stopped
1080 * state and should not touch the hardware.
1082 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1087 DEBUGFUNC("ixgbe_stop_adapter_generic");
1090 * Set the adapter_stopped flag so other driver functions stop touching
1093 hw->adapter_stopped = true;
1095 /* Disable the receive unit */
1096 ixgbe_disable_rx(hw);
1098 /* Clear interrupt mask to stop interrupts from being generated */
1099 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1101 /* Clear any pending interrupts, flush previous writes */
1102 IXGBE_READ_REG(hw, IXGBE_EICR);
1104 /* Disable the transmit unit. Each queue must be disabled. */
1105 for (i = 0; i < hw->mac.max_tx_queues; i++)
1106 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1108 /* Disable the receive unit by stopping each queue */
1109 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1110 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1111 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1112 reg_val |= IXGBE_RXDCTL_SWFLSH;
1113 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1116 /* flush all queues disables */
1117 IXGBE_WRITE_FLUSH(hw);
1121 * Prevent the PCI-E bus from hanging by disabling PCI-E master
1122 * access and verify no pending requests
1124 return ixgbe_disable_pcie_master(hw);
1128 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1129 * @hw: pointer to hardware structure
1130 * @index: led number to turn on
1132 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1134 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1136 DEBUGFUNC("ixgbe_led_on_generic");
1139 return IXGBE_ERR_PARAM;
1141 /* To turn on the LED, set mode to ON. */
1142 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1143 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
1144 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1145 IXGBE_WRITE_FLUSH(hw);
1147 return IXGBE_SUCCESS;
1151 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1152 * @hw: pointer to hardware structure
1153 * @index: led number to turn off
1155 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1157 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1159 DEBUGFUNC("ixgbe_led_off_generic");
1162 return IXGBE_ERR_PARAM;
1164 /* To turn off the LED, set mode to OFF. */
1165 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1166 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
1167 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1168 IXGBE_WRITE_FLUSH(hw);
1170 return IXGBE_SUCCESS;
1174 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1175 * @hw: pointer to hardware structure
1177 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1178 * ixgbe_hw struct in order to set up EEPROM access.
1180 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1182 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1186 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
1188 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1189 eeprom->type = ixgbe_eeprom_none;
1190 /* Set default semaphore delay to 10ms which is a well
1192 eeprom->semaphore_delay = 10;
1193 /* Clear EEPROM page size, it will be initialized as needed */
1194 eeprom->word_page_size = 0;
1197 * Check for EEPROM present first.
1198 * If not present leave as none
1200 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1201 if (eec & IXGBE_EEC_PRES) {
1202 eeprom->type = ixgbe_eeprom_spi;
1205 * SPI EEPROM is assumed here. This code would need to
1206 * change if a future EEPROM is not SPI.
1208 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1209 IXGBE_EEC_SIZE_SHIFT);
1210 eeprom->word_size = 1 << (eeprom_size +
1211 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1214 if (eec & IXGBE_EEC_ADDR_SIZE)
1215 eeprom->address_bits = 16;
1217 eeprom->address_bits = 8;
1218 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
1219 "%d\n", eeprom->type, eeprom->word_size,
1220 eeprom->address_bits);
1223 return IXGBE_SUCCESS;
1227 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1228 * @hw: pointer to hardware structure
1229 * @offset: offset within the EEPROM to write
1230 * @words: number of word(s)
1231 * @data: 16 bit word(s) to write to EEPROM
1233 * Reads 16 bit word(s) from EEPROM through bit-bang method
1235 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1236 u16 words, u16 *data)
1238 s32 status = IXGBE_SUCCESS;
1241 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
1243 hw->eeprom.ops.init_params(hw);
1246 status = IXGBE_ERR_INVALID_ARGUMENT;
1250 if (offset + words > hw->eeprom.word_size) {
1251 status = IXGBE_ERR_EEPROM;
1256 * The EEPROM page size cannot be queried from the chip. We do lazy
1257 * initialization. It is worth to do that when we write large buffer.
1259 if ((hw->eeprom.word_page_size == 0) &&
1260 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
1261 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1264 * We cannot hold synchronization semaphores for too long
1265 * to avoid other entity starvation. However it is more efficient
1266 * to read in bursts than synchronizing access for each word.
1268 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1269 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1270 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1271 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1274 if (status != IXGBE_SUCCESS)
1283 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1284 * @hw: pointer to hardware structure
1285 * @offset: offset within the EEPROM to be written to
1286 * @words: number of word(s)
1287 * @data: 16 bit word(s) to be written to the EEPROM
1289 * If ixgbe_eeprom_update_checksum is not called after this function, the
1290 * EEPROM will most likely contain an invalid checksum.
1292 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1293 u16 words, u16 *data)
1299 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1301 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1303 /* Prepare the EEPROM for writing */
1304 status = ixgbe_acquire_eeprom(hw);
1306 if (status == IXGBE_SUCCESS) {
1307 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1308 ixgbe_release_eeprom(hw);
1309 status = IXGBE_ERR_EEPROM;
1313 if (status == IXGBE_SUCCESS) {
1314 for (i = 0; i < words; i++) {
1315 ixgbe_standby_eeprom(hw);
1317 /* Send the WRITE ENABLE command (8 bit opcode ) */
1318 ixgbe_shift_out_eeprom_bits(hw,
1319 IXGBE_EEPROM_WREN_OPCODE_SPI,
1320 IXGBE_EEPROM_OPCODE_BITS);
1322 ixgbe_standby_eeprom(hw);
1325 * Some SPI eeproms use the 8th address bit embedded
1328 if ((hw->eeprom.address_bits == 8) &&
1329 ((offset + i) >= 128))
1330 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1332 /* Send the Write command (8-bit opcode + addr) */
1333 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1334 IXGBE_EEPROM_OPCODE_BITS);
1335 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1336 hw->eeprom.address_bits);
1338 page_size = hw->eeprom.word_page_size;
1340 /* Send the data in burst via SPI*/
1343 word = (word >> 8) | (word << 8);
1344 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1349 /* do not wrap around page */
1350 if (((offset + i) & (page_size - 1)) ==
1353 } while (++i < words);
1355 ixgbe_standby_eeprom(hw);
1358 /* Done with writing - release the EEPROM */
1359 ixgbe_release_eeprom(hw);
1366 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1367 * @hw: pointer to hardware structure
1368 * @offset: offset within the EEPROM to be written to
1369 * @data: 16 bit word to be written to the EEPROM
1371 * If ixgbe_eeprom_update_checksum is not called after this function, the
1372 * EEPROM will most likely contain an invalid checksum.
1374 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1378 DEBUGFUNC("ixgbe_write_eeprom_generic");
1380 hw->eeprom.ops.init_params(hw);
1382 if (offset >= hw->eeprom.word_size) {
1383 status = IXGBE_ERR_EEPROM;
1387 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1394 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1395 * @hw: pointer to hardware structure
1396 * @offset: offset within the EEPROM to be read
1397 * @data: read 16 bit words(s) from EEPROM
1398 * @words: number of word(s)
1400 * Reads 16 bit word(s) from EEPROM through bit-bang method
1402 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1403 u16 words, u16 *data)
1405 s32 status = IXGBE_SUCCESS;
1408 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1410 hw->eeprom.ops.init_params(hw);
1413 status = IXGBE_ERR_INVALID_ARGUMENT;
1417 if (offset + words > hw->eeprom.word_size) {
1418 status = IXGBE_ERR_EEPROM;
1423 * We cannot hold synchronization semaphores for too long
1424 * to avoid other entity starvation. However it is more efficient
1425 * to read in bursts than synchronizing access for each word.
1427 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1428 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1429 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1431 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1434 if (status != IXGBE_SUCCESS)
1443 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1444 * @hw: pointer to hardware structure
1445 * @offset: offset within the EEPROM to be read
1446 * @words: number of word(s)
1447 * @data: read 16 bit word(s) from EEPROM
1449 * Reads 16 bit word(s) from EEPROM through bit-bang method
1451 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1452 u16 words, u16 *data)
1456 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1459 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1461 /* Prepare the EEPROM for reading */
1462 status = ixgbe_acquire_eeprom(hw);
1464 if (status == IXGBE_SUCCESS) {
1465 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1466 ixgbe_release_eeprom(hw);
1467 status = IXGBE_ERR_EEPROM;
1471 if (status == IXGBE_SUCCESS) {
1472 for (i = 0; i < words; i++) {
1473 ixgbe_standby_eeprom(hw);
1475 * Some SPI eeproms use the 8th address bit embedded
1478 if ((hw->eeprom.address_bits == 8) &&
1479 ((offset + i) >= 128))
1480 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1482 /* Send the READ command (opcode + addr) */
1483 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1484 IXGBE_EEPROM_OPCODE_BITS);
1485 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1486 hw->eeprom.address_bits);
1488 /* Read the data. */
1489 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1490 data[i] = (word_in >> 8) | (word_in << 8);
1493 /* End this read operation */
1494 ixgbe_release_eeprom(hw);
1501 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1502 * @hw: pointer to hardware structure
1503 * @offset: offset within the EEPROM to be read
1504 * @data: read 16 bit value from EEPROM
1506 * Reads 16 bit value from EEPROM through bit-bang method
1508 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1513 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1515 hw->eeprom.ops.init_params(hw);
1517 if (offset >= hw->eeprom.word_size) {
1518 status = IXGBE_ERR_EEPROM;
1522 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1529 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1530 * @hw: pointer to hardware structure
1531 * @offset: offset of word in the EEPROM to read
1532 * @words: number of word(s)
1533 * @data: 16 bit word(s) from the EEPROM
1535 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1537 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1538 u16 words, u16 *data)
1541 s32 status = IXGBE_SUCCESS;
1544 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1546 hw->eeprom.ops.init_params(hw);
1549 status = IXGBE_ERR_INVALID_ARGUMENT;
1550 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1554 if (offset >= hw->eeprom.word_size) {
1555 status = IXGBE_ERR_EEPROM;
1556 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1560 for (i = 0; i < words; i++) {
1561 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1562 IXGBE_EEPROM_RW_REG_START;
1564 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1565 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1567 if (status == IXGBE_SUCCESS) {
1568 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1569 IXGBE_EEPROM_RW_REG_DATA);
1571 DEBUGOUT("Eeprom read timed out\n");
1580 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1581 * @hw: pointer to hardware structure
1582 * @offset: offset within the EEPROM to be used as a scratch pad
1584 * Discover EEPROM page size by writing marching data at given offset.
1585 * This function is called only when we are writing a new large buffer
1586 * at given offset so the data would be overwritten anyway.
1588 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1591 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1592 s32 status = IXGBE_SUCCESS;
1595 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1597 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1600 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1601 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1602 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1603 hw->eeprom.word_page_size = 0;
1604 if (status != IXGBE_SUCCESS)
1607 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1608 if (status != IXGBE_SUCCESS)
1612 * When writing in burst more than the actual page size
1613 * EEPROM address wraps around current page.
1615 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1617 DEBUGOUT1("Detected EEPROM page size = %d words.",
1618 hw->eeprom.word_page_size);
1624 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1625 * @hw: pointer to hardware structure
1626 * @offset: offset of word in the EEPROM to read
1627 * @data: word read from the EEPROM
1629 * Reads a 16 bit word from the EEPROM using the EERD register.
1631 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1633 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1637 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1638 * @hw: pointer to hardware structure
1639 * @offset: offset of word in the EEPROM to write
1640 * @words: number of word(s)
1641 * @data: word(s) write to the EEPROM
1643 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1645 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1646 u16 words, u16 *data)
1649 s32 status = IXGBE_SUCCESS;
1652 DEBUGFUNC("ixgbe_write_eewr_generic");
1654 hw->eeprom.ops.init_params(hw);
1657 status = IXGBE_ERR_INVALID_ARGUMENT;
1658 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1662 if (offset >= hw->eeprom.word_size) {
1663 status = IXGBE_ERR_EEPROM;
1664 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1668 for (i = 0; i < words; i++) {
1669 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1670 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1671 IXGBE_EEPROM_RW_REG_START;
1673 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1674 if (status != IXGBE_SUCCESS) {
1675 DEBUGOUT("Eeprom write EEWR timed out\n");
1679 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1681 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1682 if (status != IXGBE_SUCCESS) {
1683 DEBUGOUT("Eeprom write EEWR timed out\n");
1693 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1694 * @hw: pointer to hardware structure
1695 * @offset: offset of word in the EEPROM to write
1696 * @data: word write to the EEPROM
1698 * Write a 16 bit word to the EEPROM using the EEWR register.
1700 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1702 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1706 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1707 * @hw: pointer to hardware structure
1708 * @ee_reg: EEPROM flag for polling
1710 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1711 * read or write is done respectively.
1713 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1717 s32 status = IXGBE_ERR_EEPROM;
1719 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1721 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1722 if (ee_reg == IXGBE_NVM_POLL_READ)
1723 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1725 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1727 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1728 status = IXGBE_SUCCESS;
1734 if (i == IXGBE_EERD_EEWR_ATTEMPTS)
1735 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1736 "EEPROM read/write done polling timed out");
1742 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1743 * @hw: pointer to hardware structure
1745 * Prepares EEPROM for access using bit-bang method. This function should
1746 * be called before issuing a command to the EEPROM.
1748 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1750 s32 status = IXGBE_SUCCESS;
1754 DEBUGFUNC("ixgbe_acquire_eeprom");
1756 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1758 status = IXGBE_ERR_SWFW_SYNC;
1760 if (status == IXGBE_SUCCESS) {
1761 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1763 /* Request EEPROM Access */
1764 eec |= IXGBE_EEC_REQ;
1765 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1767 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1768 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1769 if (eec & IXGBE_EEC_GNT)
1774 /* Release if grant not acquired */
1775 if (!(eec & IXGBE_EEC_GNT)) {
1776 eec &= ~IXGBE_EEC_REQ;
1777 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1778 DEBUGOUT("Could not acquire EEPROM grant\n");
1780 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1781 status = IXGBE_ERR_EEPROM;
1784 /* Setup EEPROM for Read/Write */
1785 if (status == IXGBE_SUCCESS) {
1786 /* Clear CS and SK */
1787 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1788 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1789 IXGBE_WRITE_FLUSH(hw);
1797 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1798 * @hw: pointer to hardware structure
1800 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1802 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1804 s32 status = IXGBE_ERR_EEPROM;
1809 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1812 /* Get SMBI software semaphore between device drivers first */
1813 for (i = 0; i < timeout; i++) {
1815 * If the SMBI bit is 0 when we read it, then the bit will be
1816 * set and we have the semaphore
1818 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1819 if (!(swsm & IXGBE_SWSM_SMBI)) {
1820 status = IXGBE_SUCCESS;
1827 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1830 * this release is particularly important because our attempts
1831 * above to get the semaphore may have succeeded, and if there
1832 * was a timeout, we should unconditionally clear the semaphore
1833 * bits to free the driver to make progress
1835 ixgbe_release_eeprom_semaphore(hw);
1840 * If the SMBI bit is 0 when we read it, then the bit will be
1841 * set and we have the semaphore
1843 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1844 if (!(swsm & IXGBE_SWSM_SMBI))
1845 status = IXGBE_SUCCESS;
1848 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1849 if (status == IXGBE_SUCCESS) {
1850 for (i = 0; i < timeout; i++) {
1851 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1853 /* Set the SW EEPROM semaphore bit to request access */
1854 swsm |= IXGBE_SWSM_SWESMBI;
1855 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
1858 * If we set the bit successfully then we got the
1861 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1862 if (swsm & IXGBE_SWSM_SWESMBI)
1869 * Release semaphores and return error if SW EEPROM semaphore
1870 * was not granted because we don't have access to the EEPROM
1873 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1874 "SWESMBI Software EEPROM semaphore not granted.\n");
1875 ixgbe_release_eeprom_semaphore(hw);
1876 status = IXGBE_ERR_EEPROM;
1879 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1880 "Software semaphore SMBI between device drivers "
1888 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1889 * @hw: pointer to hardware structure
1891 * This function clears hardware semaphore bits.
1893 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1897 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1899 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1901 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1902 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1903 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1904 IXGBE_WRITE_FLUSH(hw);
1908 * ixgbe_ready_eeprom - Polls for EEPROM ready
1909 * @hw: pointer to hardware structure
1911 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1913 s32 status = IXGBE_SUCCESS;
1917 DEBUGFUNC("ixgbe_ready_eeprom");
1920 * Read "Status Register" repeatedly until the LSB is cleared. The
1921 * EEPROM will signal that the command has been completed by clearing
1922 * bit 0 of the internal status register. If it's not cleared within
1923 * 5 milliseconds, then error out.
1925 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1926 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1927 IXGBE_EEPROM_OPCODE_BITS);
1928 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1929 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1933 ixgbe_standby_eeprom(hw);
1937 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1938 * devices (and only 0-5mSec on 5V devices)
1940 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1941 DEBUGOUT("SPI EEPROM Status error\n");
1942 status = IXGBE_ERR_EEPROM;
1949 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1950 * @hw: pointer to hardware structure
1952 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1956 DEBUGFUNC("ixgbe_standby_eeprom");
1958 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1960 /* Toggle CS to flush commands */
1961 eec |= IXGBE_EEC_CS;
1962 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1963 IXGBE_WRITE_FLUSH(hw);
1965 eec &= ~IXGBE_EEC_CS;
1966 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1967 IXGBE_WRITE_FLUSH(hw);
1972 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1973 * @hw: pointer to hardware structure
1974 * @data: data to send to the EEPROM
1975 * @count: number of bits to shift out
1977 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1984 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
1986 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1989 * Mask is used to shift "count" bits of "data" out to the EEPROM
1990 * one bit at a time. Determine the starting bit based on count
1992 mask = 0x01 << (count - 1);
1994 for (i = 0; i < count; i++) {
1996 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1997 * "1", and then raising and then lowering the clock (the SK
1998 * bit controls the clock input to the EEPROM). A "0" is
1999 * shifted out to the EEPROM by setting "DI" to "0" and then
2000 * raising and then lowering the clock.
2003 eec |= IXGBE_EEC_DI;
2005 eec &= ~IXGBE_EEC_DI;
2007 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2008 IXGBE_WRITE_FLUSH(hw);
2012 ixgbe_raise_eeprom_clk(hw, &eec);
2013 ixgbe_lower_eeprom_clk(hw, &eec);
2016 * Shift mask to signify next bit of data to shift in to the
2022 /* We leave the "DI" bit set to "0" when we leave this routine. */
2023 eec &= ~IXGBE_EEC_DI;
2024 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2025 IXGBE_WRITE_FLUSH(hw);
2029 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
2030 * @hw: pointer to hardware structure
2032 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
2038 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
2041 * In order to read a register from the EEPROM, we need to shift
2042 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
2043 * the clock input to the EEPROM (setting the SK bit), and then reading
2044 * the value of the "DO" bit. During this "shifting in" process the
2045 * "DI" bit should always be clear.
2047 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2049 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
2051 for (i = 0; i < count; i++) {
2053 ixgbe_raise_eeprom_clk(hw, &eec);
2055 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2057 eec &= ~(IXGBE_EEC_DI);
2058 if (eec & IXGBE_EEC_DO)
2061 ixgbe_lower_eeprom_clk(hw, &eec);
2068 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
2069 * @hw: pointer to hardware structure
2070 * @eec: EEC register's current value
2072 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2074 DEBUGFUNC("ixgbe_raise_eeprom_clk");
2077 * Raise the clock input to the EEPROM
2078 * (setting the SK bit), then delay
2080 *eec = *eec | IXGBE_EEC_SK;
2081 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2082 IXGBE_WRITE_FLUSH(hw);
2087 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2088 * @hw: pointer to hardware structure
2089 * @eecd: EECD's current value
2091 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2093 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2096 * Lower the clock input to the EEPROM (clearing the SK bit), then
2099 *eec = *eec & ~IXGBE_EEC_SK;
2100 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2101 IXGBE_WRITE_FLUSH(hw);
2106 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2107 * @hw: pointer to hardware structure
2109 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2113 DEBUGFUNC("ixgbe_release_eeprom");
2115 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2117 eec |= IXGBE_EEC_CS; /* Pull CS high */
2118 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
2120 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2121 IXGBE_WRITE_FLUSH(hw);
2125 /* Stop requesting EEPROM access */
2126 eec &= ~IXGBE_EEC_REQ;
2127 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2129 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2131 /* Delay before attempt to obtain semaphore again to allow FW access */
2132 msec_delay(hw->eeprom.semaphore_delay);
2136 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2137 * @hw: pointer to hardware structure
2139 * Returns a negative error code on error, or the 16-bit checksum
2141 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2150 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
2152 /* Include 0x0-0x3F in the checksum */
2153 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
2154 if (hw->eeprom.ops.read(hw, i, &word)) {
2155 DEBUGOUT("EEPROM read failed\n");
2156 return IXGBE_ERR_EEPROM;
2161 /* Include all data from pointers except for the fw pointer */
2162 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
2163 if (hw->eeprom.ops.read(hw, i, &pointer)) {
2164 DEBUGOUT("EEPROM read failed\n");
2165 return IXGBE_ERR_EEPROM;
2168 /* If the pointer seems invalid */
2169 if (pointer == 0xFFFF || pointer == 0)
2172 if (hw->eeprom.ops.read(hw, pointer, &length)) {
2173 DEBUGOUT("EEPROM read failed\n");
2174 return IXGBE_ERR_EEPROM;
2177 if (length == 0xFFFF || length == 0)
2180 for (j = pointer + 1; j <= pointer + length; j++) {
2181 if (hw->eeprom.ops.read(hw, j, &word)) {
2182 DEBUGOUT("EEPROM read failed\n");
2183 return IXGBE_ERR_EEPROM;
2189 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2191 return (s32)checksum;
2195 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2196 * @hw: pointer to hardware structure
2197 * @checksum_val: calculated checksum
2199 * Performs checksum calculation and validates the EEPROM checksum. If the
2200 * caller does not need checksum_val, the value can be NULL.
2202 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2207 u16 read_checksum = 0;
2209 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
2211 /* Read the first word from the EEPROM. If this times out or fails, do
2212 * not continue or we could be in for a very long wait while every
2215 status = hw->eeprom.ops.read(hw, 0, &checksum);
2217 DEBUGOUT("EEPROM read failed\n");
2221 status = hw->eeprom.ops.calc_checksum(hw);
2225 checksum = (u16)(status & 0xffff);
2227 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2229 DEBUGOUT("EEPROM read failed\n");
2233 /* Verify read checksum from EEPROM is the same as
2234 * calculated checksum
2236 if (read_checksum != checksum)
2237 status = IXGBE_ERR_EEPROM_CHECKSUM;
2239 /* If the user cares, return the calculated checksum */
2241 *checksum_val = checksum;
2247 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2248 * @hw: pointer to hardware structure
2250 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2255 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
2257 /* Read the first word from the EEPROM. If this times out or fails, do
2258 * not continue or we could be in for a very long wait while every
2261 status = hw->eeprom.ops.read(hw, 0, &checksum);
2263 DEBUGOUT("EEPROM read failed\n");
2267 status = hw->eeprom.ops.calc_checksum(hw);
2271 checksum = (u16)(status & 0xffff);
2273 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
2279 * ixgbe_validate_mac_addr - Validate MAC address
2280 * @mac_addr: pointer to MAC address.
2282 * Tests a MAC address to ensure it is a valid Individual Address.
2284 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
2286 s32 status = IXGBE_SUCCESS;
2288 DEBUGFUNC("ixgbe_validate_mac_addr");
2290 /* Make sure it is not a multicast address */
2291 if (IXGBE_IS_MULTICAST(mac_addr)) {
2292 status = IXGBE_ERR_INVALID_MAC_ADDR;
2293 /* Not a broadcast address */
2294 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
2295 status = IXGBE_ERR_INVALID_MAC_ADDR;
2296 /* Reject the zero address */
2297 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
2298 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
2299 status = IXGBE_ERR_INVALID_MAC_ADDR;
2305 * ixgbe_set_rar_generic - Set Rx address register
2306 * @hw: pointer to hardware structure
2307 * @index: Receive address register to write
2308 * @addr: Address to put into receive address register
2309 * @vmdq: VMDq "set" or "pool" index
2310 * @enable_addr: set flag that address is active
2312 * Puts an ethernet address into a receive address register.
2314 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2317 u32 rar_low, rar_high;
2318 u32 rar_entries = hw->mac.num_rar_entries;
2320 DEBUGFUNC("ixgbe_set_rar_generic");
2322 /* Make sure we are using a valid rar index range */
2323 if (index >= rar_entries) {
2324 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2325 "RAR index %d is out of range.\n", index);
2326 return IXGBE_ERR_INVALID_ARGUMENT;
2329 /* setup VMDq pool selection before this RAR gets enabled */
2330 hw->mac.ops.set_vmdq(hw, index, vmdq);
2333 * HW expects these in little endian so we reverse the byte
2334 * order from network order (big endian) to little endian
2336 rar_low = ((u32)addr[0] |
2337 ((u32)addr[1] << 8) |
2338 ((u32)addr[2] << 16) |
2339 ((u32)addr[3] << 24));
2341 * Some parts put the VMDq setting in the extra RAH bits,
2342 * so save everything except the lower 16 bits that hold part
2343 * of the address and the address valid bit.
2345 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2346 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2347 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2349 if (enable_addr != 0)
2350 rar_high |= IXGBE_RAH_AV;
2352 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2353 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2355 return IXGBE_SUCCESS;
2359 * ixgbe_clear_rar_generic - Remove Rx address register
2360 * @hw: pointer to hardware structure
2361 * @index: Receive address register to write
2363 * Clears an ethernet address from a receive address register.
2365 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2368 u32 rar_entries = hw->mac.num_rar_entries;
2370 DEBUGFUNC("ixgbe_clear_rar_generic");
2372 /* Make sure we are using a valid rar index range */
2373 if (index >= rar_entries) {
2374 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2375 "RAR index %d is out of range.\n", index);
2376 return IXGBE_ERR_INVALID_ARGUMENT;
2380 * Some parts put the VMDq setting in the extra RAH bits,
2381 * so save everything except the lower 16 bits that hold part
2382 * of the address and the address valid bit.
2384 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2385 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2387 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2388 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2390 /* clear VMDq pool/queue selection for this RAR */
2391 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2393 return IXGBE_SUCCESS;
2397 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2398 * @hw: pointer to hardware structure
2400 * Places the MAC address in receive address register 0 and clears the rest
2401 * of the receive address registers. Clears the multicast table. Assumes
2402 * the receiver is in reset when the routine is called.
2404 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2407 u32 rar_entries = hw->mac.num_rar_entries;
2409 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2412 * If the current mac address is valid, assume it is a software override
2413 * to the permanent address.
2414 * Otherwise, use the permanent address from the eeprom.
2416 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2417 IXGBE_ERR_INVALID_MAC_ADDR) {
2418 /* Get the MAC address from the RAR0 for later reference */
2419 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2421 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2422 hw->mac.addr[0], hw->mac.addr[1],
2424 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2425 hw->mac.addr[4], hw->mac.addr[5]);
2427 /* Setup the receive address. */
2428 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2429 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2430 hw->mac.addr[0], hw->mac.addr[1],
2432 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2433 hw->mac.addr[4], hw->mac.addr[5]);
2435 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2438 /* clear VMDq pool/queue selection for RAR 0 */
2439 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2441 hw->addr_ctrl.overflow_promisc = 0;
2443 hw->addr_ctrl.rar_used_count = 1;
2445 /* Zero out the other receive addresses. */
2446 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2447 for (i = 1; i < rar_entries; i++) {
2448 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2449 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2453 hw->addr_ctrl.mta_in_use = 0;
2454 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2456 DEBUGOUT(" Clearing MTA\n");
2457 for (i = 0; i < hw->mac.mcft_size; i++)
2458 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2460 ixgbe_init_uta_tables(hw);
2462 return IXGBE_SUCCESS;
2466 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2467 * @hw: pointer to hardware structure
2468 * @addr: new address
2470 * Adds it to unused receive address register or goes into promiscuous mode.
2472 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2474 u32 rar_entries = hw->mac.num_rar_entries;
2477 DEBUGFUNC("ixgbe_add_uc_addr");
2479 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2480 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2483 * Place this address in the RAR if there is room,
2484 * else put the controller into promiscuous mode
2486 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2487 rar = hw->addr_ctrl.rar_used_count;
2488 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2489 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2490 hw->addr_ctrl.rar_used_count++;
2492 hw->addr_ctrl.overflow_promisc++;
2495 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2499 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2500 * @hw: pointer to hardware structure
2501 * @addr_list: the list of new addresses
2502 * @addr_count: number of addresses
2503 * @next: iterator function to walk the address list
2505 * The given list replaces any existing list. Clears the secondary addrs from
2506 * receive address registers. Uses unused receive address registers for the
2507 * first secondary addresses, and falls back to promiscuous mode as needed.
2509 * Drivers using secondary unicast addresses must set user_set_promisc when
2510 * manually putting the device into promiscuous mode.
2512 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2513 u32 addr_count, ixgbe_mc_addr_itr next)
2517 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2522 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2525 * Clear accounting of old secondary address list,
2526 * don't count RAR[0]
2528 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2529 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2530 hw->addr_ctrl.overflow_promisc = 0;
2532 /* Zero out the other receive addresses */
2533 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2534 for (i = 0; i < uc_addr_in_use; i++) {
2535 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2536 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2539 /* Add the new addresses */
2540 for (i = 0; i < addr_count; i++) {
2541 DEBUGOUT(" Adding the secondary addresses:\n");
2542 addr = next(hw, &addr_list, &vmdq);
2543 ixgbe_add_uc_addr(hw, addr, vmdq);
2546 if (hw->addr_ctrl.overflow_promisc) {
2547 /* enable promisc if not already in overflow or set by user */
2548 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2549 DEBUGOUT(" Entering address overflow promisc mode\n");
2550 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2551 fctrl |= IXGBE_FCTRL_UPE;
2552 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2555 /* only disable if set by overflow, not by user */
2556 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2557 DEBUGOUT(" Leaving address overflow promisc mode\n");
2558 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2559 fctrl &= ~IXGBE_FCTRL_UPE;
2560 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2564 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2565 return IXGBE_SUCCESS;
2569 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2570 * @hw: pointer to hardware structure
2571 * @mc_addr: the multicast address
2573 * Extracts the 12 bits, from a multicast address, to determine which
2574 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2575 * incoming rx multicast addresses, to determine the bit-vector to check in
2576 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2577 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2578 * to mc_filter_type.
2580 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2584 DEBUGFUNC("ixgbe_mta_vector");
2586 switch (hw->mac.mc_filter_type) {
2587 case 0: /* use bits [47:36] of the address */
2588 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2590 case 1: /* use bits [46:35] of the address */
2591 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2593 case 2: /* use bits [45:34] of the address */
2594 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2596 case 3: /* use bits [43:32] of the address */
2597 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2599 default: /* Invalid mc_filter_type */
2600 DEBUGOUT("MC filter type param set incorrectly\n");
2605 /* vector can only be 12-bits or boundary will be exceeded */
2611 * ixgbe_set_mta - Set bit-vector in multicast table
2612 * @hw: pointer to hardware structure
2613 * @hash_value: Multicast address hash value
2615 * Sets the bit-vector in the multicast table.
2617 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2623 DEBUGFUNC("ixgbe_set_mta");
2625 hw->addr_ctrl.mta_in_use++;
2627 vector = ixgbe_mta_vector(hw, mc_addr);
2628 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2631 * The MTA is a register array of 128 32-bit registers. It is treated
2632 * like an array of 4096 bits. We want to set bit
2633 * BitArray[vector_value]. So we figure out what register the bit is
2634 * in, read it, OR in the new bit, then write back the new value. The
2635 * register is determined by the upper 7 bits of the vector value and
2636 * the bit within that register are determined by the lower 5 bits of
2639 vector_reg = (vector >> 5) & 0x7F;
2640 vector_bit = vector & 0x1F;
2641 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2645 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2646 * @hw: pointer to hardware structure
2647 * @mc_addr_list: the list of new multicast addresses
2648 * @mc_addr_count: number of addresses
2649 * @next: iterator function to walk the multicast address list
2650 * @clear: flag, when set clears the table beforehand
2652 * When the clear flag is set, the given list replaces any existing list.
2653 * Hashes the given addresses into the multicast table.
2655 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2656 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2662 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2665 * Set the new number of MC addresses that we are being requested to
2668 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2669 hw->addr_ctrl.mta_in_use = 0;
2671 /* Clear mta_shadow */
2673 DEBUGOUT(" Clearing MTA\n");
2674 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2677 /* Update mta_shadow */
2678 for (i = 0; i < mc_addr_count; i++) {
2679 DEBUGOUT(" Adding the multicast addresses:\n");
2680 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2684 for (i = 0; i < hw->mac.mcft_size; i++)
2685 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2686 hw->mac.mta_shadow[i]);
2688 if (hw->addr_ctrl.mta_in_use > 0)
2689 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2690 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2692 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2693 return IXGBE_SUCCESS;
2697 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2698 * @hw: pointer to hardware structure
2700 * Enables multicast address in RAR and the use of the multicast hash table.
2702 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2704 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2706 DEBUGFUNC("ixgbe_enable_mc_generic");
2708 if (a->mta_in_use > 0)
2709 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2710 hw->mac.mc_filter_type);
2712 return IXGBE_SUCCESS;
2716 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2717 * @hw: pointer to hardware structure
2719 * Disables multicast address in RAR and the use of the multicast hash table.
2721 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2723 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2725 DEBUGFUNC("ixgbe_disable_mc_generic");
2727 if (a->mta_in_use > 0)
2728 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2730 return IXGBE_SUCCESS;
2734 * ixgbe_fc_enable_generic - Enable flow control
2735 * @hw: pointer to hardware structure
2737 * Enable flow control according to the current settings.
2739 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2741 s32 ret_val = IXGBE_SUCCESS;
2742 u32 mflcn_reg, fccfg_reg;
2747 DEBUGFUNC("ixgbe_fc_enable_generic");
2749 /* Validate the water mark configuration */
2750 if (!hw->fc.pause_time) {
2751 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2755 /* Low water mark of zero causes XOFF floods */
2756 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2757 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2758 hw->fc.high_water[i]) {
2759 if (!hw->fc.low_water[i] ||
2760 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2761 DEBUGOUT("Invalid water mark configuration\n");
2762 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2768 /* Negotiate the fc mode to use */
2769 hw->mac.ops.fc_autoneg(hw);
2771 /* Disable any previous flow control settings */
2772 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2773 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2775 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2776 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2779 * The possible values of fc.current_mode are:
2780 * 0: Flow control is completely disabled
2781 * 1: Rx flow control is enabled (we can receive pause frames,
2782 * but not send pause frames).
2783 * 2: Tx flow control is enabled (we can send pause frames but
2784 * we do not support receiving pause frames).
2785 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2788 switch (hw->fc.current_mode) {
2791 * Flow control is disabled by software override or autoneg.
2792 * The code below will actually disable it in the HW.
2795 case ixgbe_fc_rx_pause:
2797 * Rx Flow control is enabled and Tx Flow control is
2798 * disabled by software override. Since there really
2799 * isn't a way to advertise that we are capable of RX
2800 * Pause ONLY, we will advertise that we support both
2801 * symmetric and asymmetric Rx PAUSE. Later, we will
2802 * disable the adapter's ability to send PAUSE frames.
2804 mflcn_reg |= IXGBE_MFLCN_RFCE;
2806 case ixgbe_fc_tx_pause:
2808 * Tx Flow control is enabled, and Rx Flow control is
2809 * disabled by software override.
2811 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2814 /* Flow control (both Rx and Tx) is enabled by SW override. */
2815 mflcn_reg |= IXGBE_MFLCN_RFCE;
2816 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2819 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2820 "Flow control param set incorrectly\n");
2821 ret_val = IXGBE_ERR_CONFIG;
2826 /* Set 802.3x based flow control settings. */
2827 mflcn_reg |= IXGBE_MFLCN_DPF;
2828 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2829 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2832 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2833 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2834 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2835 hw->fc.high_water[i]) {
2836 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2837 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2838 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2840 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2842 * In order to prevent Tx hangs when the internal Tx
2843 * switch is enabled we must set the high water mark
2844 * to the Rx packet buffer size - 24KB. This allows
2845 * the Tx switch to function even under heavy Rx
2848 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2851 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2854 /* Configure pause time (2 TCs per register) */
2855 reg = hw->fc.pause_time * 0x00010001;
2856 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2857 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2859 /* Configure flow control refresh threshold value */
2860 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2867 * ixgbe_negotiate_fc - Negotiate flow control
2868 * @hw: pointer to hardware structure
2869 * @adv_reg: flow control advertised settings
2870 * @lp_reg: link partner's flow control settings
2871 * @adv_sym: symmetric pause bit in advertisement
2872 * @adv_asm: asymmetric pause bit in advertisement
2873 * @lp_sym: symmetric pause bit in link partner advertisement
2874 * @lp_asm: asymmetric pause bit in link partner advertisement
2876 * Find the intersection between advertised settings and link partner's
2877 * advertised settings
2879 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2880 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2882 if ((!(adv_reg)) || (!(lp_reg))) {
2883 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
2884 "Local or link partner's advertised flow control "
2885 "settings are NULL. Local: %x, link partner: %x\n",
2887 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2890 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2892 * Now we need to check if the user selected Rx ONLY
2893 * of pause frames. In this case, we had to advertise
2894 * FULL flow control because we could not advertise RX
2895 * ONLY. Hence, we must now check to see if we need to
2896 * turn OFF the TRANSMISSION of PAUSE frames.
2898 if (hw->fc.requested_mode == ixgbe_fc_full) {
2899 hw->fc.current_mode = ixgbe_fc_full;
2900 DEBUGOUT("Flow Control = FULL.\n");
2902 hw->fc.current_mode = ixgbe_fc_rx_pause;
2903 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2905 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2906 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2907 hw->fc.current_mode = ixgbe_fc_tx_pause;
2908 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2909 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2910 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2911 hw->fc.current_mode = ixgbe_fc_rx_pause;
2912 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2914 hw->fc.current_mode = ixgbe_fc_none;
2915 DEBUGOUT("Flow Control = NONE.\n");
2917 return IXGBE_SUCCESS;
2921 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2922 * @hw: pointer to hardware structure
2924 * Enable flow control according on 1 gig fiber.
2926 STATIC s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2928 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2929 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2932 * On multispeed fiber at 1g, bail out if
2933 * - link is up but AN did not complete, or if
2934 * - link is up and AN completed but timed out
2937 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2938 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2939 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
2940 DEBUGOUT("Auto-Negotiation did not complete or timed out\n");
2944 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2945 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2947 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2948 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2949 IXGBE_PCS1GANA_ASM_PAUSE,
2950 IXGBE_PCS1GANA_SYM_PAUSE,
2951 IXGBE_PCS1GANA_ASM_PAUSE);
2958 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2959 * @hw: pointer to hardware structure
2961 * Enable flow control according to IEEE clause 37.
2963 STATIC s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2965 u32 links2, anlp1_reg, autoc_reg, links;
2966 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2969 * On backplane, bail out if
2970 * - backplane autoneg was not completed, or if
2971 * - we are 82599 and link partner is not AN enabled
2973 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2974 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
2975 DEBUGOUT("Auto-Negotiation did not complete\n");
2979 if (hw->mac.type == ixgbe_mac_82599EB) {
2980 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2981 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
2982 DEBUGOUT("Link partner is not AN enabled\n");
2987 * Read the 10g AN autoc and LP ability registers and resolve
2988 * local flow control settings accordingly
2990 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2991 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2993 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2994 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2995 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
3002 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
3003 * @hw: pointer to hardware structure
3005 * Enable flow control according to IEEE clause 37.
3007 STATIC s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
3009 u16 technology_ability_reg = 0;
3010 u16 lp_technology_ability_reg = 0;
3012 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
3013 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3014 &technology_ability_reg);
3015 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
3016 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3017 &lp_technology_ability_reg);
3019 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
3020 (u32)lp_technology_ability_reg,
3021 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
3022 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
3026 * ixgbe_fc_autoneg - Configure flow control
3027 * @hw: pointer to hardware structure
3029 * Compares our advertised flow control capabilities to those advertised by
3030 * our link partner, and determines the proper flow control mode to use.
3032 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
3034 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3035 ixgbe_link_speed speed;
3038 DEBUGFUNC("ixgbe_fc_autoneg");
3041 * AN should have completed when the cable was plugged in.
3042 * Look for reasons to bail out. Bail out if:
3043 * - FC autoneg is disabled, or if
3046 if (hw->fc.disable_fc_autoneg) {
3047 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3048 "Flow control autoneg is disabled");
3052 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3054 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3058 switch (hw->phy.media_type) {
3059 /* Autoneg flow control on fiber adapters */
3060 case ixgbe_media_type_fiber_qsfp:
3061 case ixgbe_media_type_fiber:
3062 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
3063 ret_val = ixgbe_fc_autoneg_fiber(hw);
3066 /* Autoneg flow control on backplane adapters */
3067 case ixgbe_media_type_backplane:
3068 ret_val = ixgbe_fc_autoneg_backplane(hw);
3071 /* Autoneg flow control on copper adapters */
3072 case ixgbe_media_type_copper:
3073 if (ixgbe_device_supports_autoneg_fc(hw))
3074 ret_val = ixgbe_fc_autoneg_copper(hw);
3082 if (ret_val == IXGBE_SUCCESS) {
3083 hw->fc.fc_was_autonegged = true;
3085 hw->fc.fc_was_autonegged = false;
3086 hw->fc.current_mode = hw->fc.requested_mode;
3091 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3092 * @hw: pointer to hardware structure
3094 * System-wide timeout range is encoded in PCIe Device Control2 register.
3096 * Add 10% to specified maximum and return the number of times to poll for
3097 * completion timeout, in units of 100 microsec. Never return less than
3098 * 800 = 80 millisec.
3100 STATIC u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3105 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3106 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
3109 case IXGBE_PCIDEVCTRL2_65_130ms:
3110 pollcnt = 1300; /* 130 millisec */
3112 case IXGBE_PCIDEVCTRL2_260_520ms:
3113 pollcnt = 5200; /* 520 millisec */
3115 case IXGBE_PCIDEVCTRL2_1_2s:
3116 pollcnt = 20000; /* 2 sec */
3118 case IXGBE_PCIDEVCTRL2_4_8s:
3119 pollcnt = 80000; /* 8 sec */
3121 case IXGBE_PCIDEVCTRL2_17_34s:
3122 pollcnt = 34000; /* 34 sec */
3124 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
3125 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
3126 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
3127 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
3129 pollcnt = 800; /* 80 millisec minimum */
3133 /* add 10% to spec maximum */
3134 return (pollcnt * 11) / 10;
3138 * ixgbe_disable_pcie_master - Disable PCI-express master access
3139 * @hw: pointer to hardware structure
3141 * Disables PCI-Express master access and verifies there are no pending
3142 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
3143 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
3144 * is returned signifying master requests disabled.
3146 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
3148 s32 status = IXGBE_SUCCESS;
3152 DEBUGFUNC("ixgbe_disable_pcie_master");
3154 /* Always set this bit to ensure any future transactions are blocked */
3155 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3157 /* Exit if master requests are blocked */
3158 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3159 IXGBE_REMOVED(hw->hw_addr))
3162 /* Poll for master request bit to clear */
3163 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
3165 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3170 * Two consecutive resets are required via CTRL.RST per datasheet
3171 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
3172 * of this need. The first reset prevents new master requests from
3173 * being issued by our device. We then must wait 1usec or more for any
3174 * remaining completions from the PCIe bus to trickle in, and then reset
3175 * again to clear out any effects they may have had on our device.
3177 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
3178 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3180 if (hw->mac.type >= ixgbe_mac_X550)
3184 * Before proceeding, make sure that the PCIe block does not have
3185 * transactions pending.
3187 poll = ixgbe_pcie_timeout_poll(hw);
3188 for (i = 0; i < poll; i++) {
3190 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3191 if (IXGBE_REMOVED(hw->hw_addr))
3193 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3197 ERROR_REPORT1(IXGBE_ERROR_POLLING,
3198 "PCIe transaction pending bit also did not clear.\n");
3199 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
3206 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3207 * @hw: pointer to hardware structure
3208 * @mask: Mask to specify which semaphore to acquire
3210 * Acquires the SWFW semaphore through the GSSR register for the specified
3211 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3213 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3217 u32 fwmask = mask << 5;
3221 DEBUGFUNC("ixgbe_acquire_swfw_sync");
3223 for (i = 0; i < timeout; i++) {
3225 * SW NVM semaphore bit is used for access to all
3226 * SW_FW_SYNC bits (not just NVM)
3228 if (ixgbe_get_eeprom_semaphore(hw))
3229 return IXGBE_ERR_SWFW_SYNC;
3231 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3232 if (!(gssr & (fwmask | swmask))) {
3234 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3235 ixgbe_release_eeprom_semaphore(hw);
3236 return IXGBE_SUCCESS;
3238 /* Resource is currently in use by FW or SW */
3239 ixgbe_release_eeprom_semaphore(hw);
3244 /* If time expired clear the bits holding the lock and retry */
3245 if (gssr & (fwmask | swmask))
3246 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
3249 return IXGBE_ERR_SWFW_SYNC;
3253 * ixgbe_release_swfw_sync - Release SWFW semaphore
3254 * @hw: pointer to hardware structure
3255 * @mask: Mask to specify which semaphore to release
3257 * Releases the SWFW semaphore through the GSSR register for the specified
3258 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3260 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3265 DEBUGFUNC("ixgbe_release_swfw_sync");
3267 ixgbe_get_eeprom_semaphore(hw);
3269 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3271 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3273 ixgbe_release_eeprom_semaphore(hw);
3277 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3278 * @hw: pointer to hardware structure
3280 * Stops the receive data path and waits for the HW to internally empty
3281 * the Rx security block
3283 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3285 #define IXGBE_MAX_SECRX_POLL 40
3290 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
3293 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3294 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
3295 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3296 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
3297 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3298 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
3301 /* Use interrupt-safe sleep just in case */
3305 /* For informational purposes only */
3306 if (i >= IXGBE_MAX_SECRX_POLL)
3307 DEBUGOUT("Rx unit being enabled before security "
3308 "path fully disabled. Continuing with init.\n");
3310 return IXGBE_SUCCESS;
3314 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3315 * @hw: pointer to hardware structure
3316 * @reg_val: Value we read from AUTOC
3318 * The default case requires no protection so just to the register read.
3320 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3323 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3324 return IXGBE_SUCCESS;
3328 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
3329 * @hw: pointer to hardware structure
3330 * @reg_val: value to write to AUTOC
3331 * @locked: bool to indicate whether the SW/FW lock was already taken by
3334 * The default case requires no protection so just to the register write.
3336 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
3338 UNREFERENCED_1PARAMETER(locked);
3340 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
3341 return IXGBE_SUCCESS;
3345 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3346 * @hw: pointer to hardware structure
3348 * Enables the receive data path.
3350 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3354 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
3356 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3357 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
3358 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3359 IXGBE_WRITE_FLUSH(hw);
3361 return IXGBE_SUCCESS;
3365 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3366 * @hw: pointer to hardware structure
3367 * @regval: register value to write to RXCTRL
3369 * Enables the Rx DMA unit
3371 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3373 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
3375 if (regval & IXGBE_RXCTRL_RXEN)
3376 ixgbe_enable_rx(hw);
3378 ixgbe_disable_rx(hw);
3380 return IXGBE_SUCCESS;
3384 * ixgbe_blink_led_start_generic - Blink LED based on index.
3385 * @hw: pointer to hardware structure
3386 * @index: led number to blink
3388 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3390 ixgbe_link_speed speed = 0;
3393 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3394 s32 ret_val = IXGBE_SUCCESS;
3395 bool locked = false;
3397 DEBUGFUNC("ixgbe_blink_led_start_generic");
3400 return IXGBE_ERR_PARAM;
3403 * Link must be up to auto-blink the LEDs;
3404 * Force it if link is down.
3406 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3409 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3410 if (ret_val != IXGBE_SUCCESS)
3413 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3414 autoc_reg |= IXGBE_AUTOC_FLU;
3416 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3417 if (ret_val != IXGBE_SUCCESS)
3420 IXGBE_WRITE_FLUSH(hw);
3424 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3425 led_reg |= IXGBE_LED_BLINK(index);
3426 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3427 IXGBE_WRITE_FLUSH(hw);
3434 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3435 * @hw: pointer to hardware structure
3436 * @index: led number to stop blinking
3438 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3441 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3442 s32 ret_val = IXGBE_SUCCESS;
3443 bool locked = false;
3445 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3448 return IXGBE_ERR_PARAM;
3451 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3452 if (ret_val != IXGBE_SUCCESS)
3455 autoc_reg &= ~IXGBE_AUTOC_FLU;
3456 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3458 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3459 if (ret_val != IXGBE_SUCCESS)
3462 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3463 led_reg &= ~IXGBE_LED_BLINK(index);
3464 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3465 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3466 IXGBE_WRITE_FLUSH(hw);
3473 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3474 * @hw: pointer to hardware structure
3475 * @san_mac_offset: SAN MAC address offset
3477 * This function will read the EEPROM location for the SAN MAC address
3478 * pointer, and returns the value at that location. This is used in both
3479 * get and set mac_addr routines.
3481 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3482 u16 *san_mac_offset)
3486 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3489 * First read the EEPROM pointer to see if the MAC addresses are
3492 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3495 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3496 "eeprom at offset %d failed",
3497 IXGBE_SAN_MAC_ADDR_PTR);
3504 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3505 * @hw: pointer to hardware structure
3506 * @san_mac_addr: SAN MAC address
3508 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3509 * per-port, so set_lan_id() must be called before reading the addresses.
3510 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3511 * upon for non-SFP connections, so we must call it here.
3513 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3515 u16 san_mac_data, san_mac_offset;
3519 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3522 * First read the EEPROM pointer to see if the MAC addresses are
3523 * available. If they're not, no point in calling set_lan_id() here.
3525 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3526 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3527 goto san_mac_addr_out;
3529 /* make sure we know which port we need to program */
3530 hw->mac.ops.set_lan_id(hw);
3531 /* apply the port offset to the address offset */
3532 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3533 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3534 for (i = 0; i < 3; i++) {
3535 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3538 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3539 "eeprom read at offset %d failed",
3541 goto san_mac_addr_out;
3543 san_mac_addr[i * 2] = (u8)(san_mac_data);
3544 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3547 return IXGBE_SUCCESS;
3551 * No addresses available in this EEPROM. It's not an
3552 * error though, so just wipe the local address and return.
3554 for (i = 0; i < 6; i++)
3555 san_mac_addr[i] = 0xFF;
3556 return IXGBE_SUCCESS;
3560 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3561 * @hw: pointer to hardware structure
3562 * @san_mac_addr: SAN MAC address
3564 * Write a SAN MAC address to the EEPROM.
3566 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3569 u16 san_mac_data, san_mac_offset;
3572 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3574 /* Look for SAN mac address pointer. If not defined, return */
3575 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3576 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3577 return IXGBE_ERR_NO_SAN_ADDR_PTR;
3579 /* Make sure we know which port we need to write */
3580 hw->mac.ops.set_lan_id(hw);
3581 /* Apply the port offset to the address offset */
3582 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3583 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3585 for (i = 0; i < 3; i++) {
3586 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3587 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3588 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3592 return IXGBE_SUCCESS;
3596 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3597 * @hw: pointer to hardware structure
3599 * Read PCIe configuration space, and get the MSI-X vector count from
3600 * the capabilities table.
3602 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3608 switch (hw->mac.type) {
3609 case ixgbe_mac_82598EB:
3610 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3611 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3613 case ixgbe_mac_82599EB:
3614 case ixgbe_mac_X540:
3615 case ixgbe_mac_X550:
3616 case ixgbe_mac_X550EM_x:
3617 case ixgbe_mac_X550EM_a:
3618 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3619 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3625 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3626 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3627 if (IXGBE_REMOVED(hw->hw_addr))
3629 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3631 /* MSI-X count is zero-based in HW */
3634 if (msix_count > max_msix_count)
3635 msix_count = max_msix_count;
3641 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3642 * @hw: pointer to hardware structure
3643 * @addr: Address to put into receive address register
3644 * @vmdq: VMDq pool to assign
3646 * Puts an ethernet address into a receive address register, or
3647 * finds the rar that it is aleady in; adds to the pool list
3649 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3651 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3652 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3654 u32 rar_low, rar_high;
3655 u32 addr_low, addr_high;
3657 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3659 /* swap bytes for HW little endian */
3660 addr_low = addr[0] | (addr[1] << 8)
3663 addr_high = addr[4] | (addr[5] << 8);
3666 * Either find the mac_id in rar or find the first empty space.
3667 * rar_highwater points to just after the highest currently used
3668 * rar in order to shorten the search. It grows when we add a new
3671 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3672 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3674 if (((IXGBE_RAH_AV & rar_high) == 0)
3675 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3676 first_empty_rar = rar;
3677 } else if ((rar_high & 0xFFFF) == addr_high) {
3678 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3679 if (rar_low == addr_low)
3680 break; /* found it already in the rars */
3684 if (rar < hw->mac.rar_highwater) {
3685 /* already there so just add to the pool bits */
3686 ixgbe_set_vmdq(hw, rar, vmdq);
3687 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3688 /* stick it into first empty RAR slot we found */
3689 rar = first_empty_rar;
3690 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3691 } else if (rar == hw->mac.rar_highwater) {
3692 /* add it to the top of the list and inc the highwater mark */
3693 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3694 hw->mac.rar_highwater++;
3695 } else if (rar >= hw->mac.num_rar_entries) {
3696 return IXGBE_ERR_INVALID_MAC_ADDR;
3700 * If we found rar[0], make sure the default pool bit (we use pool 0)
3701 * remains cleared to be sure default pool packets will get delivered
3704 ixgbe_clear_vmdq(hw, rar, 0);
3710 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3711 * @hw: pointer to hardware struct
3712 * @rar: receive address register index to disassociate
3713 * @vmdq: VMDq pool index to remove from the rar
3715 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3717 u32 mpsar_lo, mpsar_hi;
3718 u32 rar_entries = hw->mac.num_rar_entries;
3720 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3722 /* Make sure we are using a valid rar index range */
3723 if (rar >= rar_entries) {
3724 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3725 "RAR index %d is out of range.\n", rar);
3726 return IXGBE_ERR_INVALID_ARGUMENT;
3729 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3730 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3732 if (IXGBE_REMOVED(hw->hw_addr))
3735 if (!mpsar_lo && !mpsar_hi)
3738 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3740 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3744 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3747 } else if (vmdq < 32) {
3748 mpsar_lo &= ~(1 << vmdq);
3749 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3751 mpsar_hi &= ~(1 << (vmdq - 32));
3752 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3755 /* was that the last pool using this rar? */
3756 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
3757 hw->mac.ops.clear_rar(hw, rar);
3759 return IXGBE_SUCCESS;
3763 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3764 * @hw: pointer to hardware struct
3765 * @rar: receive address register index to associate with a VMDq index
3766 * @vmdq: VMDq pool index
3768 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3771 u32 rar_entries = hw->mac.num_rar_entries;
3773 DEBUGFUNC("ixgbe_set_vmdq_generic");
3775 /* Make sure we are using a valid rar index range */
3776 if (rar >= rar_entries) {
3777 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3778 "RAR index %d is out of range.\n", rar);
3779 return IXGBE_ERR_INVALID_ARGUMENT;
3783 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3785 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3787 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3788 mpsar |= 1 << (vmdq - 32);
3789 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3791 return IXGBE_SUCCESS;
3795 * This function should only be involved in the IOV mode.
3796 * In IOV mode, Default pool is next pool after the number of
3797 * VFs advertized and not 0.
3798 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3800 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3801 * @hw: pointer to hardware struct
3802 * @vmdq: VMDq pool index
3804 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3806 u32 rar = hw->mac.san_mac_rar_index;
3808 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3811 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3812 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3814 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3815 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3818 return IXGBE_SUCCESS;
3822 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3823 * @hw: pointer to hardware structure
3825 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3829 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3830 DEBUGOUT(" Clearing UTA\n");
3832 for (i = 0; i < 128; i++)
3833 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3835 return IXGBE_SUCCESS;
3839 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3840 * @hw: pointer to hardware structure
3841 * @vlan: VLAN id to write to VLAN filter
3843 * return the VLVF index where this VLAN id should be placed
3846 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)
3848 s32 regindex, first_empty_slot;
3851 /* short cut the special case */
3855 /* if vlvf_bypass is set we don't want to use an empty slot, we
3856 * will simply bypass the VLVF if there are no entries present in the
3857 * VLVF that contain our VLAN
3859 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0;
3861 /* add VLAN enable bit for comparison */
3862 vlan |= IXGBE_VLVF_VIEN;
3864 /* Search for the vlan id in the VLVF entries. Save off the first empty
3865 * slot found along the way.
3867 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1
3869 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) {
3870 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3873 if (!first_empty_slot && !bits)
3874 first_empty_slot = regindex;
3877 /* If we are here then we didn't find the VLAN. Return first empty
3878 * slot we found during our search, else error.
3880 if (!first_empty_slot)
3881 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "No space in VLVF.\n");
3883 return first_empty_slot ? first_empty_slot : IXGBE_ERR_NO_SPACE;
3887 * ixgbe_set_vfta_generic - Set VLAN filter table
3888 * @hw: pointer to hardware structure
3889 * @vlan: VLAN id to write to VLAN filter
3890 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
3891 * @vlan_on: boolean flag to turn on/off VLAN
3892 * @vlvf_bypass: boolean flag indicating updating default pool is okay
3894 * Turn on/off specified VLAN in the VLAN filter table.
3896 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3897 bool vlan_on, bool vlvf_bypass)
3899 u32 regidx, vfta_delta, vfta;
3902 DEBUGFUNC("ixgbe_set_vfta_generic");
3904 if (vlan > 4095 || vind > 63)
3905 return IXGBE_ERR_PARAM;
3908 * this is a 2 part operation - first the VFTA, then the
3909 * VLVF and VLVFB if VT Mode is set
3910 * We don't write the VFTA until we know the VLVF part succeeded.
3914 * The VFTA is a bitstring made up of 128 32-bit registers
3915 * that enable the particular VLAN id, much like the MTA:
3916 * bits[11-5]: which register
3917 * bits[4-0]: which bit in the register
3920 vfta_delta = 1 << (vlan % 32);
3921 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx));
3923 /* vfta_delta represents the difference between the current value
3924 * of vfta and the value we want in the register. Since the diff
3925 * is an XOR mask we can just update the vfta using an XOR
3927 vfta_delta &= vlan_on ? ~vfta : vfta;
3931 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
3933 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta,
3935 if (ret_val != IXGBE_SUCCESS) {
3942 /* Update VFTA now that we are ready for traffic */
3944 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta);
3946 return IXGBE_SUCCESS;
3950 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
3951 * @hw: pointer to hardware structure
3952 * @vlan: VLAN id to write to VLAN filter
3953 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
3954 * @vlan_on: boolean flag to turn on/off VLAN in VLVF
3955 * @vfta_delta: pointer to the difference between the current value of VFTA
3956 * and the desired value
3957 * @vfta: the desired value of the VFTA
3958 * @vlvf_bypass: boolean flag indicating updating default pool is okay
3960 * Turn on/off specified bit in VLVF table.
3962 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3963 bool vlan_on, u32 *vfta_delta, u32 vfta,
3969 DEBUGFUNC("ixgbe_set_vlvf_generic");
3971 if (vlan > 4095 || vind > 63)
3972 return IXGBE_ERR_PARAM;
3974 /* If VT Mode is set
3976 * make sure the vlan is in VLVF
3977 * set the vind bit in the matching VLVFB
3979 * clear the pool bit and possibly the vind
3981 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE))
3982 return IXGBE_SUCCESS;
3983 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
3987 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32));
3989 /* set the pool bit */
3990 bits |= 1 << (vind % 32);
3994 /* clear the pool bit */
3995 bits ^= 1 << (vind % 32);
3998 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) {
3999 /* Clear VFTA first, then disable VLVF. Otherwise
4000 * we run the risk of stray packets leaking into
4001 * the PF via the default pool
4004 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta);
4006 /* disable VLVF and clear remaining bit from pool */
4007 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
4008 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0);
4010 return IXGBE_SUCCESS;
4012 /* If there are still bits set in the VLVFB registers
4013 * for the VLAN ID indicated we need to see if the
4014 * caller is requesting that we clear the VFTA entry bit.
4015 * If the caller has requested that we clear the VFTA
4016 * entry bit but there are still pools/VFs using this VLAN
4017 * ID entry then ignore the request. We're not worried
4018 * about the case where we're turning the VFTA VLAN ID
4019 * entry bit on, only when requested to turn it off as
4020 * there may be multiple pools and/or VFs using the
4021 * VLAN ID entry. In that case we cannot clear the
4022 * VFTA bit until all pools/VFs using that VLAN ID have also
4023 * been cleared. This will be indicated by "bits" being
4029 /* record pool change and enable VLAN ID if not already enabled */
4030 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits);
4031 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan);
4033 return IXGBE_SUCCESS;
4037 * ixgbe_clear_vfta_generic - Clear VLAN filter table
4038 * @hw: pointer to hardware structure
4040 * Clears the VLAN filer table, and the VMDq index associated with the filter
4042 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
4046 DEBUGFUNC("ixgbe_clear_vfta_generic");
4048 for (offset = 0; offset < hw->mac.vft_size; offset++)
4049 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
4051 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
4052 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
4053 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
4054 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0);
4057 return IXGBE_SUCCESS;
4061 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
4062 * @hw: pointer to hardware structure
4064 * Contains the logic to identify if we need to verify link for the
4067 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw)
4070 /* Does FW say we need the fix */
4071 if (!hw->need_crosstalk_fix)
4074 /* Only consider SFP+ PHYs i.e. media type fiber */
4075 switch (hw->mac.ops.get_media_type(hw)) {
4076 case ixgbe_media_type_fiber:
4077 case ixgbe_media_type_fiber_qsfp:
4087 * ixgbe_check_mac_link_generic - Determine link and speed status
4088 * @hw: pointer to hardware structure
4089 * @speed: pointer to link speed
4090 * @link_up: true when link is up
4091 * @link_up_wait_to_complete: bool used to wait for link up or not
4093 * Reads the links register to determine if link is up and the current speed
4095 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4096 bool *link_up, bool link_up_wait_to_complete)
4098 u32 links_reg, links_orig;
4101 DEBUGFUNC("ixgbe_check_mac_link_generic");
4103 /* If Crosstalk fix enabled do the sanity check of making sure
4104 * the SFP+ cage is full.
4106 if (ixgbe_need_crosstalk_fix(hw)) {
4109 switch (hw->mac.type) {
4110 case ixgbe_mac_82599EB:
4111 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4114 case ixgbe_mac_X550EM_x:
4115 case ixgbe_mac_X550EM_a:
4116 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4120 /* sanity check - No SFP+ devices here */
4121 sfp_cage_full = false;
4125 if (!sfp_cage_full) {
4127 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4128 return IXGBE_SUCCESS;
4132 /* clear the old state */
4133 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
4135 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4137 if (links_orig != links_reg) {
4138 DEBUGOUT2("LINKS changed from %08X to %08X\n",
4139 links_orig, links_reg);
4142 if (link_up_wait_to_complete) {
4143 for (i = 0; i < hw->mac.max_link_up_time; i++) {
4144 if (links_reg & IXGBE_LINKS_UP) {
4151 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4154 if (links_reg & IXGBE_LINKS_UP)
4160 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4161 case IXGBE_LINKS_SPEED_10G_82599:
4162 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4163 if (hw->mac.type >= ixgbe_mac_X550) {
4164 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4165 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4168 case IXGBE_LINKS_SPEED_1G_82599:
4169 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4171 case IXGBE_LINKS_SPEED_100_82599:
4172 *speed = IXGBE_LINK_SPEED_100_FULL;
4173 if (hw->mac.type >= ixgbe_mac_X550) {
4174 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4175 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4178 case IXGBE_LINKS_SPEED_10_X550EM_A:
4179 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4180 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4181 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
4182 *speed = IXGBE_LINK_SPEED_10_FULL;
4186 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4189 return IXGBE_SUCCESS;
4193 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4195 * @hw: pointer to hardware structure
4196 * @wwnn_prefix: the alternative WWNN prefix
4197 * @wwpn_prefix: the alternative WWPN prefix
4199 * This function will read the EEPROM from the alternative SAN MAC address
4200 * block to check the support for the alternative WWNN/WWPN prefix support.
4202 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4206 u16 alt_san_mac_blk_offset;
4208 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
4210 /* clear output first */
4211 *wwnn_prefix = 0xFFFF;
4212 *wwpn_prefix = 0xFFFF;
4214 /* check if alternative SAN MAC is supported */
4215 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
4216 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4217 goto wwn_prefix_err;
4219 if ((alt_san_mac_blk_offset == 0) ||
4220 (alt_san_mac_blk_offset == 0xFFFF))
4221 goto wwn_prefix_out;
4223 /* check capability in alternative san mac address block */
4224 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
4225 if (hw->eeprom.ops.read(hw, offset, &caps))
4226 goto wwn_prefix_err;
4227 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
4228 goto wwn_prefix_out;
4230 /* get the corresponding prefix for WWNN/WWPN */
4231 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
4232 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4233 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4234 "eeprom read at offset %d failed", offset);
4237 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
4238 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4239 goto wwn_prefix_err;
4242 return IXGBE_SUCCESS;
4245 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4246 "eeprom read at offset %d failed", offset);
4247 return IXGBE_SUCCESS;
4251 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4252 * @hw: pointer to hardware structure
4253 * @bs: the fcoe boot status
4255 * This function will read the FCOE boot status from the iSCSI FCOE block
4257 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4259 u16 offset, caps, flags;
4262 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
4264 /* clear output first */
4265 *bs = ixgbe_fcoe_bootstatus_unavailable;
4267 /* check if FCOE IBA block is present */
4268 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
4269 status = hw->eeprom.ops.read(hw, offset, &caps);
4270 if (status != IXGBE_SUCCESS)
4273 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
4276 /* check if iSCSI FCOE block is populated */
4277 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4278 if (status != IXGBE_SUCCESS)
4281 if ((offset == 0) || (offset == 0xFFFF))
4284 /* read fcoe flags in iSCSI FCOE block */
4285 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
4286 status = hw->eeprom.ops.read(hw, offset, &flags);
4287 if (status != IXGBE_SUCCESS)
4290 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
4291 *bs = ixgbe_fcoe_bootstatus_enabled;
4293 *bs = ixgbe_fcoe_bootstatus_disabled;
4300 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4301 * @hw: pointer to hardware structure
4302 * @enable: enable or disable switch for MAC anti-spoofing
4303 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
4306 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4308 int vf_target_reg = vf >> 3;
4309 int vf_target_shift = vf % 8;
4312 if (hw->mac.type == ixgbe_mac_82598EB)
4315 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4317 pfvfspoof |= (1 << vf_target_shift);
4319 pfvfspoof &= ~(1 << vf_target_shift);
4320 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4324 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4325 * @hw: pointer to hardware structure
4326 * @enable: enable or disable switch for VLAN anti-spoofing
4327 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4330 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4332 int vf_target_reg = vf >> 3;
4333 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
4336 if (hw->mac.type == ixgbe_mac_82598EB)
4339 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4341 pfvfspoof |= (1 << vf_target_shift);
4343 pfvfspoof &= ~(1 << vf_target_shift);
4344 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4348 * ixgbe_get_device_caps_generic - Get additional device capabilities
4349 * @hw: pointer to hardware structure
4350 * @device_caps: the EEPROM word with the extra device capabilities
4352 * This function will read the EEPROM location for the device capabilities,
4353 * and return the word through device_caps.
4355 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4357 DEBUGFUNC("ixgbe_get_device_caps_generic");
4359 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4361 return IXGBE_SUCCESS;
4365 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4366 * @hw: pointer to hardware structure
4369 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4374 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
4376 /* Enable relaxed ordering */
4377 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4378 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4379 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4380 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4383 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4384 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4385 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
4386 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4387 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4393 * ixgbe_calculate_checksum - Calculate checksum for buffer
4394 * @buffer: pointer to EEPROM
4395 * @length: size of EEPROM to calculate a checksum for
4396 * Calculates the checksum for some buffer on a specified length. The
4397 * checksum calculated is returned.
4399 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4404 DEBUGFUNC("ixgbe_calculate_checksum");
4409 for (i = 0; i < length; i++)
4412 return (u8) (0 - sum);
4416 * ixgbe_hic_unlocked - Issue command to manageability block unlocked
4417 * @hw: pointer to the HW structure
4418 * @buffer: command to write and where the return status will be placed
4419 * @length: length of buffer, must be multiple of 4 bytes
4420 * @timeout: time in ms to wait for command completion
4422 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4423 * else returns semaphore error when encountering an error acquiring
4424 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4426 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held
4429 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length,
4435 DEBUGFUNC("ixgbe_hic_unlocked");
4437 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4438 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4439 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4442 /* Set bit 9 of FWSTS clearing FW reset indication */
4443 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
4444 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
4446 /* Check that the host interface is enabled. */
4447 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4448 if (!(hicr & IXGBE_HICR_EN)) {
4449 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
4450 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4453 /* Calculate length in DWORDs. We must be DWORD aligned */
4454 if (length % sizeof(u32)) {
4455 DEBUGOUT("Buffer length failure, not aligned to dword");
4456 return IXGBE_ERR_INVALID_ARGUMENT;
4459 dword_len = length >> 2;
4461 /* The device driver writes the relevant command block
4462 * into the ram area.
4464 for (i = 0; i < dword_len; i++)
4465 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4466 i, IXGBE_CPU_TO_LE32(buffer[i]));
4468 /* Setting this bit tells the ARC that a new command is pending. */
4469 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4471 for (i = 0; i < timeout; i++) {
4472 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4473 if (!(hicr & IXGBE_HICR_C))
4478 /* Check command completion */
4479 if ((timeout && i == timeout) ||
4480 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
4481 ERROR_REPORT1(IXGBE_ERROR_CAUTION,
4482 "Command has failed with no status valid.\n");
4483 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4486 return IXGBE_SUCCESS;
4490 * ixgbe_host_interface_command - Issue command to manageability block
4491 * @hw: pointer to the HW structure
4492 * @buffer: contains the command to write and where the return status will
4494 * @length: length of buffer, must be multiple of 4 bytes
4495 * @timeout: time in ms to wait for command completion
4496 * @return_data: read and return data from the buffer (true) or not (false)
4497 * Needed because FW structures are big endian and decoding of
4498 * these fields can be 8 bit or 16 bit based on command. Decoding
4499 * is not easily understood without making a table of commands.
4500 * So we will leave this up to the caller to read back the data
4503 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4504 * else returns semaphore error when encountering an error acquiring
4505 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4507 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4508 u32 length, u32 timeout, bool return_data)
4510 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4516 DEBUGFUNC("ixgbe_host_interface_command");
4518 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4519 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4520 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4523 /* Take management host interface semaphore */
4524 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4528 status = ixgbe_hic_unlocked(hw, buffer, length, timeout);
4535 /* Calculate length in DWORDs */
4536 dword_len = hdr_size >> 2;
4538 /* first pull in the header so we know the buffer length */
4539 for (bi = 0; bi < dword_len; bi++) {
4540 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4541 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4544 /* If there is any thing in data position pull it in */
4545 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
4549 if (length < buf_len + hdr_size) {
4550 DEBUGOUT("Buffer not large enough for reply message.\n");
4551 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4555 /* Calculate length in DWORDs, add 3 for odd lengths */
4556 dword_len = (buf_len + 3) >> 2;
4558 /* Pull in the rest of the buffer (bi is where we left off) */
4559 for (; bi <= dword_len; bi++) {
4560 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4561 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4565 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4571 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4572 * @hw: pointer to the HW structure
4573 * @maj: driver version major number
4574 * @min: driver version minor number
4575 * @build: driver version build number
4576 * @sub: driver version sub build number
4578 * Sends driver version number to firmware through the manageability
4579 * block. On success return IXGBE_SUCCESS
4580 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4581 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4583 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4586 struct ixgbe_hic_drv_info fw_cmd;
4588 s32 ret_val = IXGBE_SUCCESS;
4590 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4592 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4593 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4594 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4595 fw_cmd.port_num = (u8)hw->bus.func;
4596 fw_cmd.ver_maj = maj;
4597 fw_cmd.ver_min = min;
4598 fw_cmd.ver_build = build;
4599 fw_cmd.ver_sub = sub;
4600 fw_cmd.hdr.checksum = 0;
4601 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4602 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4606 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4607 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4609 IXGBE_HI_COMMAND_TIMEOUT,
4611 if (ret_val != IXGBE_SUCCESS)
4614 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4615 FW_CEM_RESP_STATUS_SUCCESS)
4616 ret_val = IXGBE_SUCCESS;
4618 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4627 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4628 * @hw: pointer to hardware structure
4629 * @num_pb: number of packet buffers to allocate
4630 * @headroom: reserve n KB of headroom
4631 * @strategy: packet buffer allocation strategy
4633 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4636 u32 pbsize = hw->mac.rx_pb_size;
4638 u32 rxpktsize, txpktsize, txpbthresh;
4640 /* Reserve headroom */
4646 /* Divide remaining packet buffer space amongst the number of packet
4647 * buffers requested using supplied strategy.
4650 case PBA_STRATEGY_WEIGHTED:
4651 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4652 * buffer with 5/8 of the packet buffer space.
4654 rxpktsize = (pbsize * 5) / (num_pb * 4);
4655 pbsize -= rxpktsize * (num_pb / 2);
4656 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4657 for (; i < (num_pb / 2); i++)
4658 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4659 /* Fall through to configure remaining packet buffers */
4660 case PBA_STRATEGY_EQUAL:
4661 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4662 for (; i < num_pb; i++)
4663 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4669 /* Only support an equally distributed Tx packet buffer strategy. */
4670 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4671 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4672 for (i = 0; i < num_pb; i++) {
4673 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4674 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4677 /* Clear unused TCs, if any, to zero buffer size*/
4678 for (; i < IXGBE_MAX_PB; i++) {
4679 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4680 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4681 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4686 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4687 * @hw: pointer to the hardware structure
4689 * The 82599 and x540 MACs can experience issues if TX work is still pending
4690 * when a reset occurs. This function prevents this by flushing the PCIe
4691 * buffers on the system.
4693 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4695 u32 gcr_ext, hlreg0, i, poll;
4699 * If double reset is not requested then all transactions should
4700 * already be clear and as such there is no work to do
4702 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4706 * Set loopback enable to prevent any transmits from being sent
4707 * should the link come up. This assumes that the RXCTRL.RXEN bit
4708 * has already been cleared.
4710 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4711 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4713 /* Wait for a last completion before clearing buffers */
4714 IXGBE_WRITE_FLUSH(hw);
4718 * Before proceeding, make sure that the PCIe block does not have
4719 * transactions pending.
4721 poll = ixgbe_pcie_timeout_poll(hw);
4722 for (i = 0; i < poll; i++) {
4724 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
4725 if (IXGBE_REMOVED(hw->hw_addr))
4727 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
4732 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4733 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4734 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4735 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4737 /* Flush all writes and allow 20usec for all transactions to clear */
4738 IXGBE_WRITE_FLUSH(hw);
4741 /* restore previous register values */
4742 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4743 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4746 STATIC const u8 ixgbe_emc_temp_data[4] = {
4747 IXGBE_EMC_INTERNAL_DATA,
4748 IXGBE_EMC_DIODE1_DATA,
4749 IXGBE_EMC_DIODE2_DATA,
4750 IXGBE_EMC_DIODE3_DATA
4752 STATIC const u8 ixgbe_emc_therm_limit[4] = {
4753 IXGBE_EMC_INTERNAL_THERM_LIMIT,
4754 IXGBE_EMC_DIODE1_THERM_LIMIT,
4755 IXGBE_EMC_DIODE2_THERM_LIMIT,
4756 IXGBE_EMC_DIODE3_THERM_LIMIT
4760 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
4761 * @hw: pointer to hardware structure
4762 * @data: pointer to the thermal sensor data structure
4764 * Returns the thermal sensor data structure
4766 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
4768 s32 status = IXGBE_SUCCESS;
4776 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4778 DEBUGFUNC("ixgbe_get_thermal_sensor_data_generic");
4780 /* Only support thermal sensors attached to 82599 physical port 0 */
4781 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4782 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
4783 status = IXGBE_NOT_IMPLEMENTED;
4787 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);
4791 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) {
4792 status = IXGBE_NOT_IMPLEMENTED;
4796 status = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);
4800 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4801 != IXGBE_ETS_TYPE_EMC) {
4802 status = IXGBE_NOT_IMPLEMENTED;
4806 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4807 if (num_sensors > IXGBE_MAX_SENSORS)
4808 num_sensors = IXGBE_MAX_SENSORS;
4810 for (i = 0; i < num_sensors; i++) {
4811 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
4816 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4817 IXGBE_ETS_DATA_INDEX_SHIFT);
4818 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4819 IXGBE_ETS_DATA_LOC_SHIFT);
4821 if (sensor_location != 0) {
4822 status = hw->phy.ops.read_i2c_byte(hw,
4823 ixgbe_emc_temp_data[sensor_index],
4824 IXGBE_I2C_THERMAL_SENSOR_ADDR,
4825 &data->sensor[i].temp);
4835 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
4836 * @hw: pointer to hardware structure
4838 * Inits the thermal sensor thresholds according to the NVM map
4839 * and save off the threshold and location values into mac.thermal_sensor_data
4841 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
4843 s32 status = IXGBE_SUCCESS;
4848 u8 low_thresh_delta;
4854 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4856 DEBUGFUNC("ixgbe_init_thermal_sensor_thresh_generic");
4858 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
4860 /* Only support thermal sensors attached to 82599 physical port 0 */
4861 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4862 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
4863 return IXGBE_NOT_IMPLEMENTED;
4865 offset = IXGBE_ETS_CFG;
4866 if (hw->eeprom.ops.read(hw, offset, &ets_offset))
4868 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
4869 return IXGBE_NOT_IMPLEMENTED;
4871 offset = ets_offset;
4872 if (hw->eeprom.ops.read(hw, offset, &ets_cfg))
4874 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4875 != IXGBE_ETS_TYPE_EMC)
4876 return IXGBE_NOT_IMPLEMENTED;
4878 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
4879 IXGBE_ETS_LTHRES_DELTA_SHIFT);
4880 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4882 for (i = 0; i < num_sensors; i++) {
4883 offset = ets_offset + 1 + i;
4884 if (hw->eeprom.ops.read(hw, offset, &ets_sensor)) {
4885 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4886 "eeprom read at offset %d failed",
4890 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4891 IXGBE_ETS_DATA_INDEX_SHIFT);
4892 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4893 IXGBE_ETS_DATA_LOC_SHIFT);
4894 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
4896 hw->phy.ops.write_i2c_byte(hw,
4897 ixgbe_emc_therm_limit[sensor_index],
4898 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
4900 if ((i < IXGBE_MAX_SENSORS) && (sensor_location != 0)) {
4901 data->sensor[i].location = sensor_location;
4902 data->sensor[i].caution_thresh = therm_limit;
4903 data->sensor[i].max_op_thresh = therm_limit -
4910 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4911 "eeprom read at offset %d failed", offset);
4912 return IXGBE_NOT_IMPLEMENTED;
4917 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
4918 * @hw: pointer to hardware structure
4919 * @map: pointer to u8 arr for returning map
4921 * Read the rtrup2tc HW register and resolve its content into map
4923 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
4927 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
4928 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
4929 map[i] = IXGBE_RTRUP2TC_UP_MASK &
4930 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
4934 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
4939 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4940 if (rxctrl & IXGBE_RXCTRL_RXEN) {
4941 if (hw->mac.type != ixgbe_mac_82598EB) {
4942 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4943 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
4944 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4945 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4946 hw->mac.set_lben = true;
4948 hw->mac.set_lben = false;
4951 rxctrl &= ~IXGBE_RXCTRL_RXEN;
4952 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
4956 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
4961 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4962 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
4964 if (hw->mac.type != ixgbe_mac_82598EB) {
4965 if (hw->mac.set_lben) {
4966 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4967 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
4968 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4969 hw->mac.set_lben = false;
4975 * ixgbe_mng_present - returns true when management capability is present
4976 * @hw: pointer to hardware structure
4978 bool ixgbe_mng_present(struct ixgbe_hw *hw)
4982 if (hw->mac.type < ixgbe_mac_82599EB)
4985 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
4986 fwsm &= IXGBE_FWSM_MODE_MASK;
4987 return fwsm == IXGBE_FWSM_FW_MODE_PT;
4991 * ixgbe_mng_enabled - Is the manageability engine enabled?
4992 * @hw: pointer to hardware structure
4994 * Returns true if the manageability engine is enabled.
4996 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
4998 u32 fwsm, manc, factps;
5000 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5001 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
5004 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
5005 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
5008 if (hw->mac.type <= ixgbe_mac_X540) {
5009 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
5010 if (factps & IXGBE_FACTPS_MNGCG)
5018 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
5019 * @hw: pointer to hardware structure
5020 * @speed: new link speed
5021 * @autoneg_wait_to_complete: true when waiting for completion is needed
5023 * Set the link speed in the MAC and/or PHY register and restarts link.
5025 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
5026 ixgbe_link_speed speed,
5027 bool autoneg_wait_to_complete)
5029 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
5030 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
5031 s32 status = IXGBE_SUCCESS;
5034 bool autoneg, link_up = false;
5036 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
5038 /* Mask off requested but non-supported speeds */
5039 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
5040 if (status != IXGBE_SUCCESS)
5043 speed &= link_speed;
5045 /* Try each speed one by one, highest priority first. We do this in
5046 * software because 10Gb fiber doesn't support speed autonegotiation.
5048 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
5050 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5052 /* If we already have link at this speed, just jump out */
5053 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
5054 if (status != IXGBE_SUCCESS)
5057 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
5060 /* Set the module link speed */
5061 switch (hw->phy.media_type) {
5062 case ixgbe_media_type_fiber:
5063 ixgbe_set_rate_select_speed(hw,
5064 IXGBE_LINK_SPEED_10GB_FULL);
5066 case ixgbe_media_type_fiber_qsfp:
5067 /* QSFP module automatically detects MAC link speed */
5070 DEBUGOUT("Unexpected media type.\n");
5074 /* Allow module to change analog characteristics (1G->10G) */
5077 status = ixgbe_setup_mac_link(hw,
5078 IXGBE_LINK_SPEED_10GB_FULL,
5079 autoneg_wait_to_complete);
5080 if (status != IXGBE_SUCCESS)
5083 /* Flap the Tx laser if it has not already been done */
5084 ixgbe_flap_tx_laser(hw);
5086 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
5087 * Section 73.10.2, we may have to wait up to 500ms if KR is
5088 * attempted. 82599 uses the same timing for 10g SFI.
5090 for (i = 0; i < 5; i++) {
5091 /* Wait for the link partner to also set speed */
5094 /* If we have link, just jump out */
5095 status = ixgbe_check_link(hw, &link_speed,
5097 if (status != IXGBE_SUCCESS)
5105 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
5107 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
5108 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
5110 /* If we already have link at this speed, just jump out */
5111 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
5112 if (status != IXGBE_SUCCESS)
5115 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
5118 /* Set the module link speed */
5119 switch (hw->phy.media_type) {
5120 case ixgbe_media_type_fiber:
5121 ixgbe_set_rate_select_speed(hw,
5122 IXGBE_LINK_SPEED_1GB_FULL);
5124 case ixgbe_media_type_fiber_qsfp:
5125 /* QSFP module automatically detects link speed */
5128 DEBUGOUT("Unexpected media type.\n");
5132 /* Allow module to change analog characteristics (10G->1G) */
5135 status = ixgbe_setup_mac_link(hw,
5136 IXGBE_LINK_SPEED_1GB_FULL,
5137 autoneg_wait_to_complete);
5138 if (status != IXGBE_SUCCESS)
5141 /* Flap the Tx laser if it has not already been done */
5142 ixgbe_flap_tx_laser(hw);
5144 /* Wait for the link partner to also set speed */
5147 /* If we have link, just jump out */
5148 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
5149 if (status != IXGBE_SUCCESS)
5156 /* We didn't get link. Configure back to the highest speed we tried,
5157 * (if there was more than one). We call ourselves back with just the
5158 * single highest speed that the user requested.
5161 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
5163 autoneg_wait_to_complete);
5166 /* Set autoneg_advertised value based on input link speed */
5167 hw->phy.autoneg_advertised = 0;
5169 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
5170 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
5172 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
5173 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
5179 * ixgbe_set_soft_rate_select_speed - Set module link speed
5180 * @hw: pointer to hardware structure
5181 * @speed: link speed to set
5183 * Set module link speed via the soft rate select.
5185 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
5186 ixgbe_link_speed speed)
5192 case IXGBE_LINK_SPEED_10GB_FULL:
5193 /* one bit mask same as setting on */
5194 rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
5196 case IXGBE_LINK_SPEED_1GB_FULL:
5197 rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
5200 DEBUGOUT("Invalid fixed module speed\n");
5205 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5206 IXGBE_I2C_EEPROM_DEV_ADDR2,
5209 DEBUGOUT("Failed to read Rx Rate Select RS0\n");
5213 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5215 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5216 IXGBE_I2C_EEPROM_DEV_ADDR2,
5219 DEBUGOUT("Failed to write Rx Rate Select RS0\n");
5224 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5225 IXGBE_I2C_EEPROM_DEV_ADDR2,
5228 DEBUGOUT("Failed to read Rx Rate Select RS1\n");
5232 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5234 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5235 IXGBE_I2C_EEPROM_DEV_ADDR2,
5238 DEBUGOUT("Failed to write Rx Rate Select RS1\n");