1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
36 #include "ixgbe_dcb.h"
37 #include "ixgbe_dcb_82599.h"
38 #include "ixgbe_api.h"
40 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
41 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
42 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
43 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
44 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
45 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
47 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
48 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
49 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
50 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw);
52 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
53 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
55 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
56 u16 words, u16 *data);
57 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
58 u16 words, u16 *data);
59 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
63 * ixgbe_init_ops_generic - Inits function ptrs
64 * @hw: pointer to the hardware structure
66 * Initialize the function pointers.
68 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
70 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
71 struct ixgbe_mac_info *mac = &hw->mac;
72 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
74 DEBUGFUNC("ixgbe_init_ops_generic");
77 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic;
78 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
79 if (eec & IXGBE_EEC_PRES) {
80 eeprom->ops.read = ixgbe_read_eerd_generic;
81 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic;
83 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic;
84 eeprom->ops.read_buffer =
85 ixgbe_read_eeprom_buffer_bit_bang_generic;
87 eeprom->ops.write = ixgbe_write_eeprom_generic;
88 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic;
89 eeprom->ops.validate_checksum =
90 ixgbe_validate_eeprom_checksum_generic;
91 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic;
92 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic;
95 mac->ops.init_hw = ixgbe_init_hw_generic;
96 mac->ops.reset_hw = NULL;
97 mac->ops.start_hw = ixgbe_start_hw_generic;
98 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic;
99 mac->ops.get_media_type = NULL;
100 mac->ops.get_supported_physical_layer = NULL;
101 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic;
102 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic;
103 mac->ops.stop_adapter = ixgbe_stop_adapter_generic;
104 mac->ops.get_bus_info = ixgbe_get_bus_info_generic;
105 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie;
106 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync;
107 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync;
108 mac->ops.prot_autoc_read = prot_autoc_read_generic;
109 mac->ops.prot_autoc_write = prot_autoc_write_generic;
112 mac->ops.led_on = ixgbe_led_on_generic;
113 mac->ops.led_off = ixgbe_led_off_generic;
114 mac->ops.blink_led_start = ixgbe_blink_led_start_generic;
115 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic;
116 mac->ops.init_led_link_act = ixgbe_init_led_link_act_generic;
118 /* RAR, Multicast, VLAN */
119 mac->ops.set_rar = ixgbe_set_rar_generic;
120 mac->ops.clear_rar = ixgbe_clear_rar_generic;
121 mac->ops.insert_mac_addr = NULL;
122 mac->ops.set_vmdq = NULL;
123 mac->ops.clear_vmdq = NULL;
124 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic;
125 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic;
126 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic;
127 mac->ops.enable_mc = ixgbe_enable_mc_generic;
128 mac->ops.disable_mc = ixgbe_disable_mc_generic;
129 mac->ops.clear_vfta = NULL;
130 mac->ops.set_vfta = NULL;
131 mac->ops.set_vlvf = NULL;
132 mac->ops.init_uta_tables = NULL;
133 mac->ops.enable_rx = ixgbe_enable_rx_generic;
134 mac->ops.disable_rx = ixgbe_disable_rx_generic;
137 mac->ops.fc_enable = ixgbe_fc_enable_generic;
138 mac->ops.setup_fc = ixgbe_setup_fc_generic;
139 mac->ops.fc_autoneg = ixgbe_fc_autoneg;
142 mac->ops.get_link_capabilities = NULL;
143 mac->ops.setup_link = NULL;
144 mac->ops.check_link = NULL;
145 mac->ops.dmac_config = NULL;
146 mac->ops.dmac_update_tcs = NULL;
147 mac->ops.dmac_config_tcs = NULL;
149 return IXGBE_SUCCESS;
153 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
155 * @hw: pointer to hardware structure
157 * This function returns true if the device supports flow control
158 * autonegotiation, and false if it does not.
161 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
163 bool supported = false;
164 ixgbe_link_speed speed;
167 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
169 switch (hw->phy.media_type) {
170 case ixgbe_media_type_fiber_qsfp:
171 case ixgbe_media_type_fiber:
172 /* flow control autoneg black list */
173 switch (hw->device_id) {
174 case IXGBE_DEV_ID_X550EM_A_SFP:
175 case IXGBE_DEV_ID_X550EM_A_SFP_N:
176 case IXGBE_DEV_ID_X550EM_A_QSFP:
177 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
181 hw->mac.ops.check_link(hw, &speed, &link_up, false);
182 /* if link is down, assume supported */
184 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
191 case ixgbe_media_type_backplane:
192 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI)
197 case ixgbe_media_type_copper:
198 /* only some copper devices support flow control autoneg */
199 switch (hw->device_id) {
200 case IXGBE_DEV_ID_82599_T3_LOM:
201 case IXGBE_DEV_ID_X540T:
202 case IXGBE_DEV_ID_X540T1:
203 case IXGBE_DEV_ID_X550T:
204 case IXGBE_DEV_ID_X550T1:
205 case IXGBE_DEV_ID_X550EM_X_10G_T:
206 case IXGBE_DEV_ID_X550EM_A_10G_T:
207 case IXGBE_DEV_ID_X550EM_A_1G_T:
208 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
219 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
220 "Device %x does not support flow control autoneg",
226 * ixgbe_setup_fc_generic - Set up flow control
227 * @hw: pointer to hardware structure
229 * Called at init time to set up flow control.
231 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
233 s32 ret_val = IXGBE_SUCCESS;
234 u32 reg = 0, reg_bp = 0;
238 DEBUGFUNC("ixgbe_setup_fc_generic");
240 /* Validate the requested mode */
241 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
242 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
243 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
244 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
249 * 10gig parts do not have a word in the EEPROM to determine the
250 * default flow control setting, so we explicitly set it to full.
252 if (hw->fc.requested_mode == ixgbe_fc_default)
253 hw->fc.requested_mode = ixgbe_fc_full;
256 * Set up the 1G and 10G flow control advertisement registers so the
257 * HW will be able to do fc autoneg once the cable is plugged in. If
258 * we link at 10G, the 1G advertisement is harmless and vice versa.
260 switch (hw->phy.media_type) {
261 case ixgbe_media_type_backplane:
262 /* some MAC's need RMW protection on AUTOC */
263 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
264 if (ret_val != IXGBE_SUCCESS)
267 /* fall through - only backplane uses autoc */
268 case ixgbe_media_type_fiber_qsfp:
269 case ixgbe_media_type_fiber:
270 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
273 case ixgbe_media_type_copper:
274 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
275 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
282 * The possible values of fc.requested_mode are:
283 * 0: Flow control is completely disabled
284 * 1: Rx flow control is enabled (we can receive pause frames,
285 * but not send pause frames).
286 * 2: Tx flow control is enabled (we can send pause frames but
287 * we do not support receiving pause frames).
288 * 3: Both Rx and Tx flow control (symmetric) are enabled.
291 switch (hw->fc.requested_mode) {
293 /* Flow control completely disabled by software override. */
294 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
295 if (hw->phy.media_type == ixgbe_media_type_backplane)
296 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
297 IXGBE_AUTOC_ASM_PAUSE);
298 else if (hw->phy.media_type == ixgbe_media_type_copper)
299 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
301 case ixgbe_fc_tx_pause:
303 * Tx Flow control is enabled, and Rx Flow control is
304 * disabled by software override.
306 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
307 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
308 if (hw->phy.media_type == ixgbe_media_type_backplane) {
309 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
310 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
311 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
312 reg_cu |= IXGBE_TAF_ASM_PAUSE;
313 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
316 case ixgbe_fc_rx_pause:
318 * Rx Flow control is enabled and Tx Flow control is
319 * disabled by software override. Since there really
320 * isn't a way to advertise that we are capable of RX
321 * Pause ONLY, we will advertise that we support both
322 * symmetric and asymmetric Rx PAUSE, as such we fall
323 * through to the fc_full statement. Later, we will
324 * disable the adapter's ability to send PAUSE frames.
327 /* Flow control (both Rx and Tx) is enabled by SW override. */
328 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
329 if (hw->phy.media_type == ixgbe_media_type_backplane)
330 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
331 IXGBE_AUTOC_ASM_PAUSE;
332 else if (hw->phy.media_type == ixgbe_media_type_copper)
333 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
336 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
337 "Flow control param set incorrectly\n");
338 ret_val = IXGBE_ERR_CONFIG;
343 if (hw->mac.type < ixgbe_mac_X540) {
345 * Enable auto-negotiation between the MAC & PHY;
346 * the MAC will advertise clause 37 flow control.
348 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
349 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
351 /* Disable AN timeout */
352 if (hw->fc.strict_ieee)
353 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
355 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
356 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
360 * AUTOC restart handles negotiation of 1G and 10G on backplane
361 * and copper. There is no need to set the PCS1GCTL register.
364 if (hw->phy.media_type == ixgbe_media_type_backplane) {
365 reg_bp |= IXGBE_AUTOC_AN_RESTART;
366 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
369 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
370 (ixgbe_device_supports_autoneg_fc(hw))) {
371 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
372 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
375 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
381 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
382 * @hw: pointer to hardware structure
384 * Starts the hardware by filling the bus info structure and media type, clears
385 * all on chip counters, initializes receive address registers, multicast
386 * table, VLAN filter table, calls routine to set up link and flow control
387 * settings, and leaves transmit and receive units disabled and uninitialized
389 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
395 DEBUGFUNC("ixgbe_start_hw_generic");
397 /* Set the media type */
398 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
400 /* PHY ops initialization must be done in reset_hw() */
402 /* Clear the VLAN filter table */
403 hw->mac.ops.clear_vfta(hw);
405 /* Clear statistics registers */
406 hw->mac.ops.clear_hw_cntrs(hw);
408 /* Set No Snoop Disable */
409 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
410 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
411 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
412 IXGBE_WRITE_FLUSH(hw);
414 /* Setup flow control */
415 ret_val = ixgbe_setup_fc(hw);
416 if (ret_val != IXGBE_SUCCESS && ret_val != IXGBE_NOT_IMPLEMENTED) {
417 DEBUGOUT1("Flow control setup failed, returning %d\n", ret_val);
421 /* Cache bit indicating need for crosstalk fix */
422 switch (hw->mac.type) {
423 case ixgbe_mac_82599EB:
424 case ixgbe_mac_X550EM_x:
425 case ixgbe_mac_X550EM_a:
426 hw->mac.ops.get_device_caps(hw, &device_caps);
427 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
428 hw->need_crosstalk_fix = false;
430 hw->need_crosstalk_fix = true;
433 hw->need_crosstalk_fix = false;
437 /* Clear adapter stopped flag */
438 hw->adapter_stopped = false;
440 return IXGBE_SUCCESS;
444 * ixgbe_start_hw_gen2 - Init sequence for common device family
445 * @hw: pointer to hw structure
447 * Performs the init sequence common to the second generation
449 * Devices in the second generation:
453 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
458 /* Clear the rate limiters */
459 for (i = 0; i < hw->mac.max_tx_queues; i++) {
460 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
461 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
463 IXGBE_WRITE_FLUSH(hw);
465 /* Disable relaxed ordering */
466 for (i = 0; i < hw->mac.max_tx_queues; i++) {
467 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
468 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
469 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
472 for (i = 0; i < hw->mac.max_rx_queues; i++) {
473 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
474 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
475 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
476 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
479 return IXGBE_SUCCESS;
483 * ixgbe_init_hw_generic - Generic hardware initialization
484 * @hw: pointer to hardware structure
486 * Initialize the hardware by resetting the hardware, filling the bus info
487 * structure and media type, clears all on chip counters, initializes receive
488 * address registers, multicast table, VLAN filter table, calls routine to set
489 * up link and flow control settings, and leaves transmit and receive units
490 * disabled and uninitialized
492 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
496 DEBUGFUNC("ixgbe_init_hw_generic");
498 /* Reset the hardware */
499 status = hw->mac.ops.reset_hw(hw);
501 if (status == IXGBE_SUCCESS || status == IXGBE_ERR_SFP_NOT_PRESENT) {
503 status = hw->mac.ops.start_hw(hw);
506 /* Initialize the LED link active for LED blink support */
507 if (hw->mac.ops.init_led_link_act)
508 hw->mac.ops.init_led_link_act(hw);
510 if (status != IXGBE_SUCCESS)
511 DEBUGOUT1("Failed to initialize HW, STATUS = %d\n", status);
517 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
518 * @hw: pointer to hardware structure
520 * Clears all hardware statistics counters by reading them from the hardware
521 * Statistics counters are clear on read.
523 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
527 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
529 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
530 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
531 IXGBE_READ_REG(hw, IXGBE_ERRBC);
532 IXGBE_READ_REG(hw, IXGBE_MSPDC);
533 for (i = 0; i < 8; i++)
534 IXGBE_READ_REG(hw, IXGBE_MPC(i));
536 IXGBE_READ_REG(hw, IXGBE_MLFC);
537 IXGBE_READ_REG(hw, IXGBE_MRFC);
538 IXGBE_READ_REG(hw, IXGBE_RLEC);
539 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
540 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
541 if (hw->mac.type >= ixgbe_mac_82599EB) {
542 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
543 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
545 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
546 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
549 for (i = 0; i < 8; i++) {
550 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
551 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
552 if (hw->mac.type >= ixgbe_mac_82599EB) {
553 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
554 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
556 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
557 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
560 if (hw->mac.type >= ixgbe_mac_82599EB)
561 for (i = 0; i < 8; i++)
562 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
563 IXGBE_READ_REG(hw, IXGBE_PRC64);
564 IXGBE_READ_REG(hw, IXGBE_PRC127);
565 IXGBE_READ_REG(hw, IXGBE_PRC255);
566 IXGBE_READ_REG(hw, IXGBE_PRC511);
567 IXGBE_READ_REG(hw, IXGBE_PRC1023);
568 IXGBE_READ_REG(hw, IXGBE_PRC1522);
569 IXGBE_READ_REG(hw, IXGBE_GPRC);
570 IXGBE_READ_REG(hw, IXGBE_BPRC);
571 IXGBE_READ_REG(hw, IXGBE_MPRC);
572 IXGBE_READ_REG(hw, IXGBE_GPTC);
573 IXGBE_READ_REG(hw, IXGBE_GORCL);
574 IXGBE_READ_REG(hw, IXGBE_GORCH);
575 IXGBE_READ_REG(hw, IXGBE_GOTCL);
576 IXGBE_READ_REG(hw, IXGBE_GOTCH);
577 if (hw->mac.type == ixgbe_mac_82598EB)
578 for (i = 0; i < 8; i++)
579 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
580 IXGBE_READ_REG(hw, IXGBE_RUC);
581 IXGBE_READ_REG(hw, IXGBE_RFC);
582 IXGBE_READ_REG(hw, IXGBE_ROC);
583 IXGBE_READ_REG(hw, IXGBE_RJC);
584 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
585 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
586 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
587 IXGBE_READ_REG(hw, IXGBE_TORL);
588 IXGBE_READ_REG(hw, IXGBE_TORH);
589 IXGBE_READ_REG(hw, IXGBE_TPR);
590 IXGBE_READ_REG(hw, IXGBE_TPT);
591 IXGBE_READ_REG(hw, IXGBE_PTC64);
592 IXGBE_READ_REG(hw, IXGBE_PTC127);
593 IXGBE_READ_REG(hw, IXGBE_PTC255);
594 IXGBE_READ_REG(hw, IXGBE_PTC511);
595 IXGBE_READ_REG(hw, IXGBE_PTC1023);
596 IXGBE_READ_REG(hw, IXGBE_PTC1522);
597 IXGBE_READ_REG(hw, IXGBE_MPTC);
598 IXGBE_READ_REG(hw, IXGBE_BPTC);
599 for (i = 0; i < 16; i++) {
600 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
601 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
602 if (hw->mac.type >= ixgbe_mac_82599EB) {
603 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
604 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
605 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
606 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
607 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
609 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
610 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
614 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
616 ixgbe_identify_phy(hw);
617 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
618 IXGBE_MDIO_PCS_DEV_TYPE, &i);
619 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
620 IXGBE_MDIO_PCS_DEV_TYPE, &i);
621 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
622 IXGBE_MDIO_PCS_DEV_TYPE, &i);
623 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
624 IXGBE_MDIO_PCS_DEV_TYPE, &i);
627 return IXGBE_SUCCESS;
631 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
632 * @hw: pointer to hardware structure
633 * @pba_num: stores the part number string from the EEPROM
634 * @pba_num_size: part number string buffer length
636 * Reads the part number string from the EEPROM.
638 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
647 DEBUGFUNC("ixgbe_read_pba_string_generic");
649 if (pba_num == NULL) {
650 DEBUGOUT("PBA string buffer was null\n");
651 return IXGBE_ERR_INVALID_ARGUMENT;
654 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
656 DEBUGOUT("NVM Read Error\n");
660 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
662 DEBUGOUT("NVM Read Error\n");
667 * if data is not ptr guard the PBA must be in legacy format which
668 * means pba_ptr is actually our second data word for the PBA number
669 * and we can decode it into an ascii string
671 if (data != IXGBE_PBANUM_PTR_GUARD) {
672 DEBUGOUT("NVM PBA number is not stored as string\n");
674 /* we will need 11 characters to store the PBA */
675 if (pba_num_size < 11) {
676 DEBUGOUT("PBA string buffer too small\n");
677 return IXGBE_ERR_NO_SPACE;
680 /* extract hex string from data and pba_ptr */
681 pba_num[0] = (data >> 12) & 0xF;
682 pba_num[1] = (data >> 8) & 0xF;
683 pba_num[2] = (data >> 4) & 0xF;
684 pba_num[3] = data & 0xF;
685 pba_num[4] = (pba_ptr >> 12) & 0xF;
686 pba_num[5] = (pba_ptr >> 8) & 0xF;
689 pba_num[8] = (pba_ptr >> 4) & 0xF;
690 pba_num[9] = pba_ptr & 0xF;
692 /* put a null character on the end of our string */
695 /* switch all the data but the '-' to hex char */
696 for (offset = 0; offset < 10; offset++) {
697 if (pba_num[offset] < 0xA)
698 pba_num[offset] += '0';
699 else if (pba_num[offset] < 0x10)
700 pba_num[offset] += 'A' - 0xA;
703 return IXGBE_SUCCESS;
706 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
708 DEBUGOUT("NVM Read Error\n");
712 if (length == 0xFFFF || length == 0) {
713 DEBUGOUT("NVM PBA number section invalid length\n");
714 return IXGBE_ERR_PBA_SECTION;
717 /* check if pba_num buffer is big enough */
718 if (pba_num_size < (((u32)length * 2) - 1)) {
719 DEBUGOUT("PBA string buffer too small\n");
720 return IXGBE_ERR_NO_SPACE;
723 /* trim pba length from start of string */
727 for (offset = 0; offset < length; offset++) {
728 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
730 DEBUGOUT("NVM Read Error\n");
733 pba_num[offset * 2] = (u8)(data >> 8);
734 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
736 pba_num[offset * 2] = '\0';
738 return IXGBE_SUCCESS;
742 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
743 * @hw: pointer to hardware structure
744 * @pba_num: stores the part number from the EEPROM
746 * Reads the part number from the EEPROM.
748 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
753 DEBUGFUNC("ixgbe_read_pba_num_generic");
755 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
757 DEBUGOUT("NVM Read Error\n");
759 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
760 DEBUGOUT("NVM Not supported\n");
761 return IXGBE_NOT_IMPLEMENTED;
763 *pba_num = (u32)(data << 16);
765 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
767 DEBUGOUT("NVM Read Error\n");
772 return IXGBE_SUCCESS;
777 * @hw: pointer to the HW structure
778 * @eeprom_buf: optional pointer to EEPROM image
779 * @eeprom_buf_size: size of EEPROM image in words
780 * @max_pba_block_size: PBA block size limit
781 * @pba: pointer to output PBA structure
783 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
784 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
787 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
788 u32 eeprom_buf_size, u16 max_pba_block_size,
789 struct ixgbe_pba *pba)
795 return IXGBE_ERR_PARAM;
797 if (eeprom_buf == NULL) {
798 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
803 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
804 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
805 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
807 return IXGBE_ERR_PARAM;
811 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
812 if (pba->pba_block == NULL)
813 return IXGBE_ERR_PARAM;
815 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
821 if (pba_block_size > max_pba_block_size)
822 return IXGBE_ERR_PARAM;
824 if (eeprom_buf == NULL) {
825 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
831 if (eeprom_buf_size > (u32)(pba->word[1] +
833 memcpy(pba->pba_block,
834 &eeprom_buf[pba->word[1]],
835 pba_block_size * sizeof(u16));
837 return IXGBE_ERR_PARAM;
842 return IXGBE_SUCCESS;
846 * ixgbe_write_pba_raw
847 * @hw: pointer to the HW structure
848 * @eeprom_buf: optional pointer to EEPROM image
849 * @eeprom_buf_size: size of EEPROM image in words
850 * @pba: pointer to PBA structure
852 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
853 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
856 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
857 u32 eeprom_buf_size, struct ixgbe_pba *pba)
862 return IXGBE_ERR_PARAM;
864 if (eeprom_buf == NULL) {
865 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
870 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
871 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
872 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
874 return IXGBE_ERR_PARAM;
878 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
879 if (pba->pba_block == NULL)
880 return IXGBE_ERR_PARAM;
882 if (eeprom_buf == NULL) {
883 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
889 if (eeprom_buf_size > (u32)(pba->word[1] +
890 pba->pba_block[0])) {
891 memcpy(&eeprom_buf[pba->word[1]],
893 pba->pba_block[0] * sizeof(u16));
895 return IXGBE_ERR_PARAM;
900 return IXGBE_SUCCESS;
904 * ixgbe_get_pba_block_size
905 * @hw: pointer to the HW structure
906 * @eeprom_buf: optional pointer to EEPROM image
907 * @eeprom_buf_size: size of EEPROM image in words
908 * @pba_data_size: pointer to output variable
910 * Returns the size of the PBA block in words. Function operates on EEPROM
911 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
915 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
916 u32 eeprom_buf_size, u16 *pba_block_size)
922 DEBUGFUNC("ixgbe_get_pba_block_size");
924 if (eeprom_buf == NULL) {
925 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
930 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
931 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
932 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
934 return IXGBE_ERR_PARAM;
938 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
939 if (eeprom_buf == NULL) {
940 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
945 if (eeprom_buf_size > pba_word[1])
946 length = eeprom_buf[pba_word[1] + 0];
948 return IXGBE_ERR_PARAM;
951 if (length == 0xFFFF || length == 0)
952 return IXGBE_ERR_PBA_SECTION;
954 /* PBA number in legacy format, there is no PBA Block. */
958 if (pba_block_size != NULL)
959 *pba_block_size = length;
961 return IXGBE_SUCCESS;
965 * ixgbe_get_mac_addr_generic - Generic get MAC address
966 * @hw: pointer to hardware structure
967 * @mac_addr: Adapter MAC address
969 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
970 * A reset of the adapter must be performed prior to calling this function
971 * in order for the MAC address to have been loaded from the EEPROM into RAR0
973 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
979 DEBUGFUNC("ixgbe_get_mac_addr_generic");
981 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
982 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
984 for (i = 0; i < 4; i++)
985 mac_addr[i] = (u8)(rar_low >> (i*8));
987 for (i = 0; i < 2; i++)
988 mac_addr[i+4] = (u8)(rar_high >> (i*8));
990 return IXGBE_SUCCESS;
994 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
995 * @hw: pointer to hardware structure
996 * @link_status: the link status returned by the PCI config space
998 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
1000 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
1002 struct ixgbe_mac_info *mac = &hw->mac;
1004 if (hw->bus.type == ixgbe_bus_type_unknown)
1005 hw->bus.type = ixgbe_bus_type_pci_express;
1007 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
1008 case IXGBE_PCI_LINK_WIDTH_1:
1009 hw->bus.width = ixgbe_bus_width_pcie_x1;
1011 case IXGBE_PCI_LINK_WIDTH_2:
1012 hw->bus.width = ixgbe_bus_width_pcie_x2;
1014 case IXGBE_PCI_LINK_WIDTH_4:
1015 hw->bus.width = ixgbe_bus_width_pcie_x4;
1017 case IXGBE_PCI_LINK_WIDTH_8:
1018 hw->bus.width = ixgbe_bus_width_pcie_x8;
1021 hw->bus.width = ixgbe_bus_width_unknown;
1025 switch (link_status & IXGBE_PCI_LINK_SPEED) {
1026 case IXGBE_PCI_LINK_SPEED_2500:
1027 hw->bus.speed = ixgbe_bus_speed_2500;
1029 case IXGBE_PCI_LINK_SPEED_5000:
1030 hw->bus.speed = ixgbe_bus_speed_5000;
1032 case IXGBE_PCI_LINK_SPEED_8000:
1033 hw->bus.speed = ixgbe_bus_speed_8000;
1036 hw->bus.speed = ixgbe_bus_speed_unknown;
1040 mac->ops.set_lan_id(hw);
1044 * ixgbe_get_bus_info_generic - Generic set PCI bus info
1045 * @hw: pointer to hardware structure
1047 * Gets the PCI bus info (speed, width, type) then calls helper function to
1048 * store this data within the ixgbe_hw structure.
1050 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
1054 DEBUGFUNC("ixgbe_get_bus_info_generic");
1056 /* Get the negotiated link width and speed from PCI config space */
1057 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
1059 ixgbe_set_pci_config_data_generic(hw, link_status);
1061 return IXGBE_SUCCESS;
1065 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
1066 * @hw: pointer to the HW structure
1068 * Determines the LAN function id by reading memory-mapped registers and swaps
1069 * the port value if requested, and set MAC instance for devices that share
1072 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
1074 struct ixgbe_bus_info *bus = &hw->bus;
1078 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
1080 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
1081 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
1082 bus->lan_id = (u8)bus->func;
1084 /* check for a port swap */
1085 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
1086 if (reg & IXGBE_FACTPS_LFS)
1089 /* Get MAC instance from EEPROM for configuring CS4227 */
1090 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) {
1091 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4);
1092 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >>
1093 IXGBE_EE_CTRL_4_INST_ID_SHIFT;
1098 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1099 * @hw: pointer to hardware structure
1101 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
1102 * disables transmit and receive units. The adapter_stopped flag is used by
1103 * the shared code and drivers to determine if the adapter is in a stopped
1104 * state and should not touch the hardware.
1106 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1111 DEBUGFUNC("ixgbe_stop_adapter_generic");
1114 * Set the adapter_stopped flag so other driver functions stop touching
1117 hw->adapter_stopped = true;
1119 /* Disable the receive unit */
1120 ixgbe_disable_rx(hw);
1122 /* Clear interrupt mask to stop interrupts from being generated */
1123 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1125 /* Clear any pending interrupts, flush previous writes */
1126 IXGBE_READ_REG(hw, IXGBE_EICR);
1128 /* Disable the transmit unit. Each queue must be disabled. */
1129 for (i = 0; i < hw->mac.max_tx_queues; i++)
1130 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1132 /* Disable the receive unit by stopping each queue */
1133 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1134 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1135 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1136 reg_val |= IXGBE_RXDCTL_SWFLSH;
1137 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1140 /* flush all queues disables */
1141 IXGBE_WRITE_FLUSH(hw);
1145 * Prevent the PCI-E bus from hanging by disabling PCI-E master
1146 * access and verify no pending requests
1148 return ixgbe_disable_pcie_master(hw);
1152 * ixgbe_init_led_link_act_generic - Store the LED index link/activity.
1153 * @hw: pointer to hardware structure
1155 * Store the index for the link active LED. This will be used to support
1158 s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw)
1160 struct ixgbe_mac_info *mac = &hw->mac;
1161 u32 led_reg, led_mode;
1164 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1166 /* Get LED link active from the LEDCTL register */
1167 for (i = 0; i < 4; i++) {
1168 led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i);
1170 if ((led_mode & IXGBE_LED_MODE_MASK_BASE) ==
1171 IXGBE_LED_LINK_ACTIVE) {
1172 mac->led_link_act = i;
1173 return IXGBE_SUCCESS;
1178 * If LEDCTL register does not have the LED link active set, then use
1179 * known MAC defaults.
1181 switch (hw->mac.type) {
1182 case ixgbe_mac_X550EM_a:
1183 case ixgbe_mac_X550EM_x:
1184 mac->led_link_act = 1;
1187 mac->led_link_act = 2;
1189 return IXGBE_SUCCESS;
1193 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1194 * @hw: pointer to hardware structure
1195 * @index: led number to turn on
1197 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1199 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1201 DEBUGFUNC("ixgbe_led_on_generic");
1204 return IXGBE_ERR_PARAM;
1206 /* To turn on the LED, set mode to ON. */
1207 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1208 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
1209 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1210 IXGBE_WRITE_FLUSH(hw);
1212 return IXGBE_SUCCESS;
1216 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1217 * @hw: pointer to hardware structure
1218 * @index: led number to turn off
1220 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1222 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1224 DEBUGFUNC("ixgbe_led_off_generic");
1227 return IXGBE_ERR_PARAM;
1229 /* To turn off the LED, set mode to OFF. */
1230 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1231 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
1232 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1233 IXGBE_WRITE_FLUSH(hw);
1235 return IXGBE_SUCCESS;
1239 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1240 * @hw: pointer to hardware structure
1242 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1243 * ixgbe_hw struct in order to set up EEPROM access.
1245 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1247 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1251 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
1253 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1254 eeprom->type = ixgbe_eeprom_none;
1255 /* Set default semaphore delay to 10ms which is a well
1257 eeprom->semaphore_delay = 10;
1258 /* Clear EEPROM page size, it will be initialized as needed */
1259 eeprom->word_page_size = 0;
1262 * Check for EEPROM present first.
1263 * If not present leave as none
1265 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1266 if (eec & IXGBE_EEC_PRES) {
1267 eeprom->type = ixgbe_eeprom_spi;
1270 * SPI EEPROM is assumed here. This code would need to
1271 * change if a future EEPROM is not SPI.
1273 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1274 IXGBE_EEC_SIZE_SHIFT);
1275 eeprom->word_size = 1 << (eeprom_size +
1276 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1279 if (eec & IXGBE_EEC_ADDR_SIZE)
1280 eeprom->address_bits = 16;
1282 eeprom->address_bits = 8;
1283 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
1284 "%d\n", eeprom->type, eeprom->word_size,
1285 eeprom->address_bits);
1288 return IXGBE_SUCCESS;
1292 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1293 * @hw: pointer to hardware structure
1294 * @offset: offset within the EEPROM to write
1295 * @words: number of word(s)
1296 * @data: 16 bit word(s) to write to EEPROM
1298 * Reads 16 bit word(s) from EEPROM through bit-bang method
1300 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1301 u16 words, u16 *data)
1303 s32 status = IXGBE_SUCCESS;
1306 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
1308 hw->eeprom.ops.init_params(hw);
1311 status = IXGBE_ERR_INVALID_ARGUMENT;
1315 if (offset + words > hw->eeprom.word_size) {
1316 status = IXGBE_ERR_EEPROM;
1321 * The EEPROM page size cannot be queried from the chip. We do lazy
1322 * initialization. It is worth to do that when we write large buffer.
1324 if ((hw->eeprom.word_page_size == 0) &&
1325 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
1326 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1329 * We cannot hold synchronization semaphores for too long
1330 * to avoid other entity starvation. However it is more efficient
1331 * to read in bursts than synchronizing access for each word.
1333 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1334 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1335 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1336 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1339 if (status != IXGBE_SUCCESS)
1348 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1349 * @hw: pointer to hardware structure
1350 * @offset: offset within the EEPROM to be written to
1351 * @words: number of word(s)
1352 * @data: 16 bit word(s) to be written to the EEPROM
1354 * If ixgbe_eeprom_update_checksum is not called after this function, the
1355 * EEPROM will most likely contain an invalid checksum.
1357 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1358 u16 words, u16 *data)
1364 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1366 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1368 /* Prepare the EEPROM for writing */
1369 status = ixgbe_acquire_eeprom(hw);
1371 if (status == IXGBE_SUCCESS) {
1372 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1373 ixgbe_release_eeprom(hw);
1374 status = IXGBE_ERR_EEPROM;
1378 if (status == IXGBE_SUCCESS) {
1379 for (i = 0; i < words; i++) {
1380 ixgbe_standby_eeprom(hw);
1382 /* Send the WRITE ENABLE command (8 bit opcode ) */
1383 ixgbe_shift_out_eeprom_bits(hw,
1384 IXGBE_EEPROM_WREN_OPCODE_SPI,
1385 IXGBE_EEPROM_OPCODE_BITS);
1387 ixgbe_standby_eeprom(hw);
1390 * Some SPI eeproms use the 8th address bit embedded
1393 if ((hw->eeprom.address_bits == 8) &&
1394 ((offset + i) >= 128))
1395 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1397 /* Send the Write command (8-bit opcode + addr) */
1398 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1399 IXGBE_EEPROM_OPCODE_BITS);
1400 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1401 hw->eeprom.address_bits);
1403 page_size = hw->eeprom.word_page_size;
1405 /* Send the data in burst via SPI*/
1408 word = (word >> 8) | (word << 8);
1409 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1414 /* do not wrap around page */
1415 if (((offset + i) & (page_size - 1)) ==
1418 } while (++i < words);
1420 ixgbe_standby_eeprom(hw);
1423 /* Done with writing - release the EEPROM */
1424 ixgbe_release_eeprom(hw);
1431 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1432 * @hw: pointer to hardware structure
1433 * @offset: offset within the EEPROM to be written to
1434 * @data: 16 bit word to be written to the EEPROM
1436 * If ixgbe_eeprom_update_checksum is not called after this function, the
1437 * EEPROM will most likely contain an invalid checksum.
1439 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1443 DEBUGFUNC("ixgbe_write_eeprom_generic");
1445 hw->eeprom.ops.init_params(hw);
1447 if (offset >= hw->eeprom.word_size) {
1448 status = IXGBE_ERR_EEPROM;
1452 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1459 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1460 * @hw: pointer to hardware structure
1461 * @offset: offset within the EEPROM to be read
1462 * @data: read 16 bit words(s) from EEPROM
1463 * @words: number of word(s)
1465 * Reads 16 bit word(s) from EEPROM through bit-bang method
1467 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1468 u16 words, u16 *data)
1470 s32 status = IXGBE_SUCCESS;
1473 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1475 hw->eeprom.ops.init_params(hw);
1478 status = IXGBE_ERR_INVALID_ARGUMENT;
1482 if (offset + words > hw->eeprom.word_size) {
1483 status = IXGBE_ERR_EEPROM;
1488 * We cannot hold synchronization semaphores for too long
1489 * to avoid other entity starvation. However it is more efficient
1490 * to read in bursts than synchronizing access for each word.
1492 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1493 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1494 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1496 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1499 if (status != IXGBE_SUCCESS)
1508 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1509 * @hw: pointer to hardware structure
1510 * @offset: offset within the EEPROM to be read
1511 * @words: number of word(s)
1512 * @data: read 16 bit word(s) from EEPROM
1514 * Reads 16 bit word(s) from EEPROM through bit-bang method
1516 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1517 u16 words, u16 *data)
1521 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1524 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1526 /* Prepare the EEPROM for reading */
1527 status = ixgbe_acquire_eeprom(hw);
1529 if (status == IXGBE_SUCCESS) {
1530 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1531 ixgbe_release_eeprom(hw);
1532 status = IXGBE_ERR_EEPROM;
1536 if (status == IXGBE_SUCCESS) {
1537 for (i = 0; i < words; i++) {
1538 ixgbe_standby_eeprom(hw);
1540 * Some SPI eeproms use the 8th address bit embedded
1543 if ((hw->eeprom.address_bits == 8) &&
1544 ((offset + i) >= 128))
1545 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1547 /* Send the READ command (opcode + addr) */
1548 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1549 IXGBE_EEPROM_OPCODE_BITS);
1550 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1551 hw->eeprom.address_bits);
1553 /* Read the data. */
1554 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1555 data[i] = (word_in >> 8) | (word_in << 8);
1558 /* End this read operation */
1559 ixgbe_release_eeprom(hw);
1566 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1567 * @hw: pointer to hardware structure
1568 * @offset: offset within the EEPROM to be read
1569 * @data: read 16 bit value from EEPROM
1571 * Reads 16 bit value from EEPROM through bit-bang method
1573 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1578 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1580 hw->eeprom.ops.init_params(hw);
1582 if (offset >= hw->eeprom.word_size) {
1583 status = IXGBE_ERR_EEPROM;
1587 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1594 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1595 * @hw: pointer to hardware structure
1596 * @offset: offset of word in the EEPROM to read
1597 * @words: number of word(s)
1598 * @data: 16 bit word(s) from the EEPROM
1600 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1602 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1603 u16 words, u16 *data)
1606 s32 status = IXGBE_SUCCESS;
1609 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1611 hw->eeprom.ops.init_params(hw);
1614 status = IXGBE_ERR_INVALID_ARGUMENT;
1615 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1619 if (offset >= hw->eeprom.word_size) {
1620 status = IXGBE_ERR_EEPROM;
1621 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1625 for (i = 0; i < words; i++) {
1626 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1627 IXGBE_EEPROM_RW_REG_START;
1629 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1630 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1632 if (status == IXGBE_SUCCESS) {
1633 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1634 IXGBE_EEPROM_RW_REG_DATA);
1636 DEBUGOUT("Eeprom read timed out\n");
1645 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1646 * @hw: pointer to hardware structure
1647 * @offset: offset within the EEPROM to be used as a scratch pad
1649 * Discover EEPROM page size by writing marching data at given offset.
1650 * This function is called only when we are writing a new large buffer
1651 * at given offset so the data would be overwritten anyway.
1653 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1656 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1657 s32 status = IXGBE_SUCCESS;
1660 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1662 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1665 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1666 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1667 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1668 hw->eeprom.word_page_size = 0;
1669 if (status != IXGBE_SUCCESS)
1672 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1673 if (status != IXGBE_SUCCESS)
1677 * When writing in burst more than the actual page size
1678 * EEPROM address wraps around current page.
1680 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1682 DEBUGOUT1("Detected EEPROM page size = %d words.",
1683 hw->eeprom.word_page_size);
1689 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1690 * @hw: pointer to hardware structure
1691 * @offset: offset of word in the EEPROM to read
1692 * @data: word read from the EEPROM
1694 * Reads a 16 bit word from the EEPROM using the EERD register.
1696 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1698 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1702 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1703 * @hw: pointer to hardware structure
1704 * @offset: offset of word in the EEPROM to write
1705 * @words: number of word(s)
1706 * @data: word(s) write to the EEPROM
1708 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1710 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1711 u16 words, u16 *data)
1714 s32 status = IXGBE_SUCCESS;
1717 DEBUGFUNC("ixgbe_write_eewr_generic");
1719 hw->eeprom.ops.init_params(hw);
1722 status = IXGBE_ERR_INVALID_ARGUMENT;
1723 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1727 if (offset >= hw->eeprom.word_size) {
1728 status = IXGBE_ERR_EEPROM;
1729 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1733 for (i = 0; i < words; i++) {
1734 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1735 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1736 IXGBE_EEPROM_RW_REG_START;
1738 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1739 if (status != IXGBE_SUCCESS) {
1740 DEBUGOUT("Eeprom write EEWR timed out\n");
1744 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1746 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1747 if (status != IXGBE_SUCCESS) {
1748 DEBUGOUT("Eeprom write EEWR timed out\n");
1758 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1759 * @hw: pointer to hardware structure
1760 * @offset: offset of word in the EEPROM to write
1761 * @data: word write to the EEPROM
1763 * Write a 16 bit word to the EEPROM using the EEWR register.
1765 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1767 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1771 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1772 * @hw: pointer to hardware structure
1773 * @ee_reg: EEPROM flag for polling
1775 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1776 * read or write is done respectively.
1778 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1782 s32 status = IXGBE_ERR_EEPROM;
1784 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1786 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1787 if (ee_reg == IXGBE_NVM_POLL_READ)
1788 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1790 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1792 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1793 status = IXGBE_SUCCESS;
1799 if (i == IXGBE_EERD_EEWR_ATTEMPTS)
1800 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1801 "EEPROM read/write done polling timed out");
1807 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1808 * @hw: pointer to hardware structure
1810 * Prepares EEPROM for access using bit-bang method. This function should
1811 * be called before issuing a command to the EEPROM.
1813 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1815 s32 status = IXGBE_SUCCESS;
1819 DEBUGFUNC("ixgbe_acquire_eeprom");
1821 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1823 status = IXGBE_ERR_SWFW_SYNC;
1825 if (status == IXGBE_SUCCESS) {
1826 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1828 /* Request EEPROM Access */
1829 eec |= IXGBE_EEC_REQ;
1830 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1832 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1833 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1834 if (eec & IXGBE_EEC_GNT)
1839 /* Release if grant not acquired */
1840 if (!(eec & IXGBE_EEC_GNT)) {
1841 eec &= ~IXGBE_EEC_REQ;
1842 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1843 DEBUGOUT("Could not acquire EEPROM grant\n");
1845 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1846 status = IXGBE_ERR_EEPROM;
1849 /* Setup EEPROM for Read/Write */
1850 if (status == IXGBE_SUCCESS) {
1851 /* Clear CS and SK */
1852 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1853 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1854 IXGBE_WRITE_FLUSH(hw);
1862 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1863 * @hw: pointer to hardware structure
1865 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1867 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1869 s32 status = IXGBE_ERR_EEPROM;
1874 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1877 /* Get SMBI software semaphore between device drivers first */
1878 for (i = 0; i < timeout; i++) {
1880 * If the SMBI bit is 0 when we read it, then the bit will be
1881 * set and we have the semaphore
1883 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1884 if (!(swsm & IXGBE_SWSM_SMBI)) {
1885 status = IXGBE_SUCCESS;
1892 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1895 * this release is particularly important because our attempts
1896 * above to get the semaphore may have succeeded, and if there
1897 * was a timeout, we should unconditionally clear the semaphore
1898 * bits to free the driver to make progress
1900 ixgbe_release_eeprom_semaphore(hw);
1905 * If the SMBI bit is 0 when we read it, then the bit will be
1906 * set and we have the semaphore
1908 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1909 if (!(swsm & IXGBE_SWSM_SMBI))
1910 status = IXGBE_SUCCESS;
1913 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1914 if (status == IXGBE_SUCCESS) {
1915 for (i = 0; i < timeout; i++) {
1916 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1918 /* Set the SW EEPROM semaphore bit to request access */
1919 swsm |= IXGBE_SWSM_SWESMBI;
1920 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
1923 * If we set the bit successfully then we got the
1926 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1927 if (swsm & IXGBE_SWSM_SWESMBI)
1934 * Release semaphores and return error if SW EEPROM semaphore
1935 * was not granted because we don't have access to the EEPROM
1938 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1939 "SWESMBI Software EEPROM semaphore not granted.\n");
1940 ixgbe_release_eeprom_semaphore(hw);
1941 status = IXGBE_ERR_EEPROM;
1944 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1945 "Software semaphore SMBI between device drivers "
1953 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1954 * @hw: pointer to hardware structure
1956 * This function clears hardware semaphore bits.
1958 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1962 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1964 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1966 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1967 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1968 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1969 IXGBE_WRITE_FLUSH(hw);
1973 * ixgbe_ready_eeprom - Polls for EEPROM ready
1974 * @hw: pointer to hardware structure
1976 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1978 s32 status = IXGBE_SUCCESS;
1982 DEBUGFUNC("ixgbe_ready_eeprom");
1985 * Read "Status Register" repeatedly until the LSB is cleared. The
1986 * EEPROM will signal that the command has been completed by clearing
1987 * bit 0 of the internal status register. If it's not cleared within
1988 * 5 milliseconds, then error out.
1990 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1991 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1992 IXGBE_EEPROM_OPCODE_BITS);
1993 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1994 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1998 ixgbe_standby_eeprom(hw);
2002 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
2003 * devices (and only 0-5mSec on 5V devices)
2005 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
2006 DEBUGOUT("SPI EEPROM Status error\n");
2007 status = IXGBE_ERR_EEPROM;
2014 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
2015 * @hw: pointer to hardware structure
2017 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
2021 DEBUGFUNC("ixgbe_standby_eeprom");
2023 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2025 /* Toggle CS to flush commands */
2026 eec |= IXGBE_EEC_CS;
2027 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2028 IXGBE_WRITE_FLUSH(hw);
2030 eec &= ~IXGBE_EEC_CS;
2031 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2032 IXGBE_WRITE_FLUSH(hw);
2037 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
2038 * @hw: pointer to hardware structure
2039 * @data: data to send to the EEPROM
2040 * @count: number of bits to shift out
2042 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
2049 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
2051 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2054 * Mask is used to shift "count" bits of "data" out to the EEPROM
2055 * one bit at a time. Determine the starting bit based on count
2057 mask = 0x01 << (count - 1);
2059 for (i = 0; i < count; i++) {
2061 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
2062 * "1", and then raising and then lowering the clock (the SK
2063 * bit controls the clock input to the EEPROM). A "0" is
2064 * shifted out to the EEPROM by setting "DI" to "0" and then
2065 * raising and then lowering the clock.
2068 eec |= IXGBE_EEC_DI;
2070 eec &= ~IXGBE_EEC_DI;
2072 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2073 IXGBE_WRITE_FLUSH(hw);
2077 ixgbe_raise_eeprom_clk(hw, &eec);
2078 ixgbe_lower_eeprom_clk(hw, &eec);
2081 * Shift mask to signify next bit of data to shift in to the
2087 /* We leave the "DI" bit set to "0" when we leave this routine. */
2088 eec &= ~IXGBE_EEC_DI;
2089 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2090 IXGBE_WRITE_FLUSH(hw);
2094 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
2095 * @hw: pointer to hardware structure
2097 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
2103 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
2106 * In order to read a register from the EEPROM, we need to shift
2107 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
2108 * the clock input to the EEPROM (setting the SK bit), and then reading
2109 * the value of the "DO" bit. During this "shifting in" process the
2110 * "DI" bit should always be clear.
2112 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2114 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
2116 for (i = 0; i < count; i++) {
2118 ixgbe_raise_eeprom_clk(hw, &eec);
2120 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2122 eec &= ~(IXGBE_EEC_DI);
2123 if (eec & IXGBE_EEC_DO)
2126 ixgbe_lower_eeprom_clk(hw, &eec);
2133 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
2134 * @hw: pointer to hardware structure
2135 * @eec: EEC register's current value
2137 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2139 DEBUGFUNC("ixgbe_raise_eeprom_clk");
2142 * Raise the clock input to the EEPROM
2143 * (setting the SK bit), then delay
2145 *eec = *eec | IXGBE_EEC_SK;
2146 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2147 IXGBE_WRITE_FLUSH(hw);
2152 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2153 * @hw: pointer to hardware structure
2154 * @eecd: EECD's current value
2156 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2158 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2161 * Lower the clock input to the EEPROM (clearing the SK bit), then
2164 *eec = *eec & ~IXGBE_EEC_SK;
2165 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2166 IXGBE_WRITE_FLUSH(hw);
2171 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2172 * @hw: pointer to hardware structure
2174 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2178 DEBUGFUNC("ixgbe_release_eeprom");
2180 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2182 eec |= IXGBE_EEC_CS; /* Pull CS high */
2183 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
2185 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2186 IXGBE_WRITE_FLUSH(hw);
2190 /* Stop requesting EEPROM access */
2191 eec &= ~IXGBE_EEC_REQ;
2192 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2194 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2196 /* Delay before attempt to obtain semaphore again to allow FW access */
2197 msec_delay(hw->eeprom.semaphore_delay);
2201 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2202 * @hw: pointer to hardware structure
2204 * Returns a negative error code on error, or the 16-bit checksum
2206 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2215 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
2217 /* Include 0x0-0x3F in the checksum */
2218 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
2219 if (hw->eeprom.ops.read(hw, i, &word)) {
2220 DEBUGOUT("EEPROM read failed\n");
2221 return IXGBE_ERR_EEPROM;
2226 /* Include all data from pointers except for the fw pointer */
2227 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
2228 if (hw->eeprom.ops.read(hw, i, &pointer)) {
2229 DEBUGOUT("EEPROM read failed\n");
2230 return IXGBE_ERR_EEPROM;
2233 /* If the pointer seems invalid */
2234 if (pointer == 0xFFFF || pointer == 0)
2237 if (hw->eeprom.ops.read(hw, pointer, &length)) {
2238 DEBUGOUT("EEPROM read failed\n");
2239 return IXGBE_ERR_EEPROM;
2242 if (length == 0xFFFF || length == 0)
2245 for (j = pointer + 1; j <= pointer + length; j++) {
2246 if (hw->eeprom.ops.read(hw, j, &word)) {
2247 DEBUGOUT("EEPROM read failed\n");
2248 return IXGBE_ERR_EEPROM;
2254 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2256 return (s32)checksum;
2260 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2261 * @hw: pointer to hardware structure
2262 * @checksum_val: calculated checksum
2264 * Performs checksum calculation and validates the EEPROM checksum. If the
2265 * caller does not need checksum_val, the value can be NULL.
2267 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2272 u16 read_checksum = 0;
2274 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
2276 /* Read the first word from the EEPROM. If this times out or fails, do
2277 * not continue or we could be in for a very long wait while every
2280 status = hw->eeprom.ops.read(hw, 0, &checksum);
2282 DEBUGOUT("EEPROM read failed\n");
2286 status = hw->eeprom.ops.calc_checksum(hw);
2290 checksum = (u16)(status & 0xffff);
2292 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2294 DEBUGOUT("EEPROM read failed\n");
2298 /* Verify read checksum from EEPROM is the same as
2299 * calculated checksum
2301 if (read_checksum != checksum)
2302 status = IXGBE_ERR_EEPROM_CHECKSUM;
2304 /* If the user cares, return the calculated checksum */
2306 *checksum_val = checksum;
2312 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2313 * @hw: pointer to hardware structure
2315 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2320 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
2322 /* Read the first word from the EEPROM. If this times out or fails, do
2323 * not continue or we could be in for a very long wait while every
2326 status = hw->eeprom.ops.read(hw, 0, &checksum);
2328 DEBUGOUT("EEPROM read failed\n");
2332 status = hw->eeprom.ops.calc_checksum(hw);
2336 checksum = (u16)(status & 0xffff);
2338 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
2344 * ixgbe_validate_mac_addr - Validate MAC address
2345 * @mac_addr: pointer to MAC address.
2347 * Tests a MAC address to ensure it is a valid Individual Address.
2349 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
2351 s32 status = IXGBE_SUCCESS;
2353 DEBUGFUNC("ixgbe_validate_mac_addr");
2355 /* Make sure it is not a multicast address */
2356 if (IXGBE_IS_MULTICAST(mac_addr)) {
2357 status = IXGBE_ERR_INVALID_MAC_ADDR;
2358 /* Not a broadcast address */
2359 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
2360 status = IXGBE_ERR_INVALID_MAC_ADDR;
2361 /* Reject the zero address */
2362 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
2363 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
2364 status = IXGBE_ERR_INVALID_MAC_ADDR;
2370 * ixgbe_set_rar_generic - Set Rx address register
2371 * @hw: pointer to hardware structure
2372 * @index: Receive address register to write
2373 * @addr: Address to put into receive address register
2374 * @vmdq: VMDq "set" or "pool" index
2375 * @enable_addr: set flag that address is active
2377 * Puts an ethernet address into a receive address register.
2379 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2382 u32 rar_low, rar_high;
2383 u32 rar_entries = hw->mac.num_rar_entries;
2385 DEBUGFUNC("ixgbe_set_rar_generic");
2387 /* Make sure we are using a valid rar index range */
2388 if (index >= rar_entries) {
2389 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2390 "RAR index %d is out of range.\n", index);
2391 return IXGBE_ERR_INVALID_ARGUMENT;
2394 /* setup VMDq pool selection before this RAR gets enabled */
2395 hw->mac.ops.set_vmdq(hw, index, vmdq);
2398 * HW expects these in little endian so we reverse the byte
2399 * order from network order (big endian) to little endian
2401 rar_low = ((u32)addr[0] |
2402 ((u32)addr[1] << 8) |
2403 ((u32)addr[2] << 16) |
2404 ((u32)addr[3] << 24));
2406 * Some parts put the VMDq setting in the extra RAH bits,
2407 * so save everything except the lower 16 bits that hold part
2408 * of the address and the address valid bit.
2410 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2411 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2412 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2414 if (enable_addr != 0)
2415 rar_high |= IXGBE_RAH_AV;
2417 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2418 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2420 return IXGBE_SUCCESS;
2424 * ixgbe_clear_rar_generic - Remove Rx address register
2425 * @hw: pointer to hardware structure
2426 * @index: Receive address register to write
2428 * Clears an ethernet address from a receive address register.
2430 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2433 u32 rar_entries = hw->mac.num_rar_entries;
2435 DEBUGFUNC("ixgbe_clear_rar_generic");
2437 /* Make sure we are using a valid rar index range */
2438 if (index >= rar_entries) {
2439 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2440 "RAR index %d is out of range.\n", index);
2441 return IXGBE_ERR_INVALID_ARGUMENT;
2445 * Some parts put the VMDq setting in the extra RAH bits,
2446 * so save everything except the lower 16 bits that hold part
2447 * of the address and the address valid bit.
2449 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2450 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2452 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2453 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2455 /* clear VMDq pool/queue selection for this RAR */
2456 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2458 return IXGBE_SUCCESS;
2462 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2463 * @hw: pointer to hardware structure
2465 * Places the MAC address in receive address register 0 and clears the rest
2466 * of the receive address registers. Clears the multicast table. Assumes
2467 * the receiver is in reset when the routine is called.
2469 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2472 u32 rar_entries = hw->mac.num_rar_entries;
2474 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2477 * If the current mac address is valid, assume it is a software override
2478 * to the permanent address.
2479 * Otherwise, use the permanent address from the eeprom.
2481 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2482 IXGBE_ERR_INVALID_MAC_ADDR) {
2483 /* Get the MAC address from the RAR0 for later reference */
2484 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2486 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2487 hw->mac.addr[0], hw->mac.addr[1],
2489 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2490 hw->mac.addr[4], hw->mac.addr[5]);
2492 /* Setup the receive address. */
2493 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2494 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2495 hw->mac.addr[0], hw->mac.addr[1],
2497 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2498 hw->mac.addr[4], hw->mac.addr[5]);
2500 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2503 /* clear VMDq pool/queue selection for RAR 0 */
2504 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2506 hw->addr_ctrl.overflow_promisc = 0;
2508 hw->addr_ctrl.rar_used_count = 1;
2510 /* Zero out the other receive addresses. */
2511 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2512 for (i = 1; i < rar_entries; i++) {
2513 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2514 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2518 hw->addr_ctrl.mta_in_use = 0;
2519 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2521 DEBUGOUT(" Clearing MTA\n");
2522 for (i = 0; i < hw->mac.mcft_size; i++)
2523 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2525 ixgbe_init_uta_tables(hw);
2527 return IXGBE_SUCCESS;
2531 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2532 * @hw: pointer to hardware structure
2533 * @addr: new address
2535 * Adds it to unused receive address register or goes into promiscuous mode.
2537 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2539 u32 rar_entries = hw->mac.num_rar_entries;
2542 DEBUGFUNC("ixgbe_add_uc_addr");
2544 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2545 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2548 * Place this address in the RAR if there is room,
2549 * else put the controller into promiscuous mode
2551 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2552 rar = hw->addr_ctrl.rar_used_count;
2553 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2554 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2555 hw->addr_ctrl.rar_used_count++;
2557 hw->addr_ctrl.overflow_promisc++;
2560 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2564 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2565 * @hw: pointer to hardware structure
2566 * @addr_list: the list of new addresses
2567 * @addr_count: number of addresses
2568 * @next: iterator function to walk the address list
2570 * The given list replaces any existing list. Clears the secondary addrs from
2571 * receive address registers. Uses unused receive address registers for the
2572 * first secondary addresses, and falls back to promiscuous mode as needed.
2574 * Drivers using secondary unicast addresses must set user_set_promisc when
2575 * manually putting the device into promiscuous mode.
2577 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2578 u32 addr_count, ixgbe_mc_addr_itr next)
2582 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2587 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2590 * Clear accounting of old secondary address list,
2591 * don't count RAR[0]
2593 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2594 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2595 hw->addr_ctrl.overflow_promisc = 0;
2597 /* Zero out the other receive addresses */
2598 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2599 for (i = 0; i < uc_addr_in_use; i++) {
2600 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2601 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2604 /* Add the new addresses */
2605 for (i = 0; i < addr_count; i++) {
2606 DEBUGOUT(" Adding the secondary addresses:\n");
2607 addr = next(hw, &addr_list, &vmdq);
2608 ixgbe_add_uc_addr(hw, addr, vmdq);
2611 if (hw->addr_ctrl.overflow_promisc) {
2612 /* enable promisc if not already in overflow or set by user */
2613 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2614 DEBUGOUT(" Entering address overflow promisc mode\n");
2615 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2616 fctrl |= IXGBE_FCTRL_UPE;
2617 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2620 /* only disable if set by overflow, not by user */
2621 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2622 DEBUGOUT(" Leaving address overflow promisc mode\n");
2623 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2624 fctrl &= ~IXGBE_FCTRL_UPE;
2625 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2629 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2630 return IXGBE_SUCCESS;
2634 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2635 * @hw: pointer to hardware structure
2636 * @mc_addr: the multicast address
2638 * Extracts the 12 bits, from a multicast address, to determine which
2639 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2640 * incoming rx multicast addresses, to determine the bit-vector to check in
2641 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2642 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2643 * to mc_filter_type.
2645 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2649 DEBUGFUNC("ixgbe_mta_vector");
2651 switch (hw->mac.mc_filter_type) {
2652 case 0: /* use bits [47:36] of the address */
2653 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2655 case 1: /* use bits [46:35] of the address */
2656 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2658 case 2: /* use bits [45:34] of the address */
2659 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2661 case 3: /* use bits [43:32] of the address */
2662 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2664 default: /* Invalid mc_filter_type */
2665 DEBUGOUT("MC filter type param set incorrectly\n");
2670 /* vector can only be 12-bits or boundary will be exceeded */
2676 * ixgbe_set_mta - Set bit-vector in multicast table
2677 * @hw: pointer to hardware structure
2678 * @hash_value: Multicast address hash value
2680 * Sets the bit-vector in the multicast table.
2682 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2688 DEBUGFUNC("ixgbe_set_mta");
2690 hw->addr_ctrl.mta_in_use++;
2692 vector = ixgbe_mta_vector(hw, mc_addr);
2693 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2696 * The MTA is a register array of 128 32-bit registers. It is treated
2697 * like an array of 4096 bits. We want to set bit
2698 * BitArray[vector_value]. So we figure out what register the bit is
2699 * in, read it, OR in the new bit, then write back the new value. The
2700 * register is determined by the upper 7 bits of the vector value and
2701 * the bit within that register are determined by the lower 5 bits of
2704 vector_reg = (vector >> 5) & 0x7F;
2705 vector_bit = vector & 0x1F;
2706 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2710 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2711 * @hw: pointer to hardware structure
2712 * @mc_addr_list: the list of new multicast addresses
2713 * @mc_addr_count: number of addresses
2714 * @next: iterator function to walk the multicast address list
2715 * @clear: flag, when set clears the table beforehand
2717 * When the clear flag is set, the given list replaces any existing list.
2718 * Hashes the given addresses into the multicast table.
2720 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2721 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2727 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2730 * Set the new number of MC addresses that we are being requested to
2733 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2734 hw->addr_ctrl.mta_in_use = 0;
2736 /* Clear mta_shadow */
2738 DEBUGOUT(" Clearing MTA\n");
2739 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2742 /* Update mta_shadow */
2743 for (i = 0; i < mc_addr_count; i++) {
2744 DEBUGOUT(" Adding the multicast addresses:\n");
2745 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2749 for (i = 0; i < hw->mac.mcft_size; i++)
2750 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2751 hw->mac.mta_shadow[i]);
2753 if (hw->addr_ctrl.mta_in_use > 0)
2754 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2755 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2757 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2758 return IXGBE_SUCCESS;
2762 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2763 * @hw: pointer to hardware structure
2765 * Enables multicast address in RAR and the use of the multicast hash table.
2767 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2769 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2771 DEBUGFUNC("ixgbe_enable_mc_generic");
2773 if (a->mta_in_use > 0)
2774 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2775 hw->mac.mc_filter_type);
2777 return IXGBE_SUCCESS;
2781 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2782 * @hw: pointer to hardware structure
2784 * Disables multicast address in RAR and the use of the multicast hash table.
2786 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2788 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2790 DEBUGFUNC("ixgbe_disable_mc_generic");
2792 if (a->mta_in_use > 0)
2793 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2795 return IXGBE_SUCCESS;
2799 * ixgbe_fc_enable_generic - Enable flow control
2800 * @hw: pointer to hardware structure
2802 * Enable flow control according to the current settings.
2804 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2806 s32 ret_val = IXGBE_SUCCESS;
2807 u32 mflcn_reg, fccfg_reg;
2812 DEBUGFUNC("ixgbe_fc_enable_generic");
2814 /* Validate the water mark configuration */
2815 if (!hw->fc.pause_time) {
2816 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2820 /* Low water mark of zero causes XOFF floods */
2821 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2822 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2823 hw->fc.high_water[i]) {
2824 if (!hw->fc.low_water[i] ||
2825 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2826 DEBUGOUT("Invalid water mark configuration\n");
2827 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2833 /* Negotiate the fc mode to use */
2834 hw->mac.ops.fc_autoneg(hw);
2836 /* Disable any previous flow control settings */
2837 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2838 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2840 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2841 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2844 * The possible values of fc.current_mode are:
2845 * 0: Flow control is completely disabled
2846 * 1: Rx flow control is enabled (we can receive pause frames,
2847 * but not send pause frames).
2848 * 2: Tx flow control is enabled (we can send pause frames but
2849 * we do not support receiving pause frames).
2850 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2853 switch (hw->fc.current_mode) {
2856 * Flow control is disabled by software override or autoneg.
2857 * The code below will actually disable it in the HW.
2860 case ixgbe_fc_rx_pause:
2862 * Rx Flow control is enabled and Tx Flow control is
2863 * disabled by software override. Since there really
2864 * isn't a way to advertise that we are capable of RX
2865 * Pause ONLY, we will advertise that we support both
2866 * symmetric and asymmetric Rx PAUSE. Later, we will
2867 * disable the adapter's ability to send PAUSE frames.
2869 mflcn_reg |= IXGBE_MFLCN_RFCE;
2871 case ixgbe_fc_tx_pause:
2873 * Tx Flow control is enabled, and Rx Flow control is
2874 * disabled by software override.
2876 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2879 /* Flow control (both Rx and Tx) is enabled by SW override. */
2880 mflcn_reg |= IXGBE_MFLCN_RFCE;
2881 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2884 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2885 "Flow control param set incorrectly\n");
2886 ret_val = IXGBE_ERR_CONFIG;
2891 /* Set 802.3x based flow control settings. */
2892 mflcn_reg |= IXGBE_MFLCN_DPF;
2893 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2894 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2897 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2898 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2899 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2900 hw->fc.high_water[i]) {
2901 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2902 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2903 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2905 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2907 * In order to prevent Tx hangs when the internal Tx
2908 * switch is enabled we must set the high water mark
2909 * to the Rx packet buffer size - 24KB. This allows
2910 * the Tx switch to function even under heavy Rx
2913 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2916 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2919 /* Configure pause time (2 TCs per register) */
2920 reg = hw->fc.pause_time * 0x00010001;
2921 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2922 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2924 /* Configure flow control refresh threshold value */
2925 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2932 * ixgbe_negotiate_fc - Negotiate flow control
2933 * @hw: pointer to hardware structure
2934 * @adv_reg: flow control advertised settings
2935 * @lp_reg: link partner's flow control settings
2936 * @adv_sym: symmetric pause bit in advertisement
2937 * @adv_asm: asymmetric pause bit in advertisement
2938 * @lp_sym: symmetric pause bit in link partner advertisement
2939 * @lp_asm: asymmetric pause bit in link partner advertisement
2941 * Find the intersection between advertised settings and link partner's
2942 * advertised settings
2944 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2945 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2947 if ((!(adv_reg)) || (!(lp_reg))) {
2948 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
2949 "Local or link partner's advertised flow control "
2950 "settings are NULL. Local: %x, link partner: %x\n",
2952 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2955 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2957 * Now we need to check if the user selected Rx ONLY
2958 * of pause frames. In this case, we had to advertise
2959 * FULL flow control because we could not advertise RX
2960 * ONLY. Hence, we must now check to see if we need to
2961 * turn OFF the TRANSMISSION of PAUSE frames.
2963 if (hw->fc.requested_mode == ixgbe_fc_full) {
2964 hw->fc.current_mode = ixgbe_fc_full;
2965 DEBUGOUT("Flow Control = FULL.\n");
2967 hw->fc.current_mode = ixgbe_fc_rx_pause;
2968 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2970 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2971 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2972 hw->fc.current_mode = ixgbe_fc_tx_pause;
2973 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2974 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2975 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2976 hw->fc.current_mode = ixgbe_fc_rx_pause;
2977 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2979 hw->fc.current_mode = ixgbe_fc_none;
2980 DEBUGOUT("Flow Control = NONE.\n");
2982 return IXGBE_SUCCESS;
2986 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2987 * @hw: pointer to hardware structure
2989 * Enable flow control according on 1 gig fiber.
2991 STATIC s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2993 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2994 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2997 * On multispeed fiber at 1g, bail out if
2998 * - link is up but AN did not complete, or if
2999 * - link is up and AN completed but timed out
3002 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
3003 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
3004 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
3005 DEBUGOUT("Auto-Negotiation did not complete or timed out\n");
3009 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
3010 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
3012 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
3013 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
3014 IXGBE_PCS1GANA_ASM_PAUSE,
3015 IXGBE_PCS1GANA_SYM_PAUSE,
3016 IXGBE_PCS1GANA_ASM_PAUSE);
3023 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
3024 * @hw: pointer to hardware structure
3026 * Enable flow control according to IEEE clause 37.
3028 STATIC s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
3030 u32 links2, anlp1_reg, autoc_reg, links;
3031 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3034 * On backplane, bail out if
3035 * - backplane autoneg was not completed, or if
3036 * - we are 82599 and link partner is not AN enabled
3038 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
3039 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
3040 DEBUGOUT("Auto-Negotiation did not complete\n");
3044 if (hw->mac.type == ixgbe_mac_82599EB) {
3045 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
3046 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
3047 DEBUGOUT("Link partner is not AN enabled\n");
3052 * Read the 10g AN autoc and LP ability registers and resolve
3053 * local flow control settings accordingly
3055 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3056 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
3058 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
3059 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
3060 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
3067 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
3068 * @hw: pointer to hardware structure
3070 * Enable flow control according to IEEE clause 37.
3072 STATIC s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
3074 u16 technology_ability_reg = 0;
3075 u16 lp_technology_ability_reg = 0;
3077 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
3078 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3079 &technology_ability_reg);
3080 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
3081 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3082 &lp_technology_ability_reg);
3084 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
3085 (u32)lp_technology_ability_reg,
3086 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
3087 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
3091 * ixgbe_fc_autoneg - Configure flow control
3092 * @hw: pointer to hardware structure
3094 * Compares our advertised flow control capabilities to those advertised by
3095 * our link partner, and determines the proper flow control mode to use.
3097 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
3099 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3100 ixgbe_link_speed speed;
3103 DEBUGFUNC("ixgbe_fc_autoneg");
3106 * AN should have completed when the cable was plugged in.
3107 * Look for reasons to bail out. Bail out if:
3108 * - FC autoneg is disabled, or if
3111 if (hw->fc.disable_fc_autoneg) {
3112 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3113 "Flow control autoneg is disabled");
3117 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3119 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3123 switch (hw->phy.media_type) {
3124 /* Autoneg flow control on fiber adapters */
3125 case ixgbe_media_type_fiber_qsfp:
3126 case ixgbe_media_type_fiber:
3127 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
3128 ret_val = ixgbe_fc_autoneg_fiber(hw);
3131 /* Autoneg flow control on backplane adapters */
3132 case ixgbe_media_type_backplane:
3133 ret_val = ixgbe_fc_autoneg_backplane(hw);
3136 /* Autoneg flow control on copper adapters */
3137 case ixgbe_media_type_copper:
3138 if (ixgbe_device_supports_autoneg_fc(hw))
3139 ret_val = ixgbe_fc_autoneg_copper(hw);
3147 if (ret_val == IXGBE_SUCCESS) {
3148 hw->fc.fc_was_autonegged = true;
3150 hw->fc.fc_was_autonegged = false;
3151 hw->fc.current_mode = hw->fc.requested_mode;
3156 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3157 * @hw: pointer to hardware structure
3159 * System-wide timeout range is encoded in PCIe Device Control2 register.
3161 * Add 10% to specified maximum and return the number of times to poll for
3162 * completion timeout, in units of 100 microsec. Never return less than
3163 * 800 = 80 millisec.
3165 STATIC u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3170 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3171 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
3174 case IXGBE_PCIDEVCTRL2_65_130ms:
3175 pollcnt = 1300; /* 130 millisec */
3177 case IXGBE_PCIDEVCTRL2_260_520ms:
3178 pollcnt = 5200; /* 520 millisec */
3180 case IXGBE_PCIDEVCTRL2_1_2s:
3181 pollcnt = 20000; /* 2 sec */
3183 case IXGBE_PCIDEVCTRL2_4_8s:
3184 pollcnt = 80000; /* 8 sec */
3186 case IXGBE_PCIDEVCTRL2_17_34s:
3187 pollcnt = 34000; /* 34 sec */
3189 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
3190 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
3191 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
3192 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
3194 pollcnt = 800; /* 80 millisec minimum */
3198 /* add 10% to spec maximum */
3199 return (pollcnt * 11) / 10;
3203 * ixgbe_disable_pcie_master - Disable PCI-express master access
3204 * @hw: pointer to hardware structure
3206 * Disables PCI-Express master access and verifies there are no pending
3207 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
3208 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
3209 * is returned signifying master requests disabled.
3211 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
3213 s32 status = IXGBE_SUCCESS;
3217 DEBUGFUNC("ixgbe_disable_pcie_master");
3219 /* Always set this bit to ensure any future transactions are blocked */
3220 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3222 /* Exit if master requests are blocked */
3223 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3224 IXGBE_REMOVED(hw->hw_addr))
3227 /* Poll for master request bit to clear */
3228 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
3230 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3235 * Two consecutive resets are required via CTRL.RST per datasheet
3236 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
3237 * of this need. The first reset prevents new master requests from
3238 * being issued by our device. We then must wait 1usec or more for any
3239 * remaining completions from the PCIe bus to trickle in, and then reset
3240 * again to clear out any effects they may have had on our device.
3242 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
3243 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3245 if (hw->mac.type >= ixgbe_mac_X550)
3249 * Before proceeding, make sure that the PCIe block does not have
3250 * transactions pending.
3252 poll = ixgbe_pcie_timeout_poll(hw);
3253 for (i = 0; i < poll; i++) {
3255 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3256 if (IXGBE_REMOVED(hw->hw_addr))
3258 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3262 ERROR_REPORT1(IXGBE_ERROR_POLLING,
3263 "PCIe transaction pending bit also did not clear.\n");
3264 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
3271 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3272 * @hw: pointer to hardware structure
3273 * @mask: Mask to specify which semaphore to acquire
3275 * Acquires the SWFW semaphore through the GSSR register for the specified
3276 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3278 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3282 u32 fwmask = mask << 5;
3286 DEBUGFUNC("ixgbe_acquire_swfw_sync");
3288 for (i = 0; i < timeout; i++) {
3290 * SW NVM semaphore bit is used for access to all
3291 * SW_FW_SYNC bits (not just NVM)
3293 if (ixgbe_get_eeprom_semaphore(hw))
3294 return IXGBE_ERR_SWFW_SYNC;
3296 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3297 if (!(gssr & (fwmask | swmask))) {
3299 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3300 ixgbe_release_eeprom_semaphore(hw);
3301 return IXGBE_SUCCESS;
3303 /* Resource is currently in use by FW or SW */
3304 ixgbe_release_eeprom_semaphore(hw);
3309 /* If time expired clear the bits holding the lock and retry */
3310 if (gssr & (fwmask | swmask))
3311 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
3314 return IXGBE_ERR_SWFW_SYNC;
3318 * ixgbe_release_swfw_sync - Release SWFW semaphore
3319 * @hw: pointer to hardware structure
3320 * @mask: Mask to specify which semaphore to release
3322 * Releases the SWFW semaphore through the GSSR register for the specified
3323 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3325 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3330 DEBUGFUNC("ixgbe_release_swfw_sync");
3332 ixgbe_get_eeprom_semaphore(hw);
3334 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3336 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3338 ixgbe_release_eeprom_semaphore(hw);
3342 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3343 * @hw: pointer to hardware structure
3345 * Stops the receive data path and waits for the HW to internally empty
3346 * the Rx security block
3348 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3350 #define IXGBE_MAX_SECRX_POLL 4000
3355 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
3358 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3359 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
3360 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3361 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
3362 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3363 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
3366 /* Use interrupt-safe sleep just in case */
3370 /* For informational purposes only */
3371 if (i >= IXGBE_MAX_SECRX_POLL)
3372 DEBUGOUT("Rx unit being enabled before security "
3373 "path fully disabled. Continuing with init.\n");
3375 return IXGBE_SUCCESS;
3379 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3380 * @hw: pointer to hardware structure
3381 * @reg_val: Value we read from AUTOC
3383 * The default case requires no protection so just to the register read.
3385 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3388 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3389 return IXGBE_SUCCESS;
3393 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
3394 * @hw: pointer to hardware structure
3395 * @reg_val: value to write to AUTOC
3396 * @locked: bool to indicate whether the SW/FW lock was already taken by
3399 * The default case requires no protection so just to the register write.
3401 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
3403 UNREFERENCED_1PARAMETER(locked);
3405 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
3406 return IXGBE_SUCCESS;
3410 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3411 * @hw: pointer to hardware structure
3413 * Enables the receive data path.
3415 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3419 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
3421 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3422 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
3423 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3424 IXGBE_WRITE_FLUSH(hw);
3426 return IXGBE_SUCCESS;
3430 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3431 * @hw: pointer to hardware structure
3432 * @regval: register value to write to RXCTRL
3434 * Enables the Rx DMA unit
3436 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3438 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
3440 if (regval & IXGBE_RXCTRL_RXEN)
3441 ixgbe_enable_rx(hw);
3443 ixgbe_disable_rx(hw);
3445 return IXGBE_SUCCESS;
3449 * ixgbe_blink_led_start_generic - Blink LED based on index.
3450 * @hw: pointer to hardware structure
3451 * @index: led number to blink
3453 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3455 ixgbe_link_speed speed = 0;
3458 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3459 s32 ret_val = IXGBE_SUCCESS;
3460 bool locked = false;
3462 DEBUGFUNC("ixgbe_blink_led_start_generic");
3465 return IXGBE_ERR_PARAM;
3468 * Link must be up to auto-blink the LEDs;
3469 * Force it if link is down.
3471 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3474 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3475 if (ret_val != IXGBE_SUCCESS)
3478 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3479 autoc_reg |= IXGBE_AUTOC_FLU;
3481 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3482 if (ret_val != IXGBE_SUCCESS)
3485 IXGBE_WRITE_FLUSH(hw);
3489 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3490 led_reg |= IXGBE_LED_BLINK(index);
3491 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3492 IXGBE_WRITE_FLUSH(hw);
3499 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3500 * @hw: pointer to hardware structure
3501 * @index: led number to stop blinking
3503 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3506 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3507 s32 ret_val = IXGBE_SUCCESS;
3508 bool locked = false;
3510 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3513 return IXGBE_ERR_PARAM;
3516 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3517 if (ret_val != IXGBE_SUCCESS)
3520 autoc_reg &= ~IXGBE_AUTOC_FLU;
3521 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3523 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3524 if (ret_val != IXGBE_SUCCESS)
3527 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3528 led_reg &= ~IXGBE_LED_BLINK(index);
3529 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3530 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3531 IXGBE_WRITE_FLUSH(hw);
3538 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3539 * @hw: pointer to hardware structure
3540 * @san_mac_offset: SAN MAC address offset
3542 * This function will read the EEPROM location for the SAN MAC address
3543 * pointer, and returns the value at that location. This is used in both
3544 * get and set mac_addr routines.
3546 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3547 u16 *san_mac_offset)
3551 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3554 * First read the EEPROM pointer to see if the MAC addresses are
3557 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3560 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3561 "eeprom at offset %d failed",
3562 IXGBE_SAN_MAC_ADDR_PTR);
3569 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3570 * @hw: pointer to hardware structure
3571 * @san_mac_addr: SAN MAC address
3573 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3574 * per-port, so set_lan_id() must be called before reading the addresses.
3575 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3576 * upon for non-SFP connections, so we must call it here.
3578 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3580 u16 san_mac_data, san_mac_offset;
3584 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3587 * First read the EEPROM pointer to see if the MAC addresses are
3588 * available. If they're not, no point in calling set_lan_id() here.
3590 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3591 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3592 goto san_mac_addr_out;
3594 /* make sure we know which port we need to program */
3595 hw->mac.ops.set_lan_id(hw);
3596 /* apply the port offset to the address offset */
3597 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3598 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3599 for (i = 0; i < 3; i++) {
3600 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3603 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3604 "eeprom read at offset %d failed",
3606 goto san_mac_addr_out;
3608 san_mac_addr[i * 2] = (u8)(san_mac_data);
3609 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3612 return IXGBE_SUCCESS;
3616 * No addresses available in this EEPROM. It's not an
3617 * error though, so just wipe the local address and return.
3619 for (i = 0; i < 6; i++)
3620 san_mac_addr[i] = 0xFF;
3621 return IXGBE_SUCCESS;
3625 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3626 * @hw: pointer to hardware structure
3627 * @san_mac_addr: SAN MAC address
3629 * Write a SAN MAC address to the EEPROM.
3631 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3634 u16 san_mac_data, san_mac_offset;
3637 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3639 /* Look for SAN mac address pointer. If not defined, return */
3640 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3641 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3642 return IXGBE_ERR_NO_SAN_ADDR_PTR;
3644 /* Make sure we know which port we need to write */
3645 hw->mac.ops.set_lan_id(hw);
3646 /* Apply the port offset to the address offset */
3647 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3648 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3650 for (i = 0; i < 3; i++) {
3651 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3652 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3653 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3657 return IXGBE_SUCCESS;
3661 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3662 * @hw: pointer to hardware structure
3664 * Read PCIe configuration space, and get the MSI-X vector count from
3665 * the capabilities table.
3667 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3673 switch (hw->mac.type) {
3674 case ixgbe_mac_82598EB:
3675 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3676 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3678 case ixgbe_mac_82599EB:
3679 case ixgbe_mac_X540:
3680 case ixgbe_mac_X550:
3681 case ixgbe_mac_X550EM_x:
3682 case ixgbe_mac_X550EM_a:
3683 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3684 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3690 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3691 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3692 if (IXGBE_REMOVED(hw->hw_addr))
3694 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3696 /* MSI-X count is zero-based in HW */
3699 if (msix_count > max_msix_count)
3700 msix_count = max_msix_count;
3706 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3707 * @hw: pointer to hardware structure
3708 * @addr: Address to put into receive address register
3709 * @vmdq: VMDq pool to assign
3711 * Puts an ethernet address into a receive address register, or
3712 * finds the rar that it is aleady in; adds to the pool list
3714 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3716 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3717 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3719 u32 rar_low, rar_high;
3720 u32 addr_low, addr_high;
3722 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3724 /* swap bytes for HW little endian */
3725 addr_low = addr[0] | (addr[1] << 8)
3728 addr_high = addr[4] | (addr[5] << 8);
3731 * Either find the mac_id in rar or find the first empty space.
3732 * rar_highwater points to just after the highest currently used
3733 * rar in order to shorten the search. It grows when we add a new
3736 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3737 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3739 if (((IXGBE_RAH_AV & rar_high) == 0)
3740 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3741 first_empty_rar = rar;
3742 } else if ((rar_high & 0xFFFF) == addr_high) {
3743 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3744 if (rar_low == addr_low)
3745 break; /* found it already in the rars */
3749 if (rar < hw->mac.rar_highwater) {
3750 /* already there so just add to the pool bits */
3751 ixgbe_set_vmdq(hw, rar, vmdq);
3752 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3753 /* stick it into first empty RAR slot we found */
3754 rar = first_empty_rar;
3755 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3756 } else if (rar == hw->mac.rar_highwater) {
3757 /* add it to the top of the list and inc the highwater mark */
3758 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3759 hw->mac.rar_highwater++;
3760 } else if (rar >= hw->mac.num_rar_entries) {
3761 return IXGBE_ERR_INVALID_MAC_ADDR;
3765 * If we found rar[0], make sure the default pool bit (we use pool 0)
3766 * remains cleared to be sure default pool packets will get delivered
3769 ixgbe_clear_vmdq(hw, rar, 0);
3775 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3776 * @hw: pointer to hardware struct
3777 * @rar: receive address register index to disassociate
3778 * @vmdq: VMDq pool index to remove from the rar
3780 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3782 u32 mpsar_lo, mpsar_hi;
3783 u32 rar_entries = hw->mac.num_rar_entries;
3785 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3787 /* Make sure we are using a valid rar index range */
3788 if (rar >= rar_entries) {
3789 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3790 "RAR index %d is out of range.\n", rar);
3791 return IXGBE_ERR_INVALID_ARGUMENT;
3794 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3795 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3797 if (IXGBE_REMOVED(hw->hw_addr))
3800 if (!mpsar_lo && !mpsar_hi)
3803 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3805 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3809 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3812 } else if (vmdq < 32) {
3813 mpsar_lo &= ~(1 << vmdq);
3814 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3816 mpsar_hi &= ~(1 << (vmdq - 32));
3817 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3820 /* was that the last pool using this rar? */
3821 if (mpsar_lo == 0 && mpsar_hi == 0 &&
3822 rar != 0 && rar != hw->mac.san_mac_rar_index)
3823 hw->mac.ops.clear_rar(hw, rar);
3825 return IXGBE_SUCCESS;
3829 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3830 * @hw: pointer to hardware struct
3831 * @rar: receive address register index to associate with a VMDq index
3832 * @vmdq: VMDq pool index
3834 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3837 u32 rar_entries = hw->mac.num_rar_entries;
3839 DEBUGFUNC("ixgbe_set_vmdq_generic");
3841 /* Make sure we are using a valid rar index range */
3842 if (rar >= rar_entries) {
3843 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3844 "RAR index %d is out of range.\n", rar);
3845 return IXGBE_ERR_INVALID_ARGUMENT;
3849 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3851 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3853 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3854 mpsar |= 1 << (vmdq - 32);
3855 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3857 return IXGBE_SUCCESS;
3861 * This function should only be involved in the IOV mode.
3862 * In IOV mode, Default pool is next pool after the number of
3863 * VFs advertized and not 0.
3864 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3866 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3867 * @hw: pointer to hardware struct
3868 * @vmdq: VMDq pool index
3870 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3872 u32 rar = hw->mac.san_mac_rar_index;
3874 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3877 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3878 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3880 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3881 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3884 return IXGBE_SUCCESS;
3888 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3889 * @hw: pointer to hardware structure
3891 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3895 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3896 DEBUGOUT(" Clearing UTA\n");
3898 for (i = 0; i < 128; i++)
3899 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3901 return IXGBE_SUCCESS;
3905 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3906 * @hw: pointer to hardware structure
3907 * @vlan: VLAN id to write to VLAN filter
3909 * return the VLVF index where this VLAN id should be placed
3912 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)
3914 s32 regindex, first_empty_slot;
3917 /* short cut the special case */
3921 /* if vlvf_bypass is set we don't want to use an empty slot, we
3922 * will simply bypass the VLVF if there are no entries present in the
3923 * VLVF that contain our VLAN
3925 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0;
3927 /* add VLAN enable bit for comparison */
3928 vlan |= IXGBE_VLVF_VIEN;
3930 /* Search for the vlan id in the VLVF entries. Save off the first empty
3931 * slot found along the way.
3933 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1
3935 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) {
3936 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3939 if (!first_empty_slot && !bits)
3940 first_empty_slot = regindex;
3943 /* If we are here then we didn't find the VLAN. Return first empty
3944 * slot we found during our search, else error.
3946 if (!first_empty_slot)
3947 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "No space in VLVF.\n");
3949 return first_empty_slot ? first_empty_slot : IXGBE_ERR_NO_SPACE;
3953 * ixgbe_set_vfta_generic - Set VLAN filter table
3954 * @hw: pointer to hardware structure
3955 * @vlan: VLAN id to write to VLAN filter
3956 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
3957 * @vlan_on: boolean flag to turn on/off VLAN
3958 * @vlvf_bypass: boolean flag indicating updating default pool is okay
3960 * Turn on/off specified VLAN in the VLAN filter table.
3962 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3963 bool vlan_on, bool vlvf_bypass)
3965 u32 regidx, vfta_delta, vfta;
3968 DEBUGFUNC("ixgbe_set_vfta_generic");
3970 if (vlan > 4095 || vind > 63)
3971 return IXGBE_ERR_PARAM;
3974 * this is a 2 part operation - first the VFTA, then the
3975 * VLVF and VLVFB if VT Mode is set
3976 * We don't write the VFTA until we know the VLVF part succeeded.
3980 * The VFTA is a bitstring made up of 128 32-bit registers
3981 * that enable the particular VLAN id, much like the MTA:
3982 * bits[11-5]: which register
3983 * bits[4-0]: which bit in the register
3986 vfta_delta = 1 << (vlan % 32);
3987 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx));
3990 * vfta_delta represents the difference between the current value
3991 * of vfta and the value we want in the register. Since the diff
3992 * is an XOR mask we can just update the vfta using an XOR
3994 vfta_delta &= vlan_on ? ~vfta : vfta;
3998 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
4000 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta,
4002 if (ret_val != IXGBE_SUCCESS) {
4009 /* Update VFTA now that we are ready for traffic */
4011 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta);
4013 return IXGBE_SUCCESS;
4017 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
4018 * @hw: pointer to hardware structure
4019 * @vlan: VLAN id to write to VLAN filter
4020 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
4021 * @vlan_on: boolean flag to turn on/off VLAN in VLVF
4022 * @vfta_delta: pointer to the difference between the current value of VFTA
4023 * and the desired value
4024 * @vfta: the desired value of the VFTA
4025 * @vlvf_bypass: boolean flag indicating updating default pool is okay
4027 * Turn on/off specified bit in VLVF table.
4029 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
4030 bool vlan_on, u32 *vfta_delta, u32 vfta,
4036 DEBUGFUNC("ixgbe_set_vlvf_generic");
4038 if (vlan > 4095 || vind > 63)
4039 return IXGBE_ERR_PARAM;
4041 /* If VT Mode is set
4043 * make sure the vlan is in VLVF
4044 * set the vind bit in the matching VLVFB
4046 * clear the pool bit and possibly the vind
4048 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE))
4049 return IXGBE_SUCCESS;
4051 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
4055 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32));
4057 /* set the pool bit */
4058 bits |= 1 << (vind % 32);
4062 /* clear the pool bit */
4063 bits ^= 1 << (vind % 32);
4066 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) {
4067 /* Clear VFTA first, then disable VLVF. Otherwise
4068 * we run the risk of stray packets leaking into
4069 * the PF via the default pool
4072 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta);
4074 /* disable VLVF and clear remaining bit from pool */
4075 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
4076 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0);
4078 return IXGBE_SUCCESS;
4081 /* If there are still bits set in the VLVFB registers
4082 * for the VLAN ID indicated we need to see if the
4083 * caller is requesting that we clear the VFTA entry bit.
4084 * If the caller has requested that we clear the VFTA
4085 * entry bit but there are still pools/VFs using this VLAN
4086 * ID entry then ignore the request. We're not worried
4087 * about the case where we're turning the VFTA VLAN ID
4088 * entry bit on, only when requested to turn it off as
4089 * there may be multiple pools and/or VFs using the
4090 * VLAN ID entry. In that case we cannot clear the
4091 * VFTA bit until all pools/VFs using that VLAN ID have also
4092 * been cleared. This will be indicated by "bits" being
4098 /* record pool change and enable VLAN ID if not already enabled */
4099 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits);
4100 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan);
4102 return IXGBE_SUCCESS;
4106 * ixgbe_clear_vfta_generic - Clear VLAN filter table
4107 * @hw: pointer to hardware structure
4109 * Clears the VLAN filer table, and the VMDq index associated with the filter
4111 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
4115 DEBUGFUNC("ixgbe_clear_vfta_generic");
4117 for (offset = 0; offset < hw->mac.vft_size; offset++)
4118 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
4120 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
4121 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
4122 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
4123 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0);
4126 return IXGBE_SUCCESS;
4130 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
4131 * @hw: pointer to hardware structure
4133 * Contains the logic to identify if we need to verify link for the
4136 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw)
4139 /* Does FW say we need the fix */
4140 if (!hw->need_crosstalk_fix)
4143 /* Only consider SFP+ PHYs i.e. media type fiber */
4144 switch (hw->mac.ops.get_media_type(hw)) {
4145 case ixgbe_media_type_fiber:
4146 case ixgbe_media_type_fiber_qsfp:
4156 * ixgbe_check_mac_link_generic - Determine link and speed status
4157 * @hw: pointer to hardware structure
4158 * @speed: pointer to link speed
4159 * @link_up: true when link is up
4160 * @link_up_wait_to_complete: bool used to wait for link up or not
4162 * Reads the links register to determine if link is up and the current speed
4164 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4165 bool *link_up, bool link_up_wait_to_complete)
4167 u32 links_reg, links_orig;
4170 DEBUGFUNC("ixgbe_check_mac_link_generic");
4172 /* If Crosstalk fix enabled do the sanity check of making sure
4173 * the SFP+ cage is full.
4175 if (ixgbe_need_crosstalk_fix(hw)) {
4178 switch (hw->mac.type) {
4179 case ixgbe_mac_82599EB:
4180 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4183 case ixgbe_mac_X550EM_x:
4184 case ixgbe_mac_X550EM_a:
4185 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4189 /* sanity check - No SFP+ devices here */
4190 sfp_cage_full = false;
4194 if (!sfp_cage_full) {
4196 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4197 return IXGBE_SUCCESS;
4201 /* clear the old state */
4202 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
4204 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4206 if (links_orig != links_reg) {
4207 DEBUGOUT2("LINKS changed from %08X to %08X\n",
4208 links_orig, links_reg);
4211 if (link_up_wait_to_complete) {
4212 for (i = 0; i < hw->mac.max_link_up_time; i++) {
4213 if (links_reg & IXGBE_LINKS_UP) {
4220 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4223 if (links_reg & IXGBE_LINKS_UP)
4229 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4230 case IXGBE_LINKS_SPEED_10G_82599:
4231 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4232 if (hw->mac.type >= ixgbe_mac_X550) {
4233 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4234 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4237 case IXGBE_LINKS_SPEED_1G_82599:
4238 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4240 case IXGBE_LINKS_SPEED_100_82599:
4241 *speed = IXGBE_LINK_SPEED_100_FULL;
4242 if (hw->mac.type == ixgbe_mac_X550) {
4243 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4244 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4247 case IXGBE_LINKS_SPEED_10_X550EM_A:
4248 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4249 #ifdef PREBOOT_SUPPORT
4250 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4251 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L ||
4252 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
4253 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
4254 *speed = IXGBE_LINK_SPEED_10_FULL;
4256 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4257 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4258 *speed = IXGBE_LINK_SPEED_10_FULL;
4259 #endif /* PREBOOT_SUPPORT */
4262 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4265 return IXGBE_SUCCESS;
4269 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4271 * @hw: pointer to hardware structure
4272 * @wwnn_prefix: the alternative WWNN prefix
4273 * @wwpn_prefix: the alternative WWPN prefix
4275 * This function will read the EEPROM from the alternative SAN MAC address
4276 * block to check the support for the alternative WWNN/WWPN prefix support.
4278 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4282 u16 alt_san_mac_blk_offset;
4284 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
4286 /* clear output first */
4287 *wwnn_prefix = 0xFFFF;
4288 *wwpn_prefix = 0xFFFF;
4290 /* check if alternative SAN MAC is supported */
4291 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
4292 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4293 goto wwn_prefix_err;
4295 if ((alt_san_mac_blk_offset == 0) ||
4296 (alt_san_mac_blk_offset == 0xFFFF))
4297 goto wwn_prefix_out;
4299 /* check capability in alternative san mac address block */
4300 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
4301 if (hw->eeprom.ops.read(hw, offset, &caps))
4302 goto wwn_prefix_err;
4303 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
4304 goto wwn_prefix_out;
4306 /* get the corresponding prefix for WWNN/WWPN */
4307 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
4308 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4309 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4310 "eeprom read at offset %d failed", offset);
4313 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
4314 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4315 goto wwn_prefix_err;
4318 return IXGBE_SUCCESS;
4321 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4322 "eeprom read at offset %d failed", offset);
4323 return IXGBE_SUCCESS;
4327 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4328 * @hw: pointer to hardware structure
4329 * @bs: the fcoe boot status
4331 * This function will read the FCOE boot status from the iSCSI FCOE block
4333 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4335 u16 offset, caps, flags;
4338 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
4340 /* clear output first */
4341 *bs = ixgbe_fcoe_bootstatus_unavailable;
4343 /* check if FCOE IBA block is present */
4344 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
4345 status = hw->eeprom.ops.read(hw, offset, &caps);
4346 if (status != IXGBE_SUCCESS)
4349 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
4352 /* check if iSCSI FCOE block is populated */
4353 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4354 if (status != IXGBE_SUCCESS)
4357 if ((offset == 0) || (offset == 0xFFFF))
4360 /* read fcoe flags in iSCSI FCOE block */
4361 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
4362 status = hw->eeprom.ops.read(hw, offset, &flags);
4363 if (status != IXGBE_SUCCESS)
4366 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
4367 *bs = ixgbe_fcoe_bootstatus_enabled;
4369 *bs = ixgbe_fcoe_bootstatus_disabled;
4376 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4377 * @hw: pointer to hardware structure
4378 * @enable: enable or disable switch for MAC anti-spoofing
4379 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
4382 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4384 int vf_target_reg = vf >> 3;
4385 int vf_target_shift = vf % 8;
4388 if (hw->mac.type == ixgbe_mac_82598EB)
4391 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4393 pfvfspoof |= (1 << vf_target_shift);
4395 pfvfspoof &= ~(1 << vf_target_shift);
4396 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4400 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4401 * @hw: pointer to hardware structure
4402 * @enable: enable or disable switch for VLAN anti-spoofing
4403 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4406 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4408 int vf_target_reg = vf >> 3;
4409 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
4412 if (hw->mac.type == ixgbe_mac_82598EB)
4415 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4417 pfvfspoof |= (1 << vf_target_shift);
4419 pfvfspoof &= ~(1 << vf_target_shift);
4420 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4424 * ixgbe_get_device_caps_generic - Get additional device capabilities
4425 * @hw: pointer to hardware structure
4426 * @device_caps: the EEPROM word with the extra device capabilities
4428 * This function will read the EEPROM location for the device capabilities,
4429 * and return the word through device_caps.
4431 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4433 DEBUGFUNC("ixgbe_get_device_caps_generic");
4435 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4437 return IXGBE_SUCCESS;
4441 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4442 * @hw: pointer to hardware structure
4445 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4450 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
4452 /* Enable relaxed ordering */
4453 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4454 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4455 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4456 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4459 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4460 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4461 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
4462 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4463 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4469 * ixgbe_calculate_checksum - Calculate checksum for buffer
4470 * @buffer: pointer to EEPROM
4471 * @length: size of EEPROM to calculate a checksum for
4472 * Calculates the checksum for some buffer on a specified length. The
4473 * checksum calculated is returned.
4475 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4480 DEBUGFUNC("ixgbe_calculate_checksum");
4485 for (i = 0; i < length; i++)
4488 return (u8) (0 - sum);
4492 * ixgbe_hic_unlocked - Issue command to manageability block unlocked
4493 * @hw: pointer to the HW structure
4494 * @buffer: command to write and where the return status will be placed
4495 * @length: length of buffer, must be multiple of 4 bytes
4496 * @timeout: time in ms to wait for command completion
4498 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4499 * else returns semaphore error when encountering an error acquiring
4500 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4502 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held
4505 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length,
4511 DEBUGFUNC("ixgbe_hic_unlocked");
4513 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4514 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4515 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4518 /* Set bit 9 of FWSTS clearing FW reset indication */
4519 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
4520 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
4522 /* Check that the host interface is enabled. */
4523 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4524 if (!(hicr & IXGBE_HICR_EN)) {
4525 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
4526 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4529 /* Calculate length in DWORDs. We must be DWORD aligned */
4530 if (length % sizeof(u32)) {
4531 DEBUGOUT("Buffer length failure, not aligned to dword");
4532 return IXGBE_ERR_INVALID_ARGUMENT;
4535 dword_len = length >> 2;
4537 /* The device driver writes the relevant command block
4538 * into the ram area.
4540 for (i = 0; i < dword_len; i++)
4541 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4542 i, IXGBE_CPU_TO_LE32(buffer[i]));
4544 /* Setting this bit tells the ARC that a new command is pending. */
4545 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4547 for (i = 0; i < timeout; i++) {
4548 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4549 if (!(hicr & IXGBE_HICR_C))
4554 /* Check command completion */
4555 if ((timeout && i == timeout) ||
4556 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
4557 ERROR_REPORT1(IXGBE_ERROR_CAUTION,
4558 "Command has failed with no status valid.\n");
4559 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4562 return IXGBE_SUCCESS;
4566 * ixgbe_host_interface_command - Issue command to manageability block
4567 * @hw: pointer to the HW structure
4568 * @buffer: contains the command to write and where the return status will
4570 * @length: length of buffer, must be multiple of 4 bytes
4571 * @timeout: time in ms to wait for command completion
4572 * @return_data: read and return data from the buffer (true) or not (false)
4573 * Needed because FW structures are big endian and decoding of
4574 * these fields can be 8 bit or 16 bit based on command. Decoding
4575 * is not easily understood without making a table of commands.
4576 * So we will leave this up to the caller to read back the data
4579 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4580 * else returns semaphore error when encountering an error acquiring
4581 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4583 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4584 u32 length, u32 timeout, bool return_data)
4586 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4587 struct ixgbe_hic_hdr *resp = (struct ixgbe_hic_hdr *)buffer;
4593 DEBUGFUNC("ixgbe_host_interface_command");
4595 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4596 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4597 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4600 /* Take management host interface semaphore */
4601 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4605 status = ixgbe_hic_unlocked(hw, buffer, length, timeout);
4612 /* Calculate length in DWORDs */
4613 dword_len = hdr_size >> 2;
4615 /* first pull in the header so we know the buffer length */
4616 for (bi = 0; bi < dword_len; bi++) {
4617 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4618 IXGBE_LE32_TO_CPUS((uintptr_t)&buffer[bi]);
4622 * If there is any thing in data position pull it in
4623 * Read Flash command requires reading buffer length from
4624 * two byes instead of one byte
4626 if (resp->cmd == 0x30) {
4627 for (; bi < dword_len + 2; bi++) {
4628 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4630 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4632 buf_len = (((u16)(resp->cmd_or_resp.ret_status) << 3)
4633 & 0xF00) | resp->buf_len;
4634 hdr_size += (2 << 2);
4636 buf_len = resp->buf_len;
4641 if (length < buf_len + hdr_size) {
4642 DEBUGOUT("Buffer not large enough for reply message.\n");
4643 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4647 /* Calculate length in DWORDs, add 3 for odd lengths */
4648 dword_len = (buf_len + 3) >> 2;
4650 /* Pull in the rest of the buffer (bi is where we left off) */
4651 for (; bi <= dword_len; bi++) {
4652 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4653 IXGBE_LE32_TO_CPUS((uintptr_t)&buffer[bi]);
4657 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4663 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4664 * @hw: pointer to the HW structure
4665 * @maj: driver version major number
4666 * @min: driver version minor number
4667 * @build: driver version build number
4668 * @sub: driver version sub build number
4670 * Sends driver version number to firmware through the manageability
4671 * block. On success return IXGBE_SUCCESS
4672 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4673 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4675 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4676 u8 build, u8 sub, u16 len,
4677 const char *driver_ver)
4679 struct ixgbe_hic_drv_info fw_cmd;
4681 s32 ret_val = IXGBE_SUCCESS;
4683 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4684 UNREFERENCED_2PARAMETER(len, driver_ver);
4686 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4687 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4688 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4689 fw_cmd.port_num = (u8)hw->bus.func;
4690 fw_cmd.ver_maj = maj;
4691 fw_cmd.ver_min = min;
4692 fw_cmd.ver_build = build;
4693 fw_cmd.ver_sub = sub;
4694 fw_cmd.hdr.checksum = 0;
4697 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4698 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4700 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4701 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4703 IXGBE_HI_COMMAND_TIMEOUT,
4705 if (ret_val != IXGBE_SUCCESS)
4708 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4709 FW_CEM_RESP_STATUS_SUCCESS)
4710 ret_val = IXGBE_SUCCESS;
4712 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4721 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4722 * @hw: pointer to hardware structure
4723 * @num_pb: number of packet buffers to allocate
4724 * @headroom: reserve n KB of headroom
4725 * @strategy: packet buffer allocation strategy
4727 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4730 u32 pbsize = hw->mac.rx_pb_size;
4732 u32 rxpktsize, txpktsize, txpbthresh;
4734 /* Reserve headroom */
4740 /* Divide remaining packet buffer space amongst the number of packet
4741 * buffers requested using supplied strategy.
4744 case PBA_STRATEGY_WEIGHTED:
4745 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4746 * buffer with 5/8 of the packet buffer space.
4748 rxpktsize = (pbsize * 5) / (num_pb * 4);
4749 pbsize -= rxpktsize * (num_pb / 2);
4750 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4751 for (; i < (num_pb / 2); i++)
4752 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4753 /* fall through - configure remaining packet buffers */
4754 case PBA_STRATEGY_EQUAL:
4755 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4756 for (; i < num_pb; i++)
4757 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4763 /* Only support an equally distributed Tx packet buffer strategy. */
4764 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4765 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4766 for (i = 0; i < num_pb; i++) {
4767 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4768 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4771 /* Clear unused TCs, if any, to zero buffer size*/
4772 for (; i < IXGBE_MAX_PB; i++) {
4773 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4774 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4775 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4780 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4781 * @hw: pointer to the hardware structure
4783 * The 82599 and x540 MACs can experience issues if TX work is still pending
4784 * when a reset occurs. This function prevents this by flushing the PCIe
4785 * buffers on the system.
4787 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4789 u32 gcr_ext, hlreg0, i, poll;
4793 * If double reset is not requested then all transactions should
4794 * already be clear and as such there is no work to do
4796 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4800 * Set loopback enable to prevent any transmits from being sent
4801 * should the link come up. This assumes that the RXCTRL.RXEN bit
4802 * has already been cleared.
4804 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4805 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4807 /* Wait for a last completion before clearing buffers */
4808 IXGBE_WRITE_FLUSH(hw);
4812 * Before proceeding, make sure that the PCIe block does not have
4813 * transactions pending.
4815 poll = ixgbe_pcie_timeout_poll(hw);
4816 for (i = 0; i < poll; i++) {
4818 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
4819 if (IXGBE_REMOVED(hw->hw_addr))
4821 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
4826 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4827 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4828 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4829 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4831 /* Flush all writes and allow 20usec for all transactions to clear */
4832 IXGBE_WRITE_FLUSH(hw);
4835 /* restore previous register values */
4836 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4837 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4840 STATIC const u8 ixgbe_emc_temp_data[4] = {
4841 IXGBE_EMC_INTERNAL_DATA,
4842 IXGBE_EMC_DIODE1_DATA,
4843 IXGBE_EMC_DIODE2_DATA,
4844 IXGBE_EMC_DIODE3_DATA
4846 STATIC const u8 ixgbe_emc_therm_limit[4] = {
4847 IXGBE_EMC_INTERNAL_THERM_LIMIT,
4848 IXGBE_EMC_DIODE1_THERM_LIMIT,
4849 IXGBE_EMC_DIODE2_THERM_LIMIT,
4850 IXGBE_EMC_DIODE3_THERM_LIMIT
4854 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
4855 * @hw: pointer to hardware structure
4856 * @data: pointer to the thermal sensor data structure
4858 * Returns the thermal sensor data structure
4860 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
4862 s32 status = IXGBE_SUCCESS;
4870 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4872 DEBUGFUNC("ixgbe_get_thermal_sensor_data_generic");
4874 /* Only support thermal sensors attached to 82599 physical port 0 */
4875 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4876 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
4877 status = IXGBE_NOT_IMPLEMENTED;
4881 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);
4885 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) {
4886 status = IXGBE_NOT_IMPLEMENTED;
4890 status = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);
4894 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4895 != IXGBE_ETS_TYPE_EMC) {
4896 status = IXGBE_NOT_IMPLEMENTED;
4900 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4901 if (num_sensors > IXGBE_MAX_SENSORS)
4902 num_sensors = IXGBE_MAX_SENSORS;
4904 for (i = 0; i < num_sensors; i++) {
4905 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
4910 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4911 IXGBE_ETS_DATA_INDEX_SHIFT);
4912 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4913 IXGBE_ETS_DATA_LOC_SHIFT);
4915 if (sensor_location != 0) {
4916 status = hw->phy.ops.read_i2c_byte(hw,
4917 ixgbe_emc_temp_data[sensor_index],
4918 IXGBE_I2C_THERMAL_SENSOR_ADDR,
4919 &data->sensor[i].temp);
4929 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
4930 * @hw: pointer to hardware structure
4932 * Inits the thermal sensor thresholds according to the NVM map
4933 * and save off the threshold and location values into mac.thermal_sensor_data
4935 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
4937 s32 status = IXGBE_SUCCESS;
4942 u8 low_thresh_delta;
4948 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4950 DEBUGFUNC("ixgbe_init_thermal_sensor_thresh_generic");
4952 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
4954 /* Only support thermal sensors attached to 82599 physical port 0 */
4955 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4956 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
4957 return IXGBE_NOT_IMPLEMENTED;
4959 offset = IXGBE_ETS_CFG;
4960 if (hw->eeprom.ops.read(hw, offset, &ets_offset))
4962 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
4963 return IXGBE_NOT_IMPLEMENTED;
4965 offset = ets_offset;
4966 if (hw->eeprom.ops.read(hw, offset, &ets_cfg))
4968 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4969 != IXGBE_ETS_TYPE_EMC)
4970 return IXGBE_NOT_IMPLEMENTED;
4972 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
4973 IXGBE_ETS_LTHRES_DELTA_SHIFT);
4974 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4976 for (i = 0; i < num_sensors; i++) {
4977 offset = ets_offset + 1 + i;
4978 if (hw->eeprom.ops.read(hw, offset, &ets_sensor)) {
4979 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4980 "eeprom read at offset %d failed",
4984 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4985 IXGBE_ETS_DATA_INDEX_SHIFT);
4986 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4987 IXGBE_ETS_DATA_LOC_SHIFT);
4988 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
4990 hw->phy.ops.write_i2c_byte(hw,
4991 ixgbe_emc_therm_limit[sensor_index],
4992 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
4994 if ((i < IXGBE_MAX_SENSORS) && (sensor_location != 0)) {
4995 data->sensor[i].location = sensor_location;
4996 data->sensor[i].caution_thresh = therm_limit;
4997 data->sensor[i].max_op_thresh = therm_limit -
5004 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
5005 "eeprom read at offset %d failed", offset);
5006 return IXGBE_NOT_IMPLEMENTED;
5010 * ixgbe_get_orom_version - Return option ROM from EEPROM
5012 * @hw: pointer to hardware structure
5013 * @nvm_ver: pointer to output structure
5015 * if valid option ROM version, nvm_ver->or_valid set to true
5016 * else nvm_ver->or_valid is false.
5018 void ixgbe_get_orom_version(struct ixgbe_hw *hw,
5019 struct ixgbe_nvm_version *nvm_ver)
5021 u16 offset, eeprom_cfg_blkh, eeprom_cfg_blkl;
5023 nvm_ver->or_valid = false;
5024 /* Option Rom may or may not be present. Start with pointer */
5025 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset);
5027 /* make sure offset is valid */
5028 if ((offset == 0x0) || (offset == NVM_INVALID_PTR))
5031 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh);
5032 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl);
5034 /* option rom exists and is valid */
5035 if ((eeprom_cfg_blkl | eeprom_cfg_blkh) == 0x0 ||
5036 eeprom_cfg_blkl == NVM_VER_INVALID ||
5037 eeprom_cfg_blkh == NVM_VER_INVALID)
5040 nvm_ver->or_valid = true;
5041 nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT;
5042 nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) |
5043 (eeprom_cfg_blkh >> NVM_OROM_SHIFT);
5044 nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK;
5048 * ixgbe_get_oem_prod_version - Return OEM Product version
5050 * @hw: pointer to hardware structure
5051 * @nvm_ver: pointer to output structure
5053 * if valid OEM product version, nvm_ver->oem_valid set to true
5054 * else nvm_ver->oem_valid is false.
5056 void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw,
5057 struct ixgbe_nvm_version *nvm_ver)
5059 u16 rel_num, prod_ver, mod_len, cap, offset;
5061 nvm_ver->oem_valid = false;
5062 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset);
5064 /* Return is offset to OEM Product Version block is invalid */
5065 if (offset == 0x0 && offset == NVM_INVALID_PTR)
5068 /* Read product version block */
5069 hw->eeprom.ops.read(hw, offset, &mod_len);
5070 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap);
5072 /* Return if OEM product version block is invalid */
5073 if (mod_len != NVM_OEM_PROD_VER_MOD_LEN ||
5074 (cap & NVM_OEM_PROD_VER_CAP_MASK) != 0x0)
5077 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver);
5078 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num);
5080 /* Return if version is invalid */
5081 if ((rel_num | prod_ver) == 0x0 ||
5082 rel_num == NVM_VER_INVALID || prod_ver == NVM_VER_INVALID)
5085 nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT;
5086 nvm_ver->oem_minor = prod_ver & NVM_VER_MASK;
5087 nvm_ver->oem_release = rel_num;
5088 nvm_ver->oem_valid = true;
5092 * ixgbe_get_etk_id - Return Etrack ID from EEPROM
5094 * @hw: pointer to hardware structure
5095 * @nvm_ver: pointer to output structure
5097 * word read errors will return 0xFFFF
5099 void ixgbe_get_etk_id(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver)
5101 u16 etk_id_l, etk_id_h;
5103 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l))
5104 etk_id_l = NVM_VER_INVALID;
5105 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h))
5106 etk_id_h = NVM_VER_INVALID;
5108 /* The word order for the version format is determined by high order
5111 if ((etk_id_h & NVM_ETK_VALID) == 0) {
5112 nvm_ver->etk_id = etk_id_h;
5113 nvm_ver->etk_id |= (etk_id_l << NVM_ETK_SHIFT);
5115 nvm_ver->etk_id = etk_id_l;
5116 nvm_ver->etk_id |= (etk_id_h << NVM_ETK_SHIFT);
5122 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
5123 * @hw: pointer to hardware structure
5124 * @map: pointer to u8 arr for returning map
5126 * Read the rtrup2tc HW register and resolve its content into map
5128 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
5132 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
5133 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
5134 map[i] = IXGBE_RTRUP2TC_UP_MASK &
5135 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
5139 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
5144 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5145 if (rxctrl & IXGBE_RXCTRL_RXEN) {
5146 if (hw->mac.type != ixgbe_mac_82598EB) {
5147 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5148 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
5149 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
5150 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
5151 hw->mac.set_lben = true;
5153 hw->mac.set_lben = false;
5156 rxctrl &= ~IXGBE_RXCTRL_RXEN;
5157 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
5161 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
5166 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5167 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
5169 if (hw->mac.type != ixgbe_mac_82598EB) {
5170 if (hw->mac.set_lben) {
5171 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5172 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
5173 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
5174 hw->mac.set_lben = false;
5180 * ixgbe_mng_present - returns true when management capability is present
5181 * @hw: pointer to hardware structure
5183 bool ixgbe_mng_present(struct ixgbe_hw *hw)
5187 if (hw->mac.type < ixgbe_mac_82599EB)
5190 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5192 return !!(fwsm & IXGBE_FWSM_FW_MODE_PT);
5196 * ixgbe_mng_enabled - Is the manageability engine enabled?
5197 * @hw: pointer to hardware structure
5199 * Returns true if the manageability engine is enabled.
5201 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
5203 u32 fwsm, manc, factps;
5205 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5206 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
5209 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
5210 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
5213 if (hw->mac.type <= ixgbe_mac_X540) {
5214 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
5215 if (factps & IXGBE_FACTPS_MNGCG)
5223 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
5224 * @hw: pointer to hardware structure
5225 * @speed: new link speed
5226 * @autoneg_wait_to_complete: true when waiting for completion is needed
5228 * Set the link speed in the MAC and/or PHY register and restarts link.
5230 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
5231 ixgbe_link_speed speed,
5232 bool autoneg_wait_to_complete)
5234 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
5235 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
5236 s32 status = IXGBE_SUCCESS;
5239 bool autoneg, link_up = false;
5241 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
5243 /* Mask off requested but non-supported speeds */
5244 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
5245 if (status != IXGBE_SUCCESS)
5248 speed &= link_speed;
5250 /* Try each speed one by one, highest priority first. We do this in
5251 * software because 10Gb fiber doesn't support speed autonegotiation.
5253 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
5255 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5257 /* Set the module link speed */
5258 switch (hw->phy.media_type) {
5259 case ixgbe_media_type_fiber:
5260 ixgbe_set_rate_select_speed(hw,
5261 IXGBE_LINK_SPEED_10GB_FULL);
5263 case ixgbe_media_type_fiber_qsfp:
5264 /* QSFP module automatically detects MAC link speed */
5267 DEBUGOUT("Unexpected media type.\n");
5271 /* Allow module to change analog characteristics (1G->10G) */
5274 status = ixgbe_setup_mac_link(hw,
5275 IXGBE_LINK_SPEED_10GB_FULL,
5276 autoneg_wait_to_complete);
5277 if (status != IXGBE_SUCCESS)
5280 /* Flap the Tx laser if it has not already been done */
5281 ixgbe_flap_tx_laser(hw);
5283 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
5284 * Section 73.10.2, we may have to wait up to 500ms if KR is
5285 * attempted. 82599 uses the same timing for 10g SFI.
5287 for (i = 0; i < 5; i++) {
5288 /* Wait for the link partner to also set speed */
5291 /* If we have link, just jump out */
5292 status = ixgbe_check_link(hw, &link_speed,
5294 if (status != IXGBE_SUCCESS)
5302 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
5304 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
5305 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
5307 /* Set the module link speed */
5308 switch (hw->phy.media_type) {
5309 case ixgbe_media_type_fiber:
5310 ixgbe_set_rate_select_speed(hw,
5311 IXGBE_LINK_SPEED_1GB_FULL);
5313 case ixgbe_media_type_fiber_qsfp:
5314 /* QSFP module automatically detects link speed */
5317 DEBUGOUT("Unexpected media type.\n");
5321 /* Allow module to change analog characteristics (10G->1G) */
5324 status = ixgbe_setup_mac_link(hw,
5325 IXGBE_LINK_SPEED_1GB_FULL,
5326 autoneg_wait_to_complete);
5327 if (status != IXGBE_SUCCESS)
5330 /* Flap the Tx laser if it has not already been done */
5331 ixgbe_flap_tx_laser(hw);
5333 /* Wait for the link partner to also set speed */
5336 /* If we have link, just jump out */
5337 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
5338 if (status != IXGBE_SUCCESS)
5345 /* We didn't get link. Configure back to the highest speed we tried,
5346 * (if there was more than one). We call ourselves back with just the
5347 * single highest speed that the user requested.
5350 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
5352 autoneg_wait_to_complete);
5355 /* Set autoneg_advertised value based on input link speed */
5356 hw->phy.autoneg_advertised = 0;
5358 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
5359 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
5361 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
5362 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
5368 * ixgbe_set_soft_rate_select_speed - Set module link speed
5369 * @hw: pointer to hardware structure
5370 * @speed: link speed to set
5372 * Set module link speed via the soft rate select.
5374 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
5375 ixgbe_link_speed speed)
5381 case IXGBE_LINK_SPEED_10GB_FULL:
5382 /* one bit mask same as setting on */
5383 rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
5385 case IXGBE_LINK_SPEED_1GB_FULL:
5386 rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
5389 DEBUGOUT("Invalid fixed module speed\n");
5394 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5395 IXGBE_I2C_EEPROM_DEV_ADDR2,
5398 DEBUGOUT("Failed to read Rx Rate Select RS0\n");
5402 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5404 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5405 IXGBE_I2C_EEPROM_DEV_ADDR2,
5408 DEBUGOUT("Failed to write Rx Rate Select RS0\n");
5413 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5414 IXGBE_I2C_EEPROM_DEV_ADDR2,
5417 DEBUGOUT("Failed to read Rx Rate Select RS1\n");
5421 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5423 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5424 IXGBE_I2C_EEPROM_DEV_ADDR2,
5427 DEBUGOUT("Failed to write Rx Rate Select RS1\n");