1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
36 #include "ixgbe_dcb.h"
37 #include "ixgbe_dcb_82599.h"
38 #include "ixgbe_api.h"
40 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
41 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
42 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
43 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
44 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
45 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
47 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
48 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
49 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
50 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw);
52 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
53 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
55 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
56 u16 words, u16 *data);
57 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
58 u16 words, u16 *data);
59 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
63 * ixgbe_init_ops_generic - Inits function ptrs
64 * @hw: pointer to the hardware structure
66 * Initialize the function pointers.
68 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
70 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
71 struct ixgbe_mac_info *mac = &hw->mac;
72 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
74 DEBUGFUNC("ixgbe_init_ops_generic");
77 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic;
78 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
79 if (eec & IXGBE_EEC_PRES) {
80 eeprom->ops.read = ixgbe_read_eerd_generic;
81 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic;
83 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic;
84 eeprom->ops.read_buffer =
85 ixgbe_read_eeprom_buffer_bit_bang_generic;
87 eeprom->ops.write = ixgbe_write_eeprom_generic;
88 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic;
89 eeprom->ops.validate_checksum =
90 ixgbe_validate_eeprom_checksum_generic;
91 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic;
92 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic;
95 mac->ops.init_hw = ixgbe_init_hw_generic;
96 mac->ops.reset_hw = NULL;
97 mac->ops.start_hw = ixgbe_start_hw_generic;
98 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic;
99 mac->ops.get_media_type = NULL;
100 mac->ops.get_supported_physical_layer = NULL;
101 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic;
102 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic;
103 mac->ops.stop_adapter = ixgbe_stop_adapter_generic;
104 mac->ops.get_bus_info = ixgbe_get_bus_info_generic;
105 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie;
106 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync;
107 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync;
108 mac->ops.prot_autoc_read = prot_autoc_read_generic;
109 mac->ops.prot_autoc_write = prot_autoc_write_generic;
112 mac->ops.led_on = ixgbe_led_on_generic;
113 mac->ops.led_off = ixgbe_led_off_generic;
114 mac->ops.blink_led_start = ixgbe_blink_led_start_generic;
115 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic;
116 mac->ops.init_led_link_act = ixgbe_init_led_link_act_generic;
118 /* RAR, Multicast, VLAN */
119 mac->ops.set_rar = ixgbe_set_rar_generic;
120 mac->ops.clear_rar = ixgbe_clear_rar_generic;
121 mac->ops.insert_mac_addr = NULL;
122 mac->ops.set_vmdq = NULL;
123 mac->ops.clear_vmdq = NULL;
124 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic;
125 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic;
126 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic;
127 mac->ops.enable_mc = ixgbe_enable_mc_generic;
128 mac->ops.disable_mc = ixgbe_disable_mc_generic;
129 mac->ops.clear_vfta = NULL;
130 mac->ops.set_vfta = NULL;
131 mac->ops.set_vlvf = NULL;
132 mac->ops.init_uta_tables = NULL;
133 mac->ops.enable_rx = ixgbe_enable_rx_generic;
134 mac->ops.disable_rx = ixgbe_disable_rx_generic;
137 mac->ops.fc_enable = ixgbe_fc_enable_generic;
138 mac->ops.setup_fc = ixgbe_setup_fc_generic;
139 mac->ops.fc_autoneg = ixgbe_fc_autoneg;
142 mac->ops.get_link_capabilities = NULL;
143 mac->ops.setup_link = NULL;
144 mac->ops.check_link = NULL;
145 mac->ops.dmac_config = NULL;
146 mac->ops.dmac_update_tcs = NULL;
147 mac->ops.dmac_config_tcs = NULL;
149 return IXGBE_SUCCESS;
153 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
155 * @hw: pointer to hardware structure
157 * This function returns true if the device supports flow control
158 * autonegotiation, and false if it does not.
161 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
163 bool supported = false;
164 ixgbe_link_speed speed;
167 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
169 switch (hw->phy.media_type) {
170 case ixgbe_media_type_fiber_qsfp:
171 case ixgbe_media_type_fiber:
172 /* flow control autoneg black list */
173 switch (hw->device_id) {
174 case IXGBE_DEV_ID_X550EM_A_SFP:
175 case IXGBE_DEV_ID_X550EM_A_SFP_N:
176 case IXGBE_DEV_ID_X550EM_A_QSFP:
177 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
181 hw->mac.ops.check_link(hw, &speed, &link_up, false);
182 /* if link is down, assume supported */
184 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
191 case ixgbe_media_type_backplane:
192 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI)
197 case ixgbe_media_type_copper:
198 /* only some copper devices support flow control autoneg */
199 switch (hw->device_id) {
200 case IXGBE_DEV_ID_82599_T3_LOM:
201 case IXGBE_DEV_ID_X540T:
202 case IXGBE_DEV_ID_X540T1:
203 case IXGBE_DEV_ID_X550T:
204 case IXGBE_DEV_ID_X550T1:
205 case IXGBE_DEV_ID_X550EM_X_10G_T:
206 case IXGBE_DEV_ID_X550EM_A_10G_T:
207 case IXGBE_DEV_ID_X550EM_A_1G_T:
208 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
219 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
220 "Device %x does not support flow control autoneg",
226 * ixgbe_setup_fc_generic - Set up flow control
227 * @hw: pointer to hardware structure
229 * Called at init time to set up flow control.
231 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
233 s32 ret_val = IXGBE_SUCCESS;
234 u32 reg = 0, reg_bp = 0;
238 DEBUGFUNC("ixgbe_setup_fc_generic");
240 /* Validate the requested mode */
241 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
242 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
243 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
244 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
249 * 10gig parts do not have a word in the EEPROM to determine the
250 * default flow control setting, so we explicitly set it to full.
252 if (hw->fc.requested_mode == ixgbe_fc_default)
253 hw->fc.requested_mode = ixgbe_fc_full;
256 * Set up the 1G and 10G flow control advertisement registers so the
257 * HW will be able to do fc autoneg once the cable is plugged in. If
258 * we link at 10G, the 1G advertisement is harmless and vice versa.
260 switch (hw->phy.media_type) {
261 case ixgbe_media_type_backplane:
262 /* some MAC's need RMW protection on AUTOC */
263 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
264 if (ret_val != IXGBE_SUCCESS)
267 /* fall through - only backplane uses autoc */
268 case ixgbe_media_type_fiber_qsfp:
269 case ixgbe_media_type_fiber:
270 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
273 case ixgbe_media_type_copper:
274 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
275 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
282 * The possible values of fc.requested_mode are:
283 * 0: Flow control is completely disabled
284 * 1: Rx flow control is enabled (we can receive pause frames,
285 * but not send pause frames).
286 * 2: Tx flow control is enabled (we can send pause frames but
287 * we do not support receiving pause frames).
288 * 3: Both Rx and Tx flow control (symmetric) are enabled.
291 switch (hw->fc.requested_mode) {
293 /* Flow control completely disabled by software override. */
294 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
295 if (hw->phy.media_type == ixgbe_media_type_backplane)
296 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
297 IXGBE_AUTOC_ASM_PAUSE);
298 else if (hw->phy.media_type == ixgbe_media_type_copper)
299 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
301 case ixgbe_fc_tx_pause:
303 * Tx Flow control is enabled, and Rx Flow control is
304 * disabled by software override.
306 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
307 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
308 if (hw->phy.media_type == ixgbe_media_type_backplane) {
309 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
310 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
311 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
312 reg_cu |= IXGBE_TAF_ASM_PAUSE;
313 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
316 case ixgbe_fc_rx_pause:
318 * Rx Flow control is enabled and Tx Flow control is
319 * disabled by software override. Since there really
320 * isn't a way to advertise that we are capable of RX
321 * Pause ONLY, we will advertise that we support both
322 * symmetric and asymmetric Rx PAUSE, as such we fall
323 * through to the fc_full statement. Later, we will
324 * disable the adapter's ability to send PAUSE frames.
327 /* Flow control (both Rx and Tx) is enabled by SW override. */
328 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
329 if (hw->phy.media_type == ixgbe_media_type_backplane)
330 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
331 IXGBE_AUTOC_ASM_PAUSE;
332 else if (hw->phy.media_type == ixgbe_media_type_copper)
333 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
336 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
337 "Flow control param set incorrectly\n");
338 ret_val = IXGBE_ERR_CONFIG;
343 if (hw->mac.type < ixgbe_mac_X540) {
345 * Enable auto-negotiation between the MAC & PHY;
346 * the MAC will advertise clause 37 flow control.
348 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
349 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
351 /* Disable AN timeout */
352 if (hw->fc.strict_ieee)
353 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
355 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
356 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
360 * AUTOC restart handles negotiation of 1G and 10G on backplane
361 * and copper. There is no need to set the PCS1GCTL register.
364 if (hw->phy.media_type == ixgbe_media_type_backplane) {
365 reg_bp |= IXGBE_AUTOC_AN_RESTART;
366 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
369 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
370 (ixgbe_device_supports_autoneg_fc(hw))) {
371 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
372 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
375 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
381 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
382 * @hw: pointer to hardware structure
384 * Starts the hardware by filling the bus info structure and media type, clears
385 * all on chip counters, initializes receive address registers, multicast
386 * table, VLAN filter table, calls routine to set up link and flow control
387 * settings, and leaves transmit and receive units disabled and uninitialized
389 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
395 DEBUGFUNC("ixgbe_start_hw_generic");
397 /* Set the media type */
398 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
400 /* PHY ops initialization must be done in reset_hw() */
402 /* Clear the VLAN filter table */
403 hw->mac.ops.clear_vfta(hw);
405 /* Clear statistics registers */
406 hw->mac.ops.clear_hw_cntrs(hw);
408 /* Set No Snoop Disable */
409 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
410 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
411 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
412 IXGBE_WRITE_FLUSH(hw);
414 /* Setup flow control */
415 ret_val = ixgbe_setup_fc(hw);
416 if (ret_val != IXGBE_SUCCESS && ret_val != IXGBE_NOT_IMPLEMENTED) {
417 DEBUGOUT1("Flow control setup failed, returning %d\n", ret_val);
421 /* Cache bit indicating need for crosstalk fix */
422 switch (hw->mac.type) {
423 case ixgbe_mac_82599EB:
424 case ixgbe_mac_X550EM_x:
425 case ixgbe_mac_X550EM_a:
426 hw->mac.ops.get_device_caps(hw, &device_caps);
427 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
428 hw->need_crosstalk_fix = false;
430 hw->need_crosstalk_fix = true;
433 hw->need_crosstalk_fix = false;
437 /* Clear adapter stopped flag */
438 hw->adapter_stopped = false;
440 return IXGBE_SUCCESS;
444 * ixgbe_start_hw_gen2 - Init sequence for common device family
445 * @hw: pointer to hw structure
447 * Performs the init sequence common to the second generation
449 * Devices in the second generation:
453 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
458 /* Clear the rate limiters */
459 for (i = 0; i < hw->mac.max_tx_queues; i++) {
460 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
461 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
463 IXGBE_WRITE_FLUSH(hw);
465 /* Disable relaxed ordering */
466 for (i = 0; i < hw->mac.max_tx_queues; i++) {
467 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
468 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
469 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
472 for (i = 0; i < hw->mac.max_rx_queues; i++) {
473 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
474 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
475 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
476 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
479 return IXGBE_SUCCESS;
483 * ixgbe_init_hw_generic - Generic hardware initialization
484 * @hw: pointer to hardware structure
486 * Initialize the hardware by resetting the hardware, filling the bus info
487 * structure and media type, clears all on chip counters, initializes receive
488 * address registers, multicast table, VLAN filter table, calls routine to set
489 * up link and flow control settings, and leaves transmit and receive units
490 * disabled and uninitialized
492 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
496 DEBUGFUNC("ixgbe_init_hw_generic");
498 /* Reset the hardware */
499 status = hw->mac.ops.reset_hw(hw);
501 if (status == IXGBE_SUCCESS || status == IXGBE_ERR_SFP_NOT_PRESENT) {
503 status = hw->mac.ops.start_hw(hw);
506 /* Initialize the LED link active for LED blink support */
507 if (hw->mac.ops.init_led_link_act)
508 hw->mac.ops.init_led_link_act(hw);
510 if (status != IXGBE_SUCCESS)
511 DEBUGOUT1("Failed to initialize HW, STATUS = %d\n", status);
517 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
518 * @hw: pointer to hardware structure
520 * Clears all hardware statistics counters by reading them from the hardware
521 * Statistics counters are clear on read.
523 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
527 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
529 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
530 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
531 IXGBE_READ_REG(hw, IXGBE_ERRBC);
532 IXGBE_READ_REG(hw, IXGBE_MSPDC);
533 for (i = 0; i < 8; i++)
534 IXGBE_READ_REG(hw, IXGBE_MPC(i));
536 IXGBE_READ_REG(hw, IXGBE_MLFC);
537 IXGBE_READ_REG(hw, IXGBE_MRFC);
538 IXGBE_READ_REG(hw, IXGBE_RLEC);
539 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
540 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
541 if (hw->mac.type >= ixgbe_mac_82599EB) {
542 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
543 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
545 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
546 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
549 for (i = 0; i < 8; i++) {
550 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
551 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
552 if (hw->mac.type >= ixgbe_mac_82599EB) {
553 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
554 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
556 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
557 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
560 if (hw->mac.type >= ixgbe_mac_82599EB)
561 for (i = 0; i < 8; i++)
562 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
563 IXGBE_READ_REG(hw, IXGBE_PRC64);
564 IXGBE_READ_REG(hw, IXGBE_PRC127);
565 IXGBE_READ_REG(hw, IXGBE_PRC255);
566 IXGBE_READ_REG(hw, IXGBE_PRC511);
567 IXGBE_READ_REG(hw, IXGBE_PRC1023);
568 IXGBE_READ_REG(hw, IXGBE_PRC1522);
569 IXGBE_READ_REG(hw, IXGBE_GPRC);
570 IXGBE_READ_REG(hw, IXGBE_BPRC);
571 IXGBE_READ_REG(hw, IXGBE_MPRC);
572 IXGBE_READ_REG(hw, IXGBE_GPTC);
573 IXGBE_READ_REG(hw, IXGBE_GORCL);
574 IXGBE_READ_REG(hw, IXGBE_GORCH);
575 IXGBE_READ_REG(hw, IXGBE_GOTCL);
576 IXGBE_READ_REG(hw, IXGBE_GOTCH);
577 if (hw->mac.type == ixgbe_mac_82598EB)
578 for (i = 0; i < 8; i++)
579 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
580 IXGBE_READ_REG(hw, IXGBE_RUC);
581 IXGBE_READ_REG(hw, IXGBE_RFC);
582 IXGBE_READ_REG(hw, IXGBE_ROC);
583 IXGBE_READ_REG(hw, IXGBE_RJC);
584 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
585 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
586 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
587 IXGBE_READ_REG(hw, IXGBE_TORL);
588 IXGBE_READ_REG(hw, IXGBE_TORH);
589 IXGBE_READ_REG(hw, IXGBE_TPR);
590 IXGBE_READ_REG(hw, IXGBE_TPT);
591 IXGBE_READ_REG(hw, IXGBE_PTC64);
592 IXGBE_READ_REG(hw, IXGBE_PTC127);
593 IXGBE_READ_REG(hw, IXGBE_PTC255);
594 IXGBE_READ_REG(hw, IXGBE_PTC511);
595 IXGBE_READ_REG(hw, IXGBE_PTC1023);
596 IXGBE_READ_REG(hw, IXGBE_PTC1522);
597 IXGBE_READ_REG(hw, IXGBE_MPTC);
598 IXGBE_READ_REG(hw, IXGBE_BPTC);
599 for (i = 0; i < 16; i++) {
600 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
601 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
602 if (hw->mac.type >= ixgbe_mac_82599EB) {
603 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
604 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
605 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
606 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
607 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
609 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
610 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
614 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
616 ixgbe_identify_phy(hw);
617 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
618 IXGBE_MDIO_PCS_DEV_TYPE, &i);
619 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
620 IXGBE_MDIO_PCS_DEV_TYPE, &i);
621 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
622 IXGBE_MDIO_PCS_DEV_TYPE, &i);
623 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
624 IXGBE_MDIO_PCS_DEV_TYPE, &i);
627 return IXGBE_SUCCESS;
631 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
632 * @hw: pointer to hardware structure
633 * @pba_num: stores the part number string from the EEPROM
634 * @pba_num_size: part number string buffer length
636 * Reads the part number string from the EEPROM.
638 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
647 DEBUGFUNC("ixgbe_read_pba_string_generic");
649 if (pba_num == NULL) {
650 DEBUGOUT("PBA string buffer was null\n");
651 return IXGBE_ERR_INVALID_ARGUMENT;
654 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
656 DEBUGOUT("NVM Read Error\n");
660 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
662 DEBUGOUT("NVM Read Error\n");
667 * if data is not ptr guard the PBA must be in legacy format which
668 * means pba_ptr is actually our second data word for the PBA number
669 * and we can decode it into an ascii string
671 if (data != IXGBE_PBANUM_PTR_GUARD) {
672 DEBUGOUT("NVM PBA number is not stored as string\n");
674 /* we will need 11 characters to store the PBA */
675 if (pba_num_size < 11) {
676 DEBUGOUT("PBA string buffer too small\n");
677 return IXGBE_ERR_NO_SPACE;
680 /* extract hex string from data and pba_ptr */
681 pba_num[0] = (data >> 12) & 0xF;
682 pba_num[1] = (data >> 8) & 0xF;
683 pba_num[2] = (data >> 4) & 0xF;
684 pba_num[3] = data & 0xF;
685 pba_num[4] = (pba_ptr >> 12) & 0xF;
686 pba_num[5] = (pba_ptr >> 8) & 0xF;
689 pba_num[8] = (pba_ptr >> 4) & 0xF;
690 pba_num[9] = pba_ptr & 0xF;
692 /* put a null character on the end of our string */
695 /* switch all the data but the '-' to hex char */
696 for (offset = 0; offset < 10; offset++) {
697 if (pba_num[offset] < 0xA)
698 pba_num[offset] += '0';
699 else if (pba_num[offset] < 0x10)
700 pba_num[offset] += 'A' - 0xA;
703 return IXGBE_SUCCESS;
706 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
708 DEBUGOUT("NVM Read Error\n");
712 if (length == 0xFFFF || length == 0) {
713 DEBUGOUT("NVM PBA number section invalid length\n");
714 return IXGBE_ERR_PBA_SECTION;
717 /* check if pba_num buffer is big enough */
718 if (pba_num_size < (((u32)length * 2) - 1)) {
719 DEBUGOUT("PBA string buffer too small\n");
720 return IXGBE_ERR_NO_SPACE;
723 /* trim pba length from start of string */
727 for (offset = 0; offset < length; offset++) {
728 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
730 DEBUGOUT("NVM Read Error\n");
733 pba_num[offset * 2] = (u8)(data >> 8);
734 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
736 pba_num[offset * 2] = '\0';
738 return IXGBE_SUCCESS;
742 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
743 * @hw: pointer to hardware structure
744 * @pba_num: stores the part number from the EEPROM
746 * Reads the part number from the EEPROM.
748 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
753 DEBUGFUNC("ixgbe_read_pba_num_generic");
755 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
757 DEBUGOUT("NVM Read Error\n");
759 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
760 DEBUGOUT("NVM Not supported\n");
761 return IXGBE_NOT_IMPLEMENTED;
763 *pba_num = (u32)(data << 16);
765 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
767 DEBUGOUT("NVM Read Error\n");
772 return IXGBE_SUCCESS;
777 * @hw: pointer to the HW structure
778 * @eeprom_buf: optional pointer to EEPROM image
779 * @eeprom_buf_size: size of EEPROM image in words
780 * @max_pba_block_size: PBA block size limit
781 * @pba: pointer to output PBA structure
783 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
784 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
787 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
788 u32 eeprom_buf_size, u16 max_pba_block_size,
789 struct ixgbe_pba *pba)
795 return IXGBE_ERR_PARAM;
797 if (eeprom_buf == NULL) {
798 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
803 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
804 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
805 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
807 return IXGBE_ERR_PARAM;
811 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
812 if (pba->pba_block == NULL)
813 return IXGBE_ERR_PARAM;
815 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
821 if (pba_block_size > max_pba_block_size)
822 return IXGBE_ERR_PARAM;
824 if (eeprom_buf == NULL) {
825 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
831 if (eeprom_buf_size > (u32)(pba->word[1] +
833 memcpy(pba->pba_block,
834 &eeprom_buf[pba->word[1]],
835 pba_block_size * sizeof(u16));
837 return IXGBE_ERR_PARAM;
842 return IXGBE_SUCCESS;
846 * ixgbe_write_pba_raw
847 * @hw: pointer to the HW structure
848 * @eeprom_buf: optional pointer to EEPROM image
849 * @eeprom_buf_size: size of EEPROM image in words
850 * @pba: pointer to PBA structure
852 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
853 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
856 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
857 u32 eeprom_buf_size, struct ixgbe_pba *pba)
862 return IXGBE_ERR_PARAM;
864 if (eeprom_buf == NULL) {
865 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
870 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
871 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
872 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
874 return IXGBE_ERR_PARAM;
878 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
879 if (pba->pba_block == NULL)
880 return IXGBE_ERR_PARAM;
882 if (eeprom_buf == NULL) {
883 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
889 if (eeprom_buf_size > (u32)(pba->word[1] +
890 pba->pba_block[0])) {
891 memcpy(&eeprom_buf[pba->word[1]],
893 pba->pba_block[0] * sizeof(u16));
895 return IXGBE_ERR_PARAM;
900 return IXGBE_SUCCESS;
904 * ixgbe_get_pba_block_size
905 * @hw: pointer to the HW structure
906 * @eeprom_buf: optional pointer to EEPROM image
907 * @eeprom_buf_size: size of EEPROM image in words
908 * @pba_data_size: pointer to output variable
910 * Returns the size of the PBA block in words. Function operates on EEPROM
911 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
915 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
916 u32 eeprom_buf_size, u16 *pba_block_size)
922 DEBUGFUNC("ixgbe_get_pba_block_size");
924 if (eeprom_buf == NULL) {
925 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
930 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
931 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
932 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
934 return IXGBE_ERR_PARAM;
938 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
939 if (eeprom_buf == NULL) {
940 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
945 if (eeprom_buf_size > pba_word[1])
946 length = eeprom_buf[pba_word[1] + 0];
948 return IXGBE_ERR_PARAM;
951 if (length == 0xFFFF || length == 0)
952 return IXGBE_ERR_PBA_SECTION;
954 /* PBA number in legacy format, there is no PBA Block. */
958 if (pba_block_size != NULL)
959 *pba_block_size = length;
961 return IXGBE_SUCCESS;
965 * ixgbe_get_mac_addr_generic - Generic get MAC address
966 * @hw: pointer to hardware structure
967 * @mac_addr: Adapter MAC address
969 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
970 * A reset of the adapter must be performed prior to calling this function
971 * in order for the MAC address to have been loaded from the EEPROM into RAR0
973 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
979 DEBUGFUNC("ixgbe_get_mac_addr_generic");
981 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
982 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
984 for (i = 0; i < 4; i++)
985 mac_addr[i] = (u8)(rar_low >> (i*8));
987 for (i = 0; i < 2; i++)
988 mac_addr[i+4] = (u8)(rar_high >> (i*8));
990 return IXGBE_SUCCESS;
994 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
995 * @hw: pointer to hardware structure
996 * @link_status: the link status returned by the PCI config space
998 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
1000 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
1002 struct ixgbe_mac_info *mac = &hw->mac;
1004 if (hw->bus.type == ixgbe_bus_type_unknown)
1005 hw->bus.type = ixgbe_bus_type_pci_express;
1007 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
1008 case IXGBE_PCI_LINK_WIDTH_1:
1009 hw->bus.width = ixgbe_bus_width_pcie_x1;
1011 case IXGBE_PCI_LINK_WIDTH_2:
1012 hw->bus.width = ixgbe_bus_width_pcie_x2;
1014 case IXGBE_PCI_LINK_WIDTH_4:
1015 hw->bus.width = ixgbe_bus_width_pcie_x4;
1017 case IXGBE_PCI_LINK_WIDTH_8:
1018 hw->bus.width = ixgbe_bus_width_pcie_x8;
1021 hw->bus.width = ixgbe_bus_width_unknown;
1025 switch (link_status & IXGBE_PCI_LINK_SPEED) {
1026 case IXGBE_PCI_LINK_SPEED_2500:
1027 hw->bus.speed = ixgbe_bus_speed_2500;
1029 case IXGBE_PCI_LINK_SPEED_5000:
1030 hw->bus.speed = ixgbe_bus_speed_5000;
1032 case IXGBE_PCI_LINK_SPEED_8000:
1033 hw->bus.speed = ixgbe_bus_speed_8000;
1036 hw->bus.speed = ixgbe_bus_speed_unknown;
1040 mac->ops.set_lan_id(hw);
1044 * ixgbe_get_bus_info_generic - Generic set PCI bus info
1045 * @hw: pointer to hardware structure
1047 * Gets the PCI bus info (speed, width, type) then calls helper function to
1048 * store this data within the ixgbe_hw structure.
1050 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
1054 DEBUGFUNC("ixgbe_get_bus_info_generic");
1056 /* Get the negotiated link width and speed from PCI config space */
1057 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
1059 ixgbe_set_pci_config_data_generic(hw, link_status);
1061 return IXGBE_SUCCESS;
1065 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
1066 * @hw: pointer to the HW structure
1068 * Determines the LAN function id by reading memory-mapped registers and swaps
1069 * the port value if requested, and set MAC instance for devices that share
1072 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
1074 struct ixgbe_bus_info *bus = &hw->bus;
1078 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
1080 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
1081 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
1082 bus->lan_id = (u8)bus->func;
1084 /* check for a port swap */
1085 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
1086 if (reg & IXGBE_FACTPS_LFS)
1089 /* Get MAC instance from EEPROM for configuring CS4227 */
1090 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) {
1091 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4);
1092 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >>
1093 IXGBE_EE_CTRL_4_INST_ID_SHIFT;
1098 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1099 * @hw: pointer to hardware structure
1101 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
1102 * disables transmit and receive units. The adapter_stopped flag is used by
1103 * the shared code and drivers to determine if the adapter is in a stopped
1104 * state and should not touch the hardware.
1106 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1111 DEBUGFUNC("ixgbe_stop_adapter_generic");
1114 * Set the adapter_stopped flag so other driver functions stop touching
1117 hw->adapter_stopped = true;
1119 /* Disable the receive unit */
1120 ixgbe_disable_rx(hw);
1122 /* Clear interrupt mask to stop interrupts from being generated */
1123 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1125 /* Clear any pending interrupts, flush previous writes */
1126 IXGBE_READ_REG(hw, IXGBE_EICR);
1128 /* Disable the transmit unit. Each queue must be disabled. */
1129 for (i = 0; i < hw->mac.max_tx_queues; i++)
1130 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1132 /* Disable the receive unit by stopping each queue */
1133 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1134 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1135 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1136 reg_val |= IXGBE_RXDCTL_SWFLSH;
1137 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1140 /* flush all queues disables */
1141 IXGBE_WRITE_FLUSH(hw);
1145 * Prevent the PCI-E bus from hanging by disabling PCI-E master
1146 * access and verify no pending requests
1148 return ixgbe_disable_pcie_master(hw);
1152 * ixgbe_init_led_link_act_generic - Store the LED index link/activity.
1153 * @hw: pointer to hardware structure
1155 * Store the index for the link active LED. This will be used to support
1158 s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw)
1160 struct ixgbe_mac_info *mac = &hw->mac;
1161 u32 led_reg, led_mode;
1164 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1166 /* Get LED link active from the LEDCTL register */
1167 for (i = 0; i < 4; i++) {
1168 led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i);
1170 if ((led_mode & IXGBE_LED_MODE_MASK_BASE) ==
1171 IXGBE_LED_LINK_ACTIVE) {
1172 mac->led_link_act = i;
1173 return IXGBE_SUCCESS;
1178 * If LEDCTL register does not have the LED link active set, then use
1179 * known MAC defaults.
1181 switch (hw->mac.type) {
1182 case ixgbe_mac_X550EM_a:
1183 case ixgbe_mac_X550EM_x:
1184 mac->led_link_act = 1;
1187 mac->led_link_act = 2;
1189 return IXGBE_SUCCESS;
1193 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1194 * @hw: pointer to hardware structure
1195 * @index: led number to turn on
1197 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1199 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1201 DEBUGFUNC("ixgbe_led_on_generic");
1204 return IXGBE_ERR_PARAM;
1206 /* To turn on the LED, set mode to ON. */
1207 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1208 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
1209 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1210 IXGBE_WRITE_FLUSH(hw);
1212 return IXGBE_SUCCESS;
1216 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1217 * @hw: pointer to hardware structure
1218 * @index: led number to turn off
1220 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1222 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1224 DEBUGFUNC("ixgbe_led_off_generic");
1227 return IXGBE_ERR_PARAM;
1229 /* To turn off the LED, set mode to OFF. */
1230 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1231 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
1232 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1233 IXGBE_WRITE_FLUSH(hw);
1235 return IXGBE_SUCCESS;
1239 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1240 * @hw: pointer to hardware structure
1242 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1243 * ixgbe_hw struct in order to set up EEPROM access.
1245 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1247 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1251 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
1253 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1254 eeprom->type = ixgbe_eeprom_none;
1255 /* Set default semaphore delay to 10ms which is a well
1257 eeprom->semaphore_delay = 10;
1258 /* Clear EEPROM page size, it will be initialized as needed */
1259 eeprom->word_page_size = 0;
1262 * Check for EEPROM present first.
1263 * If not present leave as none
1265 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1266 if (eec & IXGBE_EEC_PRES) {
1267 eeprom->type = ixgbe_eeprom_spi;
1270 * SPI EEPROM is assumed here. This code would need to
1271 * change if a future EEPROM is not SPI.
1273 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1274 IXGBE_EEC_SIZE_SHIFT);
1275 eeprom->word_size = 1 << (eeprom_size +
1276 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1279 if (eec & IXGBE_EEC_ADDR_SIZE)
1280 eeprom->address_bits = 16;
1282 eeprom->address_bits = 8;
1283 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
1284 "%d\n", eeprom->type, eeprom->word_size,
1285 eeprom->address_bits);
1288 return IXGBE_SUCCESS;
1292 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1293 * @hw: pointer to hardware structure
1294 * @offset: offset within the EEPROM to write
1295 * @words: number of word(s)
1296 * @data: 16 bit word(s) to write to EEPROM
1298 * Reads 16 bit word(s) from EEPROM through bit-bang method
1300 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1301 u16 words, u16 *data)
1303 s32 status = IXGBE_SUCCESS;
1306 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
1308 hw->eeprom.ops.init_params(hw);
1311 status = IXGBE_ERR_INVALID_ARGUMENT;
1315 if (offset + words > hw->eeprom.word_size) {
1316 status = IXGBE_ERR_EEPROM;
1321 * The EEPROM page size cannot be queried from the chip. We do lazy
1322 * initialization. It is worth to do that when we write large buffer.
1324 if ((hw->eeprom.word_page_size == 0) &&
1325 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
1326 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1329 * We cannot hold synchronization semaphores for too long
1330 * to avoid other entity starvation. However it is more efficient
1331 * to read in bursts than synchronizing access for each word.
1333 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1334 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1335 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1336 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1339 if (status != IXGBE_SUCCESS)
1348 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1349 * @hw: pointer to hardware structure
1350 * @offset: offset within the EEPROM to be written to
1351 * @words: number of word(s)
1352 * @data: 16 bit word(s) to be written to the EEPROM
1354 * If ixgbe_eeprom_update_checksum is not called after this function, the
1355 * EEPROM will most likely contain an invalid checksum.
1357 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1358 u16 words, u16 *data)
1364 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1366 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1368 /* Prepare the EEPROM for writing */
1369 status = ixgbe_acquire_eeprom(hw);
1371 if (status == IXGBE_SUCCESS) {
1372 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1373 ixgbe_release_eeprom(hw);
1374 status = IXGBE_ERR_EEPROM;
1378 if (status == IXGBE_SUCCESS) {
1379 for (i = 0; i < words; i++) {
1380 ixgbe_standby_eeprom(hw);
1382 /* Send the WRITE ENABLE command (8 bit opcode ) */
1383 ixgbe_shift_out_eeprom_bits(hw,
1384 IXGBE_EEPROM_WREN_OPCODE_SPI,
1385 IXGBE_EEPROM_OPCODE_BITS);
1387 ixgbe_standby_eeprom(hw);
1390 * Some SPI eeproms use the 8th address bit embedded
1393 if ((hw->eeprom.address_bits == 8) &&
1394 ((offset + i) >= 128))
1395 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1397 /* Send the Write command (8-bit opcode + addr) */
1398 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1399 IXGBE_EEPROM_OPCODE_BITS);
1400 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1401 hw->eeprom.address_bits);
1403 page_size = hw->eeprom.word_page_size;
1405 /* Send the data in burst via SPI*/
1408 word = (word >> 8) | (word << 8);
1409 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1414 /* do not wrap around page */
1415 if (((offset + i) & (page_size - 1)) ==
1418 } while (++i < words);
1420 ixgbe_standby_eeprom(hw);
1423 /* Done with writing - release the EEPROM */
1424 ixgbe_release_eeprom(hw);
1431 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1432 * @hw: pointer to hardware structure
1433 * @offset: offset within the EEPROM to be written to
1434 * @data: 16 bit word to be written to the EEPROM
1436 * If ixgbe_eeprom_update_checksum is not called after this function, the
1437 * EEPROM will most likely contain an invalid checksum.
1439 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1443 DEBUGFUNC("ixgbe_write_eeprom_generic");
1445 hw->eeprom.ops.init_params(hw);
1447 if (offset >= hw->eeprom.word_size) {
1448 status = IXGBE_ERR_EEPROM;
1452 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1459 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1460 * @hw: pointer to hardware structure
1461 * @offset: offset within the EEPROM to be read
1462 * @data: read 16 bit words(s) from EEPROM
1463 * @words: number of word(s)
1465 * Reads 16 bit word(s) from EEPROM through bit-bang method
1467 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1468 u16 words, u16 *data)
1470 s32 status = IXGBE_SUCCESS;
1473 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1475 hw->eeprom.ops.init_params(hw);
1478 status = IXGBE_ERR_INVALID_ARGUMENT;
1482 if (offset + words > hw->eeprom.word_size) {
1483 status = IXGBE_ERR_EEPROM;
1488 * We cannot hold synchronization semaphores for too long
1489 * to avoid other entity starvation. However it is more efficient
1490 * to read in bursts than synchronizing access for each word.
1492 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1493 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1494 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1496 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1499 if (status != IXGBE_SUCCESS)
1508 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1509 * @hw: pointer to hardware structure
1510 * @offset: offset within the EEPROM to be read
1511 * @words: number of word(s)
1512 * @data: read 16 bit word(s) from EEPROM
1514 * Reads 16 bit word(s) from EEPROM through bit-bang method
1516 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1517 u16 words, u16 *data)
1521 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1524 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1526 /* Prepare the EEPROM for reading */
1527 status = ixgbe_acquire_eeprom(hw);
1529 if (status == IXGBE_SUCCESS) {
1530 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1531 ixgbe_release_eeprom(hw);
1532 status = IXGBE_ERR_EEPROM;
1536 if (status == IXGBE_SUCCESS) {
1537 for (i = 0; i < words; i++) {
1538 ixgbe_standby_eeprom(hw);
1540 * Some SPI eeproms use the 8th address bit embedded
1543 if ((hw->eeprom.address_bits == 8) &&
1544 ((offset + i) >= 128))
1545 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1547 /* Send the READ command (opcode + addr) */
1548 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1549 IXGBE_EEPROM_OPCODE_BITS);
1550 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1551 hw->eeprom.address_bits);
1553 /* Read the data. */
1554 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1555 data[i] = (word_in >> 8) | (word_in << 8);
1558 /* End this read operation */
1559 ixgbe_release_eeprom(hw);
1566 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1567 * @hw: pointer to hardware structure
1568 * @offset: offset within the EEPROM to be read
1569 * @data: read 16 bit value from EEPROM
1571 * Reads 16 bit value from EEPROM through bit-bang method
1573 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1578 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1580 hw->eeprom.ops.init_params(hw);
1582 if (offset >= hw->eeprom.word_size) {
1583 status = IXGBE_ERR_EEPROM;
1587 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1594 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1595 * @hw: pointer to hardware structure
1596 * @offset: offset of word in the EEPROM to read
1597 * @words: number of word(s)
1598 * @data: 16 bit word(s) from the EEPROM
1600 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1602 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1603 u16 words, u16 *data)
1606 s32 status = IXGBE_SUCCESS;
1609 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1611 hw->eeprom.ops.init_params(hw);
1614 status = IXGBE_ERR_INVALID_ARGUMENT;
1615 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1619 if (offset >= hw->eeprom.word_size) {
1620 status = IXGBE_ERR_EEPROM;
1621 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1625 for (i = 0; i < words; i++) {
1626 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1627 IXGBE_EEPROM_RW_REG_START;
1629 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1630 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1632 if (status == IXGBE_SUCCESS) {
1633 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1634 IXGBE_EEPROM_RW_REG_DATA);
1636 DEBUGOUT("Eeprom read timed out\n");
1645 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1646 * @hw: pointer to hardware structure
1647 * @offset: offset within the EEPROM to be used as a scratch pad
1649 * Discover EEPROM page size by writing marching data at given offset.
1650 * This function is called only when we are writing a new large buffer
1651 * at given offset so the data would be overwritten anyway.
1653 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1656 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1657 s32 status = IXGBE_SUCCESS;
1660 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1662 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1665 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1666 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1667 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1668 hw->eeprom.word_page_size = 0;
1669 if (status != IXGBE_SUCCESS)
1672 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1673 if (status != IXGBE_SUCCESS)
1677 * When writing in burst more than the actual page size
1678 * EEPROM address wraps around current page.
1680 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1682 DEBUGOUT1("Detected EEPROM page size = %d words.",
1683 hw->eeprom.word_page_size);
1689 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1690 * @hw: pointer to hardware structure
1691 * @offset: offset of word in the EEPROM to read
1692 * @data: word read from the EEPROM
1694 * Reads a 16 bit word from the EEPROM using the EERD register.
1696 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1698 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1702 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1703 * @hw: pointer to hardware structure
1704 * @offset: offset of word in the EEPROM to write
1705 * @words: number of word(s)
1706 * @data: word(s) write to the EEPROM
1708 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1710 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1711 u16 words, u16 *data)
1714 s32 status = IXGBE_SUCCESS;
1717 DEBUGFUNC("ixgbe_write_eewr_generic");
1719 hw->eeprom.ops.init_params(hw);
1722 status = IXGBE_ERR_INVALID_ARGUMENT;
1723 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1727 if (offset >= hw->eeprom.word_size) {
1728 status = IXGBE_ERR_EEPROM;
1729 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1733 for (i = 0; i < words; i++) {
1734 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1735 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1736 IXGBE_EEPROM_RW_REG_START;
1738 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1739 if (status != IXGBE_SUCCESS) {
1740 DEBUGOUT("Eeprom write EEWR timed out\n");
1744 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1746 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1747 if (status != IXGBE_SUCCESS) {
1748 DEBUGOUT("Eeprom write EEWR timed out\n");
1758 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1759 * @hw: pointer to hardware structure
1760 * @offset: offset of word in the EEPROM to write
1761 * @data: word write to the EEPROM
1763 * Write a 16 bit word to the EEPROM using the EEWR register.
1765 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1767 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1771 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1772 * @hw: pointer to hardware structure
1773 * @ee_reg: EEPROM flag for polling
1775 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1776 * read or write is done respectively.
1778 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1782 s32 status = IXGBE_ERR_EEPROM;
1784 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1786 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1787 if (ee_reg == IXGBE_NVM_POLL_READ)
1788 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1790 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1792 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1793 status = IXGBE_SUCCESS;
1799 if (i == IXGBE_EERD_EEWR_ATTEMPTS)
1800 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1801 "EEPROM read/write done polling timed out");
1807 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1808 * @hw: pointer to hardware structure
1810 * Prepares EEPROM for access using bit-bang method. This function should
1811 * be called before issuing a command to the EEPROM.
1813 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1815 s32 status = IXGBE_SUCCESS;
1819 DEBUGFUNC("ixgbe_acquire_eeprom");
1821 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1823 status = IXGBE_ERR_SWFW_SYNC;
1825 if (status == IXGBE_SUCCESS) {
1826 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1828 /* Request EEPROM Access */
1829 eec |= IXGBE_EEC_REQ;
1830 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1832 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1833 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1834 if (eec & IXGBE_EEC_GNT)
1839 /* Release if grant not acquired */
1840 if (!(eec & IXGBE_EEC_GNT)) {
1841 eec &= ~IXGBE_EEC_REQ;
1842 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1843 DEBUGOUT("Could not acquire EEPROM grant\n");
1845 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1846 status = IXGBE_ERR_EEPROM;
1849 /* Setup EEPROM for Read/Write */
1850 if (status == IXGBE_SUCCESS) {
1851 /* Clear CS and SK */
1852 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1853 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1854 IXGBE_WRITE_FLUSH(hw);
1862 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1863 * @hw: pointer to hardware structure
1865 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1867 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1869 s32 status = IXGBE_ERR_EEPROM;
1874 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1877 /* Get SMBI software semaphore between device drivers first */
1878 for (i = 0; i < timeout; i++) {
1880 * If the SMBI bit is 0 when we read it, then the bit will be
1881 * set and we have the semaphore
1883 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1884 if (!(swsm & IXGBE_SWSM_SMBI)) {
1885 status = IXGBE_SUCCESS;
1892 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1895 * this release is particularly important because our attempts
1896 * above to get the semaphore may have succeeded, and if there
1897 * was a timeout, we should unconditionally clear the semaphore
1898 * bits to free the driver to make progress
1900 ixgbe_release_eeprom_semaphore(hw);
1905 * If the SMBI bit is 0 when we read it, then the bit will be
1906 * set and we have the semaphore
1908 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1909 if (!(swsm & IXGBE_SWSM_SMBI))
1910 status = IXGBE_SUCCESS;
1913 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1914 if (status == IXGBE_SUCCESS) {
1915 for (i = 0; i < timeout; i++) {
1916 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1918 /* Set the SW EEPROM semaphore bit to request access */
1919 swsm |= IXGBE_SWSM_SWESMBI;
1920 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
1923 * If we set the bit successfully then we got the
1926 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1927 if (swsm & IXGBE_SWSM_SWESMBI)
1934 * Release semaphores and return error if SW EEPROM semaphore
1935 * was not granted because we don't have access to the EEPROM
1938 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1939 "SWESMBI Software EEPROM semaphore not granted.\n");
1940 ixgbe_release_eeprom_semaphore(hw);
1941 status = IXGBE_ERR_EEPROM;
1944 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1945 "Software semaphore SMBI between device drivers "
1953 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1954 * @hw: pointer to hardware structure
1956 * This function clears hardware semaphore bits.
1958 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1962 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1964 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1966 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1967 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1968 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1969 IXGBE_WRITE_FLUSH(hw);
1973 * ixgbe_ready_eeprom - Polls for EEPROM ready
1974 * @hw: pointer to hardware structure
1976 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1978 s32 status = IXGBE_SUCCESS;
1982 DEBUGFUNC("ixgbe_ready_eeprom");
1985 * Read "Status Register" repeatedly until the LSB is cleared. The
1986 * EEPROM will signal that the command has been completed by clearing
1987 * bit 0 of the internal status register. If it's not cleared within
1988 * 5 milliseconds, then error out.
1990 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1991 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1992 IXGBE_EEPROM_OPCODE_BITS);
1993 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1994 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1998 ixgbe_standby_eeprom(hw);
2002 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
2003 * devices (and only 0-5mSec on 5V devices)
2005 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
2006 DEBUGOUT("SPI EEPROM Status error\n");
2007 status = IXGBE_ERR_EEPROM;
2014 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
2015 * @hw: pointer to hardware structure
2017 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
2021 DEBUGFUNC("ixgbe_standby_eeprom");
2023 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2025 /* Toggle CS to flush commands */
2026 eec |= IXGBE_EEC_CS;
2027 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2028 IXGBE_WRITE_FLUSH(hw);
2030 eec &= ~IXGBE_EEC_CS;
2031 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2032 IXGBE_WRITE_FLUSH(hw);
2037 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
2038 * @hw: pointer to hardware structure
2039 * @data: data to send to the EEPROM
2040 * @count: number of bits to shift out
2042 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
2049 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
2051 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2054 * Mask is used to shift "count" bits of "data" out to the EEPROM
2055 * one bit at a time. Determine the starting bit based on count
2057 mask = 0x01 << (count - 1);
2059 for (i = 0; i < count; i++) {
2061 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
2062 * "1", and then raising and then lowering the clock (the SK
2063 * bit controls the clock input to the EEPROM). A "0" is
2064 * shifted out to the EEPROM by setting "DI" to "0" and then
2065 * raising and then lowering the clock.
2068 eec |= IXGBE_EEC_DI;
2070 eec &= ~IXGBE_EEC_DI;
2072 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2073 IXGBE_WRITE_FLUSH(hw);
2077 ixgbe_raise_eeprom_clk(hw, &eec);
2078 ixgbe_lower_eeprom_clk(hw, &eec);
2081 * Shift mask to signify next bit of data to shift in to the
2087 /* We leave the "DI" bit set to "0" when we leave this routine. */
2088 eec &= ~IXGBE_EEC_DI;
2089 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2090 IXGBE_WRITE_FLUSH(hw);
2094 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
2095 * @hw: pointer to hardware structure
2096 * @count: number of bits to shift
2098 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
2104 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
2107 * In order to read a register from the EEPROM, we need to shift
2108 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
2109 * the clock input to the EEPROM (setting the SK bit), and then reading
2110 * the value of the "DO" bit. During this "shifting in" process the
2111 * "DI" bit should always be clear.
2113 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2115 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
2117 for (i = 0; i < count; i++) {
2119 ixgbe_raise_eeprom_clk(hw, &eec);
2121 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2123 eec &= ~(IXGBE_EEC_DI);
2124 if (eec & IXGBE_EEC_DO)
2127 ixgbe_lower_eeprom_clk(hw, &eec);
2134 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
2135 * @hw: pointer to hardware structure
2136 * @eec: EEC register's current value
2138 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2140 DEBUGFUNC("ixgbe_raise_eeprom_clk");
2143 * Raise the clock input to the EEPROM
2144 * (setting the SK bit), then delay
2146 *eec = *eec | IXGBE_EEC_SK;
2147 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2148 IXGBE_WRITE_FLUSH(hw);
2153 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2154 * @hw: pointer to hardware structure
2155 * @eec: EEC's current value
2157 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2159 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2162 * Lower the clock input to the EEPROM (clearing the SK bit), then
2165 *eec = *eec & ~IXGBE_EEC_SK;
2166 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2167 IXGBE_WRITE_FLUSH(hw);
2172 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2173 * @hw: pointer to hardware structure
2175 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2179 DEBUGFUNC("ixgbe_release_eeprom");
2181 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2183 eec |= IXGBE_EEC_CS; /* Pull CS high */
2184 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
2186 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2187 IXGBE_WRITE_FLUSH(hw);
2191 /* Stop requesting EEPROM access */
2192 eec &= ~IXGBE_EEC_REQ;
2193 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2195 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2197 /* Delay before attempt to obtain semaphore again to allow FW access */
2198 msec_delay(hw->eeprom.semaphore_delay);
2202 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2203 * @hw: pointer to hardware structure
2205 * Returns a negative error code on error, or the 16-bit checksum
2207 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2216 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
2218 /* Include 0x0-0x3F in the checksum */
2219 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
2220 if (hw->eeprom.ops.read(hw, i, &word)) {
2221 DEBUGOUT("EEPROM read failed\n");
2222 return IXGBE_ERR_EEPROM;
2227 /* Include all data from pointers except for the fw pointer */
2228 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
2229 if (hw->eeprom.ops.read(hw, i, &pointer)) {
2230 DEBUGOUT("EEPROM read failed\n");
2231 return IXGBE_ERR_EEPROM;
2234 /* If the pointer seems invalid */
2235 if (pointer == 0xFFFF || pointer == 0)
2238 if (hw->eeprom.ops.read(hw, pointer, &length)) {
2239 DEBUGOUT("EEPROM read failed\n");
2240 return IXGBE_ERR_EEPROM;
2243 if (length == 0xFFFF || length == 0)
2246 for (j = pointer + 1; j <= pointer + length; j++) {
2247 if (hw->eeprom.ops.read(hw, j, &word)) {
2248 DEBUGOUT("EEPROM read failed\n");
2249 return IXGBE_ERR_EEPROM;
2255 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2257 return (s32)checksum;
2261 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2262 * @hw: pointer to hardware structure
2263 * @checksum_val: calculated checksum
2265 * Performs checksum calculation and validates the EEPROM checksum. If the
2266 * caller does not need checksum_val, the value can be NULL.
2268 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2273 u16 read_checksum = 0;
2275 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
2277 /* Read the first word from the EEPROM. If this times out or fails, do
2278 * not continue or we could be in for a very long wait while every
2281 status = hw->eeprom.ops.read(hw, 0, &checksum);
2283 DEBUGOUT("EEPROM read failed\n");
2287 status = hw->eeprom.ops.calc_checksum(hw);
2291 checksum = (u16)(status & 0xffff);
2293 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2295 DEBUGOUT("EEPROM read failed\n");
2299 /* Verify read checksum from EEPROM is the same as
2300 * calculated checksum
2302 if (read_checksum != checksum)
2303 status = IXGBE_ERR_EEPROM_CHECKSUM;
2305 /* If the user cares, return the calculated checksum */
2307 *checksum_val = checksum;
2313 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2314 * @hw: pointer to hardware structure
2316 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2321 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
2323 /* Read the first word from the EEPROM. If this times out or fails, do
2324 * not continue or we could be in for a very long wait while every
2327 status = hw->eeprom.ops.read(hw, 0, &checksum);
2329 DEBUGOUT("EEPROM read failed\n");
2333 status = hw->eeprom.ops.calc_checksum(hw);
2337 checksum = (u16)(status & 0xffff);
2339 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
2345 * ixgbe_validate_mac_addr - Validate MAC address
2346 * @mac_addr: pointer to MAC address.
2348 * Tests a MAC address to ensure it is a valid Individual Address.
2350 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
2352 s32 status = IXGBE_SUCCESS;
2354 DEBUGFUNC("ixgbe_validate_mac_addr");
2356 /* Make sure it is not a multicast address */
2357 if (IXGBE_IS_MULTICAST(mac_addr)) {
2358 status = IXGBE_ERR_INVALID_MAC_ADDR;
2359 /* Not a broadcast address */
2360 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
2361 status = IXGBE_ERR_INVALID_MAC_ADDR;
2362 /* Reject the zero address */
2363 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
2364 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
2365 status = IXGBE_ERR_INVALID_MAC_ADDR;
2371 * ixgbe_set_rar_generic - Set Rx address register
2372 * @hw: pointer to hardware structure
2373 * @index: Receive address register to write
2374 * @addr: Address to put into receive address register
2375 * @vmdq: VMDq "set" or "pool" index
2376 * @enable_addr: set flag that address is active
2378 * Puts an ethernet address into a receive address register.
2380 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2383 u32 rar_low, rar_high;
2384 u32 rar_entries = hw->mac.num_rar_entries;
2386 DEBUGFUNC("ixgbe_set_rar_generic");
2388 /* Make sure we are using a valid rar index range */
2389 if (index >= rar_entries) {
2390 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2391 "RAR index %d is out of range.\n", index);
2392 return IXGBE_ERR_INVALID_ARGUMENT;
2395 /* setup VMDq pool selection before this RAR gets enabled */
2396 hw->mac.ops.set_vmdq(hw, index, vmdq);
2399 * HW expects these in little endian so we reverse the byte
2400 * order from network order (big endian) to little endian
2402 rar_low = ((u32)addr[0] |
2403 ((u32)addr[1] << 8) |
2404 ((u32)addr[2] << 16) |
2405 ((u32)addr[3] << 24));
2407 * Some parts put the VMDq setting in the extra RAH bits,
2408 * so save everything except the lower 16 bits that hold part
2409 * of the address and the address valid bit.
2411 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2412 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2413 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2415 if (enable_addr != 0)
2416 rar_high |= IXGBE_RAH_AV;
2418 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2419 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2421 return IXGBE_SUCCESS;
2425 * ixgbe_clear_rar_generic - Remove Rx address register
2426 * @hw: pointer to hardware structure
2427 * @index: Receive address register to write
2429 * Clears an ethernet address from a receive address register.
2431 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2434 u32 rar_entries = hw->mac.num_rar_entries;
2436 DEBUGFUNC("ixgbe_clear_rar_generic");
2438 /* Make sure we are using a valid rar index range */
2439 if (index >= rar_entries) {
2440 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2441 "RAR index %d is out of range.\n", index);
2442 return IXGBE_ERR_INVALID_ARGUMENT;
2446 * Some parts put the VMDq setting in the extra RAH bits,
2447 * so save everything except the lower 16 bits that hold part
2448 * of the address and the address valid bit.
2450 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2451 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2453 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2454 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2456 /* clear VMDq pool/queue selection for this RAR */
2457 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2459 return IXGBE_SUCCESS;
2463 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2464 * @hw: pointer to hardware structure
2466 * Places the MAC address in receive address register 0 and clears the rest
2467 * of the receive address registers. Clears the multicast table. Assumes
2468 * the receiver is in reset when the routine is called.
2470 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2473 u32 rar_entries = hw->mac.num_rar_entries;
2475 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2478 * If the current mac address is valid, assume it is a software override
2479 * to the permanent address.
2480 * Otherwise, use the permanent address from the eeprom.
2482 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2483 IXGBE_ERR_INVALID_MAC_ADDR) {
2484 /* Get the MAC address from the RAR0 for later reference */
2485 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2487 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2488 hw->mac.addr[0], hw->mac.addr[1],
2490 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2491 hw->mac.addr[4], hw->mac.addr[5]);
2493 /* Setup the receive address. */
2494 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2495 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2496 hw->mac.addr[0], hw->mac.addr[1],
2498 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2499 hw->mac.addr[4], hw->mac.addr[5]);
2501 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2504 /* clear VMDq pool/queue selection for RAR 0 */
2505 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2507 hw->addr_ctrl.overflow_promisc = 0;
2509 hw->addr_ctrl.rar_used_count = 1;
2511 /* Zero out the other receive addresses. */
2512 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2513 for (i = 1; i < rar_entries; i++) {
2514 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2515 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2519 hw->addr_ctrl.mta_in_use = 0;
2520 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2522 DEBUGOUT(" Clearing MTA\n");
2523 for (i = 0; i < hw->mac.mcft_size; i++)
2524 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2526 ixgbe_init_uta_tables(hw);
2528 return IXGBE_SUCCESS;
2532 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2533 * @hw: pointer to hardware structure
2534 * @addr: new address
2535 * @vmdq: VMDq "set" or "pool" index
2537 * Adds it to unused receive address register or goes into promiscuous mode.
2539 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2541 u32 rar_entries = hw->mac.num_rar_entries;
2544 DEBUGFUNC("ixgbe_add_uc_addr");
2546 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2547 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2550 * Place this address in the RAR if there is room,
2551 * else put the controller into promiscuous mode
2553 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2554 rar = hw->addr_ctrl.rar_used_count;
2555 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2556 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2557 hw->addr_ctrl.rar_used_count++;
2559 hw->addr_ctrl.overflow_promisc++;
2562 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2566 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2567 * @hw: pointer to hardware structure
2568 * @addr_list: the list of new addresses
2569 * @addr_count: number of addresses
2570 * @next: iterator function to walk the address list
2572 * The given list replaces any existing list. Clears the secondary addrs from
2573 * receive address registers. Uses unused receive address registers for the
2574 * first secondary addresses, and falls back to promiscuous mode as needed.
2576 * Drivers using secondary unicast addresses must set user_set_promisc when
2577 * manually putting the device into promiscuous mode.
2579 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2580 u32 addr_count, ixgbe_mc_addr_itr next)
2584 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2589 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2592 * Clear accounting of old secondary address list,
2593 * don't count RAR[0]
2595 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2596 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2597 hw->addr_ctrl.overflow_promisc = 0;
2599 /* Zero out the other receive addresses */
2600 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2601 for (i = 0; i < uc_addr_in_use; i++) {
2602 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2603 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2606 /* Add the new addresses */
2607 for (i = 0; i < addr_count; i++) {
2608 DEBUGOUT(" Adding the secondary addresses:\n");
2609 addr = next(hw, &addr_list, &vmdq);
2610 ixgbe_add_uc_addr(hw, addr, vmdq);
2613 if (hw->addr_ctrl.overflow_promisc) {
2614 /* enable promisc if not already in overflow or set by user */
2615 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2616 DEBUGOUT(" Entering address overflow promisc mode\n");
2617 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2618 fctrl |= IXGBE_FCTRL_UPE;
2619 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2622 /* only disable if set by overflow, not by user */
2623 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2624 DEBUGOUT(" Leaving address overflow promisc mode\n");
2625 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2626 fctrl &= ~IXGBE_FCTRL_UPE;
2627 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2631 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2632 return IXGBE_SUCCESS;
2636 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2637 * @hw: pointer to hardware structure
2638 * @mc_addr: the multicast address
2640 * Extracts the 12 bits, from a multicast address, to determine which
2641 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2642 * incoming rx multicast addresses, to determine the bit-vector to check in
2643 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2644 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2645 * to mc_filter_type.
2647 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2651 DEBUGFUNC("ixgbe_mta_vector");
2653 switch (hw->mac.mc_filter_type) {
2654 case 0: /* use bits [47:36] of the address */
2655 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2657 case 1: /* use bits [46:35] of the address */
2658 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2660 case 2: /* use bits [45:34] of the address */
2661 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2663 case 3: /* use bits [43:32] of the address */
2664 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2666 default: /* Invalid mc_filter_type */
2667 DEBUGOUT("MC filter type param set incorrectly\n");
2672 /* vector can only be 12-bits or boundary will be exceeded */
2678 * ixgbe_set_mta - Set bit-vector in multicast table
2679 * @hw: pointer to hardware structure
2680 * @mc_addr: Multicast address
2682 * Sets the bit-vector in the multicast table.
2684 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2690 DEBUGFUNC("ixgbe_set_mta");
2692 hw->addr_ctrl.mta_in_use++;
2694 vector = ixgbe_mta_vector(hw, mc_addr);
2695 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2698 * The MTA is a register array of 128 32-bit registers. It is treated
2699 * like an array of 4096 bits. We want to set bit
2700 * BitArray[vector_value]. So we figure out what register the bit is
2701 * in, read it, OR in the new bit, then write back the new value. The
2702 * register is determined by the upper 7 bits of the vector value and
2703 * the bit within that register are determined by the lower 5 bits of
2706 vector_reg = (vector >> 5) & 0x7F;
2707 vector_bit = vector & 0x1F;
2708 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2712 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2713 * @hw: pointer to hardware structure
2714 * @mc_addr_list: the list of new multicast addresses
2715 * @mc_addr_count: number of addresses
2716 * @next: iterator function to walk the multicast address list
2717 * @clear: flag, when set clears the table beforehand
2719 * When the clear flag is set, the given list replaces any existing list.
2720 * Hashes the given addresses into the multicast table.
2722 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2723 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2729 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2732 * Set the new number of MC addresses that we are being requested to
2735 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2736 hw->addr_ctrl.mta_in_use = 0;
2738 /* Clear mta_shadow */
2740 DEBUGOUT(" Clearing MTA\n");
2741 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2744 /* Update mta_shadow */
2745 for (i = 0; i < mc_addr_count; i++) {
2746 DEBUGOUT(" Adding the multicast addresses:\n");
2747 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2751 for (i = 0; i < hw->mac.mcft_size; i++)
2752 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2753 hw->mac.mta_shadow[i]);
2755 if (hw->addr_ctrl.mta_in_use > 0)
2756 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2757 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2759 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2760 return IXGBE_SUCCESS;
2764 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2765 * @hw: pointer to hardware structure
2767 * Enables multicast address in RAR and the use of the multicast hash table.
2769 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2771 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2773 DEBUGFUNC("ixgbe_enable_mc_generic");
2775 if (a->mta_in_use > 0)
2776 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2777 hw->mac.mc_filter_type);
2779 return IXGBE_SUCCESS;
2783 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2784 * @hw: pointer to hardware structure
2786 * Disables multicast address in RAR and the use of the multicast hash table.
2788 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2790 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2792 DEBUGFUNC("ixgbe_disable_mc_generic");
2794 if (a->mta_in_use > 0)
2795 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2797 return IXGBE_SUCCESS;
2801 * ixgbe_fc_enable_generic - Enable flow control
2802 * @hw: pointer to hardware structure
2804 * Enable flow control according to the current settings.
2806 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2808 s32 ret_val = IXGBE_SUCCESS;
2809 u32 mflcn_reg, fccfg_reg;
2814 DEBUGFUNC("ixgbe_fc_enable_generic");
2816 /* Validate the water mark configuration */
2817 if (!hw->fc.pause_time) {
2818 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2822 /* Low water mark of zero causes XOFF floods */
2823 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2824 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2825 hw->fc.high_water[i]) {
2826 if (!hw->fc.low_water[i] ||
2827 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2828 DEBUGOUT("Invalid water mark configuration\n");
2829 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2835 /* Negotiate the fc mode to use */
2836 hw->mac.ops.fc_autoneg(hw);
2838 /* Disable any previous flow control settings */
2839 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2840 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2842 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2843 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2846 * The possible values of fc.current_mode are:
2847 * 0: Flow control is completely disabled
2848 * 1: Rx flow control is enabled (we can receive pause frames,
2849 * but not send pause frames).
2850 * 2: Tx flow control is enabled (we can send pause frames but
2851 * we do not support receiving pause frames).
2852 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2855 switch (hw->fc.current_mode) {
2858 * Flow control is disabled by software override or autoneg.
2859 * The code below will actually disable it in the HW.
2862 case ixgbe_fc_rx_pause:
2864 * Rx Flow control is enabled and Tx Flow control is
2865 * disabled by software override. Since there really
2866 * isn't a way to advertise that we are capable of RX
2867 * Pause ONLY, we will advertise that we support both
2868 * symmetric and asymmetric Rx PAUSE. Later, we will
2869 * disable the adapter's ability to send PAUSE frames.
2871 mflcn_reg |= IXGBE_MFLCN_RFCE;
2873 case ixgbe_fc_tx_pause:
2875 * Tx Flow control is enabled, and Rx Flow control is
2876 * disabled by software override.
2878 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2881 /* Flow control (both Rx and Tx) is enabled by SW override. */
2882 mflcn_reg |= IXGBE_MFLCN_RFCE;
2883 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2886 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2887 "Flow control param set incorrectly\n");
2888 ret_val = IXGBE_ERR_CONFIG;
2893 /* Set 802.3x based flow control settings. */
2894 mflcn_reg |= IXGBE_MFLCN_DPF;
2895 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2896 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2899 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2900 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2901 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2902 hw->fc.high_water[i]) {
2903 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2904 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2905 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2907 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2909 * In order to prevent Tx hangs when the internal Tx
2910 * switch is enabled we must set the high water mark
2911 * to the Rx packet buffer size - 24KB. This allows
2912 * the Tx switch to function even under heavy Rx
2915 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2918 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2921 /* Configure pause time (2 TCs per register) */
2922 reg = hw->fc.pause_time * 0x00010001;
2923 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2924 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2926 /* Configure flow control refresh threshold value */
2927 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2934 * ixgbe_negotiate_fc - Negotiate flow control
2935 * @hw: pointer to hardware structure
2936 * @adv_reg: flow control advertised settings
2937 * @lp_reg: link partner's flow control settings
2938 * @adv_sym: symmetric pause bit in advertisement
2939 * @adv_asm: asymmetric pause bit in advertisement
2940 * @lp_sym: symmetric pause bit in link partner advertisement
2941 * @lp_asm: asymmetric pause bit in link partner advertisement
2943 * Find the intersection between advertised settings and link partner's
2944 * advertised settings
2946 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2947 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2949 if ((!(adv_reg)) || (!(lp_reg))) {
2950 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
2951 "Local or link partner's advertised flow control "
2952 "settings are NULL. Local: %x, link partner: %x\n",
2954 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2957 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2959 * Now we need to check if the user selected Rx ONLY
2960 * of pause frames. In this case, we had to advertise
2961 * FULL flow control because we could not advertise RX
2962 * ONLY. Hence, we must now check to see if we need to
2963 * turn OFF the TRANSMISSION of PAUSE frames.
2965 if (hw->fc.requested_mode == ixgbe_fc_full) {
2966 hw->fc.current_mode = ixgbe_fc_full;
2967 DEBUGOUT("Flow Control = FULL.\n");
2969 hw->fc.current_mode = ixgbe_fc_rx_pause;
2970 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2972 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2973 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2974 hw->fc.current_mode = ixgbe_fc_tx_pause;
2975 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2976 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2977 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2978 hw->fc.current_mode = ixgbe_fc_rx_pause;
2979 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2981 hw->fc.current_mode = ixgbe_fc_none;
2982 DEBUGOUT("Flow Control = NONE.\n");
2984 return IXGBE_SUCCESS;
2988 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2989 * @hw: pointer to hardware structure
2991 * Enable flow control according on 1 gig fiber.
2993 STATIC s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2995 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2996 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2999 * On multispeed fiber at 1g, bail out if
3000 * - link is up but AN did not complete, or if
3001 * - link is up and AN completed but timed out
3004 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
3005 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
3006 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
3007 DEBUGOUT("Auto-Negotiation did not complete or timed out\n");
3011 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
3012 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
3014 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
3015 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
3016 IXGBE_PCS1GANA_ASM_PAUSE,
3017 IXGBE_PCS1GANA_SYM_PAUSE,
3018 IXGBE_PCS1GANA_ASM_PAUSE);
3025 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
3026 * @hw: pointer to hardware structure
3028 * Enable flow control according to IEEE clause 37.
3030 STATIC s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
3032 u32 links2, anlp1_reg, autoc_reg, links;
3033 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3036 * On backplane, bail out if
3037 * - backplane autoneg was not completed, or if
3038 * - we are 82599 and link partner is not AN enabled
3040 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
3041 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
3042 DEBUGOUT("Auto-Negotiation did not complete\n");
3046 if (hw->mac.type == ixgbe_mac_82599EB) {
3047 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
3048 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
3049 DEBUGOUT("Link partner is not AN enabled\n");
3054 * Read the 10g AN autoc and LP ability registers and resolve
3055 * local flow control settings accordingly
3057 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3058 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
3060 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
3061 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
3062 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
3069 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
3070 * @hw: pointer to hardware structure
3072 * Enable flow control according to IEEE clause 37.
3074 STATIC s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
3076 u16 technology_ability_reg = 0;
3077 u16 lp_technology_ability_reg = 0;
3079 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
3080 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3081 &technology_ability_reg);
3082 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
3083 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3084 &lp_technology_ability_reg);
3086 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
3087 (u32)lp_technology_ability_reg,
3088 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
3089 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
3093 * ixgbe_fc_autoneg - Configure flow control
3094 * @hw: pointer to hardware structure
3096 * Compares our advertised flow control capabilities to those advertised by
3097 * our link partner, and determines the proper flow control mode to use.
3099 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
3101 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3102 ixgbe_link_speed speed;
3105 DEBUGFUNC("ixgbe_fc_autoneg");
3108 * AN should have completed when the cable was plugged in.
3109 * Look for reasons to bail out. Bail out if:
3110 * - FC autoneg is disabled, or if
3113 if (hw->fc.disable_fc_autoneg) {
3114 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3115 "Flow control autoneg is disabled");
3119 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3121 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3125 switch (hw->phy.media_type) {
3126 /* Autoneg flow control on fiber adapters */
3127 case ixgbe_media_type_fiber_qsfp:
3128 case ixgbe_media_type_fiber:
3129 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
3130 ret_val = ixgbe_fc_autoneg_fiber(hw);
3133 /* Autoneg flow control on backplane adapters */
3134 case ixgbe_media_type_backplane:
3135 ret_val = ixgbe_fc_autoneg_backplane(hw);
3138 /* Autoneg flow control on copper adapters */
3139 case ixgbe_media_type_copper:
3140 if (ixgbe_device_supports_autoneg_fc(hw))
3141 ret_val = ixgbe_fc_autoneg_copper(hw);
3149 if (ret_val == IXGBE_SUCCESS) {
3150 hw->fc.fc_was_autonegged = true;
3152 hw->fc.fc_was_autonegged = false;
3153 hw->fc.current_mode = hw->fc.requested_mode;
3158 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3159 * @hw: pointer to hardware structure
3161 * System-wide timeout range is encoded in PCIe Device Control2 register.
3163 * Add 10% to specified maximum and return the number of times to poll for
3164 * completion timeout, in units of 100 microsec. Never return less than
3165 * 800 = 80 millisec.
3167 STATIC u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3172 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3173 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
3176 case IXGBE_PCIDEVCTRL2_65_130ms:
3177 pollcnt = 1300; /* 130 millisec */
3179 case IXGBE_PCIDEVCTRL2_260_520ms:
3180 pollcnt = 5200; /* 520 millisec */
3182 case IXGBE_PCIDEVCTRL2_1_2s:
3183 pollcnt = 20000; /* 2 sec */
3185 case IXGBE_PCIDEVCTRL2_4_8s:
3186 pollcnt = 80000; /* 8 sec */
3188 case IXGBE_PCIDEVCTRL2_17_34s:
3189 pollcnt = 34000; /* 34 sec */
3191 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
3192 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
3193 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
3194 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
3196 pollcnt = 800; /* 80 millisec minimum */
3200 /* add 10% to spec maximum */
3201 return (pollcnt * 11) / 10;
3205 * ixgbe_disable_pcie_master - Disable PCI-express master access
3206 * @hw: pointer to hardware structure
3208 * Disables PCI-Express master access and verifies there are no pending
3209 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
3210 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
3211 * is returned signifying master requests disabled.
3213 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
3215 s32 status = IXGBE_SUCCESS;
3219 DEBUGFUNC("ixgbe_disable_pcie_master");
3221 /* Always set this bit to ensure any future transactions are blocked */
3222 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3224 /* Exit if master requests are blocked */
3225 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3226 IXGBE_REMOVED(hw->hw_addr))
3229 /* Poll for master request bit to clear */
3230 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
3232 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3237 * Two consecutive resets are required via CTRL.RST per datasheet
3238 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
3239 * of this need. The first reset prevents new master requests from
3240 * being issued by our device. We then must wait 1usec or more for any
3241 * remaining completions from the PCIe bus to trickle in, and then reset
3242 * again to clear out any effects they may have had on our device.
3244 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
3245 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3247 if (hw->mac.type >= ixgbe_mac_X550)
3251 * Before proceeding, make sure that the PCIe block does not have
3252 * transactions pending.
3254 poll = ixgbe_pcie_timeout_poll(hw);
3255 for (i = 0; i < poll; i++) {
3257 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3258 if (IXGBE_REMOVED(hw->hw_addr))
3260 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3264 ERROR_REPORT1(IXGBE_ERROR_POLLING,
3265 "PCIe transaction pending bit also did not clear.\n");
3266 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
3273 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3274 * @hw: pointer to hardware structure
3275 * @mask: Mask to specify which semaphore to acquire
3277 * Acquires the SWFW semaphore through the GSSR register for the specified
3278 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3280 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3284 u32 fwmask = mask << 5;
3288 DEBUGFUNC("ixgbe_acquire_swfw_sync");
3290 for (i = 0; i < timeout; i++) {
3292 * SW NVM semaphore bit is used for access to all
3293 * SW_FW_SYNC bits (not just NVM)
3295 if (ixgbe_get_eeprom_semaphore(hw))
3296 return IXGBE_ERR_SWFW_SYNC;
3298 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3299 if (!(gssr & (fwmask | swmask))) {
3301 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3302 ixgbe_release_eeprom_semaphore(hw);
3303 return IXGBE_SUCCESS;
3305 /* Resource is currently in use by FW or SW */
3306 ixgbe_release_eeprom_semaphore(hw);
3311 /* If time expired clear the bits holding the lock and retry */
3312 if (gssr & (fwmask | swmask))
3313 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
3316 return IXGBE_ERR_SWFW_SYNC;
3320 * ixgbe_release_swfw_sync - Release SWFW semaphore
3321 * @hw: pointer to hardware structure
3322 * @mask: Mask to specify which semaphore to release
3324 * Releases the SWFW semaphore through the GSSR register for the specified
3325 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3327 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3332 DEBUGFUNC("ixgbe_release_swfw_sync");
3334 ixgbe_get_eeprom_semaphore(hw);
3336 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3338 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3340 ixgbe_release_eeprom_semaphore(hw);
3344 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3345 * @hw: pointer to hardware structure
3347 * Stops the receive data path and waits for the HW to internally empty
3348 * the Rx security block
3350 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3352 #define IXGBE_MAX_SECRX_POLL 4000
3357 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
3360 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3361 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
3362 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3363 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
3364 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3365 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
3368 /* Use interrupt-safe sleep just in case */
3372 /* For informational purposes only */
3373 if (i >= IXGBE_MAX_SECRX_POLL)
3374 DEBUGOUT("Rx unit being enabled before security "
3375 "path fully disabled. Continuing with init.\n");
3377 return IXGBE_SUCCESS;
3381 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3382 * @hw: pointer to hardware structure
3383 * @locked: bool to indicate whether the SW/FW lock was taken
3384 * @reg_val: Value we read from AUTOC
3386 * The default case requires no protection so just to the register read.
3388 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3391 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3392 return IXGBE_SUCCESS;
3396 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
3397 * @hw: pointer to hardware structure
3398 * @reg_val: value to write to AUTOC
3399 * @locked: bool to indicate whether the SW/FW lock was already taken by
3402 * The default case requires no protection so just to the register write.
3404 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
3406 UNREFERENCED_1PARAMETER(locked);
3408 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
3409 return IXGBE_SUCCESS;
3413 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3414 * @hw: pointer to hardware structure
3416 * Enables the receive data path.
3418 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3422 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
3424 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3425 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
3426 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3427 IXGBE_WRITE_FLUSH(hw);
3429 return IXGBE_SUCCESS;
3433 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3434 * @hw: pointer to hardware structure
3435 * @regval: register value to write to RXCTRL
3437 * Enables the Rx DMA unit
3439 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3441 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
3443 if (regval & IXGBE_RXCTRL_RXEN)
3444 ixgbe_enable_rx(hw);
3446 ixgbe_disable_rx(hw);
3448 return IXGBE_SUCCESS;
3452 * ixgbe_blink_led_start_generic - Blink LED based on index.
3453 * @hw: pointer to hardware structure
3454 * @index: led number to blink
3456 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3458 ixgbe_link_speed speed = 0;
3461 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3462 s32 ret_val = IXGBE_SUCCESS;
3463 bool locked = false;
3465 DEBUGFUNC("ixgbe_blink_led_start_generic");
3468 return IXGBE_ERR_PARAM;
3471 * Link must be up to auto-blink the LEDs;
3472 * Force it if link is down.
3474 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3477 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3478 if (ret_val != IXGBE_SUCCESS)
3481 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3482 autoc_reg |= IXGBE_AUTOC_FLU;
3484 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3485 if (ret_val != IXGBE_SUCCESS)
3488 IXGBE_WRITE_FLUSH(hw);
3492 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3493 led_reg |= IXGBE_LED_BLINK(index);
3494 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3495 IXGBE_WRITE_FLUSH(hw);
3502 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3503 * @hw: pointer to hardware structure
3504 * @index: led number to stop blinking
3506 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3509 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3510 s32 ret_val = IXGBE_SUCCESS;
3511 bool locked = false;
3513 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3516 return IXGBE_ERR_PARAM;
3519 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3520 if (ret_val != IXGBE_SUCCESS)
3523 autoc_reg &= ~IXGBE_AUTOC_FLU;
3524 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3526 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3527 if (ret_val != IXGBE_SUCCESS)
3530 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3531 led_reg &= ~IXGBE_LED_BLINK(index);
3532 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3533 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3534 IXGBE_WRITE_FLUSH(hw);
3541 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3542 * @hw: pointer to hardware structure
3543 * @san_mac_offset: SAN MAC address offset
3545 * This function will read the EEPROM location for the SAN MAC address
3546 * pointer, and returns the value at that location. This is used in both
3547 * get and set mac_addr routines.
3549 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3550 u16 *san_mac_offset)
3554 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3557 * First read the EEPROM pointer to see if the MAC addresses are
3560 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3563 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3564 "eeprom at offset %d failed",
3565 IXGBE_SAN_MAC_ADDR_PTR);
3572 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3573 * @hw: pointer to hardware structure
3574 * @san_mac_addr: SAN MAC address
3576 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3577 * per-port, so set_lan_id() must be called before reading the addresses.
3578 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3579 * upon for non-SFP connections, so we must call it here.
3581 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3583 u16 san_mac_data, san_mac_offset;
3587 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3590 * First read the EEPROM pointer to see if the MAC addresses are
3591 * available. If they're not, no point in calling set_lan_id() here.
3593 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3594 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3595 goto san_mac_addr_out;
3597 /* make sure we know which port we need to program */
3598 hw->mac.ops.set_lan_id(hw);
3599 /* apply the port offset to the address offset */
3600 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3601 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3602 for (i = 0; i < 3; i++) {
3603 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3606 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3607 "eeprom read at offset %d failed",
3609 goto san_mac_addr_out;
3611 san_mac_addr[i * 2] = (u8)(san_mac_data);
3612 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3615 return IXGBE_SUCCESS;
3619 * No addresses available in this EEPROM. It's not an
3620 * error though, so just wipe the local address and return.
3622 for (i = 0; i < 6; i++)
3623 san_mac_addr[i] = 0xFF;
3624 return IXGBE_SUCCESS;
3628 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3629 * @hw: pointer to hardware structure
3630 * @san_mac_addr: SAN MAC address
3632 * Write a SAN MAC address to the EEPROM.
3634 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3637 u16 san_mac_data, san_mac_offset;
3640 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3642 /* Look for SAN mac address pointer. If not defined, return */
3643 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3644 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3645 return IXGBE_ERR_NO_SAN_ADDR_PTR;
3647 /* Make sure we know which port we need to write */
3648 hw->mac.ops.set_lan_id(hw);
3649 /* Apply the port offset to the address offset */
3650 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3651 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3653 for (i = 0; i < 3; i++) {
3654 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3655 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3656 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3660 return IXGBE_SUCCESS;
3664 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3665 * @hw: pointer to hardware structure
3667 * Read PCIe configuration space, and get the MSI-X vector count from
3668 * the capabilities table.
3670 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3676 switch (hw->mac.type) {
3677 case ixgbe_mac_82598EB:
3678 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3679 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3681 case ixgbe_mac_82599EB:
3682 case ixgbe_mac_X540:
3683 case ixgbe_mac_X550:
3684 case ixgbe_mac_X550EM_x:
3685 case ixgbe_mac_X550EM_a:
3686 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3687 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3693 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3694 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3695 if (IXGBE_REMOVED(hw->hw_addr))
3697 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3699 /* MSI-X count is zero-based in HW */
3702 if (msix_count > max_msix_count)
3703 msix_count = max_msix_count;
3709 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3710 * @hw: pointer to hardware structure
3711 * @addr: Address to put into receive address register
3712 * @vmdq: VMDq pool to assign
3714 * Puts an ethernet address into a receive address register, or
3715 * finds the rar that it is aleady in; adds to the pool list
3717 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3719 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3720 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3722 u32 rar_low, rar_high;
3723 u32 addr_low, addr_high;
3725 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3727 /* swap bytes for HW little endian */
3728 addr_low = addr[0] | (addr[1] << 8)
3731 addr_high = addr[4] | (addr[5] << 8);
3734 * Either find the mac_id in rar or find the first empty space.
3735 * rar_highwater points to just after the highest currently used
3736 * rar in order to shorten the search. It grows when we add a new
3739 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3740 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3742 if (((IXGBE_RAH_AV & rar_high) == 0)
3743 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3744 first_empty_rar = rar;
3745 } else if ((rar_high & 0xFFFF) == addr_high) {
3746 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3747 if (rar_low == addr_low)
3748 break; /* found it already in the rars */
3752 if (rar < hw->mac.rar_highwater) {
3753 /* already there so just add to the pool bits */
3754 ixgbe_set_vmdq(hw, rar, vmdq);
3755 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3756 /* stick it into first empty RAR slot we found */
3757 rar = first_empty_rar;
3758 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3759 } else if (rar == hw->mac.rar_highwater) {
3760 /* add it to the top of the list and inc the highwater mark */
3761 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3762 hw->mac.rar_highwater++;
3763 } else if (rar >= hw->mac.num_rar_entries) {
3764 return IXGBE_ERR_INVALID_MAC_ADDR;
3768 * If we found rar[0], make sure the default pool bit (we use pool 0)
3769 * remains cleared to be sure default pool packets will get delivered
3772 ixgbe_clear_vmdq(hw, rar, 0);
3778 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3779 * @hw: pointer to hardware struct
3780 * @rar: receive address register index to disassociate
3781 * @vmdq: VMDq pool index to remove from the rar
3783 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3785 u32 mpsar_lo, mpsar_hi;
3786 u32 rar_entries = hw->mac.num_rar_entries;
3788 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3790 /* Make sure we are using a valid rar index range */
3791 if (rar >= rar_entries) {
3792 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3793 "RAR index %d is out of range.\n", rar);
3794 return IXGBE_ERR_INVALID_ARGUMENT;
3797 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3798 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3800 if (IXGBE_REMOVED(hw->hw_addr))
3803 if (!mpsar_lo && !mpsar_hi)
3806 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3808 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3812 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3815 } else if (vmdq < 32) {
3816 mpsar_lo &= ~(1 << vmdq);
3817 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3819 mpsar_hi &= ~(1 << (vmdq - 32));
3820 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3823 /* was that the last pool using this rar? */
3824 if (mpsar_lo == 0 && mpsar_hi == 0 &&
3825 rar != 0 && rar != hw->mac.san_mac_rar_index)
3826 hw->mac.ops.clear_rar(hw, rar);
3828 return IXGBE_SUCCESS;
3832 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3833 * @hw: pointer to hardware struct
3834 * @rar: receive address register index to associate with a VMDq index
3835 * @vmdq: VMDq pool index
3837 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3840 u32 rar_entries = hw->mac.num_rar_entries;
3842 DEBUGFUNC("ixgbe_set_vmdq_generic");
3844 /* Make sure we are using a valid rar index range */
3845 if (rar >= rar_entries) {
3846 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3847 "RAR index %d is out of range.\n", rar);
3848 return IXGBE_ERR_INVALID_ARGUMENT;
3852 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3854 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3856 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3857 mpsar |= 1 << (vmdq - 32);
3858 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3860 return IXGBE_SUCCESS;
3864 * This function should only be involved in the IOV mode.
3865 * In IOV mode, Default pool is next pool after the number of
3866 * VFs advertized and not 0.
3867 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3869 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3870 * @hw: pointer to hardware struct
3871 * @vmdq: VMDq pool index
3873 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3875 u32 rar = hw->mac.san_mac_rar_index;
3877 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3880 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3881 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3883 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3884 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3887 return IXGBE_SUCCESS;
3891 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3892 * @hw: pointer to hardware structure
3894 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3898 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3899 DEBUGOUT(" Clearing UTA\n");
3901 for (i = 0; i < 128; i++)
3902 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3904 return IXGBE_SUCCESS;
3908 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3909 * @hw: pointer to hardware structure
3910 * @vlan: VLAN id to write to VLAN filter
3911 * @vlvf_bypass: true to find vlanid only, false returns first empty slot if
3915 * return the VLVF index where this VLAN id should be placed
3918 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)
3920 s32 regindex, first_empty_slot;
3923 /* short cut the special case */
3927 /* if vlvf_bypass is set we don't want to use an empty slot, we
3928 * will simply bypass the VLVF if there are no entries present in the
3929 * VLVF that contain our VLAN
3931 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0;
3933 /* add VLAN enable bit for comparison */
3934 vlan |= IXGBE_VLVF_VIEN;
3936 /* Search for the vlan id in the VLVF entries. Save off the first empty
3937 * slot found along the way.
3939 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1
3941 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) {
3942 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3945 if (!first_empty_slot && !bits)
3946 first_empty_slot = regindex;
3949 /* If we are here then we didn't find the VLAN. Return first empty
3950 * slot we found during our search, else error.
3952 if (!first_empty_slot)
3953 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "No space in VLVF.\n");
3955 return first_empty_slot ? first_empty_slot : IXGBE_ERR_NO_SPACE;
3959 * ixgbe_set_vfta_generic - Set VLAN filter table
3960 * @hw: pointer to hardware structure
3961 * @vlan: VLAN id to write to VLAN filter
3962 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
3963 * @vlan_on: boolean flag to turn on/off VLAN
3964 * @vlvf_bypass: boolean flag indicating updating default pool is okay
3966 * Turn on/off specified VLAN in the VLAN filter table.
3968 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3969 bool vlan_on, bool vlvf_bypass)
3971 u32 regidx, vfta_delta, vfta;
3974 DEBUGFUNC("ixgbe_set_vfta_generic");
3976 if (vlan > 4095 || vind > 63)
3977 return IXGBE_ERR_PARAM;
3980 * this is a 2 part operation - first the VFTA, then the
3981 * VLVF and VLVFB if VT Mode is set
3982 * We don't write the VFTA until we know the VLVF part succeeded.
3986 * The VFTA is a bitstring made up of 128 32-bit registers
3987 * that enable the particular VLAN id, much like the MTA:
3988 * bits[11-5]: which register
3989 * bits[4-0]: which bit in the register
3992 vfta_delta = 1 << (vlan % 32);
3993 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx));
3996 * vfta_delta represents the difference between the current value
3997 * of vfta and the value we want in the register. Since the diff
3998 * is an XOR mask we can just update the vfta using an XOR
4000 vfta_delta &= vlan_on ? ~vfta : vfta;
4004 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
4006 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta,
4008 if (ret_val != IXGBE_SUCCESS) {
4015 /* Update VFTA now that we are ready for traffic */
4017 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta);
4019 return IXGBE_SUCCESS;
4023 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
4024 * @hw: pointer to hardware structure
4025 * @vlan: VLAN id to write to VLAN filter
4026 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
4027 * @vlan_on: boolean flag to turn on/off VLAN in VLVF
4028 * @vfta_delta: pointer to the difference between the current value of VFTA
4029 * and the desired value
4030 * @vfta: the desired value of the VFTA
4031 * @vlvf_bypass: boolean flag indicating updating default pool is okay
4033 * Turn on/off specified bit in VLVF table.
4035 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
4036 bool vlan_on, u32 *vfta_delta, u32 vfta,
4042 DEBUGFUNC("ixgbe_set_vlvf_generic");
4044 if (vlan > 4095 || vind > 63)
4045 return IXGBE_ERR_PARAM;
4047 /* If VT Mode is set
4049 * make sure the vlan is in VLVF
4050 * set the vind bit in the matching VLVFB
4052 * clear the pool bit and possibly the vind
4054 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE))
4055 return IXGBE_SUCCESS;
4057 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
4061 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32));
4063 /* set the pool bit */
4064 bits |= 1 << (vind % 32);
4068 /* clear the pool bit */
4069 bits ^= 1 << (vind % 32);
4072 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) {
4073 /* Clear VFTA first, then disable VLVF. Otherwise
4074 * we run the risk of stray packets leaking into
4075 * the PF via the default pool
4078 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta);
4080 /* disable VLVF and clear remaining bit from pool */
4081 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
4082 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0);
4084 return IXGBE_SUCCESS;
4087 /* If there are still bits set in the VLVFB registers
4088 * for the VLAN ID indicated we need to see if the
4089 * caller is requesting that we clear the VFTA entry bit.
4090 * If the caller has requested that we clear the VFTA
4091 * entry bit but there are still pools/VFs using this VLAN
4092 * ID entry then ignore the request. We're not worried
4093 * about the case where we're turning the VFTA VLAN ID
4094 * entry bit on, only when requested to turn it off as
4095 * there may be multiple pools and/or VFs using the
4096 * VLAN ID entry. In that case we cannot clear the
4097 * VFTA bit until all pools/VFs using that VLAN ID have also
4098 * been cleared. This will be indicated by "bits" being
4104 /* record pool change and enable VLAN ID if not already enabled */
4105 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits);
4106 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan);
4108 return IXGBE_SUCCESS;
4112 * ixgbe_clear_vfta_generic - Clear VLAN filter table
4113 * @hw: pointer to hardware structure
4115 * Clears the VLAN filer table, and the VMDq index associated with the filter
4117 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
4121 DEBUGFUNC("ixgbe_clear_vfta_generic");
4123 for (offset = 0; offset < hw->mac.vft_size; offset++)
4124 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
4126 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
4127 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
4128 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
4129 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0);
4132 return IXGBE_SUCCESS;
4136 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
4137 * @hw: pointer to hardware structure
4139 * Contains the logic to identify if we need to verify link for the
4142 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw)
4145 /* Does FW say we need the fix */
4146 if (!hw->need_crosstalk_fix)
4149 /* Only consider SFP+ PHYs i.e. media type fiber */
4150 switch (hw->mac.ops.get_media_type(hw)) {
4151 case ixgbe_media_type_fiber:
4152 case ixgbe_media_type_fiber_qsfp:
4162 * ixgbe_check_mac_link_generic - Determine link and speed status
4163 * @hw: pointer to hardware structure
4164 * @speed: pointer to link speed
4165 * @link_up: true when link is up
4166 * @link_up_wait_to_complete: bool used to wait for link up or not
4168 * Reads the links register to determine if link is up and the current speed
4170 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4171 bool *link_up, bool link_up_wait_to_complete)
4173 u32 links_reg, links_orig;
4176 DEBUGFUNC("ixgbe_check_mac_link_generic");
4178 /* If Crosstalk fix enabled do the sanity check of making sure
4179 * the SFP+ cage is full.
4181 if (ixgbe_need_crosstalk_fix(hw)) {
4184 switch (hw->mac.type) {
4185 case ixgbe_mac_82599EB:
4186 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4189 case ixgbe_mac_X550EM_x:
4190 case ixgbe_mac_X550EM_a:
4191 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4195 /* sanity check - No SFP+ devices here */
4196 sfp_cage_full = false;
4200 if (!sfp_cage_full) {
4202 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4203 return IXGBE_SUCCESS;
4207 /* clear the old state */
4208 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
4210 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4212 if (links_orig != links_reg) {
4213 DEBUGOUT2("LINKS changed from %08X to %08X\n",
4214 links_orig, links_reg);
4217 if (link_up_wait_to_complete) {
4218 for (i = 0; i < hw->mac.max_link_up_time; i++) {
4219 if (links_reg & IXGBE_LINKS_UP) {
4226 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4229 if (links_reg & IXGBE_LINKS_UP)
4235 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4236 case IXGBE_LINKS_SPEED_10G_82599:
4237 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4238 if (hw->mac.type >= ixgbe_mac_X550) {
4239 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4240 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4243 case IXGBE_LINKS_SPEED_1G_82599:
4244 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4246 case IXGBE_LINKS_SPEED_100_82599:
4247 *speed = IXGBE_LINK_SPEED_100_FULL;
4248 if (hw->mac.type == ixgbe_mac_X550) {
4249 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4250 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4253 case IXGBE_LINKS_SPEED_10_X550EM_A:
4254 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4255 #ifdef PREBOOT_SUPPORT
4256 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4257 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L ||
4258 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
4259 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
4260 *speed = IXGBE_LINK_SPEED_10_FULL;
4262 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4263 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4264 *speed = IXGBE_LINK_SPEED_10_FULL;
4265 #endif /* PREBOOT_SUPPORT */
4268 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4271 return IXGBE_SUCCESS;
4275 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4277 * @hw: pointer to hardware structure
4278 * @wwnn_prefix: the alternative WWNN prefix
4279 * @wwpn_prefix: the alternative WWPN prefix
4281 * This function will read the EEPROM from the alternative SAN MAC address
4282 * block to check the support for the alternative WWNN/WWPN prefix support.
4284 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4288 u16 alt_san_mac_blk_offset;
4290 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
4292 /* clear output first */
4293 *wwnn_prefix = 0xFFFF;
4294 *wwpn_prefix = 0xFFFF;
4296 /* check if alternative SAN MAC is supported */
4297 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
4298 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4299 goto wwn_prefix_err;
4301 if ((alt_san_mac_blk_offset == 0) ||
4302 (alt_san_mac_blk_offset == 0xFFFF))
4303 goto wwn_prefix_out;
4305 /* check capability in alternative san mac address block */
4306 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
4307 if (hw->eeprom.ops.read(hw, offset, &caps))
4308 goto wwn_prefix_err;
4309 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
4310 goto wwn_prefix_out;
4312 /* get the corresponding prefix for WWNN/WWPN */
4313 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
4314 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4315 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4316 "eeprom read at offset %d failed", offset);
4319 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
4320 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4321 goto wwn_prefix_err;
4324 return IXGBE_SUCCESS;
4327 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4328 "eeprom read at offset %d failed", offset);
4329 return IXGBE_SUCCESS;
4333 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4334 * @hw: pointer to hardware structure
4335 * @bs: the fcoe boot status
4337 * This function will read the FCOE boot status from the iSCSI FCOE block
4339 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4341 u16 offset, caps, flags;
4344 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
4346 /* clear output first */
4347 *bs = ixgbe_fcoe_bootstatus_unavailable;
4349 /* check if FCOE IBA block is present */
4350 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
4351 status = hw->eeprom.ops.read(hw, offset, &caps);
4352 if (status != IXGBE_SUCCESS)
4355 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
4358 /* check if iSCSI FCOE block is populated */
4359 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4360 if (status != IXGBE_SUCCESS)
4363 if ((offset == 0) || (offset == 0xFFFF))
4366 /* read fcoe flags in iSCSI FCOE block */
4367 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
4368 status = hw->eeprom.ops.read(hw, offset, &flags);
4369 if (status != IXGBE_SUCCESS)
4372 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
4373 *bs = ixgbe_fcoe_bootstatus_enabled;
4375 *bs = ixgbe_fcoe_bootstatus_disabled;
4382 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4383 * @hw: pointer to hardware structure
4384 * @enable: enable or disable switch for MAC anti-spoofing
4385 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
4388 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4390 int vf_target_reg = vf >> 3;
4391 int vf_target_shift = vf % 8;
4394 if (hw->mac.type == ixgbe_mac_82598EB)
4397 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4399 pfvfspoof |= (1 << vf_target_shift);
4401 pfvfspoof &= ~(1 << vf_target_shift);
4402 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4406 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4407 * @hw: pointer to hardware structure
4408 * @enable: enable or disable switch for VLAN anti-spoofing
4409 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4412 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4414 int vf_target_reg = vf >> 3;
4415 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
4418 if (hw->mac.type == ixgbe_mac_82598EB)
4421 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4423 pfvfspoof |= (1 << vf_target_shift);
4425 pfvfspoof &= ~(1 << vf_target_shift);
4426 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4430 * ixgbe_get_device_caps_generic - Get additional device capabilities
4431 * @hw: pointer to hardware structure
4432 * @device_caps: the EEPROM word with the extra device capabilities
4434 * This function will read the EEPROM location for the device capabilities,
4435 * and return the word through device_caps.
4437 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4439 DEBUGFUNC("ixgbe_get_device_caps_generic");
4441 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4443 return IXGBE_SUCCESS;
4447 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4448 * @hw: pointer to hardware structure
4451 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4456 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
4458 /* Enable relaxed ordering */
4459 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4460 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4461 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4462 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4465 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4466 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4467 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
4468 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4469 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4475 * ixgbe_calculate_checksum - Calculate checksum for buffer
4476 * @buffer: pointer to EEPROM
4477 * @length: size of EEPROM to calculate a checksum for
4478 * Calculates the checksum for some buffer on a specified length. The
4479 * checksum calculated is returned.
4481 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4486 DEBUGFUNC("ixgbe_calculate_checksum");
4491 for (i = 0; i < length; i++)
4494 return (u8) (0 - sum);
4498 * ixgbe_hic_unlocked - Issue command to manageability block unlocked
4499 * @hw: pointer to the HW structure
4500 * @buffer: command to write and where the return status will be placed
4501 * @length: length of buffer, must be multiple of 4 bytes
4502 * @timeout: time in ms to wait for command completion
4504 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4505 * else returns semaphore error when encountering an error acquiring
4506 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4508 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held
4511 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length,
4517 DEBUGFUNC("ixgbe_hic_unlocked");
4519 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4520 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4521 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4524 /* Set bit 9 of FWSTS clearing FW reset indication */
4525 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
4526 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
4528 /* Check that the host interface is enabled. */
4529 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4530 if (!(hicr & IXGBE_HICR_EN)) {
4531 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
4532 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4535 /* Calculate length in DWORDs. We must be DWORD aligned */
4536 if (length % sizeof(u32)) {
4537 DEBUGOUT("Buffer length failure, not aligned to dword");
4538 return IXGBE_ERR_INVALID_ARGUMENT;
4541 dword_len = length >> 2;
4543 /* The device driver writes the relevant command block
4544 * into the ram area.
4546 for (i = 0; i < dword_len; i++)
4547 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4548 i, IXGBE_CPU_TO_LE32(buffer[i]));
4550 /* Setting this bit tells the ARC that a new command is pending. */
4551 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4553 for (i = 0; i < timeout; i++) {
4554 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4555 if (!(hicr & IXGBE_HICR_C))
4560 /* Check command completion */
4561 if ((timeout && i == timeout) ||
4562 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
4563 ERROR_REPORT1(IXGBE_ERROR_CAUTION,
4564 "Command has failed with no status valid.\n");
4565 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4568 return IXGBE_SUCCESS;
4572 * ixgbe_host_interface_command - Issue command to manageability block
4573 * @hw: pointer to the HW structure
4574 * @buffer: contains the command to write and where the return status will
4576 * @length: length of buffer, must be multiple of 4 bytes
4577 * @timeout: time in ms to wait for command completion
4578 * @return_data: read and return data from the buffer (true) or not (false)
4579 * Needed because FW structures are big endian and decoding of
4580 * these fields can be 8 bit or 16 bit based on command. Decoding
4581 * is not easily understood without making a table of commands.
4582 * So we will leave this up to the caller to read back the data
4585 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4586 * else returns semaphore error when encountering an error acquiring
4587 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4589 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4590 u32 length, u32 timeout, bool return_data)
4592 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4593 struct ixgbe_hic_hdr *resp = (struct ixgbe_hic_hdr *)buffer;
4599 DEBUGFUNC("ixgbe_host_interface_command");
4601 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4602 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4603 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4606 /* Take management host interface semaphore */
4607 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4611 status = ixgbe_hic_unlocked(hw, buffer, length, timeout);
4618 /* Calculate length in DWORDs */
4619 dword_len = hdr_size >> 2;
4621 /* first pull in the header so we know the buffer length */
4622 for (bi = 0; bi < dword_len; bi++) {
4623 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4624 IXGBE_LE32_TO_CPUS((uintptr_t)&buffer[bi]);
4628 * If there is any thing in data position pull it in
4629 * Read Flash command requires reading buffer length from
4630 * two byes instead of one byte
4632 if (resp->cmd == 0x30) {
4633 for (; bi < dword_len + 2; bi++) {
4634 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4636 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4638 buf_len = (((u16)(resp->cmd_or_resp.ret_status) << 3)
4639 & 0xF00) | resp->buf_len;
4640 hdr_size += (2 << 2);
4642 buf_len = resp->buf_len;
4647 if (length < buf_len + hdr_size) {
4648 DEBUGOUT("Buffer not large enough for reply message.\n");
4649 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4653 /* Calculate length in DWORDs, add 3 for odd lengths */
4654 dword_len = (buf_len + 3) >> 2;
4656 /* Pull in the rest of the buffer (bi is where we left off) */
4657 for (; bi <= dword_len; bi++) {
4658 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4659 IXGBE_LE32_TO_CPUS((uintptr_t)&buffer[bi]);
4663 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4669 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4670 * @hw: pointer to the HW structure
4671 * @maj: driver version major number
4672 * @min: driver version minor number
4673 * @build: driver version build number
4674 * @sub: driver version sub build number
4676 * @driver_ver: unused
4678 * Sends driver version number to firmware through the manageability
4679 * block. On success return IXGBE_SUCCESS
4680 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4681 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4683 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4684 u8 build, u8 sub, u16 len,
4685 const char *driver_ver)
4687 struct ixgbe_hic_drv_info fw_cmd;
4689 s32 ret_val = IXGBE_SUCCESS;
4691 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4692 UNREFERENCED_2PARAMETER(len, driver_ver);
4694 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4695 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4696 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4697 fw_cmd.port_num = (u8)hw->bus.func;
4698 fw_cmd.ver_maj = maj;
4699 fw_cmd.ver_min = min;
4700 fw_cmd.ver_build = build;
4701 fw_cmd.ver_sub = sub;
4702 fw_cmd.hdr.checksum = 0;
4705 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4706 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4708 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4709 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4711 IXGBE_HI_COMMAND_TIMEOUT,
4713 if (ret_val != IXGBE_SUCCESS)
4716 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4717 FW_CEM_RESP_STATUS_SUCCESS)
4718 ret_val = IXGBE_SUCCESS;
4720 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4729 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4730 * @hw: pointer to hardware structure
4731 * @num_pb: number of packet buffers to allocate
4732 * @headroom: reserve n KB of headroom
4733 * @strategy: packet buffer allocation strategy
4735 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4738 u32 pbsize = hw->mac.rx_pb_size;
4740 u32 rxpktsize, txpktsize, txpbthresh;
4742 /* Reserve headroom */
4748 /* Divide remaining packet buffer space amongst the number of packet
4749 * buffers requested using supplied strategy.
4752 case PBA_STRATEGY_WEIGHTED:
4753 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4754 * buffer with 5/8 of the packet buffer space.
4756 rxpktsize = (pbsize * 5) / (num_pb * 4);
4757 pbsize -= rxpktsize * (num_pb / 2);
4758 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4759 for (; i < (num_pb / 2); i++)
4760 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4761 /* fall through - configure remaining packet buffers */
4762 case PBA_STRATEGY_EQUAL:
4763 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4764 for (; i < num_pb; i++)
4765 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4771 /* Only support an equally distributed Tx packet buffer strategy. */
4772 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4773 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4774 for (i = 0; i < num_pb; i++) {
4775 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4776 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4779 /* Clear unused TCs, if any, to zero buffer size*/
4780 for (; i < IXGBE_MAX_PB; i++) {
4781 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4782 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4783 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4788 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4789 * @hw: pointer to the hardware structure
4791 * The 82599 and x540 MACs can experience issues if TX work is still pending
4792 * when a reset occurs. This function prevents this by flushing the PCIe
4793 * buffers on the system.
4795 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4797 u32 gcr_ext, hlreg0, i, poll;
4801 * If double reset is not requested then all transactions should
4802 * already be clear and as such there is no work to do
4804 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4808 * Set loopback enable to prevent any transmits from being sent
4809 * should the link come up. This assumes that the RXCTRL.RXEN bit
4810 * has already been cleared.
4812 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4813 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4815 /* Wait for a last completion before clearing buffers */
4816 IXGBE_WRITE_FLUSH(hw);
4820 * Before proceeding, make sure that the PCIe block does not have
4821 * transactions pending.
4823 poll = ixgbe_pcie_timeout_poll(hw);
4824 for (i = 0; i < poll; i++) {
4826 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
4827 if (IXGBE_REMOVED(hw->hw_addr))
4829 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
4834 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4835 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4836 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4837 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4839 /* Flush all writes and allow 20usec for all transactions to clear */
4840 IXGBE_WRITE_FLUSH(hw);
4843 /* restore previous register values */
4844 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4845 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4848 STATIC const u8 ixgbe_emc_temp_data[4] = {
4849 IXGBE_EMC_INTERNAL_DATA,
4850 IXGBE_EMC_DIODE1_DATA,
4851 IXGBE_EMC_DIODE2_DATA,
4852 IXGBE_EMC_DIODE3_DATA
4854 STATIC const u8 ixgbe_emc_therm_limit[4] = {
4855 IXGBE_EMC_INTERNAL_THERM_LIMIT,
4856 IXGBE_EMC_DIODE1_THERM_LIMIT,
4857 IXGBE_EMC_DIODE2_THERM_LIMIT,
4858 IXGBE_EMC_DIODE3_THERM_LIMIT
4862 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
4863 * @hw: pointer to hardware structure
4865 * Returns the thermal sensor data structure
4867 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
4869 s32 status = IXGBE_SUCCESS;
4877 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4879 DEBUGFUNC("ixgbe_get_thermal_sensor_data_generic");
4881 /* Only support thermal sensors attached to 82599 physical port 0 */
4882 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4883 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
4884 status = IXGBE_NOT_IMPLEMENTED;
4888 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);
4892 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) {
4893 status = IXGBE_NOT_IMPLEMENTED;
4897 status = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);
4901 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4902 != IXGBE_ETS_TYPE_EMC) {
4903 status = IXGBE_NOT_IMPLEMENTED;
4907 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4908 if (num_sensors > IXGBE_MAX_SENSORS)
4909 num_sensors = IXGBE_MAX_SENSORS;
4911 for (i = 0; i < num_sensors; i++) {
4912 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
4917 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4918 IXGBE_ETS_DATA_INDEX_SHIFT);
4919 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4920 IXGBE_ETS_DATA_LOC_SHIFT);
4922 if (sensor_location != 0) {
4923 status = hw->phy.ops.read_i2c_byte(hw,
4924 ixgbe_emc_temp_data[sensor_index],
4925 IXGBE_I2C_THERMAL_SENSOR_ADDR,
4926 &data->sensor[i].temp);
4936 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
4937 * @hw: pointer to hardware structure
4939 * Inits the thermal sensor thresholds according to the NVM map
4940 * and save off the threshold and location values into mac.thermal_sensor_data
4942 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
4944 s32 status = IXGBE_SUCCESS;
4949 u8 low_thresh_delta;
4955 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4957 DEBUGFUNC("ixgbe_init_thermal_sensor_thresh_generic");
4959 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
4961 /* Only support thermal sensors attached to 82599 physical port 0 */
4962 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4963 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
4964 return IXGBE_NOT_IMPLEMENTED;
4966 offset = IXGBE_ETS_CFG;
4967 if (hw->eeprom.ops.read(hw, offset, &ets_offset))
4969 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
4970 return IXGBE_NOT_IMPLEMENTED;
4972 offset = ets_offset;
4973 if (hw->eeprom.ops.read(hw, offset, &ets_cfg))
4975 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4976 != IXGBE_ETS_TYPE_EMC)
4977 return IXGBE_NOT_IMPLEMENTED;
4979 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
4980 IXGBE_ETS_LTHRES_DELTA_SHIFT);
4981 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4983 for (i = 0; i < num_sensors; i++) {
4984 offset = ets_offset + 1 + i;
4985 if (hw->eeprom.ops.read(hw, offset, &ets_sensor)) {
4986 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4987 "eeprom read at offset %d failed",
4991 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4992 IXGBE_ETS_DATA_INDEX_SHIFT);
4993 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4994 IXGBE_ETS_DATA_LOC_SHIFT);
4995 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
4997 hw->phy.ops.write_i2c_byte(hw,
4998 ixgbe_emc_therm_limit[sensor_index],
4999 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
5001 if ((i < IXGBE_MAX_SENSORS) && (sensor_location != 0)) {
5002 data->sensor[i].location = sensor_location;
5003 data->sensor[i].caution_thresh = therm_limit;
5004 data->sensor[i].max_op_thresh = therm_limit -
5011 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
5012 "eeprom read at offset %d failed", offset);
5013 return IXGBE_NOT_IMPLEMENTED;
5017 * ixgbe_get_orom_version - Return option ROM from EEPROM
5019 * @hw: pointer to hardware structure
5020 * @nvm_ver: pointer to output structure
5022 * if valid option ROM version, nvm_ver->or_valid set to true
5023 * else nvm_ver->or_valid is false.
5025 void ixgbe_get_orom_version(struct ixgbe_hw *hw,
5026 struct ixgbe_nvm_version *nvm_ver)
5028 u16 offset, eeprom_cfg_blkh, eeprom_cfg_blkl;
5030 nvm_ver->or_valid = false;
5031 /* Option Rom may or may not be present. Start with pointer */
5032 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset);
5034 /* make sure offset is valid */
5035 if ((offset == 0x0) || (offset == NVM_INVALID_PTR))
5038 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh);
5039 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl);
5041 /* option rom exists and is valid */
5042 if ((eeprom_cfg_blkl | eeprom_cfg_blkh) == 0x0 ||
5043 eeprom_cfg_blkl == NVM_VER_INVALID ||
5044 eeprom_cfg_blkh == NVM_VER_INVALID)
5047 nvm_ver->or_valid = true;
5048 nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT;
5049 nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) |
5050 (eeprom_cfg_blkh >> NVM_OROM_SHIFT);
5051 nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK;
5055 * ixgbe_get_oem_prod_version - Return OEM Product version
5057 * @hw: pointer to hardware structure
5058 * @nvm_ver: pointer to output structure
5060 * if valid OEM product version, nvm_ver->oem_valid set to true
5061 * else nvm_ver->oem_valid is false.
5063 void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw,
5064 struct ixgbe_nvm_version *nvm_ver)
5066 u16 rel_num, prod_ver, mod_len, cap, offset;
5068 nvm_ver->oem_valid = false;
5069 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset);
5071 /* Return is offset to OEM Product Version block is invalid */
5072 if (offset == 0x0 && offset == NVM_INVALID_PTR)
5075 /* Read product version block */
5076 hw->eeprom.ops.read(hw, offset, &mod_len);
5077 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap);
5079 /* Return if OEM product version block is invalid */
5080 if (mod_len != NVM_OEM_PROD_VER_MOD_LEN ||
5081 (cap & NVM_OEM_PROD_VER_CAP_MASK) != 0x0)
5084 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver);
5085 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num);
5087 /* Return if version is invalid */
5088 if ((rel_num | prod_ver) == 0x0 ||
5089 rel_num == NVM_VER_INVALID || prod_ver == NVM_VER_INVALID)
5092 nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT;
5093 nvm_ver->oem_minor = prod_ver & NVM_VER_MASK;
5094 nvm_ver->oem_release = rel_num;
5095 nvm_ver->oem_valid = true;
5099 * ixgbe_get_etk_id - Return Etrack ID from EEPROM
5101 * @hw: pointer to hardware structure
5102 * @nvm_ver: pointer to output structure
5104 * word read errors will return 0xFFFF
5106 void ixgbe_get_etk_id(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver)
5108 u16 etk_id_l, etk_id_h;
5110 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l))
5111 etk_id_l = NVM_VER_INVALID;
5112 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h))
5113 etk_id_h = NVM_VER_INVALID;
5115 /* The word order for the version format is determined by high order
5118 if ((etk_id_h & NVM_ETK_VALID) == 0) {
5119 nvm_ver->etk_id = etk_id_h;
5120 nvm_ver->etk_id |= (etk_id_l << NVM_ETK_SHIFT);
5122 nvm_ver->etk_id = etk_id_l;
5123 nvm_ver->etk_id |= (etk_id_h << NVM_ETK_SHIFT);
5129 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
5130 * @hw: pointer to hardware structure
5131 * @map: pointer to u8 arr for returning map
5133 * Read the rtrup2tc HW register and resolve its content into map
5135 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
5139 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
5140 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
5141 map[i] = IXGBE_RTRUP2TC_UP_MASK &
5142 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
5146 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
5151 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5152 if (rxctrl & IXGBE_RXCTRL_RXEN) {
5153 if (hw->mac.type != ixgbe_mac_82598EB) {
5154 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5155 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
5156 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
5157 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
5158 hw->mac.set_lben = true;
5160 hw->mac.set_lben = false;
5163 rxctrl &= ~IXGBE_RXCTRL_RXEN;
5164 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
5168 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
5173 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5174 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
5176 if (hw->mac.type != ixgbe_mac_82598EB) {
5177 if (hw->mac.set_lben) {
5178 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5179 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
5180 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
5181 hw->mac.set_lben = false;
5187 * ixgbe_mng_present - returns true when management capability is present
5188 * @hw: pointer to hardware structure
5190 bool ixgbe_mng_present(struct ixgbe_hw *hw)
5194 if (hw->mac.type < ixgbe_mac_82599EB)
5197 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5199 return !!(fwsm & IXGBE_FWSM_FW_MODE_PT);
5203 * ixgbe_mng_enabled - Is the manageability engine enabled?
5204 * @hw: pointer to hardware structure
5206 * Returns true if the manageability engine is enabled.
5208 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
5210 u32 fwsm, manc, factps;
5212 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5213 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
5216 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
5217 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
5220 if (hw->mac.type <= ixgbe_mac_X540) {
5221 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
5222 if (factps & IXGBE_FACTPS_MNGCG)
5230 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
5231 * @hw: pointer to hardware structure
5232 * @speed: new link speed
5233 * @autoneg_wait_to_complete: true when waiting for completion is needed
5235 * Set the link speed in the MAC and/or PHY register and restarts link.
5237 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
5238 ixgbe_link_speed speed,
5239 bool autoneg_wait_to_complete)
5241 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
5242 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
5243 s32 status = IXGBE_SUCCESS;
5246 bool autoneg, link_up = false;
5248 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
5250 /* Mask off requested but non-supported speeds */
5251 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
5252 if (status != IXGBE_SUCCESS)
5255 speed &= link_speed;
5257 /* Try each speed one by one, highest priority first. We do this in
5258 * software because 10Gb fiber doesn't support speed autonegotiation.
5260 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
5262 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5264 /* Set the module link speed */
5265 switch (hw->phy.media_type) {
5266 case ixgbe_media_type_fiber:
5267 ixgbe_set_rate_select_speed(hw,
5268 IXGBE_LINK_SPEED_10GB_FULL);
5270 case ixgbe_media_type_fiber_qsfp:
5271 /* QSFP module automatically detects MAC link speed */
5274 DEBUGOUT("Unexpected media type.\n");
5278 /* Allow module to change analog characteristics (1G->10G) */
5281 status = ixgbe_setup_mac_link(hw,
5282 IXGBE_LINK_SPEED_10GB_FULL,
5283 autoneg_wait_to_complete);
5284 if (status != IXGBE_SUCCESS)
5287 /* Flap the Tx laser if it has not already been done */
5288 ixgbe_flap_tx_laser(hw);
5290 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
5291 * Section 73.10.2, we may have to wait up to 500ms if KR is
5292 * attempted. 82599 uses the same timing for 10g SFI.
5294 for (i = 0; i < 5; i++) {
5295 /* Wait for the link partner to also set speed */
5298 /* If we have link, just jump out */
5299 status = ixgbe_check_link(hw, &link_speed,
5301 if (status != IXGBE_SUCCESS)
5309 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
5311 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
5312 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
5314 /* Set the module link speed */
5315 switch (hw->phy.media_type) {
5316 case ixgbe_media_type_fiber:
5317 ixgbe_set_rate_select_speed(hw,
5318 IXGBE_LINK_SPEED_1GB_FULL);
5320 case ixgbe_media_type_fiber_qsfp:
5321 /* QSFP module automatically detects link speed */
5324 DEBUGOUT("Unexpected media type.\n");
5328 /* Allow module to change analog characteristics (10G->1G) */
5331 status = ixgbe_setup_mac_link(hw,
5332 IXGBE_LINK_SPEED_1GB_FULL,
5333 autoneg_wait_to_complete);
5334 if (status != IXGBE_SUCCESS)
5337 /* Flap the Tx laser if it has not already been done */
5338 ixgbe_flap_tx_laser(hw);
5340 /* Wait for the link partner to also set speed */
5343 /* If we have link, just jump out */
5344 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
5345 if (status != IXGBE_SUCCESS)
5352 /* We didn't get link. Configure back to the highest speed we tried,
5353 * (if there was more than one). We call ourselves back with just the
5354 * single highest speed that the user requested.
5357 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
5359 autoneg_wait_to_complete);
5362 /* Set autoneg_advertised value based on input link speed */
5363 hw->phy.autoneg_advertised = 0;
5365 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
5366 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
5368 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
5369 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
5375 * ixgbe_set_soft_rate_select_speed - Set module link speed
5376 * @hw: pointer to hardware structure
5377 * @speed: link speed to set
5379 * Set module link speed via the soft rate select.
5381 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
5382 ixgbe_link_speed speed)
5388 case IXGBE_LINK_SPEED_10GB_FULL:
5389 /* one bit mask same as setting on */
5390 rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
5392 case IXGBE_LINK_SPEED_1GB_FULL:
5393 rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
5396 DEBUGOUT("Invalid fixed module speed\n");
5401 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5402 IXGBE_I2C_EEPROM_DEV_ADDR2,
5405 DEBUGOUT("Failed to read Rx Rate Select RS0\n");
5409 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5411 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5412 IXGBE_I2C_EEPROM_DEV_ADDR2,
5415 DEBUGOUT("Failed to write Rx Rate Select RS0\n");
5420 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5421 IXGBE_I2C_EEPROM_DEV_ADDR2,
5424 DEBUGOUT("Failed to read Rx Rate Select RS1\n");
5428 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5430 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5431 IXGBE_I2C_EEPROM_DEV_ADDR2,
5434 DEBUGOUT("Failed to write Rx Rate Select RS1\n");