1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
5 #include "ixgbe_common.h"
8 #include "ixgbe_dcb_82599.h"
11 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
12 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
13 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
14 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
15 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
16 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
18 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
19 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
20 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
21 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw);
23 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
24 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
26 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
27 u16 words, u16 *data);
28 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
29 u16 words, u16 *data);
30 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
34 * ixgbe_init_ops_generic - Inits function ptrs
35 * @hw: pointer to the hardware structure
37 * Initialize the function pointers.
39 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
41 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
42 struct ixgbe_mac_info *mac = &hw->mac;
43 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
45 DEBUGFUNC("ixgbe_init_ops_generic");
48 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic;
49 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
50 if (eec & IXGBE_EEC_PRES) {
51 eeprom->ops.read = ixgbe_read_eerd_generic;
52 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic;
54 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic;
55 eeprom->ops.read_buffer =
56 ixgbe_read_eeprom_buffer_bit_bang_generic;
58 eeprom->ops.write = ixgbe_write_eeprom_generic;
59 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic;
60 eeprom->ops.validate_checksum =
61 ixgbe_validate_eeprom_checksum_generic;
62 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic;
63 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic;
66 mac->ops.init_hw = ixgbe_init_hw_generic;
67 mac->ops.reset_hw = NULL;
68 mac->ops.start_hw = ixgbe_start_hw_generic;
69 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic;
70 mac->ops.get_media_type = NULL;
71 mac->ops.get_supported_physical_layer = NULL;
72 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic;
73 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic;
74 mac->ops.stop_adapter = ixgbe_stop_adapter_generic;
75 mac->ops.get_bus_info = ixgbe_get_bus_info_generic;
76 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie;
77 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync;
78 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync;
79 mac->ops.prot_autoc_read = prot_autoc_read_generic;
80 mac->ops.prot_autoc_write = prot_autoc_write_generic;
83 mac->ops.led_on = ixgbe_led_on_generic;
84 mac->ops.led_off = ixgbe_led_off_generic;
85 mac->ops.blink_led_start = ixgbe_blink_led_start_generic;
86 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic;
87 mac->ops.init_led_link_act = ixgbe_init_led_link_act_generic;
89 /* RAR, Multicast, VLAN */
90 mac->ops.set_rar = ixgbe_set_rar_generic;
91 mac->ops.clear_rar = ixgbe_clear_rar_generic;
92 mac->ops.insert_mac_addr = NULL;
93 mac->ops.set_vmdq = NULL;
94 mac->ops.clear_vmdq = NULL;
95 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic;
96 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic;
97 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic;
98 mac->ops.enable_mc = ixgbe_enable_mc_generic;
99 mac->ops.disable_mc = ixgbe_disable_mc_generic;
100 mac->ops.clear_vfta = NULL;
101 mac->ops.set_vfta = NULL;
102 mac->ops.set_vlvf = NULL;
103 mac->ops.init_uta_tables = NULL;
104 mac->ops.enable_rx = ixgbe_enable_rx_generic;
105 mac->ops.disable_rx = ixgbe_disable_rx_generic;
108 mac->ops.fc_enable = ixgbe_fc_enable_generic;
109 mac->ops.setup_fc = ixgbe_setup_fc_generic;
110 mac->ops.fc_autoneg = ixgbe_fc_autoneg;
113 mac->ops.get_link_capabilities = NULL;
114 mac->ops.setup_link = NULL;
115 mac->ops.check_link = NULL;
116 mac->ops.dmac_config = NULL;
117 mac->ops.dmac_update_tcs = NULL;
118 mac->ops.dmac_config_tcs = NULL;
120 return IXGBE_SUCCESS;
124 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
126 * @hw: pointer to hardware structure
128 * This function returns true if the device supports flow control
129 * autonegotiation, and false if it does not.
132 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
134 bool supported = false;
135 ixgbe_link_speed speed;
138 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
140 switch (hw->phy.media_type) {
141 case ixgbe_media_type_fiber_qsfp:
142 case ixgbe_media_type_fiber:
143 /* flow control autoneg black list */
144 switch (hw->device_id) {
145 case IXGBE_DEV_ID_X550EM_A_SFP:
146 case IXGBE_DEV_ID_X550EM_A_SFP_N:
147 case IXGBE_DEV_ID_X550EM_A_QSFP:
148 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
152 hw->mac.ops.check_link(hw, &speed, &link_up, false);
153 /* if link is down, assume supported */
155 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
162 case ixgbe_media_type_backplane:
163 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI)
168 case ixgbe_media_type_copper:
169 /* only some copper devices support flow control autoneg */
170 switch (hw->device_id) {
171 case IXGBE_DEV_ID_82599_T3_LOM:
172 case IXGBE_DEV_ID_X540T:
173 case IXGBE_DEV_ID_X540T1:
174 case IXGBE_DEV_ID_X550T:
175 case IXGBE_DEV_ID_X550T1:
176 case IXGBE_DEV_ID_X550EM_X_10G_T:
177 case IXGBE_DEV_ID_X550EM_A_10G_T:
178 case IXGBE_DEV_ID_X550EM_A_1G_T:
179 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
193 * ixgbe_setup_fc_generic - Set up flow control
194 * @hw: pointer to hardware structure
196 * Called at init time to set up flow control.
198 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
200 s32 ret_val = IXGBE_SUCCESS;
201 u32 reg = 0, reg_bp = 0;
205 DEBUGFUNC("ixgbe_setup_fc_generic");
207 /* Validate the requested mode */
208 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
209 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
210 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
211 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
216 * 10gig parts do not have a word in the EEPROM to determine the
217 * default flow control setting, so we explicitly set it to full.
219 if (hw->fc.requested_mode == ixgbe_fc_default)
220 hw->fc.requested_mode = ixgbe_fc_full;
223 * Set up the 1G and 10G flow control advertisement registers so the
224 * HW will be able to do fc autoneg once the cable is plugged in. If
225 * we link at 10G, the 1G advertisement is harmless and vice versa.
227 switch (hw->phy.media_type) {
228 case ixgbe_media_type_backplane:
229 /* some MAC's need RMW protection on AUTOC */
230 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
231 if (ret_val != IXGBE_SUCCESS)
234 /* fall through - only backplane uses autoc */
235 case ixgbe_media_type_fiber_qsfp:
236 case ixgbe_media_type_fiber:
237 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
240 case ixgbe_media_type_copper:
241 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
242 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
249 * The possible values of fc.requested_mode are:
250 * 0: Flow control is completely disabled
251 * 1: Rx flow control is enabled (we can receive pause frames,
252 * but not send pause frames).
253 * 2: Tx flow control is enabled (we can send pause frames but
254 * we do not support receiving pause frames).
255 * 3: Both Rx and Tx flow control (symmetric) are enabled.
258 switch (hw->fc.requested_mode) {
260 /* Flow control completely disabled by software override. */
261 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
262 if (hw->phy.media_type == ixgbe_media_type_backplane)
263 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
264 IXGBE_AUTOC_ASM_PAUSE);
265 else if (hw->phy.media_type == ixgbe_media_type_copper)
266 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
268 case ixgbe_fc_tx_pause:
270 * Tx Flow control is enabled, and Rx Flow control is
271 * disabled by software override.
273 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
274 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
275 if (hw->phy.media_type == ixgbe_media_type_backplane) {
276 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
277 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
278 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
279 reg_cu |= IXGBE_TAF_ASM_PAUSE;
280 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
283 case ixgbe_fc_rx_pause:
285 * Rx Flow control is enabled and Tx Flow control is
286 * disabled by software override. Since there really
287 * isn't a way to advertise that we are capable of RX
288 * Pause ONLY, we will advertise that we support both
289 * symmetric and asymmetric Rx PAUSE, as such we fall
290 * through to the fc_full statement. Later, we will
291 * disable the adapter's ability to send PAUSE frames.
294 /* Flow control (both Rx and Tx) is enabled by SW override. */
295 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
296 if (hw->phy.media_type == ixgbe_media_type_backplane)
297 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
298 IXGBE_AUTOC_ASM_PAUSE;
299 else if (hw->phy.media_type == ixgbe_media_type_copper)
300 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
303 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
304 "Flow control param set incorrectly\n");
305 ret_val = IXGBE_ERR_CONFIG;
310 if (hw->mac.type < ixgbe_mac_X540) {
312 * Enable auto-negotiation between the MAC & PHY;
313 * the MAC will advertise clause 37 flow control.
315 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
316 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
318 /* Disable AN timeout */
319 if (hw->fc.strict_ieee)
320 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
322 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
323 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
327 * AUTOC restart handles negotiation of 1G and 10G on backplane
328 * and copper. There is no need to set the PCS1GCTL register.
331 if (hw->phy.media_type == ixgbe_media_type_backplane) {
332 reg_bp |= IXGBE_AUTOC_AN_RESTART;
333 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
336 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
337 (ixgbe_device_supports_autoneg_fc(hw))) {
338 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
339 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
342 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
348 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
349 * @hw: pointer to hardware structure
351 * Starts the hardware by filling the bus info structure and media type, clears
352 * all on chip counters, initializes receive address registers, multicast
353 * table, VLAN filter table, calls routine to set up link and flow control
354 * settings, and leaves transmit and receive units disabled and uninitialized
356 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
362 DEBUGFUNC("ixgbe_start_hw_generic");
364 /* Set the media type */
365 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
367 /* PHY ops initialization must be done in reset_hw() */
369 /* Clear the VLAN filter table */
370 hw->mac.ops.clear_vfta(hw);
372 /* Clear statistics registers */
373 hw->mac.ops.clear_hw_cntrs(hw);
375 /* Set No Snoop Disable */
376 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
377 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
378 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
379 IXGBE_WRITE_FLUSH(hw);
381 /* Setup flow control */
382 ret_val = ixgbe_setup_fc(hw);
383 if (ret_val != IXGBE_SUCCESS && ret_val != IXGBE_NOT_IMPLEMENTED) {
384 DEBUGOUT1("Flow control setup failed, returning %d\n", ret_val);
388 /* Cache bit indicating need for crosstalk fix */
389 switch (hw->mac.type) {
390 case ixgbe_mac_82599EB:
391 case ixgbe_mac_X550EM_x:
392 case ixgbe_mac_X550EM_a:
393 hw->mac.ops.get_device_caps(hw, &device_caps);
394 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
395 hw->need_crosstalk_fix = false;
397 hw->need_crosstalk_fix = true;
400 hw->need_crosstalk_fix = false;
404 /* Clear adapter stopped flag */
405 hw->adapter_stopped = false;
407 return IXGBE_SUCCESS;
411 * ixgbe_start_hw_gen2 - Init sequence for common device family
412 * @hw: pointer to hw structure
414 * Performs the init sequence common to the second generation
416 * Devices in the second generation:
420 void ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
425 /* Clear the rate limiters */
426 for (i = 0; i < hw->mac.max_tx_queues; i++) {
427 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
428 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
430 IXGBE_WRITE_FLUSH(hw);
432 /* Disable relaxed ordering */
433 for (i = 0; i < hw->mac.max_tx_queues; i++) {
434 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
435 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
436 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
439 for (i = 0; i < hw->mac.max_rx_queues; i++) {
440 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
441 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
442 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
443 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
448 * ixgbe_init_hw_generic - Generic hardware initialization
449 * @hw: pointer to hardware structure
451 * Initialize the hardware by resetting the hardware, filling the bus info
452 * structure and media type, clears all on chip counters, initializes receive
453 * address registers, multicast table, VLAN filter table, calls routine to set
454 * up link and flow control settings, and leaves transmit and receive units
455 * disabled and uninitialized
457 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
461 DEBUGFUNC("ixgbe_init_hw_generic");
463 /* Reset the hardware */
464 status = hw->mac.ops.reset_hw(hw);
466 if (status == IXGBE_SUCCESS || status == IXGBE_ERR_SFP_NOT_PRESENT) {
468 status = hw->mac.ops.start_hw(hw);
471 /* Initialize the LED link active for LED blink support */
472 if (hw->mac.ops.init_led_link_act)
473 hw->mac.ops.init_led_link_act(hw);
475 if (status != IXGBE_SUCCESS)
476 DEBUGOUT1("Failed to initialize HW, STATUS = %d\n", status);
482 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
483 * @hw: pointer to hardware structure
485 * Clears all hardware statistics counters by reading them from the hardware
486 * Statistics counters are clear on read.
488 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
492 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
494 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
495 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
496 IXGBE_READ_REG(hw, IXGBE_ERRBC);
497 IXGBE_READ_REG(hw, IXGBE_MSPDC);
498 for (i = 0; i < 8; i++)
499 IXGBE_READ_REG(hw, IXGBE_MPC(i));
501 IXGBE_READ_REG(hw, IXGBE_MLFC);
502 IXGBE_READ_REG(hw, IXGBE_MRFC);
503 IXGBE_READ_REG(hw, IXGBE_RLEC);
504 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
505 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
506 if (hw->mac.type >= ixgbe_mac_82599EB) {
507 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
508 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
510 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
511 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
514 for (i = 0; i < 8; i++) {
515 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
516 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
517 if (hw->mac.type >= ixgbe_mac_82599EB) {
518 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
519 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
521 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
522 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
525 if (hw->mac.type >= ixgbe_mac_82599EB)
526 for (i = 0; i < 8; i++)
527 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
528 IXGBE_READ_REG(hw, IXGBE_PRC64);
529 IXGBE_READ_REG(hw, IXGBE_PRC127);
530 IXGBE_READ_REG(hw, IXGBE_PRC255);
531 IXGBE_READ_REG(hw, IXGBE_PRC511);
532 IXGBE_READ_REG(hw, IXGBE_PRC1023);
533 IXGBE_READ_REG(hw, IXGBE_PRC1522);
534 IXGBE_READ_REG(hw, IXGBE_GPRC);
535 IXGBE_READ_REG(hw, IXGBE_BPRC);
536 IXGBE_READ_REG(hw, IXGBE_MPRC);
537 IXGBE_READ_REG(hw, IXGBE_GPTC);
538 IXGBE_READ_REG(hw, IXGBE_GORCL);
539 IXGBE_READ_REG(hw, IXGBE_GORCH);
540 IXGBE_READ_REG(hw, IXGBE_GOTCL);
541 IXGBE_READ_REG(hw, IXGBE_GOTCH);
542 if (hw->mac.type == ixgbe_mac_82598EB)
543 for (i = 0; i < 8; i++)
544 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
545 IXGBE_READ_REG(hw, IXGBE_RUC);
546 IXGBE_READ_REG(hw, IXGBE_RFC);
547 IXGBE_READ_REG(hw, IXGBE_ROC);
548 IXGBE_READ_REG(hw, IXGBE_RJC);
549 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
550 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
551 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
552 IXGBE_READ_REG(hw, IXGBE_TORL);
553 IXGBE_READ_REG(hw, IXGBE_TORH);
554 IXGBE_READ_REG(hw, IXGBE_TPR);
555 IXGBE_READ_REG(hw, IXGBE_TPT);
556 IXGBE_READ_REG(hw, IXGBE_PTC64);
557 IXGBE_READ_REG(hw, IXGBE_PTC127);
558 IXGBE_READ_REG(hw, IXGBE_PTC255);
559 IXGBE_READ_REG(hw, IXGBE_PTC511);
560 IXGBE_READ_REG(hw, IXGBE_PTC1023);
561 IXGBE_READ_REG(hw, IXGBE_PTC1522);
562 IXGBE_READ_REG(hw, IXGBE_MPTC);
563 IXGBE_READ_REG(hw, IXGBE_BPTC);
564 for (i = 0; i < 16; i++) {
565 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
566 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
567 if (hw->mac.type >= ixgbe_mac_82599EB) {
568 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
569 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
570 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
571 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
572 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
574 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
575 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
579 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
581 ixgbe_identify_phy(hw);
582 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
583 IXGBE_MDIO_PCS_DEV_TYPE, &i);
584 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
585 IXGBE_MDIO_PCS_DEV_TYPE, &i);
586 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
587 IXGBE_MDIO_PCS_DEV_TYPE, &i);
588 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
589 IXGBE_MDIO_PCS_DEV_TYPE, &i);
592 return IXGBE_SUCCESS;
596 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
597 * @hw: pointer to hardware structure
598 * @pba_num: stores the part number string from the EEPROM
599 * @pba_num_size: part number string buffer length
601 * Reads the part number string from the EEPROM.
603 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
612 DEBUGFUNC("ixgbe_read_pba_string_generic");
614 if (pba_num == NULL) {
615 DEBUGOUT("PBA string buffer was null\n");
616 return IXGBE_ERR_INVALID_ARGUMENT;
619 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
621 DEBUGOUT("NVM Read Error\n");
625 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
627 DEBUGOUT("NVM Read Error\n");
632 * if data is not ptr guard the PBA must be in legacy format which
633 * means pba_ptr is actually our second data word for the PBA number
634 * and we can decode it into an ascii string
636 if (data != IXGBE_PBANUM_PTR_GUARD) {
637 DEBUGOUT("NVM PBA number is not stored as string\n");
639 /* we will need 11 characters to store the PBA */
640 if (pba_num_size < 11) {
641 DEBUGOUT("PBA string buffer too small\n");
642 return IXGBE_ERR_NO_SPACE;
645 /* extract hex string from data and pba_ptr */
646 pba_num[0] = (data >> 12) & 0xF;
647 pba_num[1] = (data >> 8) & 0xF;
648 pba_num[2] = (data >> 4) & 0xF;
649 pba_num[3] = data & 0xF;
650 pba_num[4] = (pba_ptr >> 12) & 0xF;
651 pba_num[5] = (pba_ptr >> 8) & 0xF;
654 pba_num[8] = (pba_ptr >> 4) & 0xF;
655 pba_num[9] = pba_ptr & 0xF;
657 /* put a null character on the end of our string */
660 /* switch all the data but the '-' to hex char */
661 for (offset = 0; offset < 10; offset++) {
662 if (pba_num[offset] < 0xA)
663 pba_num[offset] += '0';
664 else if (pba_num[offset] < 0x10)
665 pba_num[offset] += 'A' - 0xA;
668 return IXGBE_SUCCESS;
671 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
673 DEBUGOUT("NVM Read Error\n");
677 if (length == 0xFFFF || length == 0) {
678 DEBUGOUT("NVM PBA number section invalid length\n");
679 return IXGBE_ERR_PBA_SECTION;
682 /* check if pba_num buffer is big enough */
683 if (pba_num_size < (((u32)length * 2) - 1)) {
684 DEBUGOUT("PBA string buffer too small\n");
685 return IXGBE_ERR_NO_SPACE;
688 /* trim pba length from start of string */
692 for (offset = 0; offset < length; offset++) {
693 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
695 DEBUGOUT("NVM Read Error\n");
698 pba_num[offset * 2] = (u8)(data >> 8);
699 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
701 pba_num[offset * 2] = '\0';
703 return IXGBE_SUCCESS;
707 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
708 * @hw: pointer to hardware structure
709 * @pba_num: stores the part number from the EEPROM
711 * Reads the part number from the EEPROM.
713 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
718 DEBUGFUNC("ixgbe_read_pba_num_generic");
720 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
722 DEBUGOUT("NVM Read Error\n");
724 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
725 DEBUGOUT("NVM Not supported\n");
726 return IXGBE_NOT_IMPLEMENTED;
728 *pba_num = (u32)(data << 16);
730 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
732 DEBUGOUT("NVM Read Error\n");
735 *pba_num |= (u32)data;
737 return IXGBE_SUCCESS;
742 * @hw: pointer to the HW structure
743 * @eeprom_buf: optional pointer to EEPROM image
744 * @eeprom_buf_size: size of EEPROM image in words
745 * @max_pba_block_size: PBA block size limit
746 * @pba: pointer to output PBA structure
748 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
749 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
752 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
753 u32 eeprom_buf_size, u16 max_pba_block_size,
754 struct ixgbe_pba *pba)
760 return IXGBE_ERR_PARAM;
762 if (eeprom_buf == NULL) {
763 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
768 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
769 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
770 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
772 return IXGBE_ERR_PARAM;
776 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
777 if (pba->pba_block == NULL)
778 return IXGBE_ERR_PARAM;
780 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
786 if (pba_block_size > max_pba_block_size)
787 return IXGBE_ERR_PARAM;
789 if (eeprom_buf == NULL) {
790 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
796 if (eeprom_buf_size > (u32)(pba->word[1] +
798 memcpy(pba->pba_block,
799 &eeprom_buf[pba->word[1]],
800 pba_block_size * sizeof(u16));
802 return IXGBE_ERR_PARAM;
807 return IXGBE_SUCCESS;
811 * ixgbe_write_pba_raw
812 * @hw: pointer to the HW structure
813 * @eeprom_buf: optional pointer to EEPROM image
814 * @eeprom_buf_size: size of EEPROM image in words
815 * @pba: pointer to PBA structure
817 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
818 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
821 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
822 u32 eeprom_buf_size, struct ixgbe_pba *pba)
827 return IXGBE_ERR_PARAM;
829 if (eeprom_buf == NULL) {
830 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
835 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
836 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
837 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
839 return IXGBE_ERR_PARAM;
843 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
844 if (pba->pba_block == NULL)
845 return IXGBE_ERR_PARAM;
847 if (eeprom_buf == NULL) {
848 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
854 if (eeprom_buf_size > (u32)(pba->word[1] +
855 pba->pba_block[0])) {
856 memcpy(&eeprom_buf[pba->word[1]],
858 pba->pba_block[0] * sizeof(u16));
860 return IXGBE_ERR_PARAM;
865 return IXGBE_SUCCESS;
869 * ixgbe_get_pba_block_size
870 * @hw: pointer to the HW structure
871 * @eeprom_buf: optional pointer to EEPROM image
872 * @eeprom_buf_size: size of EEPROM image in words
873 * @pba_data_size: pointer to output variable
875 * Returns the size of the PBA block in words. Function operates on EEPROM
876 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
880 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
881 u32 eeprom_buf_size, u16 *pba_block_size)
887 DEBUGFUNC("ixgbe_get_pba_block_size");
889 if (eeprom_buf == NULL) {
890 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
895 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
896 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
897 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
899 return IXGBE_ERR_PARAM;
903 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
904 if (eeprom_buf == NULL) {
905 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
910 if (eeprom_buf_size > pba_word[1])
911 length = eeprom_buf[pba_word[1] + 0];
913 return IXGBE_ERR_PARAM;
916 if (length == 0xFFFF || length == 0)
917 return IXGBE_ERR_PBA_SECTION;
919 /* PBA number in legacy format, there is no PBA Block. */
923 if (pba_block_size != NULL)
924 *pba_block_size = length;
926 return IXGBE_SUCCESS;
930 * ixgbe_get_mac_addr_generic - Generic get MAC address
931 * @hw: pointer to hardware structure
932 * @mac_addr: Adapter MAC address
934 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
935 * A reset of the adapter must be performed prior to calling this function
936 * in order for the MAC address to have been loaded from the EEPROM into RAR0
938 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
944 DEBUGFUNC("ixgbe_get_mac_addr_generic");
946 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
947 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
949 for (i = 0; i < 4; i++)
950 mac_addr[i] = (u8)(rar_low >> (i*8));
952 for (i = 0; i < 2; i++)
953 mac_addr[i+4] = (u8)(rar_high >> (i*8));
955 return IXGBE_SUCCESS;
959 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
960 * @hw: pointer to hardware structure
961 * @link_status: the link status returned by the PCI config space
963 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
965 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
967 struct ixgbe_mac_info *mac = &hw->mac;
969 if (hw->bus.type == ixgbe_bus_type_unknown)
970 hw->bus.type = ixgbe_bus_type_pci_express;
972 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
973 case IXGBE_PCI_LINK_WIDTH_1:
974 hw->bus.width = ixgbe_bus_width_pcie_x1;
976 case IXGBE_PCI_LINK_WIDTH_2:
977 hw->bus.width = ixgbe_bus_width_pcie_x2;
979 case IXGBE_PCI_LINK_WIDTH_4:
980 hw->bus.width = ixgbe_bus_width_pcie_x4;
982 case IXGBE_PCI_LINK_WIDTH_8:
983 hw->bus.width = ixgbe_bus_width_pcie_x8;
986 hw->bus.width = ixgbe_bus_width_unknown;
990 switch (link_status & IXGBE_PCI_LINK_SPEED) {
991 case IXGBE_PCI_LINK_SPEED_2500:
992 hw->bus.speed = ixgbe_bus_speed_2500;
994 case IXGBE_PCI_LINK_SPEED_5000:
995 hw->bus.speed = ixgbe_bus_speed_5000;
997 case IXGBE_PCI_LINK_SPEED_8000:
998 hw->bus.speed = ixgbe_bus_speed_8000;
1001 hw->bus.speed = ixgbe_bus_speed_unknown;
1005 mac->ops.set_lan_id(hw);
1009 * ixgbe_get_bus_info_generic - Generic set PCI bus info
1010 * @hw: pointer to hardware structure
1012 * Gets the PCI bus info (speed, width, type) then calls helper function to
1013 * store this data within the ixgbe_hw structure.
1015 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
1019 DEBUGFUNC("ixgbe_get_bus_info_generic");
1021 /* Get the negotiated link width and speed from PCI config space */
1022 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
1024 ixgbe_set_pci_config_data_generic(hw, link_status);
1026 return IXGBE_SUCCESS;
1030 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
1031 * @hw: pointer to the HW structure
1033 * Determines the LAN function id by reading memory-mapped registers and swaps
1034 * the port value if requested, and set MAC instance for devices that share
1037 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
1039 struct ixgbe_bus_info *bus = &hw->bus;
1043 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
1045 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
1046 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
1047 bus->lan_id = (u8)bus->func;
1049 /* check for a port swap */
1050 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
1051 if (reg & IXGBE_FACTPS_LFS)
1054 /* Get MAC instance from EEPROM for configuring CS4227 */
1055 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) {
1056 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4);
1057 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >>
1058 IXGBE_EE_CTRL_4_INST_ID_SHIFT;
1063 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1064 * @hw: pointer to hardware structure
1066 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
1067 * disables transmit and receive units. The adapter_stopped flag is used by
1068 * the shared code and drivers to determine if the adapter is in a stopped
1069 * state and should not touch the hardware.
1071 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1076 DEBUGFUNC("ixgbe_stop_adapter_generic");
1079 * Set the adapter_stopped flag so other driver functions stop touching
1082 hw->adapter_stopped = true;
1084 /* Disable the receive unit */
1085 ixgbe_disable_rx(hw);
1087 /* Clear interrupt mask to stop interrupts from being generated */
1088 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1090 /* Clear any pending interrupts, flush previous writes */
1091 IXGBE_READ_REG(hw, IXGBE_EICR);
1093 /* Disable the transmit unit. Each queue must be disabled. */
1094 for (i = 0; i < hw->mac.max_tx_queues; i++)
1095 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1097 /* Disable the receive unit by stopping each queue */
1098 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1099 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1100 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1101 reg_val |= IXGBE_RXDCTL_SWFLSH;
1102 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1105 /* flush all queues disables */
1106 IXGBE_WRITE_FLUSH(hw);
1110 * Prevent the PCI-E bus from hanging by disabling PCI-E master
1111 * access and verify no pending requests
1113 return ixgbe_disable_pcie_master(hw);
1117 * ixgbe_init_led_link_act_generic - Store the LED index link/activity.
1118 * @hw: pointer to hardware structure
1120 * Store the index for the link active LED. This will be used to support
1123 s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw)
1125 struct ixgbe_mac_info *mac = &hw->mac;
1126 u32 led_reg, led_mode;
1129 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1131 /* Get LED link active from the LEDCTL register */
1132 for (i = 0; i < 4; i++) {
1133 led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i);
1135 if ((led_mode & IXGBE_LED_MODE_MASK_BASE) ==
1136 IXGBE_LED_LINK_ACTIVE) {
1137 mac->led_link_act = i;
1138 return IXGBE_SUCCESS;
1143 * If LEDCTL register does not have the LED link active set, then use
1144 * known MAC defaults.
1146 switch (hw->mac.type) {
1147 case ixgbe_mac_X550EM_a:
1148 case ixgbe_mac_X550EM_x:
1149 mac->led_link_act = 1;
1152 mac->led_link_act = 2;
1154 return IXGBE_SUCCESS;
1158 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1159 * @hw: pointer to hardware structure
1160 * @index: led number to turn on
1162 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1164 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1166 DEBUGFUNC("ixgbe_led_on_generic");
1169 return IXGBE_ERR_PARAM;
1171 /* To turn on the LED, set mode to ON. */
1172 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1173 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
1174 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1175 IXGBE_WRITE_FLUSH(hw);
1177 return IXGBE_SUCCESS;
1181 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1182 * @hw: pointer to hardware structure
1183 * @index: led number to turn off
1185 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1187 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1189 DEBUGFUNC("ixgbe_led_off_generic");
1192 return IXGBE_ERR_PARAM;
1194 /* To turn off the LED, set mode to OFF. */
1195 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1196 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
1197 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1198 IXGBE_WRITE_FLUSH(hw);
1200 return IXGBE_SUCCESS;
1204 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1205 * @hw: pointer to hardware structure
1207 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1208 * ixgbe_hw struct in order to set up EEPROM access.
1210 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1212 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1216 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
1218 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1219 eeprom->type = ixgbe_eeprom_none;
1220 /* Set default semaphore delay to 10ms which is a well
1222 eeprom->semaphore_delay = 10;
1223 /* Clear EEPROM page size, it will be initialized as needed */
1224 eeprom->word_page_size = 0;
1227 * Check for EEPROM present first.
1228 * If not present leave as none
1230 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1231 if (eec & IXGBE_EEC_PRES) {
1232 eeprom->type = ixgbe_eeprom_spi;
1235 * SPI EEPROM is assumed here. This code would need to
1236 * change if a future EEPROM is not SPI.
1238 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1239 IXGBE_EEC_SIZE_SHIFT);
1240 eeprom->word_size = 1 << (eeprom_size +
1241 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1244 if (eec & IXGBE_EEC_ADDR_SIZE)
1245 eeprom->address_bits = 16;
1247 eeprom->address_bits = 8;
1248 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
1249 "%d\n", eeprom->type, eeprom->word_size,
1250 eeprom->address_bits);
1253 return IXGBE_SUCCESS;
1257 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1258 * @hw: pointer to hardware structure
1259 * @offset: offset within the EEPROM to write
1260 * @words: number of word(s)
1261 * @data: 16 bit word(s) to write to EEPROM
1263 * Reads 16 bit word(s) from EEPROM through bit-bang method
1265 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1266 u16 words, u16 *data)
1268 s32 status = IXGBE_SUCCESS;
1271 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
1273 hw->eeprom.ops.init_params(hw);
1276 status = IXGBE_ERR_INVALID_ARGUMENT;
1280 if (offset + words > hw->eeprom.word_size) {
1281 status = IXGBE_ERR_EEPROM;
1286 * The EEPROM page size cannot be queried from the chip. We do lazy
1287 * initialization. It is worth to do that when we write large buffer.
1289 if ((hw->eeprom.word_page_size == 0) &&
1290 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
1291 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1294 * We cannot hold synchronization semaphores for too long
1295 * to avoid other entity starvation. However it is more efficient
1296 * to read in bursts than synchronizing access for each word.
1298 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1299 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1300 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1301 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1304 if (status != IXGBE_SUCCESS)
1313 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1314 * @hw: pointer to hardware structure
1315 * @offset: offset within the EEPROM to be written to
1316 * @words: number of word(s)
1317 * @data: 16 bit word(s) to be written to the EEPROM
1319 * If ixgbe_eeprom_update_checksum is not called after this function, the
1320 * EEPROM will most likely contain an invalid checksum.
1322 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1323 u16 words, u16 *data)
1329 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1331 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1333 /* Prepare the EEPROM for writing */
1334 status = ixgbe_acquire_eeprom(hw);
1336 if (status == IXGBE_SUCCESS) {
1337 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1338 ixgbe_release_eeprom(hw);
1339 status = IXGBE_ERR_EEPROM;
1343 if (status == IXGBE_SUCCESS) {
1344 for (i = 0; i < words; i++) {
1345 ixgbe_standby_eeprom(hw);
1347 /* Send the WRITE ENABLE command (8 bit opcode ) */
1348 ixgbe_shift_out_eeprom_bits(hw,
1349 IXGBE_EEPROM_WREN_OPCODE_SPI,
1350 IXGBE_EEPROM_OPCODE_BITS);
1352 ixgbe_standby_eeprom(hw);
1355 * Some SPI eeproms use the 8th address bit embedded
1358 if ((hw->eeprom.address_bits == 8) &&
1359 ((offset + i) >= 128))
1360 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1362 /* Send the Write command (8-bit opcode + addr) */
1363 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1364 IXGBE_EEPROM_OPCODE_BITS);
1365 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1366 hw->eeprom.address_bits);
1368 page_size = hw->eeprom.word_page_size;
1370 /* Send the data in burst via SPI*/
1373 word = (word >> 8) | (word << 8);
1374 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1379 /* do not wrap around page */
1380 if (((offset + i) & (page_size - 1)) ==
1383 } while (++i < words);
1385 ixgbe_standby_eeprom(hw);
1388 /* Done with writing - release the EEPROM */
1389 ixgbe_release_eeprom(hw);
1396 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1397 * @hw: pointer to hardware structure
1398 * @offset: offset within the EEPROM to be written to
1399 * @data: 16 bit word to be written to the EEPROM
1401 * If ixgbe_eeprom_update_checksum is not called after this function, the
1402 * EEPROM will most likely contain an invalid checksum.
1404 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1408 DEBUGFUNC("ixgbe_write_eeprom_generic");
1410 hw->eeprom.ops.init_params(hw);
1412 if (offset >= hw->eeprom.word_size) {
1413 status = IXGBE_ERR_EEPROM;
1417 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1424 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1425 * @hw: pointer to hardware structure
1426 * @offset: offset within the EEPROM to be read
1427 * @data: read 16 bit words(s) from EEPROM
1428 * @words: number of word(s)
1430 * Reads 16 bit word(s) from EEPROM through bit-bang method
1432 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1433 u16 words, u16 *data)
1435 s32 status = IXGBE_SUCCESS;
1438 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1440 hw->eeprom.ops.init_params(hw);
1443 status = IXGBE_ERR_INVALID_ARGUMENT;
1447 if (offset + words > hw->eeprom.word_size) {
1448 status = IXGBE_ERR_EEPROM;
1453 * We cannot hold synchronization semaphores for too long
1454 * to avoid other entity starvation. However it is more efficient
1455 * to read in bursts than synchronizing access for each word.
1457 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1458 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1459 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1461 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1464 if (status != IXGBE_SUCCESS)
1473 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1474 * @hw: pointer to hardware structure
1475 * @offset: offset within the EEPROM to be read
1476 * @words: number of word(s)
1477 * @data: read 16 bit word(s) from EEPROM
1479 * Reads 16 bit word(s) from EEPROM through bit-bang method
1481 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1482 u16 words, u16 *data)
1486 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1489 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1491 /* Prepare the EEPROM for reading */
1492 status = ixgbe_acquire_eeprom(hw);
1494 if (status == IXGBE_SUCCESS) {
1495 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1496 ixgbe_release_eeprom(hw);
1497 status = IXGBE_ERR_EEPROM;
1501 if (status == IXGBE_SUCCESS) {
1502 for (i = 0; i < words; i++) {
1503 ixgbe_standby_eeprom(hw);
1505 * Some SPI eeproms use the 8th address bit embedded
1508 if ((hw->eeprom.address_bits == 8) &&
1509 ((offset + i) >= 128))
1510 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1512 /* Send the READ command (opcode + addr) */
1513 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1514 IXGBE_EEPROM_OPCODE_BITS);
1515 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1516 hw->eeprom.address_bits);
1518 /* Read the data. */
1519 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1520 data[i] = (word_in >> 8) | (word_in << 8);
1523 /* End this read operation */
1524 ixgbe_release_eeprom(hw);
1531 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1532 * @hw: pointer to hardware structure
1533 * @offset: offset within the EEPROM to be read
1534 * @data: read 16 bit value from EEPROM
1536 * Reads 16 bit value from EEPROM through bit-bang method
1538 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1543 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1545 hw->eeprom.ops.init_params(hw);
1547 if (offset >= hw->eeprom.word_size) {
1548 status = IXGBE_ERR_EEPROM;
1552 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1559 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1560 * @hw: pointer to hardware structure
1561 * @offset: offset of word in the EEPROM to read
1562 * @words: number of word(s)
1563 * @data: 16 bit word(s) from the EEPROM
1565 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1567 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1568 u16 words, u16 *data)
1571 s32 status = IXGBE_SUCCESS;
1574 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1576 hw->eeprom.ops.init_params(hw);
1579 status = IXGBE_ERR_INVALID_ARGUMENT;
1580 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1584 if (offset >= hw->eeprom.word_size) {
1585 status = IXGBE_ERR_EEPROM;
1586 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1590 for (i = 0; i < words; i++) {
1591 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1592 IXGBE_EEPROM_RW_REG_START;
1594 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1595 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1597 if (status == IXGBE_SUCCESS) {
1598 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1599 IXGBE_EEPROM_RW_REG_DATA);
1601 DEBUGOUT("Eeprom read timed out\n");
1610 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1611 * @hw: pointer to hardware structure
1612 * @offset: offset within the EEPROM to be used as a scratch pad
1614 * Discover EEPROM page size by writing marching data at given offset.
1615 * This function is called only when we are writing a new large buffer
1616 * at given offset so the data would be overwritten anyway.
1618 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1621 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1622 s32 status = IXGBE_SUCCESS;
1625 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1627 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1630 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1631 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1632 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1633 hw->eeprom.word_page_size = 0;
1634 if (status != IXGBE_SUCCESS)
1637 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1638 if (status != IXGBE_SUCCESS)
1642 * When writing in burst more than the actual page size
1643 * EEPROM address wraps around current page.
1645 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1647 DEBUGOUT1("Detected EEPROM page size = %d words.",
1648 hw->eeprom.word_page_size);
1654 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1655 * @hw: pointer to hardware structure
1656 * @offset: offset of word in the EEPROM to read
1657 * @data: word read from the EEPROM
1659 * Reads a 16 bit word from the EEPROM using the EERD register.
1661 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1663 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1667 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1668 * @hw: pointer to hardware structure
1669 * @offset: offset of word in the EEPROM to write
1670 * @words: number of word(s)
1671 * @data: word(s) write to the EEPROM
1673 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1675 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1676 u16 words, u16 *data)
1679 s32 status = IXGBE_SUCCESS;
1682 DEBUGFUNC("ixgbe_write_eewr_generic");
1684 hw->eeprom.ops.init_params(hw);
1687 status = IXGBE_ERR_INVALID_ARGUMENT;
1688 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1692 if (offset >= hw->eeprom.word_size) {
1693 status = IXGBE_ERR_EEPROM;
1694 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1698 for (i = 0; i < words; i++) {
1699 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1700 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1701 IXGBE_EEPROM_RW_REG_START;
1703 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1704 if (status != IXGBE_SUCCESS) {
1705 DEBUGOUT("Eeprom write EEWR timed out\n");
1709 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1711 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1712 if (status != IXGBE_SUCCESS) {
1713 DEBUGOUT("Eeprom write EEWR timed out\n");
1723 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1724 * @hw: pointer to hardware structure
1725 * @offset: offset of word in the EEPROM to write
1726 * @data: word write to the EEPROM
1728 * Write a 16 bit word to the EEPROM using the EEWR register.
1730 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1732 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1736 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1737 * @hw: pointer to hardware structure
1738 * @ee_reg: EEPROM flag for polling
1740 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1741 * read or write is done respectively.
1743 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1747 s32 status = IXGBE_ERR_EEPROM;
1749 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1751 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1752 if (ee_reg == IXGBE_NVM_POLL_READ)
1753 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1755 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1757 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1758 status = IXGBE_SUCCESS;
1764 if (i == IXGBE_EERD_EEWR_ATTEMPTS)
1765 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1766 "EEPROM read/write done polling timed out");
1772 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1773 * @hw: pointer to hardware structure
1775 * Prepares EEPROM for access using bit-bang method. This function should
1776 * be called before issuing a command to the EEPROM.
1778 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1780 s32 status = IXGBE_SUCCESS;
1784 DEBUGFUNC("ixgbe_acquire_eeprom");
1786 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1788 status = IXGBE_ERR_SWFW_SYNC;
1790 if (status == IXGBE_SUCCESS) {
1791 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1793 /* Request EEPROM Access */
1794 eec |= IXGBE_EEC_REQ;
1795 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1797 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1798 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1799 if (eec & IXGBE_EEC_GNT)
1804 /* Release if grant not acquired */
1805 if (!(eec & IXGBE_EEC_GNT)) {
1806 eec &= ~IXGBE_EEC_REQ;
1807 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1808 DEBUGOUT("Could not acquire EEPROM grant\n");
1810 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1811 status = IXGBE_ERR_EEPROM;
1814 /* Setup EEPROM for Read/Write */
1815 if (status == IXGBE_SUCCESS) {
1816 /* Clear CS and SK */
1817 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1818 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1819 IXGBE_WRITE_FLUSH(hw);
1827 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1828 * @hw: pointer to hardware structure
1830 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1832 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1834 s32 status = IXGBE_ERR_EEPROM;
1839 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1842 /* Get SMBI software semaphore between device drivers first */
1843 for (i = 0; i < timeout; i++) {
1845 * If the SMBI bit is 0 when we read it, then the bit will be
1846 * set and we have the semaphore
1848 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1849 if (!(swsm & IXGBE_SWSM_SMBI)) {
1850 status = IXGBE_SUCCESS;
1857 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1860 * this release is particularly important because our attempts
1861 * above to get the semaphore may have succeeded, and if there
1862 * was a timeout, we should unconditionally clear the semaphore
1863 * bits to free the driver to make progress
1865 ixgbe_release_eeprom_semaphore(hw);
1870 * If the SMBI bit is 0 when we read it, then the bit will be
1871 * set and we have the semaphore
1873 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1874 if (!(swsm & IXGBE_SWSM_SMBI))
1875 status = IXGBE_SUCCESS;
1878 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1879 if (status == IXGBE_SUCCESS) {
1880 for (i = 0; i < timeout; i++) {
1881 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1883 /* Set the SW EEPROM semaphore bit to request access */
1884 swsm |= IXGBE_SWSM_SWESMBI;
1885 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
1888 * If we set the bit successfully then we got the
1891 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1892 if (swsm & IXGBE_SWSM_SWESMBI)
1899 * Release semaphores and return error if SW EEPROM semaphore
1900 * was not granted because we don't have access to the EEPROM
1903 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1904 "SWESMBI Software EEPROM semaphore not granted.\n");
1905 ixgbe_release_eeprom_semaphore(hw);
1906 status = IXGBE_ERR_EEPROM;
1909 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1910 "Software semaphore SMBI between device drivers "
1918 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1919 * @hw: pointer to hardware structure
1921 * This function clears hardware semaphore bits.
1923 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1927 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1929 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1931 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1932 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1933 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1934 IXGBE_WRITE_FLUSH(hw);
1938 * ixgbe_ready_eeprom - Polls for EEPROM ready
1939 * @hw: pointer to hardware structure
1941 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1943 s32 status = IXGBE_SUCCESS;
1947 DEBUGFUNC("ixgbe_ready_eeprom");
1950 * Read "Status Register" repeatedly until the LSB is cleared. The
1951 * EEPROM will signal that the command has been completed by clearing
1952 * bit 0 of the internal status register. If it's not cleared within
1953 * 5 milliseconds, then error out.
1955 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1956 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1957 IXGBE_EEPROM_OPCODE_BITS);
1958 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1959 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1963 ixgbe_standby_eeprom(hw);
1967 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1968 * devices (and only 0-5mSec on 5V devices)
1970 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1971 DEBUGOUT("SPI EEPROM Status error\n");
1972 status = IXGBE_ERR_EEPROM;
1979 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1980 * @hw: pointer to hardware structure
1982 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1986 DEBUGFUNC("ixgbe_standby_eeprom");
1988 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1990 /* Toggle CS to flush commands */
1991 eec |= IXGBE_EEC_CS;
1992 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1993 IXGBE_WRITE_FLUSH(hw);
1995 eec &= ~IXGBE_EEC_CS;
1996 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1997 IXGBE_WRITE_FLUSH(hw);
2002 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
2003 * @hw: pointer to hardware structure
2004 * @data: data to send to the EEPROM
2005 * @count: number of bits to shift out
2007 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
2014 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
2016 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2019 * Mask is used to shift "count" bits of "data" out to the EEPROM
2020 * one bit at a time. Determine the starting bit based on count
2022 mask = 0x01 << (count - 1);
2024 for (i = 0; i < count; i++) {
2026 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
2027 * "1", and then raising and then lowering the clock (the SK
2028 * bit controls the clock input to the EEPROM). A "0" is
2029 * shifted out to the EEPROM by setting "DI" to "0" and then
2030 * raising and then lowering the clock.
2033 eec |= IXGBE_EEC_DI;
2035 eec &= ~IXGBE_EEC_DI;
2037 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2038 IXGBE_WRITE_FLUSH(hw);
2042 ixgbe_raise_eeprom_clk(hw, &eec);
2043 ixgbe_lower_eeprom_clk(hw, &eec);
2046 * Shift mask to signify next bit of data to shift in to the
2052 /* We leave the "DI" bit set to "0" when we leave this routine. */
2053 eec &= ~IXGBE_EEC_DI;
2054 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2055 IXGBE_WRITE_FLUSH(hw);
2059 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
2060 * @hw: pointer to hardware structure
2061 * @count: number of bits to shift
2063 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
2069 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
2072 * In order to read a register from the EEPROM, we need to shift
2073 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
2074 * the clock input to the EEPROM (setting the SK bit), and then reading
2075 * the value of the "DO" bit. During this "shifting in" process the
2076 * "DI" bit should always be clear.
2078 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2080 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
2082 for (i = 0; i < count; i++) {
2084 ixgbe_raise_eeprom_clk(hw, &eec);
2086 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2088 eec &= ~(IXGBE_EEC_DI);
2089 if (eec & IXGBE_EEC_DO)
2092 ixgbe_lower_eeprom_clk(hw, &eec);
2099 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
2100 * @hw: pointer to hardware structure
2101 * @eec: EEC register's current value
2103 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2105 DEBUGFUNC("ixgbe_raise_eeprom_clk");
2108 * Raise the clock input to the EEPROM
2109 * (setting the SK bit), then delay
2111 *eec = *eec | IXGBE_EEC_SK;
2112 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2113 IXGBE_WRITE_FLUSH(hw);
2118 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2119 * @hw: pointer to hardware structure
2120 * @eec: EEC's current value
2122 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2124 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2127 * Lower the clock input to the EEPROM (clearing the SK bit), then
2130 *eec = *eec & ~IXGBE_EEC_SK;
2131 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2132 IXGBE_WRITE_FLUSH(hw);
2137 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2138 * @hw: pointer to hardware structure
2140 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2144 DEBUGFUNC("ixgbe_release_eeprom");
2146 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2148 eec |= IXGBE_EEC_CS; /* Pull CS high */
2149 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
2151 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2152 IXGBE_WRITE_FLUSH(hw);
2156 /* Stop requesting EEPROM access */
2157 eec &= ~IXGBE_EEC_REQ;
2158 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2160 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2162 /* Delay before attempt to obtain semaphore again to allow FW access */
2163 msec_delay(hw->eeprom.semaphore_delay);
2167 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2168 * @hw: pointer to hardware structure
2170 * Returns a negative error code on error, or the 16-bit checksum
2172 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2181 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
2183 /* Include 0x0-0x3F in the checksum */
2184 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
2185 if (hw->eeprom.ops.read(hw, i, &word)) {
2186 DEBUGOUT("EEPROM read failed\n");
2187 return IXGBE_ERR_EEPROM;
2192 /* Include all data from pointers except for the fw pointer */
2193 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
2194 if (hw->eeprom.ops.read(hw, i, &pointer)) {
2195 DEBUGOUT("EEPROM read failed\n");
2196 return IXGBE_ERR_EEPROM;
2199 /* If the pointer seems invalid */
2200 if (pointer == 0xFFFF || pointer == 0)
2203 if (hw->eeprom.ops.read(hw, pointer, &length)) {
2204 DEBUGOUT("EEPROM read failed\n");
2205 return IXGBE_ERR_EEPROM;
2208 if (length == 0xFFFF || length == 0)
2211 for (j = pointer + 1; j <= pointer + length; j++) {
2212 if (hw->eeprom.ops.read(hw, j, &word)) {
2213 DEBUGOUT("EEPROM read failed\n");
2214 return IXGBE_ERR_EEPROM;
2220 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2222 return (s32)checksum;
2226 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2227 * @hw: pointer to hardware structure
2228 * @checksum_val: calculated checksum
2230 * Performs checksum calculation and validates the EEPROM checksum. If the
2231 * caller does not need checksum_val, the value can be NULL.
2233 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2238 u16 read_checksum = 0;
2240 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
2242 /* Read the first word from the EEPROM. If this times out or fails, do
2243 * not continue or we could be in for a very long wait while every
2246 status = hw->eeprom.ops.read(hw, 0, &checksum);
2248 DEBUGOUT("EEPROM read failed\n");
2252 status = hw->eeprom.ops.calc_checksum(hw);
2256 checksum = (u16)(status & 0xffff);
2258 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2260 DEBUGOUT("EEPROM read failed\n");
2264 /* Verify read checksum from EEPROM is the same as
2265 * calculated checksum
2267 if (read_checksum != checksum)
2268 status = IXGBE_ERR_EEPROM_CHECKSUM;
2270 /* If the user cares, return the calculated checksum */
2272 *checksum_val = checksum;
2278 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2279 * @hw: pointer to hardware structure
2281 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2286 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
2288 /* Read the first word from the EEPROM. If this times out or fails, do
2289 * not continue or we could be in for a very long wait while every
2292 status = hw->eeprom.ops.read(hw, 0, &checksum);
2294 DEBUGOUT("EEPROM read failed\n");
2298 status = hw->eeprom.ops.calc_checksum(hw);
2302 checksum = (u16)(status & 0xffff);
2304 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
2310 * ixgbe_validate_mac_addr - Validate MAC address
2311 * @mac_addr: pointer to MAC address.
2313 * Tests a MAC address to ensure it is a valid Individual Address.
2315 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
2317 s32 status = IXGBE_SUCCESS;
2319 DEBUGFUNC("ixgbe_validate_mac_addr");
2321 /* Make sure it is not a multicast address */
2322 if (IXGBE_IS_MULTICAST(mac_addr)) {
2323 status = IXGBE_ERR_INVALID_MAC_ADDR;
2324 /* Not a broadcast address */
2325 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
2326 status = IXGBE_ERR_INVALID_MAC_ADDR;
2327 /* Reject the zero address */
2328 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
2329 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
2330 status = IXGBE_ERR_INVALID_MAC_ADDR;
2336 * ixgbe_set_rar_generic - Set Rx address register
2337 * @hw: pointer to hardware structure
2338 * @index: Receive address register to write
2339 * @addr: Address to put into receive address register
2340 * @vmdq: VMDq "set" or "pool" index
2341 * @enable_addr: set flag that address is active
2343 * Puts an ethernet address into a receive address register.
2345 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2348 u32 rar_low, rar_high;
2349 u32 rar_entries = hw->mac.num_rar_entries;
2351 DEBUGFUNC("ixgbe_set_rar_generic");
2353 /* Make sure we are using a valid rar index range */
2354 if (index >= rar_entries) {
2355 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2356 "RAR index %d is out of range.\n", index);
2357 return IXGBE_ERR_INVALID_ARGUMENT;
2360 /* setup VMDq pool selection before this RAR gets enabled */
2361 hw->mac.ops.set_vmdq(hw, index, vmdq);
2364 * HW expects these in little endian so we reverse the byte
2365 * order from network order (big endian) to little endian
2367 rar_low = ((u32)addr[0] |
2368 ((u32)addr[1] << 8) |
2369 ((u32)addr[2] << 16) |
2370 ((u32)addr[3] << 24));
2372 * Some parts put the VMDq setting in the extra RAH bits,
2373 * so save everything except the lower 16 bits that hold part
2374 * of the address and the address valid bit.
2376 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2377 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2378 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2380 if (enable_addr != 0)
2381 rar_high |= IXGBE_RAH_AV;
2383 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2384 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2386 return IXGBE_SUCCESS;
2390 * ixgbe_clear_rar_generic - Remove Rx address register
2391 * @hw: pointer to hardware structure
2392 * @index: Receive address register to write
2394 * Clears an ethernet address from a receive address register.
2396 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2399 u32 rar_entries = hw->mac.num_rar_entries;
2401 DEBUGFUNC("ixgbe_clear_rar_generic");
2403 /* Make sure we are using a valid rar index range */
2404 if (index >= rar_entries) {
2405 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2406 "RAR index %d is out of range.\n", index);
2407 return IXGBE_ERR_INVALID_ARGUMENT;
2411 * Some parts put the VMDq setting in the extra RAH bits,
2412 * so save everything except the lower 16 bits that hold part
2413 * of the address and the address valid bit.
2415 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2416 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2418 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2419 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2421 /* clear VMDq pool/queue selection for this RAR */
2422 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2424 return IXGBE_SUCCESS;
2428 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2429 * @hw: pointer to hardware structure
2431 * Places the MAC address in receive address register 0 and clears the rest
2432 * of the receive address registers. Clears the multicast table. Assumes
2433 * the receiver is in reset when the routine is called.
2435 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2438 u32 rar_entries = hw->mac.num_rar_entries;
2440 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2443 * If the current mac address is valid, assume it is a software override
2444 * to the permanent address.
2445 * Otherwise, use the permanent address from the eeprom.
2447 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2448 IXGBE_ERR_INVALID_MAC_ADDR) {
2449 /* Get the MAC address from the RAR0 for later reference */
2450 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2452 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2453 hw->mac.addr[0], hw->mac.addr[1],
2455 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2456 hw->mac.addr[4], hw->mac.addr[5]);
2458 /* Setup the receive address. */
2459 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2460 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2461 hw->mac.addr[0], hw->mac.addr[1],
2463 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2464 hw->mac.addr[4], hw->mac.addr[5]);
2466 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2469 /* clear VMDq pool/queue selection for RAR 0 */
2470 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2472 hw->addr_ctrl.overflow_promisc = 0;
2474 hw->addr_ctrl.rar_used_count = 1;
2476 /* Zero out the other receive addresses. */
2477 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2478 for (i = 1; i < rar_entries; i++) {
2479 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2480 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2484 hw->addr_ctrl.mta_in_use = 0;
2485 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2487 DEBUGOUT(" Clearing MTA\n");
2488 for (i = 0; i < hw->mac.mcft_size; i++)
2489 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2491 ixgbe_init_uta_tables(hw);
2493 return IXGBE_SUCCESS;
2497 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2498 * @hw: pointer to hardware structure
2499 * @addr: new address
2500 * @vmdq: VMDq "set" or "pool" index
2502 * Adds it to unused receive address register or goes into promiscuous mode.
2504 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2506 u32 rar_entries = hw->mac.num_rar_entries;
2509 DEBUGFUNC("ixgbe_add_uc_addr");
2511 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2512 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2515 * Place this address in the RAR if there is room,
2516 * else put the controller into promiscuous mode
2518 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2519 rar = hw->addr_ctrl.rar_used_count;
2520 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2521 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2522 hw->addr_ctrl.rar_used_count++;
2524 hw->addr_ctrl.overflow_promisc++;
2527 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2531 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2532 * @hw: pointer to hardware structure
2533 * @addr_list: the list of new addresses
2534 * @addr_count: number of addresses
2535 * @next: iterator function to walk the address list
2537 * The given list replaces any existing list. Clears the secondary addrs from
2538 * receive address registers. Uses unused receive address registers for the
2539 * first secondary addresses, and falls back to promiscuous mode as needed.
2541 * Drivers using secondary unicast addresses must set user_set_promisc when
2542 * manually putting the device into promiscuous mode.
2544 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2545 u32 addr_count, ixgbe_mc_addr_itr next)
2549 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2554 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2557 * Clear accounting of old secondary address list,
2558 * don't count RAR[0]
2560 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2561 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2562 hw->addr_ctrl.overflow_promisc = 0;
2564 /* Zero out the other receive addresses */
2565 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2566 for (i = 0; i < uc_addr_in_use; i++) {
2567 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2568 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2571 /* Add the new addresses */
2572 for (i = 0; i < addr_count; i++) {
2573 DEBUGOUT(" Adding the secondary addresses:\n");
2574 addr = next(hw, &addr_list, &vmdq);
2575 ixgbe_add_uc_addr(hw, addr, vmdq);
2578 if (hw->addr_ctrl.overflow_promisc) {
2579 /* enable promisc if not already in overflow or set by user */
2580 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2581 DEBUGOUT(" Entering address overflow promisc mode\n");
2582 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2583 fctrl |= IXGBE_FCTRL_UPE;
2584 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2587 /* only disable if set by overflow, not by user */
2588 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2589 DEBUGOUT(" Leaving address overflow promisc mode\n");
2590 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2591 fctrl &= ~IXGBE_FCTRL_UPE;
2592 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2596 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2597 return IXGBE_SUCCESS;
2601 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2602 * @hw: pointer to hardware structure
2603 * @mc_addr: the multicast address
2605 * Extracts the 12 bits, from a multicast address, to determine which
2606 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2607 * incoming rx multicast addresses, to determine the bit-vector to check in
2608 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2609 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2610 * to mc_filter_type.
2612 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2616 DEBUGFUNC("ixgbe_mta_vector");
2618 switch (hw->mac.mc_filter_type) {
2619 case 0: /* use bits [47:36] of the address */
2620 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2622 case 1: /* use bits [46:35] of the address */
2623 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2625 case 2: /* use bits [45:34] of the address */
2626 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2628 case 3: /* use bits [43:32] of the address */
2629 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2631 default: /* Invalid mc_filter_type */
2632 DEBUGOUT("MC filter type param set incorrectly\n");
2637 /* vector can only be 12-bits or boundary will be exceeded */
2643 * ixgbe_set_mta - Set bit-vector in multicast table
2644 * @hw: pointer to hardware structure
2645 * @mc_addr: Multicast address
2647 * Sets the bit-vector in the multicast table.
2649 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2655 DEBUGFUNC("ixgbe_set_mta");
2657 hw->addr_ctrl.mta_in_use++;
2659 vector = ixgbe_mta_vector(hw, mc_addr);
2660 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2663 * The MTA is a register array of 128 32-bit registers. It is treated
2664 * like an array of 4096 bits. We want to set bit
2665 * BitArray[vector_value]. So we figure out what register the bit is
2666 * in, read it, OR in the new bit, then write back the new value. The
2667 * register is determined by the upper 7 bits of the vector value and
2668 * the bit within that register are determined by the lower 5 bits of
2671 vector_reg = (vector >> 5) & 0x7F;
2672 vector_bit = vector & 0x1F;
2673 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2677 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2678 * @hw: pointer to hardware structure
2679 * @mc_addr_list: the list of new multicast addresses
2680 * @mc_addr_count: number of addresses
2681 * @next: iterator function to walk the multicast address list
2682 * @clear: flag, when set clears the table beforehand
2684 * When the clear flag is set, the given list replaces any existing list.
2685 * Hashes the given addresses into the multicast table.
2687 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2688 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2694 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2697 * Set the new number of MC addresses that we are being requested to
2700 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2701 hw->addr_ctrl.mta_in_use = 0;
2703 /* Clear mta_shadow */
2705 DEBUGOUT(" Clearing MTA\n");
2706 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2709 /* Update mta_shadow */
2710 for (i = 0; i < mc_addr_count; i++) {
2711 DEBUGOUT(" Adding the multicast addresses:\n");
2712 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2716 for (i = 0; i < hw->mac.mcft_size; i++)
2717 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2718 hw->mac.mta_shadow[i]);
2720 if (hw->addr_ctrl.mta_in_use > 0)
2721 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2722 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2724 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2725 return IXGBE_SUCCESS;
2729 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2730 * @hw: pointer to hardware structure
2732 * Enables multicast address in RAR and the use of the multicast hash table.
2734 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2736 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2738 DEBUGFUNC("ixgbe_enable_mc_generic");
2740 if (a->mta_in_use > 0)
2741 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2742 hw->mac.mc_filter_type);
2744 return IXGBE_SUCCESS;
2748 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2749 * @hw: pointer to hardware structure
2751 * Disables multicast address in RAR and the use of the multicast hash table.
2753 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2755 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2757 DEBUGFUNC("ixgbe_disable_mc_generic");
2759 if (a->mta_in_use > 0)
2760 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2762 return IXGBE_SUCCESS;
2766 * ixgbe_fc_enable_generic - Enable flow control
2767 * @hw: pointer to hardware structure
2769 * Enable flow control according to the current settings.
2771 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2773 s32 ret_val = IXGBE_SUCCESS;
2774 u32 mflcn_reg, fccfg_reg;
2779 DEBUGFUNC("ixgbe_fc_enable_generic");
2781 /* Validate the water mark configuration */
2782 if (!hw->fc.pause_time) {
2783 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2787 /* Low water mark of zero causes XOFF floods */
2788 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2789 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2790 hw->fc.high_water[i]) {
2791 if (!hw->fc.low_water[i] ||
2792 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2793 DEBUGOUT("Invalid water mark configuration\n");
2794 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2800 /* Negotiate the fc mode to use */
2801 hw->mac.ops.fc_autoneg(hw);
2803 /* Disable any previous flow control settings */
2804 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2805 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2807 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2808 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2811 * The possible values of fc.current_mode are:
2812 * 0: Flow control is completely disabled
2813 * 1: Rx flow control is enabled (we can receive pause frames,
2814 * but not send pause frames).
2815 * 2: Tx flow control is enabled (we can send pause frames but
2816 * we do not support receiving pause frames).
2817 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2820 switch (hw->fc.current_mode) {
2823 * Flow control is disabled by software override or autoneg.
2824 * The code below will actually disable it in the HW.
2827 case ixgbe_fc_rx_pause:
2829 * Rx Flow control is enabled and Tx Flow control is
2830 * disabled by software override. Since there really
2831 * isn't a way to advertise that we are capable of RX
2832 * Pause ONLY, we will advertise that we support both
2833 * symmetric and asymmetric Rx PAUSE. Later, we will
2834 * disable the adapter's ability to send PAUSE frames.
2836 mflcn_reg |= IXGBE_MFLCN_RFCE;
2838 case ixgbe_fc_tx_pause:
2840 * Tx Flow control is enabled, and Rx Flow control is
2841 * disabled by software override.
2843 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2846 /* Flow control (both Rx and Tx) is enabled by SW override. */
2847 mflcn_reg |= IXGBE_MFLCN_RFCE;
2848 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2851 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2852 "Flow control param set incorrectly\n");
2853 ret_val = IXGBE_ERR_CONFIG;
2858 /* Set 802.3x based flow control settings. */
2859 mflcn_reg |= IXGBE_MFLCN_DPF;
2860 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2861 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2864 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2865 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2866 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2867 hw->fc.high_water[i]) {
2868 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2869 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2870 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2872 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2874 * In order to prevent Tx hangs when the internal Tx
2875 * switch is enabled we must set the high water mark
2876 * to the Rx packet buffer size - 24KB. This allows
2877 * the Tx switch to function even under heavy Rx
2880 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2883 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2886 /* Configure pause time (2 TCs per register) */
2887 reg = hw->fc.pause_time * 0x00010001;
2888 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2889 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2891 /* Configure flow control refresh threshold value */
2892 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2899 * ixgbe_negotiate_fc - Negotiate flow control
2900 * @hw: pointer to hardware structure
2901 * @adv_reg: flow control advertised settings
2902 * @lp_reg: link partner's flow control settings
2903 * @adv_sym: symmetric pause bit in advertisement
2904 * @adv_asm: asymmetric pause bit in advertisement
2905 * @lp_sym: symmetric pause bit in link partner advertisement
2906 * @lp_asm: asymmetric pause bit in link partner advertisement
2908 * Find the intersection between advertised settings and link partner's
2909 * advertised settings
2911 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2912 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2914 if ((!(adv_reg)) || (!(lp_reg))) {
2915 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
2916 "Local or link partner's advertised flow control "
2917 "settings are NULL. Local: %x, link partner: %x\n",
2919 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2922 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2924 * Now we need to check if the user selected Rx ONLY
2925 * of pause frames. In this case, we had to advertise
2926 * FULL flow control because we could not advertise RX
2927 * ONLY. Hence, we must now check to see if we need to
2928 * turn OFF the TRANSMISSION of PAUSE frames.
2930 if (hw->fc.requested_mode == ixgbe_fc_full) {
2931 hw->fc.current_mode = ixgbe_fc_full;
2932 DEBUGOUT("Flow Control = FULL.\n");
2934 hw->fc.current_mode = ixgbe_fc_rx_pause;
2935 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2937 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2938 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2939 hw->fc.current_mode = ixgbe_fc_tx_pause;
2940 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2941 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2942 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2943 hw->fc.current_mode = ixgbe_fc_rx_pause;
2944 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2946 hw->fc.current_mode = ixgbe_fc_none;
2947 DEBUGOUT("Flow Control = NONE.\n");
2949 return IXGBE_SUCCESS;
2953 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2954 * @hw: pointer to hardware structure
2956 * Enable flow control according on 1 gig fiber.
2958 STATIC s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2960 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2961 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2964 * On multispeed fiber at 1g, bail out if
2965 * - link is up but AN did not complete, or if
2966 * - link is up and AN completed but timed out
2969 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2970 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2971 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
2972 DEBUGOUT("Auto-Negotiation did not complete or timed out\n");
2976 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2977 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2979 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2980 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2981 IXGBE_PCS1GANA_ASM_PAUSE,
2982 IXGBE_PCS1GANA_SYM_PAUSE,
2983 IXGBE_PCS1GANA_ASM_PAUSE);
2990 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2991 * @hw: pointer to hardware structure
2993 * Enable flow control according to IEEE clause 37.
2995 STATIC s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2997 u32 links2, anlp1_reg, autoc_reg, links;
2998 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3001 * On backplane, bail out if
3002 * - backplane autoneg was not completed, or if
3003 * - we are 82599 and link partner is not AN enabled
3005 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
3006 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
3007 DEBUGOUT("Auto-Negotiation did not complete\n");
3011 if (hw->mac.type == ixgbe_mac_82599EB) {
3012 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
3013 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
3014 DEBUGOUT("Link partner is not AN enabled\n");
3019 * Read the 10g AN autoc and LP ability registers and resolve
3020 * local flow control settings accordingly
3022 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3023 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
3025 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
3026 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
3027 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
3034 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
3035 * @hw: pointer to hardware structure
3037 * Enable flow control according to IEEE clause 37.
3039 STATIC s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
3041 u16 technology_ability_reg = 0;
3042 u16 lp_technology_ability_reg = 0;
3044 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
3045 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3046 &technology_ability_reg);
3047 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
3048 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3049 &lp_technology_ability_reg);
3051 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
3052 (u32)lp_technology_ability_reg,
3053 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
3054 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
3058 * ixgbe_fc_autoneg - Configure flow control
3059 * @hw: pointer to hardware structure
3061 * Compares our advertised flow control capabilities to those advertised by
3062 * our link partner, and determines the proper flow control mode to use.
3064 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
3066 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3067 ixgbe_link_speed speed;
3070 DEBUGFUNC("ixgbe_fc_autoneg");
3073 * AN should have completed when the cable was plugged in.
3074 * Look for reasons to bail out. Bail out if:
3075 * - FC autoneg is disabled, or if
3078 if (hw->fc.disable_fc_autoneg) {
3079 /* TODO: This should be just an informative log */
3080 ERROR_REPORT1(IXGBE_ERROR_CAUTION,
3081 "Flow control autoneg is disabled");
3085 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3087 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3091 switch (hw->phy.media_type) {
3092 /* Autoneg flow control on fiber adapters */
3093 case ixgbe_media_type_fiber_qsfp:
3094 case ixgbe_media_type_fiber:
3095 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
3096 ret_val = ixgbe_fc_autoneg_fiber(hw);
3099 /* Autoneg flow control on backplane adapters */
3100 case ixgbe_media_type_backplane:
3101 ret_val = ixgbe_fc_autoneg_backplane(hw);
3104 /* Autoneg flow control on copper adapters */
3105 case ixgbe_media_type_copper:
3106 if (ixgbe_device_supports_autoneg_fc(hw))
3107 ret_val = ixgbe_fc_autoneg_copper(hw);
3115 if (ret_val == IXGBE_SUCCESS) {
3116 hw->fc.fc_was_autonegged = true;
3118 hw->fc.fc_was_autonegged = false;
3119 hw->fc.current_mode = hw->fc.requested_mode;
3124 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3125 * @hw: pointer to hardware structure
3127 * System-wide timeout range is encoded in PCIe Device Control2 register.
3129 * Add 10% to specified maximum and return the number of times to poll for
3130 * completion timeout, in units of 100 microsec. Never return less than
3131 * 800 = 80 millisec.
3133 STATIC u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3138 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3139 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
3142 case IXGBE_PCIDEVCTRL2_65_130ms:
3143 pollcnt = 1300; /* 130 millisec */
3145 case IXGBE_PCIDEVCTRL2_260_520ms:
3146 pollcnt = 5200; /* 520 millisec */
3148 case IXGBE_PCIDEVCTRL2_1_2s:
3149 pollcnt = 20000; /* 2 sec */
3151 case IXGBE_PCIDEVCTRL2_4_8s:
3152 pollcnt = 80000; /* 8 sec */
3154 case IXGBE_PCIDEVCTRL2_17_34s:
3155 pollcnt = 34000; /* 34 sec */
3157 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
3158 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
3159 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
3160 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
3162 pollcnt = 800; /* 80 millisec minimum */
3166 /* add 10% to spec maximum */
3167 return (pollcnt * 11) / 10;
3171 * ixgbe_disable_pcie_master - Disable PCI-express master access
3172 * @hw: pointer to hardware structure
3174 * Disables PCI-Express master access and verifies there are no pending
3175 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
3176 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
3177 * is returned signifying master requests disabled.
3179 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
3181 s32 status = IXGBE_SUCCESS;
3185 DEBUGFUNC("ixgbe_disable_pcie_master");
3187 /* Always set this bit to ensure any future transactions are blocked */
3188 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3190 /* Exit if master requests are blocked */
3191 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3192 IXGBE_REMOVED(hw->hw_addr))
3195 /* Poll for master request bit to clear */
3196 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
3198 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3203 * Two consecutive resets are required via CTRL.RST per datasheet
3204 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
3205 * of this need. The first reset prevents new master requests from
3206 * being issued by our device. We then must wait 1usec or more for any
3207 * remaining completions from the PCIe bus to trickle in, and then reset
3208 * again to clear out any effects they may have had on our device.
3210 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
3211 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3213 if (hw->mac.type >= ixgbe_mac_X550)
3217 * Before proceeding, make sure that the PCIe block does not have
3218 * transactions pending.
3220 poll = ixgbe_pcie_timeout_poll(hw);
3221 for (i = 0; i < poll; i++) {
3223 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3224 if (IXGBE_REMOVED(hw->hw_addr))
3226 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3230 ERROR_REPORT1(IXGBE_ERROR_POLLING,
3231 "PCIe transaction pending bit also did not clear.\n");
3232 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
3239 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3240 * @hw: pointer to hardware structure
3241 * @mask: Mask to specify which semaphore to acquire
3243 * Acquires the SWFW semaphore through the GSSR register for the specified
3244 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3246 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3250 u32 fwmask = mask << 5;
3254 DEBUGFUNC("ixgbe_acquire_swfw_sync");
3256 for (i = 0; i < timeout; i++) {
3258 * SW NVM semaphore bit is used for access to all
3259 * SW_FW_SYNC bits (not just NVM)
3261 if (ixgbe_get_eeprom_semaphore(hw))
3262 return IXGBE_ERR_SWFW_SYNC;
3264 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3265 if (!(gssr & (fwmask | swmask))) {
3267 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3268 ixgbe_release_eeprom_semaphore(hw);
3269 return IXGBE_SUCCESS;
3271 /* Resource is currently in use by FW or SW */
3272 ixgbe_release_eeprom_semaphore(hw);
3277 /* If time expired clear the bits holding the lock and retry */
3278 if (gssr & (fwmask | swmask))
3279 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
3282 return IXGBE_ERR_SWFW_SYNC;
3286 * ixgbe_release_swfw_sync - Release SWFW semaphore
3287 * @hw: pointer to hardware structure
3288 * @mask: Mask to specify which semaphore to release
3290 * Releases the SWFW semaphore through the GSSR register for the specified
3291 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3293 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3298 DEBUGFUNC("ixgbe_release_swfw_sync");
3300 ixgbe_get_eeprom_semaphore(hw);
3302 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3304 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3306 ixgbe_release_eeprom_semaphore(hw);
3310 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3311 * @hw: pointer to hardware structure
3313 * Stops the receive data path and waits for the HW to internally empty
3314 * the Rx security block
3316 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3318 #define IXGBE_MAX_SECRX_POLL 4000
3323 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
3326 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3327 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
3328 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3329 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
3330 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3331 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
3334 /* Use interrupt-safe sleep just in case */
3338 /* For informational purposes only */
3339 if (i >= IXGBE_MAX_SECRX_POLL)
3340 DEBUGOUT("Rx unit being enabled before security "
3341 "path fully disabled. Continuing with init.\n");
3343 return IXGBE_SUCCESS;
3347 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3348 * @hw: pointer to hardware structure
3349 * @locked: bool to indicate whether the SW/FW lock was taken
3350 * @reg_val: Value we read from AUTOC
3352 * The default case requires no protection so just to the register read.
3354 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3357 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3358 return IXGBE_SUCCESS;
3362 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
3363 * @hw: pointer to hardware structure
3364 * @reg_val: value to write to AUTOC
3365 * @locked: bool to indicate whether the SW/FW lock was already taken by
3368 * The default case requires no protection so just to the register write.
3370 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
3372 UNREFERENCED_1PARAMETER(locked);
3374 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
3375 return IXGBE_SUCCESS;
3379 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3380 * @hw: pointer to hardware structure
3382 * Enables the receive data path.
3384 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3388 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
3390 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3391 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
3392 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3393 IXGBE_WRITE_FLUSH(hw);
3395 return IXGBE_SUCCESS;
3399 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3400 * @hw: pointer to hardware structure
3401 * @regval: register value to write to RXCTRL
3403 * Enables the Rx DMA unit
3405 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3407 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
3409 if (regval & IXGBE_RXCTRL_RXEN)
3410 ixgbe_enable_rx(hw);
3412 ixgbe_disable_rx(hw);
3414 return IXGBE_SUCCESS;
3418 * ixgbe_blink_led_start_generic - Blink LED based on index.
3419 * @hw: pointer to hardware structure
3420 * @index: led number to blink
3422 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3424 ixgbe_link_speed speed = 0;
3427 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3428 s32 ret_val = IXGBE_SUCCESS;
3429 bool locked = false;
3431 DEBUGFUNC("ixgbe_blink_led_start_generic");
3434 return IXGBE_ERR_PARAM;
3437 * Link must be up to auto-blink the LEDs;
3438 * Force it if link is down.
3440 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3443 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3444 if (ret_val != IXGBE_SUCCESS)
3447 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3448 autoc_reg |= IXGBE_AUTOC_FLU;
3450 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3451 if (ret_val != IXGBE_SUCCESS)
3454 IXGBE_WRITE_FLUSH(hw);
3458 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3459 led_reg |= IXGBE_LED_BLINK(index);
3460 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3461 IXGBE_WRITE_FLUSH(hw);
3468 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3469 * @hw: pointer to hardware structure
3470 * @index: led number to stop blinking
3472 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3475 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3476 s32 ret_val = IXGBE_SUCCESS;
3477 bool locked = false;
3479 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3482 return IXGBE_ERR_PARAM;
3485 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3486 if (ret_val != IXGBE_SUCCESS)
3489 autoc_reg &= ~IXGBE_AUTOC_FLU;
3490 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3492 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3493 if (ret_val != IXGBE_SUCCESS)
3496 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3497 led_reg &= ~IXGBE_LED_BLINK(index);
3498 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3499 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3500 IXGBE_WRITE_FLUSH(hw);
3507 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3508 * @hw: pointer to hardware structure
3509 * @san_mac_offset: SAN MAC address offset
3511 * This function will read the EEPROM location for the SAN MAC address
3512 * pointer, and returns the value at that location. This is used in both
3513 * get and set mac_addr routines.
3515 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3516 u16 *san_mac_offset)
3520 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3523 * First read the EEPROM pointer to see if the MAC addresses are
3526 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3529 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3530 "eeprom at offset %d failed",
3531 IXGBE_SAN_MAC_ADDR_PTR);
3538 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3539 * @hw: pointer to hardware structure
3540 * @san_mac_addr: SAN MAC address
3542 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3543 * per-port, so set_lan_id() must be called before reading the addresses.
3544 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3545 * upon for non-SFP connections, so we must call it here.
3547 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3549 u16 san_mac_data, san_mac_offset;
3553 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3556 * First read the EEPROM pointer to see if the MAC addresses are
3557 * available. If they're not, no point in calling set_lan_id() here.
3559 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3560 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3561 goto san_mac_addr_out;
3563 /* make sure we know which port we need to program */
3564 hw->mac.ops.set_lan_id(hw);
3565 /* apply the port offset to the address offset */
3566 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3567 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3568 for (i = 0; i < 3; i++) {
3569 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3572 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3573 "eeprom read at offset %d failed",
3575 goto san_mac_addr_out;
3577 san_mac_addr[i * 2] = (u8)(san_mac_data);
3578 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3581 return IXGBE_SUCCESS;
3585 * No addresses available in this EEPROM. It's not an
3586 * error though, so just wipe the local address and return.
3588 for (i = 0; i < 6; i++)
3589 san_mac_addr[i] = 0xFF;
3590 return IXGBE_SUCCESS;
3594 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3595 * @hw: pointer to hardware structure
3596 * @san_mac_addr: SAN MAC address
3598 * Write a SAN MAC address to the EEPROM.
3600 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3603 u16 san_mac_data, san_mac_offset;
3606 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3608 /* Look for SAN mac address pointer. If not defined, return */
3609 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3610 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3611 return IXGBE_ERR_NO_SAN_ADDR_PTR;
3613 /* Make sure we know which port we need to write */
3614 hw->mac.ops.set_lan_id(hw);
3615 /* Apply the port offset to the address offset */
3616 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3617 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3619 for (i = 0; i < 3; i++) {
3620 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3621 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3622 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3626 return IXGBE_SUCCESS;
3630 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3631 * @hw: pointer to hardware structure
3633 * Read PCIe configuration space, and get the MSI-X vector count from
3634 * the capabilities table.
3636 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3642 switch (hw->mac.type) {
3643 case ixgbe_mac_82598EB:
3644 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3645 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3647 case ixgbe_mac_82599EB:
3648 case ixgbe_mac_X540:
3649 case ixgbe_mac_X550:
3650 case ixgbe_mac_X550EM_x:
3651 case ixgbe_mac_X550EM_a:
3652 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3653 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3659 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3660 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3661 if (IXGBE_REMOVED(hw->hw_addr))
3663 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3665 /* MSI-X count is zero-based in HW */
3668 if (msix_count > max_msix_count)
3669 msix_count = max_msix_count;
3675 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3676 * @hw: pointer to hardware structure
3677 * @addr: Address to put into receive address register
3678 * @vmdq: VMDq pool to assign
3680 * Puts an ethernet address into a receive address register, or
3681 * finds the rar that it is already in; adds to the pool list
3683 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3685 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3686 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3688 u32 rar_low, rar_high;
3689 u32 addr_low, addr_high;
3691 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3693 /* swap bytes for HW little endian */
3694 addr_low = addr[0] | (addr[1] << 8)
3697 addr_high = addr[4] | (addr[5] << 8);
3700 * Either find the mac_id in rar or find the first empty space.
3701 * rar_highwater points to just after the highest currently used
3702 * rar in order to shorten the search. It grows when we add a new
3705 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3706 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3708 if (((IXGBE_RAH_AV & rar_high) == 0)
3709 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3710 first_empty_rar = rar;
3711 } else if ((rar_high & 0xFFFF) == addr_high) {
3712 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3713 if (rar_low == addr_low)
3714 break; /* found it already in the rars */
3718 if (rar < hw->mac.rar_highwater) {
3719 /* already there so just add to the pool bits */
3720 ixgbe_set_vmdq(hw, rar, vmdq);
3721 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3722 /* stick it into first empty RAR slot we found */
3723 rar = first_empty_rar;
3724 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3725 } else if (rar == hw->mac.rar_highwater) {
3726 /* add it to the top of the list and inc the highwater mark */
3727 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3728 hw->mac.rar_highwater++;
3729 } else if (rar >= hw->mac.num_rar_entries) {
3730 return IXGBE_ERR_INVALID_MAC_ADDR;
3734 * If we found rar[0], make sure the default pool bit (we use pool 0)
3735 * remains cleared to be sure default pool packets will get delivered
3738 ixgbe_clear_vmdq(hw, rar, 0);
3744 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3745 * @hw: pointer to hardware struct
3746 * @rar: receive address register index to disassociate
3747 * @vmdq: VMDq pool index to remove from the rar
3749 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3751 u32 mpsar_lo, mpsar_hi;
3752 u32 rar_entries = hw->mac.num_rar_entries;
3754 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3756 /* Make sure we are using a valid rar index range */
3757 if (rar >= rar_entries) {
3758 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3759 "RAR index %d is out of range.\n", rar);
3760 return IXGBE_ERR_INVALID_ARGUMENT;
3763 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3764 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3766 if (IXGBE_REMOVED(hw->hw_addr))
3769 if (!mpsar_lo && !mpsar_hi)
3772 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3774 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3775 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3778 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3779 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3781 } else if (vmdq < 32) {
3782 mpsar_lo &= ~(1 << vmdq);
3783 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3785 mpsar_hi &= ~(1 << (vmdq - 32));
3786 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3789 /* was that the last pool using this rar? */
3790 if (mpsar_lo == 0 && mpsar_hi == 0 &&
3791 rar != 0 && rar != hw->mac.san_mac_rar_index)
3792 hw->mac.ops.clear_rar(hw, rar);
3794 return IXGBE_SUCCESS;
3798 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3799 * @hw: pointer to hardware struct
3800 * @rar: receive address register index to associate with a VMDq index
3801 * @vmdq: VMDq pool index
3803 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3806 u32 rar_entries = hw->mac.num_rar_entries;
3808 DEBUGFUNC("ixgbe_set_vmdq_generic");
3810 /* Make sure we are using a valid rar index range */
3811 if (rar >= rar_entries) {
3812 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3813 "RAR index %d is out of range.\n", rar);
3814 return IXGBE_ERR_INVALID_ARGUMENT;
3818 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3820 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3822 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3823 mpsar |= 1 << (vmdq - 32);
3824 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3826 return IXGBE_SUCCESS;
3830 * This function should only be involved in the IOV mode.
3831 * In IOV mode, Default pool is next pool after the number of
3832 * VFs advertized and not 0.
3833 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3835 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3836 * @hw: pointer to hardware struct
3837 * @vmdq: VMDq pool index
3839 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3841 u32 rar = hw->mac.san_mac_rar_index;
3843 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3846 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3847 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3849 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3850 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3853 return IXGBE_SUCCESS;
3857 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3858 * @hw: pointer to hardware structure
3860 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3864 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3865 DEBUGOUT(" Clearing UTA\n");
3867 for (i = 0; i < 128; i++)
3868 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3870 return IXGBE_SUCCESS;
3874 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3875 * @hw: pointer to hardware structure
3876 * @vlan: VLAN id to write to VLAN filter
3877 * @vlvf_bypass: true to find vlanid only, false returns first empty slot if
3881 * return the VLVF index where this VLAN id should be placed
3884 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)
3886 s32 regindex, first_empty_slot;
3889 /* short cut the special case */
3893 /* if vlvf_bypass is set we don't want to use an empty slot, we
3894 * will simply bypass the VLVF if there are no entries present in the
3895 * VLVF that contain our VLAN
3897 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0;
3899 /* add VLAN enable bit for comparison */
3900 vlan |= IXGBE_VLVF_VIEN;
3902 /* Search for the vlan id in the VLVF entries. Save off the first empty
3903 * slot found along the way.
3905 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1
3907 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) {
3908 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3911 if (!first_empty_slot && !bits)
3912 first_empty_slot = regindex;
3915 /* If we are here then we didn't find the VLAN. Return first empty
3916 * slot we found during our search, else error.
3918 if (!first_empty_slot)
3919 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "No space in VLVF.\n");
3921 return first_empty_slot ? first_empty_slot : IXGBE_ERR_NO_SPACE;
3925 * ixgbe_set_vfta_generic - Set VLAN filter table
3926 * @hw: pointer to hardware structure
3927 * @vlan: VLAN id to write to VLAN filter
3928 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
3929 * @vlan_on: boolean flag to turn on/off VLAN
3930 * @vlvf_bypass: boolean flag indicating updating default pool is okay
3932 * Turn on/off specified VLAN in the VLAN filter table.
3934 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3935 bool vlan_on, bool vlvf_bypass)
3937 u32 regidx, vfta_delta, vfta;
3940 DEBUGFUNC("ixgbe_set_vfta_generic");
3942 if (vlan > 4095 || vind > 63)
3943 return IXGBE_ERR_PARAM;
3946 * this is a 2 part operation - first the VFTA, then the
3947 * VLVF and VLVFB if VT Mode is set
3948 * We don't write the VFTA until we know the VLVF part succeeded.
3952 * The VFTA is a bitstring made up of 128 32-bit registers
3953 * that enable the particular VLAN id, much like the MTA:
3954 * bits[11-5]: which register
3955 * bits[4-0]: which bit in the register
3958 vfta_delta = 1 << (vlan % 32);
3959 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx));
3962 * vfta_delta represents the difference between the current value
3963 * of vfta and the value we want in the register. Since the diff
3964 * is an XOR mask we can just update the vfta using an XOR
3966 vfta_delta &= vlan_on ? ~vfta : vfta;
3970 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
3972 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta,
3974 if (ret_val != IXGBE_SUCCESS) {
3981 /* Update VFTA now that we are ready for traffic */
3983 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta);
3985 return IXGBE_SUCCESS;
3989 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
3990 * @hw: pointer to hardware structure
3991 * @vlan: VLAN id to write to VLAN filter
3992 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
3993 * @vlan_on: boolean flag to turn on/off VLAN in VLVF
3994 * @vfta_delta: pointer to the difference between the current value of VFTA
3995 * and the desired value
3996 * @vfta: the desired value of the VFTA
3997 * @vlvf_bypass: boolean flag indicating updating default pool is okay
3999 * Turn on/off specified bit in VLVF table.
4001 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
4002 bool vlan_on, u32 *vfta_delta, u32 vfta,
4008 DEBUGFUNC("ixgbe_set_vlvf_generic");
4010 if (vlan > 4095 || vind > 63)
4011 return IXGBE_ERR_PARAM;
4013 /* If VT Mode is set
4015 * make sure the vlan is in VLVF
4016 * set the vind bit in the matching VLVFB
4018 * clear the pool bit and possibly the vind
4020 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE))
4021 return IXGBE_SUCCESS;
4023 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
4027 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32));
4029 /* set the pool bit */
4030 bits |= 1 << (vind % 32);
4034 /* clear the pool bit */
4035 bits ^= 1 << (vind % 32);
4038 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) {
4039 /* Clear VFTA first, then disable VLVF. Otherwise
4040 * we run the risk of stray packets leaking into
4041 * the PF via the default pool
4044 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta);
4046 /* disable VLVF and clear remaining bit from pool */
4047 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
4048 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0);
4050 return IXGBE_SUCCESS;
4053 /* If there are still bits set in the VLVFB registers
4054 * for the VLAN ID indicated we need to see if the
4055 * caller is requesting that we clear the VFTA entry bit.
4056 * If the caller has requested that we clear the VFTA
4057 * entry bit but there are still pools/VFs using this VLAN
4058 * ID entry then ignore the request. We're not worried
4059 * about the case where we're turning the VFTA VLAN ID
4060 * entry bit on, only when requested to turn it off as
4061 * there may be multiple pools and/or VFs using the
4062 * VLAN ID entry. In that case we cannot clear the
4063 * VFTA bit until all pools/VFs using that VLAN ID have also
4064 * been cleared. This will be indicated by "bits" being
4070 /* record pool change and enable VLAN ID if not already enabled */
4071 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits);
4072 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan);
4074 return IXGBE_SUCCESS;
4078 * ixgbe_clear_vfta_generic - Clear VLAN filter table
4079 * @hw: pointer to hardware structure
4081 * Clears the VLAN filer table, and the VMDq index associated with the filter
4083 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
4087 DEBUGFUNC("ixgbe_clear_vfta_generic");
4089 for (offset = 0; offset < hw->mac.vft_size; offset++)
4090 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
4092 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
4093 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
4094 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
4095 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0);
4098 return IXGBE_SUCCESS;
4102 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
4103 * @hw: pointer to hardware structure
4105 * Contains the logic to identify if we need to verify link for the
4108 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw)
4111 /* Does FW say we need the fix */
4112 if (!hw->need_crosstalk_fix)
4115 /* Only consider SFP+ PHYs i.e. media type fiber */
4116 switch (hw->mac.ops.get_media_type(hw)) {
4117 case ixgbe_media_type_fiber:
4118 case ixgbe_media_type_fiber_qsfp:
4128 * ixgbe_check_mac_link_generic - Determine link and speed status
4129 * @hw: pointer to hardware structure
4130 * @speed: pointer to link speed
4131 * @link_up: true when link is up
4132 * @link_up_wait_to_complete: bool used to wait for link up or not
4134 * Reads the links register to determine if link is up and the current speed
4136 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4137 bool *link_up, bool link_up_wait_to_complete)
4139 u32 links_reg, links_orig;
4142 DEBUGFUNC("ixgbe_check_mac_link_generic");
4144 /* If Crosstalk fix enabled do the sanity check of making sure
4145 * the SFP+ cage is full.
4147 if (ixgbe_need_crosstalk_fix(hw)) {
4150 switch (hw->mac.type) {
4151 case ixgbe_mac_82599EB:
4152 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4155 case ixgbe_mac_X550EM_x:
4156 case ixgbe_mac_X550EM_a:
4157 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4161 /* sanity check - No SFP+ devices here */
4162 sfp_cage_full = false;
4166 if (!sfp_cage_full) {
4168 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4169 return IXGBE_SUCCESS;
4173 /* clear the old state */
4174 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
4176 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4178 if (links_orig != links_reg) {
4179 DEBUGOUT2("LINKS changed from %08X to %08X\n",
4180 links_orig, links_reg);
4183 if (link_up_wait_to_complete) {
4184 for (i = 0; i < hw->mac.max_link_up_time; i++) {
4185 if (links_reg & IXGBE_LINKS_UP) {
4192 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4195 if (links_reg & IXGBE_LINKS_UP)
4201 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4202 case IXGBE_LINKS_SPEED_10G_82599:
4203 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4204 if (hw->mac.type >= ixgbe_mac_X550) {
4205 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4206 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4209 case IXGBE_LINKS_SPEED_1G_82599:
4210 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4212 case IXGBE_LINKS_SPEED_100_82599:
4213 *speed = IXGBE_LINK_SPEED_100_FULL;
4214 if (hw->mac.type == ixgbe_mac_X550) {
4215 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4216 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4219 case IXGBE_LINKS_SPEED_10_X550EM_A:
4220 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4221 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4222 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4223 *speed = IXGBE_LINK_SPEED_10_FULL;
4226 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4229 return IXGBE_SUCCESS;
4233 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4235 * @hw: pointer to hardware structure
4236 * @wwnn_prefix: the alternative WWNN prefix
4237 * @wwpn_prefix: the alternative WWPN prefix
4239 * This function will read the EEPROM from the alternative SAN MAC address
4240 * block to check the support for the alternative WWNN/WWPN prefix support.
4242 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4246 u16 alt_san_mac_blk_offset;
4248 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
4250 /* clear output first */
4251 *wwnn_prefix = 0xFFFF;
4252 *wwpn_prefix = 0xFFFF;
4254 /* check if alternative SAN MAC is supported */
4255 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
4256 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4257 goto wwn_prefix_err;
4259 if ((alt_san_mac_blk_offset == 0) ||
4260 (alt_san_mac_blk_offset == 0xFFFF))
4261 goto wwn_prefix_out;
4263 /* check capability in alternative san mac address block */
4264 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
4265 if (hw->eeprom.ops.read(hw, offset, &caps))
4266 goto wwn_prefix_err;
4267 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
4268 goto wwn_prefix_out;
4270 /* get the corresponding prefix for WWNN/WWPN */
4271 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
4272 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4273 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4274 "eeprom read at offset %d failed", offset);
4277 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
4278 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4279 goto wwn_prefix_err;
4282 return IXGBE_SUCCESS;
4285 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4286 "eeprom read at offset %d failed", offset);
4287 return IXGBE_SUCCESS;
4291 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4292 * @hw: pointer to hardware structure
4293 * @bs: the fcoe boot status
4295 * This function will read the FCOE boot status from the iSCSI FCOE block
4297 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4299 u16 offset, caps, flags;
4302 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
4304 /* clear output first */
4305 *bs = ixgbe_fcoe_bootstatus_unavailable;
4307 /* check if FCOE IBA block is present */
4308 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
4309 status = hw->eeprom.ops.read(hw, offset, &caps);
4310 if (status != IXGBE_SUCCESS)
4313 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
4316 /* check if iSCSI FCOE block is populated */
4317 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4318 if (status != IXGBE_SUCCESS)
4321 if ((offset == 0) || (offset == 0xFFFF))
4324 /* read fcoe flags in iSCSI FCOE block */
4325 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
4326 status = hw->eeprom.ops.read(hw, offset, &flags);
4327 if (status != IXGBE_SUCCESS)
4330 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
4331 *bs = ixgbe_fcoe_bootstatus_enabled;
4333 *bs = ixgbe_fcoe_bootstatus_disabled;
4340 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4341 * @hw: pointer to hardware structure
4342 * @enable: enable or disable switch for MAC anti-spoofing
4343 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
4346 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4348 int vf_target_reg = vf >> 3;
4349 int vf_target_shift = vf % 8;
4352 if (hw->mac.type == ixgbe_mac_82598EB)
4355 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4357 pfvfspoof |= (1 << vf_target_shift);
4359 pfvfspoof &= ~(1 << vf_target_shift);
4360 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4364 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4365 * @hw: pointer to hardware structure
4366 * @enable: enable or disable switch for VLAN anti-spoofing
4367 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4370 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4372 int vf_target_reg = vf >> 3;
4373 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
4376 if (hw->mac.type == ixgbe_mac_82598EB)
4379 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4381 pfvfspoof |= (1 << vf_target_shift);
4383 pfvfspoof &= ~(1 << vf_target_shift);
4384 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4388 * ixgbe_get_device_caps_generic - Get additional device capabilities
4389 * @hw: pointer to hardware structure
4390 * @device_caps: the EEPROM word with the extra device capabilities
4392 * This function will read the EEPROM location for the device capabilities,
4393 * and return the word through device_caps.
4395 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4397 DEBUGFUNC("ixgbe_get_device_caps_generic");
4399 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4401 return IXGBE_SUCCESS;
4405 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4406 * @hw: pointer to hardware structure
4409 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4414 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
4416 /* Enable relaxed ordering */
4417 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4418 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4419 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4420 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4423 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4424 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4425 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
4426 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4427 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4433 * ixgbe_calculate_checksum - Calculate checksum for buffer
4434 * @buffer: pointer to EEPROM
4435 * @length: size of EEPROM to calculate a checksum for
4436 * Calculates the checksum for some buffer on a specified length. The
4437 * checksum calculated is returned.
4439 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4444 DEBUGFUNC("ixgbe_calculate_checksum");
4449 for (i = 0; i < length; i++)
4452 return (u8) (0 - sum);
4456 * ixgbe_hic_unlocked - Issue command to manageability block unlocked
4457 * @hw: pointer to the HW structure
4458 * @buffer: command to write and where the return status will be placed
4459 * @length: length of buffer, must be multiple of 4 bytes
4460 * @timeout: time in ms to wait for command completion
4462 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4463 * else returns semaphore error when encountering an error acquiring
4464 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4466 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held
4469 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length,
4475 DEBUGFUNC("ixgbe_hic_unlocked");
4477 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4478 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4479 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4482 /* Set bit 9 of FWSTS clearing FW reset indication */
4483 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
4484 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
4486 /* Check that the host interface is enabled. */
4487 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4488 if (!(hicr & IXGBE_HICR_EN)) {
4489 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
4490 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4493 /* Calculate length in DWORDs. We must be DWORD aligned */
4494 if (length % sizeof(u32)) {
4495 DEBUGOUT("Buffer length failure, not aligned to dword");
4496 return IXGBE_ERR_INVALID_ARGUMENT;
4499 dword_len = length >> 2;
4501 /* The device driver writes the relevant command block
4502 * into the ram area.
4504 for (i = 0; i < dword_len; i++)
4505 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4506 i, IXGBE_CPU_TO_LE32(buffer[i]));
4508 /* Setting this bit tells the ARC that a new command is pending. */
4509 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4511 for (i = 0; i < timeout; i++) {
4512 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4513 if (!(hicr & IXGBE_HICR_C))
4518 /* For each command except "Apply Update" perform
4519 * status checks in the HICR registry.
4521 if ((buffer[0] & IXGBE_HOST_INTERFACE_MASK_CMD) ==
4522 IXGBE_HOST_INTERFACE_APPLY_UPDATE_CMD)
4523 return IXGBE_SUCCESS;
4525 /* Check command completion */
4526 if ((timeout && i == timeout) ||
4527 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
4528 ERROR_REPORT1(IXGBE_ERROR_CAUTION,
4529 "Command has failed with no status valid.\n");
4530 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4533 return IXGBE_SUCCESS;
4537 * ixgbe_host_interface_command - Issue command to manageability block
4538 * @hw: pointer to the HW structure
4539 * @buffer: contains the command to write and where the return status will
4541 * @length: length of buffer, must be multiple of 4 bytes
4542 * @timeout: time in ms to wait for command completion
4543 * @return_data: read and return data from the buffer (true) or not (false)
4544 * Needed because FW structures are big endian and decoding of
4545 * these fields can be 8 bit or 16 bit based on command. Decoding
4546 * is not easily understood without making a table of commands.
4547 * So we will leave this up to the caller to read back the data
4550 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4551 * else returns semaphore error when encountering an error acquiring
4552 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4554 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4555 u32 length, u32 timeout, bool return_data)
4557 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4558 struct ixgbe_hic_hdr *resp = (struct ixgbe_hic_hdr *)buffer;
4564 DEBUGFUNC("ixgbe_host_interface_command");
4566 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4567 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4568 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4571 /* Take management host interface semaphore */
4572 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4576 status = ixgbe_hic_unlocked(hw, buffer, length, timeout);
4583 /* Calculate length in DWORDs */
4584 dword_len = hdr_size >> 2;
4586 /* first pull in the header so we know the buffer length */
4587 for (bi = 0; bi < dword_len; bi++) {
4588 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4589 IXGBE_LE32_TO_CPUS((uintptr_t)&buffer[bi]);
4593 * If there is any thing in data position pull it in
4594 * Read Flash command requires reading buffer length from
4595 * two byes instead of one byte
4597 if (resp->cmd == IXGBE_HOST_INTERFACE_FLASH_READ_CMD ||
4598 resp->cmd == IXGBE_HOST_INTERFACE_SHADOW_RAM_READ_CMD) {
4599 for (; bi < dword_len + 2; bi++) {
4600 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4602 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4604 buf_len = (((u16)(resp->cmd_or_resp.ret_status) << 3)
4605 & 0xF00) | resp->buf_len;
4606 hdr_size += (2 << 2);
4608 buf_len = resp->buf_len;
4613 if (length < buf_len + hdr_size) {
4614 DEBUGOUT("Buffer not large enough for reply message.\n");
4615 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4619 /* Calculate length in DWORDs, add 3 for odd lengths */
4620 dword_len = (buf_len + 3) >> 2;
4622 /* Pull in the rest of the buffer (bi is where we left off) */
4623 for (; bi <= dword_len; bi++) {
4624 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4625 IXGBE_LE32_TO_CPUS((uintptr_t)&buffer[bi]);
4629 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4635 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4636 * @hw: pointer to the HW structure
4637 * @maj: driver version major number
4638 * @min: driver version minor number
4639 * @build: driver version build number
4640 * @sub: driver version sub build number
4642 * @driver_ver: unused
4644 * Sends driver version number to firmware through the manageability
4645 * block. On success return IXGBE_SUCCESS
4646 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4647 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4649 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4650 u8 build, u8 sub, u16 len,
4651 const char *driver_ver)
4653 struct ixgbe_hic_drv_info fw_cmd;
4655 s32 ret_val = IXGBE_SUCCESS;
4657 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4658 UNREFERENCED_2PARAMETER(len, driver_ver);
4660 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4661 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4662 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4663 fw_cmd.port_num = (u8)hw->bus.func;
4664 fw_cmd.ver_maj = maj;
4665 fw_cmd.ver_min = min;
4666 fw_cmd.ver_build = build;
4667 fw_cmd.ver_sub = sub;
4668 fw_cmd.hdr.checksum = 0;
4671 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4672 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4674 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4675 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4677 IXGBE_HI_COMMAND_TIMEOUT,
4679 if (ret_val != IXGBE_SUCCESS)
4682 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4683 FW_CEM_RESP_STATUS_SUCCESS)
4684 ret_val = IXGBE_SUCCESS;
4686 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4695 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4696 * @hw: pointer to hardware structure
4697 * @num_pb: number of packet buffers to allocate
4698 * @headroom: reserve n KB of headroom
4699 * @strategy: packet buffer allocation strategy
4701 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4704 u32 pbsize = hw->mac.rx_pb_size;
4706 u32 rxpktsize, txpktsize, txpbthresh;
4708 /* Reserve headroom */
4714 /* Divide remaining packet buffer space amongst the number of packet
4715 * buffers requested using supplied strategy.
4718 case PBA_STRATEGY_WEIGHTED:
4719 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4720 * buffer with 5/8 of the packet buffer space.
4722 rxpktsize = (pbsize * 5) / (num_pb * 4);
4723 pbsize -= rxpktsize * (num_pb / 2);
4724 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4725 for (; i < (num_pb / 2); i++)
4726 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4727 /* fall through - configure remaining packet buffers */
4728 case PBA_STRATEGY_EQUAL:
4729 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4730 for (; i < num_pb; i++)
4731 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4737 /* Only support an equally distributed Tx packet buffer strategy. */
4738 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4739 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4740 for (i = 0; i < num_pb; i++) {
4741 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4742 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4745 /* Clear unused TCs, if any, to zero buffer size*/
4746 for (; i < IXGBE_MAX_PB; i++) {
4747 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4748 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4749 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4754 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4755 * @hw: pointer to the hardware structure
4757 * The 82599 and x540 MACs can experience issues if TX work is still pending
4758 * when a reset occurs. This function prevents this by flushing the PCIe
4759 * buffers on the system.
4761 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4763 u32 gcr_ext, hlreg0, i, poll;
4767 * If double reset is not requested then all transactions should
4768 * already be clear and as such there is no work to do
4770 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4774 * Set loopback enable to prevent any transmits from being sent
4775 * should the link come up. This assumes that the RXCTRL.RXEN bit
4776 * has already been cleared.
4778 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4779 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4781 /* Wait for a last completion before clearing buffers */
4782 IXGBE_WRITE_FLUSH(hw);
4786 * Before proceeding, make sure that the PCIe block does not have
4787 * transactions pending.
4789 poll = ixgbe_pcie_timeout_poll(hw);
4790 for (i = 0; i < poll; i++) {
4792 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
4793 if (IXGBE_REMOVED(hw->hw_addr))
4795 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
4800 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4801 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4802 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4803 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4805 /* Flush all writes and allow 20usec for all transactions to clear */
4806 IXGBE_WRITE_FLUSH(hw);
4809 /* restore previous register values */
4810 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4811 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4814 STATIC const u8 ixgbe_emc_temp_data[4] = {
4815 IXGBE_EMC_INTERNAL_DATA,
4816 IXGBE_EMC_DIODE1_DATA,
4817 IXGBE_EMC_DIODE2_DATA,
4818 IXGBE_EMC_DIODE3_DATA
4820 STATIC const u8 ixgbe_emc_therm_limit[4] = {
4821 IXGBE_EMC_INTERNAL_THERM_LIMIT,
4822 IXGBE_EMC_DIODE1_THERM_LIMIT,
4823 IXGBE_EMC_DIODE2_THERM_LIMIT,
4824 IXGBE_EMC_DIODE3_THERM_LIMIT
4828 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
4829 * @hw: pointer to hardware structure
4831 * Returns the thermal sensor data structure
4833 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
4835 s32 status = IXGBE_SUCCESS;
4843 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4845 DEBUGFUNC("ixgbe_get_thermal_sensor_data_generic");
4847 /* Only support thermal sensors attached to 82599 physical port 0 */
4848 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4849 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
4850 status = IXGBE_NOT_IMPLEMENTED;
4854 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);
4858 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) {
4859 status = IXGBE_NOT_IMPLEMENTED;
4863 status = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);
4867 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4868 != IXGBE_ETS_TYPE_EMC) {
4869 status = IXGBE_NOT_IMPLEMENTED;
4873 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4874 if (num_sensors > IXGBE_MAX_SENSORS)
4875 num_sensors = IXGBE_MAX_SENSORS;
4877 for (i = 0; i < num_sensors; i++) {
4878 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
4883 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4884 IXGBE_ETS_DATA_INDEX_SHIFT);
4885 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4886 IXGBE_ETS_DATA_LOC_SHIFT);
4888 if (sensor_location != 0) {
4889 status = hw->phy.ops.read_i2c_byte(hw,
4890 ixgbe_emc_temp_data[sensor_index],
4891 IXGBE_I2C_THERMAL_SENSOR_ADDR,
4892 &data->sensor[i].temp);
4902 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
4903 * @hw: pointer to hardware structure
4905 * Inits the thermal sensor thresholds according to the NVM map
4906 * and save off the threshold and location values into mac.thermal_sensor_data
4908 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
4910 s32 status = IXGBE_SUCCESS;
4915 u8 low_thresh_delta;
4921 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4923 DEBUGFUNC("ixgbe_init_thermal_sensor_thresh_generic");
4925 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
4927 /* Only support thermal sensors attached to 82599 physical port 0 */
4928 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4929 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
4930 return IXGBE_NOT_IMPLEMENTED;
4932 offset = IXGBE_ETS_CFG;
4933 if (hw->eeprom.ops.read(hw, offset, &ets_offset))
4935 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
4936 return IXGBE_NOT_IMPLEMENTED;
4938 offset = ets_offset;
4939 if (hw->eeprom.ops.read(hw, offset, &ets_cfg))
4941 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4942 != IXGBE_ETS_TYPE_EMC)
4943 return IXGBE_NOT_IMPLEMENTED;
4945 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
4946 IXGBE_ETS_LTHRES_DELTA_SHIFT);
4947 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4949 for (i = 0; i < num_sensors; i++) {
4950 offset = ets_offset + 1 + i;
4951 if (hw->eeprom.ops.read(hw, offset, &ets_sensor)) {
4952 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4953 "eeprom read at offset %d failed",
4957 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4958 IXGBE_ETS_DATA_INDEX_SHIFT);
4959 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4960 IXGBE_ETS_DATA_LOC_SHIFT);
4961 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
4963 hw->phy.ops.write_i2c_byte(hw,
4964 ixgbe_emc_therm_limit[sensor_index],
4965 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
4967 if ((i < IXGBE_MAX_SENSORS) && (sensor_location != 0)) {
4968 data->sensor[i].location = sensor_location;
4969 data->sensor[i].caution_thresh = therm_limit;
4970 data->sensor[i].max_op_thresh = therm_limit -
4977 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4978 "eeprom read at offset %d failed", offset);
4979 return IXGBE_NOT_IMPLEMENTED;
4983 * ixgbe_get_orom_version - Return option ROM from EEPROM
4985 * @hw: pointer to hardware structure
4986 * @nvm_ver: pointer to output structure
4988 * if valid option ROM version, nvm_ver->or_valid set to true
4989 * else nvm_ver->or_valid is false.
4991 void ixgbe_get_orom_version(struct ixgbe_hw *hw,
4992 struct ixgbe_nvm_version *nvm_ver)
4994 u16 offset, eeprom_cfg_blkh, eeprom_cfg_blkl;
4996 nvm_ver->or_valid = false;
4997 /* Option Rom may or may not be present. Start with pointer */
4998 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset);
5000 /* make sure offset is valid */
5001 if ((offset == 0x0) || (offset == NVM_INVALID_PTR))
5004 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh);
5005 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl);
5007 /* option rom exists and is valid */
5008 if ((eeprom_cfg_blkl | eeprom_cfg_blkh) == 0x0 ||
5009 eeprom_cfg_blkl == NVM_VER_INVALID ||
5010 eeprom_cfg_blkh == NVM_VER_INVALID)
5013 nvm_ver->or_valid = true;
5014 nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT;
5015 nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) |
5016 (eeprom_cfg_blkh >> NVM_OROM_SHIFT);
5017 nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK;
5021 * ixgbe_get_oem_prod_version - Return OEM Product version
5023 * @hw: pointer to hardware structure
5024 * @nvm_ver: pointer to output structure
5026 * if valid OEM product version, nvm_ver->oem_valid set to true
5027 * else nvm_ver->oem_valid is false.
5029 void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw,
5030 struct ixgbe_nvm_version *nvm_ver)
5032 u16 rel_num, prod_ver, mod_len, cap, offset;
5034 nvm_ver->oem_valid = false;
5035 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset);
5037 /* Return is offset to OEM Product Version block is invalid */
5038 if (offset == 0x0 || offset == NVM_INVALID_PTR)
5041 /* Read product version block */
5042 hw->eeprom.ops.read(hw, offset, &mod_len);
5043 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap);
5045 /* Return if OEM product version block is invalid */
5046 if (mod_len != NVM_OEM_PROD_VER_MOD_LEN ||
5047 (cap & NVM_OEM_PROD_VER_CAP_MASK) != 0x0)
5050 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver);
5051 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num);
5053 /* Return if version is invalid */
5054 if ((rel_num | prod_ver) == 0x0 ||
5055 rel_num == NVM_VER_INVALID || prod_ver == NVM_VER_INVALID)
5058 nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT;
5059 nvm_ver->oem_minor = prod_ver & NVM_VER_MASK;
5060 nvm_ver->oem_release = rel_num;
5061 nvm_ver->oem_valid = true;
5065 * ixgbe_get_etk_id - Return Etrack ID from EEPROM
5067 * @hw: pointer to hardware structure
5068 * @nvm_ver: pointer to output structure
5070 * word read errors will return 0xFFFF
5072 void ixgbe_get_etk_id(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver)
5074 u16 etk_id_l, etk_id_h;
5076 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l))
5077 etk_id_l = NVM_VER_INVALID;
5078 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h))
5079 etk_id_h = NVM_VER_INVALID;
5081 /* The word order for the version format is determined by high order
5084 if ((etk_id_h & NVM_ETK_VALID) == 0) {
5085 nvm_ver->etk_id = etk_id_h;
5086 nvm_ver->etk_id |= (etk_id_l << NVM_ETK_SHIFT);
5088 nvm_ver->etk_id = etk_id_l;
5089 nvm_ver->etk_id |= (etk_id_h << NVM_ETK_SHIFT);
5095 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
5096 * @hw: pointer to hardware structure
5097 * @map: pointer to u8 arr for returning map
5099 * Read the rtrup2tc HW register and resolve its content into map
5101 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
5105 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
5106 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
5107 map[i] = IXGBE_RTRUP2TC_UP_MASK &
5108 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
5112 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
5117 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5118 if (rxctrl & IXGBE_RXCTRL_RXEN) {
5119 if (hw->mac.type != ixgbe_mac_82598EB) {
5120 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5121 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
5122 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
5123 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
5124 hw->mac.set_lben = true;
5126 hw->mac.set_lben = false;
5129 rxctrl &= ~IXGBE_RXCTRL_RXEN;
5130 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
5134 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
5139 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5140 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
5142 if (hw->mac.type != ixgbe_mac_82598EB) {
5143 if (hw->mac.set_lben) {
5144 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5145 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
5146 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
5147 hw->mac.set_lben = false;
5153 * ixgbe_mng_present - returns true when management capability is present
5154 * @hw: pointer to hardware structure
5156 bool ixgbe_mng_present(struct ixgbe_hw *hw)
5160 if (hw->mac.type < ixgbe_mac_82599EB)
5163 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5165 return !!(fwsm & IXGBE_FWSM_FW_MODE_PT);
5169 * ixgbe_mng_enabled - Is the manageability engine enabled?
5170 * @hw: pointer to hardware structure
5172 * Returns true if the manageability engine is enabled.
5174 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
5176 u32 fwsm, manc, factps;
5178 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5179 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
5182 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
5183 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
5186 if (hw->mac.type <= ixgbe_mac_X540) {
5187 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
5188 if (factps & IXGBE_FACTPS_MNGCG)
5196 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
5197 * @hw: pointer to hardware structure
5198 * @speed: new link speed
5199 * @autoneg_wait_to_complete: true when waiting for completion is needed
5201 * Set the link speed in the MAC and/or PHY register and restarts link.
5203 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
5204 ixgbe_link_speed speed,
5205 bool autoneg_wait_to_complete)
5207 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
5208 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
5209 s32 status = IXGBE_SUCCESS;
5212 bool autoneg, link_up = false;
5214 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
5216 /* Mask off requested but non-supported speeds */
5217 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
5218 if (status != IXGBE_SUCCESS)
5221 speed &= link_speed;
5223 /* Try each speed one by one, highest priority first. We do this in
5224 * software because 10Gb fiber doesn't support speed autonegotiation.
5226 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
5228 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5230 /* Set the module link speed */
5231 switch (hw->phy.media_type) {
5232 case ixgbe_media_type_fiber:
5233 ixgbe_set_rate_select_speed(hw,
5234 IXGBE_LINK_SPEED_10GB_FULL);
5236 case ixgbe_media_type_fiber_qsfp:
5237 /* QSFP module automatically detects MAC link speed */
5240 DEBUGOUT("Unexpected media type.\n");
5244 /* Allow module to change analog characteristics (1G->10G) */
5247 status = ixgbe_setup_mac_link(hw,
5248 IXGBE_LINK_SPEED_10GB_FULL,
5249 autoneg_wait_to_complete);
5250 if (status != IXGBE_SUCCESS)
5253 /* Flap the Tx laser if it has not already been done */
5254 ixgbe_flap_tx_laser(hw);
5256 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
5257 * Section 73.10.2, we may have to wait up to 1000ms if KR is
5258 * attempted. 82599 uses the same timing for 10g SFI.
5260 for (i = 0; i < 10; i++) {
5261 /* Wait for the link partner to also set speed */
5264 /* If we have link, just jump out */
5265 status = ixgbe_check_link(hw, &link_speed,
5267 if (status != IXGBE_SUCCESS)
5275 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
5277 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
5278 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
5280 /* Set the module link speed */
5281 switch (hw->phy.media_type) {
5282 case ixgbe_media_type_fiber:
5283 ixgbe_set_rate_select_speed(hw,
5284 IXGBE_LINK_SPEED_1GB_FULL);
5286 case ixgbe_media_type_fiber_qsfp:
5287 /* QSFP module automatically detects link speed */
5290 DEBUGOUT("Unexpected media type.\n");
5294 /* Allow module to change analog characteristics (10G->1G) */
5297 status = ixgbe_setup_mac_link(hw,
5298 IXGBE_LINK_SPEED_1GB_FULL,
5299 autoneg_wait_to_complete);
5300 if (status != IXGBE_SUCCESS)
5303 /* Flap the Tx laser if it has not already been done */
5304 ixgbe_flap_tx_laser(hw);
5306 /* Wait for the link partner to also set speed */
5309 /* If we have link, just jump out */
5310 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
5311 if (status != IXGBE_SUCCESS)
5318 /* We didn't get link. Configure back to the highest speed we tried,
5319 * (if there was more than one). We call ourselves back with just the
5320 * single highest speed that the user requested.
5323 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
5325 autoneg_wait_to_complete);
5328 /* Set autoneg_advertised value based on input link speed */
5329 hw->phy.autoneg_advertised = 0;
5331 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
5332 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
5334 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
5335 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
5341 * ixgbe_set_soft_rate_select_speed - Set module link speed
5342 * @hw: pointer to hardware structure
5343 * @speed: link speed to set
5345 * Set module link speed via the soft rate select.
5347 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
5348 ixgbe_link_speed speed)
5354 case IXGBE_LINK_SPEED_10GB_FULL:
5355 /* one bit mask same as setting on */
5356 rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
5358 case IXGBE_LINK_SPEED_1GB_FULL:
5359 rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
5362 DEBUGOUT("Invalid fixed module speed\n");
5367 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5368 IXGBE_I2C_EEPROM_DEV_ADDR2,
5371 DEBUGOUT("Failed to read Rx Rate Select RS0\n");
5375 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5377 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5378 IXGBE_I2C_EEPROM_DEV_ADDR2,
5381 DEBUGOUT("Failed to write Rx Rate Select RS0\n");
5386 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5387 IXGBE_I2C_EEPROM_DEV_ADDR2,
5390 DEBUGOUT("Failed to read Rx Rate Select RS1\n");
5394 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5396 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5397 IXGBE_I2C_EEPROM_DEV_ADDR2,
5400 DEBUGOUT("Failed to write Rx Rate Select RS1\n");