1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2018
5 #include "ixgbe_common.h"
8 #include "ixgbe_dcb_82599.h"
11 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
12 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
13 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
14 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
15 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
16 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
18 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
19 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
20 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
21 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw);
23 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
24 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
26 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
27 u16 words, u16 *data);
28 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
29 u16 words, u16 *data);
30 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
34 * ixgbe_init_ops_generic - Inits function ptrs
35 * @hw: pointer to the hardware structure
37 * Initialize the function pointers.
39 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
41 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
42 struct ixgbe_mac_info *mac = &hw->mac;
43 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
45 DEBUGFUNC("ixgbe_init_ops_generic");
48 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic;
49 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
50 if (eec & IXGBE_EEC_PRES) {
51 eeprom->ops.read = ixgbe_read_eerd_generic;
52 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic;
54 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic;
55 eeprom->ops.read_buffer =
56 ixgbe_read_eeprom_buffer_bit_bang_generic;
58 eeprom->ops.write = ixgbe_write_eeprom_generic;
59 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic;
60 eeprom->ops.validate_checksum =
61 ixgbe_validate_eeprom_checksum_generic;
62 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic;
63 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic;
66 mac->ops.init_hw = ixgbe_init_hw_generic;
67 mac->ops.reset_hw = NULL;
68 mac->ops.start_hw = ixgbe_start_hw_generic;
69 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic;
70 mac->ops.get_media_type = NULL;
71 mac->ops.get_supported_physical_layer = NULL;
72 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic;
73 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic;
74 mac->ops.stop_adapter = ixgbe_stop_adapter_generic;
75 mac->ops.get_bus_info = ixgbe_get_bus_info_generic;
76 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie;
77 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync;
78 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync;
79 mac->ops.prot_autoc_read = prot_autoc_read_generic;
80 mac->ops.prot_autoc_write = prot_autoc_write_generic;
83 mac->ops.led_on = ixgbe_led_on_generic;
84 mac->ops.led_off = ixgbe_led_off_generic;
85 mac->ops.blink_led_start = ixgbe_blink_led_start_generic;
86 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic;
87 mac->ops.init_led_link_act = ixgbe_init_led_link_act_generic;
89 /* RAR, Multicast, VLAN */
90 mac->ops.set_rar = ixgbe_set_rar_generic;
91 mac->ops.clear_rar = ixgbe_clear_rar_generic;
92 mac->ops.insert_mac_addr = NULL;
93 mac->ops.set_vmdq = NULL;
94 mac->ops.clear_vmdq = NULL;
95 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic;
96 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic;
97 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic;
98 mac->ops.enable_mc = ixgbe_enable_mc_generic;
99 mac->ops.disable_mc = ixgbe_disable_mc_generic;
100 mac->ops.clear_vfta = NULL;
101 mac->ops.set_vfta = NULL;
102 mac->ops.set_vlvf = NULL;
103 mac->ops.init_uta_tables = NULL;
104 mac->ops.enable_rx = ixgbe_enable_rx_generic;
105 mac->ops.disable_rx = ixgbe_disable_rx_generic;
108 mac->ops.fc_enable = ixgbe_fc_enable_generic;
109 mac->ops.setup_fc = ixgbe_setup_fc_generic;
110 mac->ops.fc_autoneg = ixgbe_fc_autoneg;
113 mac->ops.get_link_capabilities = NULL;
114 mac->ops.setup_link = NULL;
115 mac->ops.check_link = NULL;
116 mac->ops.dmac_config = NULL;
117 mac->ops.dmac_update_tcs = NULL;
118 mac->ops.dmac_config_tcs = NULL;
120 return IXGBE_SUCCESS;
124 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
126 * @hw: pointer to hardware structure
128 * This function returns true if the device supports flow control
129 * autonegotiation, and false if it does not.
132 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
134 bool supported = false;
135 ixgbe_link_speed speed;
138 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
140 switch (hw->phy.media_type) {
141 case ixgbe_media_type_fiber_fixed:
142 case ixgbe_media_type_fiber_qsfp:
143 case ixgbe_media_type_fiber:
144 /* flow control autoneg black list */
145 switch (hw->device_id) {
146 case IXGBE_DEV_ID_X550EM_A_SFP:
147 case IXGBE_DEV_ID_X550EM_A_SFP_N:
148 case IXGBE_DEV_ID_X550EM_A_QSFP:
149 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
153 hw->mac.ops.check_link(hw, &speed, &link_up, false);
154 /* if link is down, assume supported */
156 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
163 case ixgbe_media_type_backplane:
164 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI)
169 case ixgbe_media_type_copper:
170 /* only some copper devices support flow control autoneg */
171 switch (hw->device_id) {
172 case IXGBE_DEV_ID_82599_T3_LOM:
173 case IXGBE_DEV_ID_X540T:
174 case IXGBE_DEV_ID_X540T1:
175 case IXGBE_DEV_ID_X540_BYPASS:
176 case IXGBE_DEV_ID_X550T:
177 case IXGBE_DEV_ID_X550T1:
178 case IXGBE_DEV_ID_X550EM_X_10G_T:
179 case IXGBE_DEV_ID_X550EM_A_10G_T:
180 case IXGBE_DEV_ID_X550EM_A_1G_T:
181 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
192 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
193 "Device %x does not support flow control autoneg",
199 * ixgbe_setup_fc_generic - Set up flow control
200 * @hw: pointer to hardware structure
202 * Called at init time to set up flow control.
204 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
206 s32 ret_val = IXGBE_SUCCESS;
207 u32 reg = 0, reg_bp = 0;
211 DEBUGFUNC("ixgbe_setup_fc_generic");
213 /* Validate the requested mode */
214 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
215 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
216 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
217 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
222 * 10gig parts do not have a word in the EEPROM to determine the
223 * default flow control setting, so we explicitly set it to full.
225 if (hw->fc.requested_mode == ixgbe_fc_default)
226 hw->fc.requested_mode = ixgbe_fc_full;
229 * Set up the 1G and 10G flow control advertisement registers so the
230 * HW will be able to do fc autoneg once the cable is plugged in. If
231 * we link at 10G, the 1G advertisement is harmless and vice versa.
233 switch (hw->phy.media_type) {
234 case ixgbe_media_type_backplane:
235 /* some MAC's need RMW protection on AUTOC */
236 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
237 if (ret_val != IXGBE_SUCCESS)
240 /* fall through - only backplane uses autoc */
241 case ixgbe_media_type_fiber_fixed:
242 case ixgbe_media_type_fiber_qsfp:
243 case ixgbe_media_type_fiber:
244 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
247 case ixgbe_media_type_copper:
248 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
249 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
256 * The possible values of fc.requested_mode are:
257 * 0: Flow control is completely disabled
258 * 1: Rx flow control is enabled (we can receive pause frames,
259 * but not send pause frames).
260 * 2: Tx flow control is enabled (we can send pause frames but
261 * we do not support receiving pause frames).
262 * 3: Both Rx and Tx flow control (symmetric) are enabled.
265 switch (hw->fc.requested_mode) {
267 /* Flow control completely disabled by software override. */
268 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
269 if (hw->phy.media_type == ixgbe_media_type_backplane)
270 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
271 IXGBE_AUTOC_ASM_PAUSE);
272 else if (hw->phy.media_type == ixgbe_media_type_copper)
273 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
275 case ixgbe_fc_tx_pause:
277 * Tx Flow control is enabled, and Rx Flow control is
278 * disabled by software override.
280 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
281 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
282 if (hw->phy.media_type == ixgbe_media_type_backplane) {
283 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
284 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
285 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
286 reg_cu |= IXGBE_TAF_ASM_PAUSE;
287 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
290 case ixgbe_fc_rx_pause:
292 * Rx Flow control is enabled and Tx Flow control is
293 * disabled by software override. Since there really
294 * isn't a way to advertise that we are capable of RX
295 * Pause ONLY, we will advertise that we support both
296 * symmetric and asymmetric Rx PAUSE, as such we fall
297 * through to the fc_full statement. Later, we will
298 * disable the adapter's ability to send PAUSE frames.
301 /* Flow control (both Rx and Tx) is enabled by SW override. */
302 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
303 if (hw->phy.media_type == ixgbe_media_type_backplane)
304 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
305 IXGBE_AUTOC_ASM_PAUSE;
306 else if (hw->phy.media_type == ixgbe_media_type_copper)
307 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
310 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
311 "Flow control param set incorrectly\n");
312 ret_val = IXGBE_ERR_CONFIG;
317 if (hw->mac.type < ixgbe_mac_X540) {
319 * Enable auto-negotiation between the MAC & PHY;
320 * the MAC will advertise clause 37 flow control.
322 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
323 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
325 /* Disable AN timeout */
326 if (hw->fc.strict_ieee)
327 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
329 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
330 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
334 * AUTOC restart handles negotiation of 1G and 10G on backplane
335 * and copper. There is no need to set the PCS1GCTL register.
338 if (hw->phy.media_type == ixgbe_media_type_backplane) {
339 reg_bp |= IXGBE_AUTOC_AN_RESTART;
340 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
343 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
344 (ixgbe_device_supports_autoneg_fc(hw))) {
345 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
346 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
349 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
355 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
356 * @hw: pointer to hardware structure
358 * Starts the hardware by filling the bus info structure and media type, clears
359 * all on chip counters, initializes receive address registers, multicast
360 * table, VLAN filter table, calls routine to set up link and flow control
361 * settings, and leaves transmit and receive units disabled and uninitialized
363 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
369 DEBUGFUNC("ixgbe_start_hw_generic");
371 /* Set the media type */
372 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
374 /* PHY ops initialization must be done in reset_hw() */
376 /* Clear the VLAN filter table */
377 hw->mac.ops.clear_vfta(hw);
379 /* Clear statistics registers */
380 hw->mac.ops.clear_hw_cntrs(hw);
382 /* Set No Snoop Disable */
383 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
384 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
385 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
386 IXGBE_WRITE_FLUSH(hw);
388 /* Setup flow control */
389 ret_val = ixgbe_setup_fc(hw);
390 if (ret_val != IXGBE_SUCCESS && ret_val != IXGBE_NOT_IMPLEMENTED) {
391 DEBUGOUT1("Flow control setup failed, returning %d\n", ret_val);
395 /* Cache bit indicating need for crosstalk fix */
396 switch (hw->mac.type) {
397 case ixgbe_mac_82599EB:
398 case ixgbe_mac_X550EM_x:
399 case ixgbe_mac_X550EM_a:
400 hw->mac.ops.get_device_caps(hw, &device_caps);
401 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
402 hw->need_crosstalk_fix = false;
404 hw->need_crosstalk_fix = true;
407 hw->need_crosstalk_fix = false;
411 /* Clear adapter stopped flag */
412 hw->adapter_stopped = false;
414 return IXGBE_SUCCESS;
418 * ixgbe_start_hw_gen2 - Init sequence for common device family
419 * @hw: pointer to hw structure
421 * Performs the init sequence common to the second generation
423 * Devices in the second generation:
427 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
432 /* Clear the rate limiters */
433 for (i = 0; i < hw->mac.max_tx_queues; i++) {
434 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
435 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
437 IXGBE_WRITE_FLUSH(hw);
439 /* Disable relaxed ordering */
440 for (i = 0; i < hw->mac.max_tx_queues; i++) {
441 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
442 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
443 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
446 for (i = 0; i < hw->mac.max_rx_queues; i++) {
447 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
448 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
449 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
450 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
453 return IXGBE_SUCCESS;
457 * ixgbe_init_hw_generic - Generic hardware initialization
458 * @hw: pointer to hardware structure
460 * Initialize the hardware by resetting the hardware, filling the bus info
461 * structure and media type, clears all on chip counters, initializes receive
462 * address registers, multicast table, VLAN filter table, calls routine to set
463 * up link and flow control settings, and leaves transmit and receive units
464 * disabled and uninitialized
466 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
470 DEBUGFUNC("ixgbe_init_hw_generic");
472 /* Reset the hardware */
473 status = hw->mac.ops.reset_hw(hw);
475 if (status == IXGBE_SUCCESS || status == IXGBE_ERR_SFP_NOT_PRESENT) {
477 status = hw->mac.ops.start_hw(hw);
480 /* Initialize the LED link active for LED blink support */
481 if (hw->mac.ops.init_led_link_act)
482 hw->mac.ops.init_led_link_act(hw);
484 if (status != IXGBE_SUCCESS)
485 DEBUGOUT1("Failed to initialize HW, STATUS = %d\n", status);
491 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
492 * @hw: pointer to hardware structure
494 * Clears all hardware statistics counters by reading them from the hardware
495 * Statistics counters are clear on read.
497 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
501 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
503 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
504 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
505 IXGBE_READ_REG(hw, IXGBE_ERRBC);
506 IXGBE_READ_REG(hw, IXGBE_MSPDC);
507 for (i = 0; i < 8; i++)
508 IXGBE_READ_REG(hw, IXGBE_MPC(i));
510 IXGBE_READ_REG(hw, IXGBE_MLFC);
511 IXGBE_READ_REG(hw, IXGBE_MRFC);
512 IXGBE_READ_REG(hw, IXGBE_RLEC);
513 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
514 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
515 if (hw->mac.type >= ixgbe_mac_82599EB) {
516 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
517 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
519 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
520 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
523 for (i = 0; i < 8; i++) {
524 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
525 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
526 if (hw->mac.type >= ixgbe_mac_82599EB) {
527 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
528 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
530 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
531 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
534 if (hw->mac.type >= ixgbe_mac_82599EB)
535 for (i = 0; i < 8; i++)
536 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
537 IXGBE_READ_REG(hw, IXGBE_PRC64);
538 IXGBE_READ_REG(hw, IXGBE_PRC127);
539 IXGBE_READ_REG(hw, IXGBE_PRC255);
540 IXGBE_READ_REG(hw, IXGBE_PRC511);
541 IXGBE_READ_REG(hw, IXGBE_PRC1023);
542 IXGBE_READ_REG(hw, IXGBE_PRC1522);
543 IXGBE_READ_REG(hw, IXGBE_GPRC);
544 IXGBE_READ_REG(hw, IXGBE_BPRC);
545 IXGBE_READ_REG(hw, IXGBE_MPRC);
546 IXGBE_READ_REG(hw, IXGBE_GPTC);
547 IXGBE_READ_REG(hw, IXGBE_GORCL);
548 IXGBE_READ_REG(hw, IXGBE_GORCH);
549 IXGBE_READ_REG(hw, IXGBE_GOTCL);
550 IXGBE_READ_REG(hw, IXGBE_GOTCH);
551 if (hw->mac.type == ixgbe_mac_82598EB)
552 for (i = 0; i < 8; i++)
553 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
554 IXGBE_READ_REG(hw, IXGBE_RUC);
555 IXGBE_READ_REG(hw, IXGBE_RFC);
556 IXGBE_READ_REG(hw, IXGBE_ROC);
557 IXGBE_READ_REG(hw, IXGBE_RJC);
558 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
559 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
560 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
561 IXGBE_READ_REG(hw, IXGBE_TORL);
562 IXGBE_READ_REG(hw, IXGBE_TORH);
563 IXGBE_READ_REG(hw, IXGBE_TPR);
564 IXGBE_READ_REG(hw, IXGBE_TPT);
565 IXGBE_READ_REG(hw, IXGBE_PTC64);
566 IXGBE_READ_REG(hw, IXGBE_PTC127);
567 IXGBE_READ_REG(hw, IXGBE_PTC255);
568 IXGBE_READ_REG(hw, IXGBE_PTC511);
569 IXGBE_READ_REG(hw, IXGBE_PTC1023);
570 IXGBE_READ_REG(hw, IXGBE_PTC1522);
571 IXGBE_READ_REG(hw, IXGBE_MPTC);
572 IXGBE_READ_REG(hw, IXGBE_BPTC);
573 for (i = 0; i < 16; i++) {
574 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
575 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
576 if (hw->mac.type >= ixgbe_mac_82599EB) {
577 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
578 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
579 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
580 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
581 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
583 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
584 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
588 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
590 ixgbe_identify_phy(hw);
591 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
592 IXGBE_MDIO_PCS_DEV_TYPE, &i);
593 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
594 IXGBE_MDIO_PCS_DEV_TYPE, &i);
595 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
596 IXGBE_MDIO_PCS_DEV_TYPE, &i);
597 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
598 IXGBE_MDIO_PCS_DEV_TYPE, &i);
601 return IXGBE_SUCCESS;
605 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
606 * @hw: pointer to hardware structure
607 * @pba_num: stores the part number string from the EEPROM
608 * @pba_num_size: part number string buffer length
610 * Reads the part number string from the EEPROM.
612 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
621 DEBUGFUNC("ixgbe_read_pba_string_generic");
623 if (pba_num == NULL) {
624 DEBUGOUT("PBA string buffer was null\n");
625 return IXGBE_ERR_INVALID_ARGUMENT;
628 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
630 DEBUGOUT("NVM Read Error\n");
634 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
636 DEBUGOUT("NVM Read Error\n");
641 * if data is not ptr guard the PBA must be in legacy format which
642 * means pba_ptr is actually our second data word for the PBA number
643 * and we can decode it into an ascii string
645 if (data != IXGBE_PBANUM_PTR_GUARD) {
646 DEBUGOUT("NVM PBA number is not stored as string\n");
648 /* we will need 11 characters to store the PBA */
649 if (pba_num_size < 11) {
650 DEBUGOUT("PBA string buffer too small\n");
651 return IXGBE_ERR_NO_SPACE;
654 /* extract hex string from data and pba_ptr */
655 pba_num[0] = (data >> 12) & 0xF;
656 pba_num[1] = (data >> 8) & 0xF;
657 pba_num[2] = (data >> 4) & 0xF;
658 pba_num[3] = data & 0xF;
659 pba_num[4] = (pba_ptr >> 12) & 0xF;
660 pba_num[5] = (pba_ptr >> 8) & 0xF;
663 pba_num[8] = (pba_ptr >> 4) & 0xF;
664 pba_num[9] = pba_ptr & 0xF;
666 /* put a null character on the end of our string */
669 /* switch all the data but the '-' to hex char */
670 for (offset = 0; offset < 10; offset++) {
671 if (pba_num[offset] < 0xA)
672 pba_num[offset] += '0';
673 else if (pba_num[offset] < 0x10)
674 pba_num[offset] += 'A' - 0xA;
677 return IXGBE_SUCCESS;
680 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
682 DEBUGOUT("NVM Read Error\n");
686 if (length == 0xFFFF || length == 0) {
687 DEBUGOUT("NVM PBA number section invalid length\n");
688 return IXGBE_ERR_PBA_SECTION;
691 /* check if pba_num buffer is big enough */
692 if (pba_num_size < (((u32)length * 2) - 1)) {
693 DEBUGOUT("PBA string buffer too small\n");
694 return IXGBE_ERR_NO_SPACE;
697 /* trim pba length from start of string */
701 for (offset = 0; offset < length; offset++) {
702 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
704 DEBUGOUT("NVM Read Error\n");
707 pba_num[offset * 2] = (u8)(data >> 8);
708 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
710 pba_num[offset * 2] = '\0';
712 return IXGBE_SUCCESS;
716 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
717 * @hw: pointer to hardware structure
718 * @pba_num: stores the part number from the EEPROM
720 * Reads the part number from the EEPROM.
722 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
727 DEBUGFUNC("ixgbe_read_pba_num_generic");
729 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
731 DEBUGOUT("NVM Read Error\n");
733 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
734 DEBUGOUT("NVM Not supported\n");
735 return IXGBE_NOT_IMPLEMENTED;
737 *pba_num = (u32)(data << 16);
739 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
741 DEBUGOUT("NVM Read Error\n");
746 return IXGBE_SUCCESS;
751 * @hw: pointer to the HW structure
752 * @eeprom_buf: optional pointer to EEPROM image
753 * @eeprom_buf_size: size of EEPROM image in words
754 * @max_pba_block_size: PBA block size limit
755 * @pba: pointer to output PBA structure
757 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
758 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
761 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
762 u32 eeprom_buf_size, u16 max_pba_block_size,
763 struct ixgbe_pba *pba)
769 return IXGBE_ERR_PARAM;
771 if (eeprom_buf == NULL) {
772 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
777 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
778 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
779 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
781 return IXGBE_ERR_PARAM;
785 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
786 if (pba->pba_block == NULL)
787 return IXGBE_ERR_PARAM;
789 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
795 if (pba_block_size > max_pba_block_size)
796 return IXGBE_ERR_PARAM;
798 if (eeprom_buf == NULL) {
799 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
805 if (eeprom_buf_size > (u32)(pba->word[1] +
807 memcpy(pba->pba_block,
808 &eeprom_buf[pba->word[1]],
809 pba_block_size * sizeof(u16));
811 return IXGBE_ERR_PARAM;
816 return IXGBE_SUCCESS;
820 * ixgbe_write_pba_raw
821 * @hw: pointer to the HW structure
822 * @eeprom_buf: optional pointer to EEPROM image
823 * @eeprom_buf_size: size of EEPROM image in words
824 * @pba: pointer to PBA structure
826 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
827 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
830 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
831 u32 eeprom_buf_size, struct ixgbe_pba *pba)
836 return IXGBE_ERR_PARAM;
838 if (eeprom_buf == NULL) {
839 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
844 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
845 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
846 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
848 return IXGBE_ERR_PARAM;
852 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
853 if (pba->pba_block == NULL)
854 return IXGBE_ERR_PARAM;
856 if (eeprom_buf == NULL) {
857 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
863 if (eeprom_buf_size > (u32)(pba->word[1] +
864 pba->pba_block[0])) {
865 memcpy(&eeprom_buf[pba->word[1]],
867 pba->pba_block[0] * sizeof(u16));
869 return IXGBE_ERR_PARAM;
874 return IXGBE_SUCCESS;
878 * ixgbe_get_pba_block_size
879 * @hw: pointer to the HW structure
880 * @eeprom_buf: optional pointer to EEPROM image
881 * @eeprom_buf_size: size of EEPROM image in words
882 * @pba_data_size: pointer to output variable
884 * Returns the size of the PBA block in words. Function operates on EEPROM
885 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
889 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
890 u32 eeprom_buf_size, u16 *pba_block_size)
896 DEBUGFUNC("ixgbe_get_pba_block_size");
898 if (eeprom_buf == NULL) {
899 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
904 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
905 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
906 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
908 return IXGBE_ERR_PARAM;
912 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
913 if (eeprom_buf == NULL) {
914 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
919 if (eeprom_buf_size > pba_word[1])
920 length = eeprom_buf[pba_word[1] + 0];
922 return IXGBE_ERR_PARAM;
925 if (length == 0xFFFF || length == 0)
926 return IXGBE_ERR_PBA_SECTION;
928 /* PBA number in legacy format, there is no PBA Block. */
932 if (pba_block_size != NULL)
933 *pba_block_size = length;
935 return IXGBE_SUCCESS;
939 * ixgbe_get_mac_addr_generic - Generic get MAC address
940 * @hw: pointer to hardware structure
941 * @mac_addr: Adapter MAC address
943 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
944 * A reset of the adapter must be performed prior to calling this function
945 * in order for the MAC address to have been loaded from the EEPROM into RAR0
947 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
953 DEBUGFUNC("ixgbe_get_mac_addr_generic");
955 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
956 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
958 for (i = 0; i < 4; i++)
959 mac_addr[i] = (u8)(rar_low >> (i*8));
961 for (i = 0; i < 2; i++)
962 mac_addr[i+4] = (u8)(rar_high >> (i*8));
964 return IXGBE_SUCCESS;
968 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
969 * @hw: pointer to hardware structure
970 * @link_status: the link status returned by the PCI config space
972 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
974 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
976 struct ixgbe_mac_info *mac = &hw->mac;
978 if (hw->bus.type == ixgbe_bus_type_unknown)
979 hw->bus.type = ixgbe_bus_type_pci_express;
981 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
982 case IXGBE_PCI_LINK_WIDTH_1:
983 hw->bus.width = ixgbe_bus_width_pcie_x1;
985 case IXGBE_PCI_LINK_WIDTH_2:
986 hw->bus.width = ixgbe_bus_width_pcie_x2;
988 case IXGBE_PCI_LINK_WIDTH_4:
989 hw->bus.width = ixgbe_bus_width_pcie_x4;
991 case IXGBE_PCI_LINK_WIDTH_8:
992 hw->bus.width = ixgbe_bus_width_pcie_x8;
995 hw->bus.width = ixgbe_bus_width_unknown;
999 switch (link_status & IXGBE_PCI_LINK_SPEED) {
1000 case IXGBE_PCI_LINK_SPEED_2500:
1001 hw->bus.speed = ixgbe_bus_speed_2500;
1003 case IXGBE_PCI_LINK_SPEED_5000:
1004 hw->bus.speed = ixgbe_bus_speed_5000;
1006 case IXGBE_PCI_LINK_SPEED_8000:
1007 hw->bus.speed = ixgbe_bus_speed_8000;
1010 hw->bus.speed = ixgbe_bus_speed_unknown;
1014 mac->ops.set_lan_id(hw);
1018 * ixgbe_get_bus_info_generic - Generic set PCI bus info
1019 * @hw: pointer to hardware structure
1021 * Gets the PCI bus info (speed, width, type) then calls helper function to
1022 * store this data within the ixgbe_hw structure.
1024 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
1028 DEBUGFUNC("ixgbe_get_bus_info_generic");
1030 /* Get the negotiated link width and speed from PCI config space */
1031 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
1033 ixgbe_set_pci_config_data_generic(hw, link_status);
1035 return IXGBE_SUCCESS;
1039 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
1040 * @hw: pointer to the HW structure
1042 * Determines the LAN function id by reading memory-mapped registers and swaps
1043 * the port value if requested, and set MAC instance for devices that share
1046 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
1048 struct ixgbe_bus_info *bus = &hw->bus;
1052 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
1054 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
1055 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
1056 bus->lan_id = (u8)bus->func;
1058 /* check for a port swap */
1059 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
1060 if (reg & IXGBE_FACTPS_LFS)
1063 /* Get MAC instance from EEPROM for configuring CS4227 */
1064 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) {
1065 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4);
1066 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >>
1067 IXGBE_EE_CTRL_4_INST_ID_SHIFT;
1072 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1073 * @hw: pointer to hardware structure
1075 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
1076 * disables transmit and receive units. The adapter_stopped flag is used by
1077 * the shared code and drivers to determine if the adapter is in a stopped
1078 * state and should not touch the hardware.
1080 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1085 DEBUGFUNC("ixgbe_stop_adapter_generic");
1088 * Set the adapter_stopped flag so other driver functions stop touching
1091 hw->adapter_stopped = true;
1093 /* Disable the receive unit */
1094 ixgbe_disable_rx(hw);
1096 /* Clear interrupt mask to stop interrupts from being generated */
1097 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1099 /* Clear any pending interrupts, flush previous writes */
1100 IXGBE_READ_REG(hw, IXGBE_EICR);
1102 /* Disable the transmit unit. Each queue must be disabled. */
1103 for (i = 0; i < hw->mac.max_tx_queues; i++)
1104 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1106 /* Disable the receive unit by stopping each queue */
1107 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1108 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1109 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1110 reg_val |= IXGBE_RXDCTL_SWFLSH;
1111 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1114 /* flush all queues disables */
1115 IXGBE_WRITE_FLUSH(hw);
1119 * Prevent the PCI-E bus from hanging by disabling PCI-E master
1120 * access and verify no pending requests
1122 return ixgbe_disable_pcie_master(hw);
1126 * ixgbe_init_led_link_act_generic - Store the LED index link/activity.
1127 * @hw: pointer to hardware structure
1129 * Store the index for the link active LED. This will be used to support
1132 s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw)
1134 struct ixgbe_mac_info *mac = &hw->mac;
1135 u32 led_reg, led_mode;
1138 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1140 /* Get LED link active from the LEDCTL register */
1141 for (i = 0; i < 4; i++) {
1142 led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i);
1144 if ((led_mode & IXGBE_LED_MODE_MASK_BASE) ==
1145 IXGBE_LED_LINK_ACTIVE) {
1146 mac->led_link_act = i;
1147 return IXGBE_SUCCESS;
1152 * If LEDCTL register does not have the LED link active set, then use
1153 * known MAC defaults.
1155 switch (hw->mac.type) {
1156 case ixgbe_mac_X550EM_a:
1157 case ixgbe_mac_X550EM_x:
1158 mac->led_link_act = 1;
1161 mac->led_link_act = 2;
1163 return IXGBE_SUCCESS;
1167 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1168 * @hw: pointer to hardware structure
1169 * @index: led number to turn on
1171 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1173 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1175 DEBUGFUNC("ixgbe_led_on_generic");
1178 return IXGBE_ERR_PARAM;
1180 /* To turn on the LED, set mode to ON. */
1181 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1182 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
1183 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1184 IXGBE_WRITE_FLUSH(hw);
1186 return IXGBE_SUCCESS;
1190 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1191 * @hw: pointer to hardware structure
1192 * @index: led number to turn off
1194 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1196 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1198 DEBUGFUNC("ixgbe_led_off_generic");
1201 return IXGBE_ERR_PARAM;
1203 /* To turn off the LED, set mode to OFF. */
1204 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1205 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
1206 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1207 IXGBE_WRITE_FLUSH(hw);
1209 return IXGBE_SUCCESS;
1213 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1214 * @hw: pointer to hardware structure
1216 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1217 * ixgbe_hw struct in order to set up EEPROM access.
1219 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1221 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1225 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
1227 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1228 eeprom->type = ixgbe_eeprom_none;
1229 /* Set default semaphore delay to 10ms which is a well
1231 eeprom->semaphore_delay = 10;
1232 /* Clear EEPROM page size, it will be initialized as needed */
1233 eeprom->word_page_size = 0;
1236 * Check for EEPROM present first.
1237 * If not present leave as none
1239 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1240 if (eec & IXGBE_EEC_PRES) {
1241 eeprom->type = ixgbe_eeprom_spi;
1244 * SPI EEPROM is assumed here. This code would need to
1245 * change if a future EEPROM is not SPI.
1247 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1248 IXGBE_EEC_SIZE_SHIFT);
1249 eeprom->word_size = 1 << (eeprom_size +
1250 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1253 if (eec & IXGBE_EEC_ADDR_SIZE)
1254 eeprom->address_bits = 16;
1256 eeprom->address_bits = 8;
1257 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
1258 "%d\n", eeprom->type, eeprom->word_size,
1259 eeprom->address_bits);
1262 return IXGBE_SUCCESS;
1266 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1267 * @hw: pointer to hardware structure
1268 * @offset: offset within the EEPROM to write
1269 * @words: number of word(s)
1270 * @data: 16 bit word(s) to write to EEPROM
1272 * Reads 16 bit word(s) from EEPROM through bit-bang method
1274 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1275 u16 words, u16 *data)
1277 s32 status = IXGBE_SUCCESS;
1280 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
1282 hw->eeprom.ops.init_params(hw);
1285 status = IXGBE_ERR_INVALID_ARGUMENT;
1289 if (offset + words > hw->eeprom.word_size) {
1290 status = IXGBE_ERR_EEPROM;
1295 * The EEPROM page size cannot be queried from the chip. We do lazy
1296 * initialization. It is worth to do that when we write large buffer.
1298 if ((hw->eeprom.word_page_size == 0) &&
1299 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
1300 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1303 * We cannot hold synchronization semaphores for too long
1304 * to avoid other entity starvation. However it is more efficient
1305 * to read in bursts than synchronizing access for each word.
1307 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1308 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1309 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1310 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1313 if (status != IXGBE_SUCCESS)
1322 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1323 * @hw: pointer to hardware structure
1324 * @offset: offset within the EEPROM to be written to
1325 * @words: number of word(s)
1326 * @data: 16 bit word(s) to be written to the EEPROM
1328 * If ixgbe_eeprom_update_checksum is not called after this function, the
1329 * EEPROM will most likely contain an invalid checksum.
1331 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1332 u16 words, u16 *data)
1338 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1340 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1342 /* Prepare the EEPROM for writing */
1343 status = ixgbe_acquire_eeprom(hw);
1345 if (status == IXGBE_SUCCESS) {
1346 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1347 ixgbe_release_eeprom(hw);
1348 status = IXGBE_ERR_EEPROM;
1352 if (status == IXGBE_SUCCESS) {
1353 for (i = 0; i < words; i++) {
1354 ixgbe_standby_eeprom(hw);
1356 /* Send the WRITE ENABLE command (8 bit opcode ) */
1357 ixgbe_shift_out_eeprom_bits(hw,
1358 IXGBE_EEPROM_WREN_OPCODE_SPI,
1359 IXGBE_EEPROM_OPCODE_BITS);
1361 ixgbe_standby_eeprom(hw);
1364 * Some SPI eeproms use the 8th address bit embedded
1367 if ((hw->eeprom.address_bits == 8) &&
1368 ((offset + i) >= 128))
1369 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1371 /* Send the Write command (8-bit opcode + addr) */
1372 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1373 IXGBE_EEPROM_OPCODE_BITS);
1374 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1375 hw->eeprom.address_bits);
1377 page_size = hw->eeprom.word_page_size;
1379 /* Send the data in burst via SPI*/
1382 word = (word >> 8) | (word << 8);
1383 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1388 /* do not wrap around page */
1389 if (((offset + i) & (page_size - 1)) ==
1392 } while (++i < words);
1394 ixgbe_standby_eeprom(hw);
1397 /* Done with writing - release the EEPROM */
1398 ixgbe_release_eeprom(hw);
1405 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1406 * @hw: pointer to hardware structure
1407 * @offset: offset within the EEPROM to be written to
1408 * @data: 16 bit word to be written to the EEPROM
1410 * If ixgbe_eeprom_update_checksum is not called after this function, the
1411 * EEPROM will most likely contain an invalid checksum.
1413 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1417 DEBUGFUNC("ixgbe_write_eeprom_generic");
1419 hw->eeprom.ops.init_params(hw);
1421 if (offset >= hw->eeprom.word_size) {
1422 status = IXGBE_ERR_EEPROM;
1426 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1433 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1434 * @hw: pointer to hardware structure
1435 * @offset: offset within the EEPROM to be read
1436 * @data: read 16 bit words(s) from EEPROM
1437 * @words: number of word(s)
1439 * Reads 16 bit word(s) from EEPROM through bit-bang method
1441 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1442 u16 words, u16 *data)
1444 s32 status = IXGBE_SUCCESS;
1447 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1449 hw->eeprom.ops.init_params(hw);
1452 status = IXGBE_ERR_INVALID_ARGUMENT;
1456 if (offset + words > hw->eeprom.word_size) {
1457 status = IXGBE_ERR_EEPROM;
1462 * We cannot hold synchronization semaphores for too long
1463 * to avoid other entity starvation. However it is more efficient
1464 * to read in bursts than synchronizing access for each word.
1466 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1467 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1468 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1470 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1473 if (status != IXGBE_SUCCESS)
1482 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1483 * @hw: pointer to hardware structure
1484 * @offset: offset within the EEPROM to be read
1485 * @words: number of word(s)
1486 * @data: read 16 bit word(s) from EEPROM
1488 * Reads 16 bit word(s) from EEPROM through bit-bang method
1490 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1491 u16 words, u16 *data)
1495 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1498 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1500 /* Prepare the EEPROM for reading */
1501 status = ixgbe_acquire_eeprom(hw);
1503 if (status == IXGBE_SUCCESS) {
1504 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1505 ixgbe_release_eeprom(hw);
1506 status = IXGBE_ERR_EEPROM;
1510 if (status == IXGBE_SUCCESS) {
1511 for (i = 0; i < words; i++) {
1512 ixgbe_standby_eeprom(hw);
1514 * Some SPI eeproms use the 8th address bit embedded
1517 if ((hw->eeprom.address_bits == 8) &&
1518 ((offset + i) >= 128))
1519 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1521 /* Send the READ command (opcode + addr) */
1522 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1523 IXGBE_EEPROM_OPCODE_BITS);
1524 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1525 hw->eeprom.address_bits);
1527 /* Read the data. */
1528 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1529 data[i] = (word_in >> 8) | (word_in << 8);
1532 /* End this read operation */
1533 ixgbe_release_eeprom(hw);
1540 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1541 * @hw: pointer to hardware structure
1542 * @offset: offset within the EEPROM to be read
1543 * @data: read 16 bit value from EEPROM
1545 * Reads 16 bit value from EEPROM through bit-bang method
1547 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1552 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1554 hw->eeprom.ops.init_params(hw);
1556 if (offset >= hw->eeprom.word_size) {
1557 status = IXGBE_ERR_EEPROM;
1561 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1568 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1569 * @hw: pointer to hardware structure
1570 * @offset: offset of word in the EEPROM to read
1571 * @words: number of word(s)
1572 * @data: 16 bit word(s) from the EEPROM
1574 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1576 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1577 u16 words, u16 *data)
1580 s32 status = IXGBE_SUCCESS;
1583 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1585 hw->eeprom.ops.init_params(hw);
1588 status = IXGBE_ERR_INVALID_ARGUMENT;
1589 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1593 if (offset >= hw->eeprom.word_size) {
1594 status = IXGBE_ERR_EEPROM;
1595 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1599 for (i = 0; i < words; i++) {
1600 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1601 IXGBE_EEPROM_RW_REG_START;
1603 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1604 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1606 if (status == IXGBE_SUCCESS) {
1607 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1608 IXGBE_EEPROM_RW_REG_DATA);
1610 DEBUGOUT("Eeprom read timed out\n");
1619 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1620 * @hw: pointer to hardware structure
1621 * @offset: offset within the EEPROM to be used as a scratch pad
1623 * Discover EEPROM page size by writing marching data at given offset.
1624 * This function is called only when we are writing a new large buffer
1625 * at given offset so the data would be overwritten anyway.
1627 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1630 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1631 s32 status = IXGBE_SUCCESS;
1634 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1636 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1639 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1640 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1641 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1642 hw->eeprom.word_page_size = 0;
1643 if (status != IXGBE_SUCCESS)
1646 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1647 if (status != IXGBE_SUCCESS)
1651 * When writing in burst more than the actual page size
1652 * EEPROM address wraps around current page.
1654 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1656 DEBUGOUT1("Detected EEPROM page size = %d words.",
1657 hw->eeprom.word_page_size);
1663 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1664 * @hw: pointer to hardware structure
1665 * @offset: offset of word in the EEPROM to read
1666 * @data: word read from the EEPROM
1668 * Reads a 16 bit word from the EEPROM using the EERD register.
1670 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1672 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1676 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1677 * @hw: pointer to hardware structure
1678 * @offset: offset of word in the EEPROM to write
1679 * @words: number of word(s)
1680 * @data: word(s) write to the EEPROM
1682 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1684 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1685 u16 words, u16 *data)
1688 s32 status = IXGBE_SUCCESS;
1691 DEBUGFUNC("ixgbe_write_eewr_generic");
1693 hw->eeprom.ops.init_params(hw);
1696 status = IXGBE_ERR_INVALID_ARGUMENT;
1697 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1701 if (offset >= hw->eeprom.word_size) {
1702 status = IXGBE_ERR_EEPROM;
1703 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1707 for (i = 0; i < words; i++) {
1708 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1709 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1710 IXGBE_EEPROM_RW_REG_START;
1712 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1713 if (status != IXGBE_SUCCESS) {
1714 DEBUGOUT("Eeprom write EEWR timed out\n");
1718 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1720 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1721 if (status != IXGBE_SUCCESS) {
1722 DEBUGOUT("Eeprom write EEWR timed out\n");
1732 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1733 * @hw: pointer to hardware structure
1734 * @offset: offset of word in the EEPROM to write
1735 * @data: word write to the EEPROM
1737 * Write a 16 bit word to the EEPROM using the EEWR register.
1739 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1741 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1745 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1746 * @hw: pointer to hardware structure
1747 * @ee_reg: EEPROM flag for polling
1749 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1750 * read or write is done respectively.
1752 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1756 s32 status = IXGBE_ERR_EEPROM;
1758 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1760 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1761 if (ee_reg == IXGBE_NVM_POLL_READ)
1762 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1764 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1766 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1767 status = IXGBE_SUCCESS;
1773 if (i == IXGBE_EERD_EEWR_ATTEMPTS)
1774 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1775 "EEPROM read/write done polling timed out");
1781 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1782 * @hw: pointer to hardware structure
1784 * Prepares EEPROM for access using bit-bang method. This function should
1785 * be called before issuing a command to the EEPROM.
1787 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1789 s32 status = IXGBE_SUCCESS;
1793 DEBUGFUNC("ixgbe_acquire_eeprom");
1795 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1797 status = IXGBE_ERR_SWFW_SYNC;
1799 if (status == IXGBE_SUCCESS) {
1800 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1802 /* Request EEPROM Access */
1803 eec |= IXGBE_EEC_REQ;
1804 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1806 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1807 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1808 if (eec & IXGBE_EEC_GNT)
1813 /* Release if grant not acquired */
1814 if (!(eec & IXGBE_EEC_GNT)) {
1815 eec &= ~IXGBE_EEC_REQ;
1816 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1817 DEBUGOUT("Could not acquire EEPROM grant\n");
1819 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1820 status = IXGBE_ERR_EEPROM;
1823 /* Setup EEPROM for Read/Write */
1824 if (status == IXGBE_SUCCESS) {
1825 /* Clear CS and SK */
1826 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1827 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1828 IXGBE_WRITE_FLUSH(hw);
1836 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1837 * @hw: pointer to hardware structure
1839 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1841 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1843 s32 status = IXGBE_ERR_EEPROM;
1848 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1851 /* Get SMBI software semaphore between device drivers first */
1852 for (i = 0; i < timeout; i++) {
1854 * If the SMBI bit is 0 when we read it, then the bit will be
1855 * set and we have the semaphore
1857 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1858 if (!(swsm & IXGBE_SWSM_SMBI)) {
1859 status = IXGBE_SUCCESS;
1866 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1869 * this release is particularly important because our attempts
1870 * above to get the semaphore may have succeeded, and if there
1871 * was a timeout, we should unconditionally clear the semaphore
1872 * bits to free the driver to make progress
1874 ixgbe_release_eeprom_semaphore(hw);
1879 * If the SMBI bit is 0 when we read it, then the bit will be
1880 * set and we have the semaphore
1882 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1883 if (!(swsm & IXGBE_SWSM_SMBI))
1884 status = IXGBE_SUCCESS;
1887 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1888 if (status == IXGBE_SUCCESS) {
1889 for (i = 0; i < timeout; i++) {
1890 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1892 /* Set the SW EEPROM semaphore bit to request access */
1893 swsm |= IXGBE_SWSM_SWESMBI;
1894 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
1897 * If we set the bit successfully then we got the
1900 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1901 if (swsm & IXGBE_SWSM_SWESMBI)
1908 * Release semaphores and return error if SW EEPROM semaphore
1909 * was not granted because we don't have access to the EEPROM
1912 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1913 "SWESMBI Software EEPROM semaphore not granted.\n");
1914 ixgbe_release_eeprom_semaphore(hw);
1915 status = IXGBE_ERR_EEPROM;
1918 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1919 "Software semaphore SMBI between device drivers "
1927 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1928 * @hw: pointer to hardware structure
1930 * This function clears hardware semaphore bits.
1932 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1936 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1938 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1940 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1941 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1942 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1943 IXGBE_WRITE_FLUSH(hw);
1947 * ixgbe_ready_eeprom - Polls for EEPROM ready
1948 * @hw: pointer to hardware structure
1950 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1952 s32 status = IXGBE_SUCCESS;
1956 DEBUGFUNC("ixgbe_ready_eeprom");
1959 * Read "Status Register" repeatedly until the LSB is cleared. The
1960 * EEPROM will signal that the command has been completed by clearing
1961 * bit 0 of the internal status register. If it's not cleared within
1962 * 5 milliseconds, then error out.
1964 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1965 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1966 IXGBE_EEPROM_OPCODE_BITS);
1967 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1968 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1972 ixgbe_standby_eeprom(hw);
1976 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1977 * devices (and only 0-5mSec on 5V devices)
1979 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1980 DEBUGOUT("SPI EEPROM Status error\n");
1981 status = IXGBE_ERR_EEPROM;
1988 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1989 * @hw: pointer to hardware structure
1991 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1995 DEBUGFUNC("ixgbe_standby_eeprom");
1997 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1999 /* Toggle CS to flush commands */
2000 eec |= IXGBE_EEC_CS;
2001 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2002 IXGBE_WRITE_FLUSH(hw);
2004 eec &= ~IXGBE_EEC_CS;
2005 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2006 IXGBE_WRITE_FLUSH(hw);
2011 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
2012 * @hw: pointer to hardware structure
2013 * @data: data to send to the EEPROM
2014 * @count: number of bits to shift out
2016 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
2023 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
2025 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2028 * Mask is used to shift "count" bits of "data" out to the EEPROM
2029 * one bit at a time. Determine the starting bit based on count
2031 mask = 0x01 << (count - 1);
2033 for (i = 0; i < count; i++) {
2035 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
2036 * "1", and then raising and then lowering the clock (the SK
2037 * bit controls the clock input to the EEPROM). A "0" is
2038 * shifted out to the EEPROM by setting "DI" to "0" and then
2039 * raising and then lowering the clock.
2042 eec |= IXGBE_EEC_DI;
2044 eec &= ~IXGBE_EEC_DI;
2046 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2047 IXGBE_WRITE_FLUSH(hw);
2051 ixgbe_raise_eeprom_clk(hw, &eec);
2052 ixgbe_lower_eeprom_clk(hw, &eec);
2055 * Shift mask to signify next bit of data to shift in to the
2061 /* We leave the "DI" bit set to "0" when we leave this routine. */
2062 eec &= ~IXGBE_EEC_DI;
2063 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2064 IXGBE_WRITE_FLUSH(hw);
2068 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
2069 * @hw: pointer to hardware structure
2070 * @count: number of bits to shift
2072 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
2078 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
2081 * In order to read a register from the EEPROM, we need to shift
2082 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
2083 * the clock input to the EEPROM (setting the SK bit), and then reading
2084 * the value of the "DO" bit. During this "shifting in" process the
2085 * "DI" bit should always be clear.
2087 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2089 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
2091 for (i = 0; i < count; i++) {
2093 ixgbe_raise_eeprom_clk(hw, &eec);
2095 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2097 eec &= ~(IXGBE_EEC_DI);
2098 if (eec & IXGBE_EEC_DO)
2101 ixgbe_lower_eeprom_clk(hw, &eec);
2108 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
2109 * @hw: pointer to hardware structure
2110 * @eec: EEC register's current value
2112 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2114 DEBUGFUNC("ixgbe_raise_eeprom_clk");
2117 * Raise the clock input to the EEPROM
2118 * (setting the SK bit), then delay
2120 *eec = *eec | IXGBE_EEC_SK;
2121 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2122 IXGBE_WRITE_FLUSH(hw);
2127 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2128 * @hw: pointer to hardware structure
2129 * @eec: EEC's current value
2131 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2133 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2136 * Lower the clock input to the EEPROM (clearing the SK bit), then
2139 *eec = *eec & ~IXGBE_EEC_SK;
2140 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2141 IXGBE_WRITE_FLUSH(hw);
2146 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2147 * @hw: pointer to hardware structure
2149 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2153 DEBUGFUNC("ixgbe_release_eeprom");
2155 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2157 eec |= IXGBE_EEC_CS; /* Pull CS high */
2158 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
2160 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2161 IXGBE_WRITE_FLUSH(hw);
2165 /* Stop requesting EEPROM access */
2166 eec &= ~IXGBE_EEC_REQ;
2167 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2169 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2171 /* Delay before attempt to obtain semaphore again to allow FW access */
2172 msec_delay(hw->eeprom.semaphore_delay);
2176 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2177 * @hw: pointer to hardware structure
2179 * Returns a negative error code on error, or the 16-bit checksum
2181 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2190 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
2192 /* Include 0x0-0x3F in the checksum */
2193 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
2194 if (hw->eeprom.ops.read(hw, i, &word)) {
2195 DEBUGOUT("EEPROM read failed\n");
2196 return IXGBE_ERR_EEPROM;
2201 /* Include all data from pointers except for the fw pointer */
2202 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
2203 if (hw->eeprom.ops.read(hw, i, &pointer)) {
2204 DEBUGOUT("EEPROM read failed\n");
2205 return IXGBE_ERR_EEPROM;
2208 /* If the pointer seems invalid */
2209 if (pointer == 0xFFFF || pointer == 0)
2212 if (hw->eeprom.ops.read(hw, pointer, &length)) {
2213 DEBUGOUT("EEPROM read failed\n");
2214 return IXGBE_ERR_EEPROM;
2217 if (length == 0xFFFF || length == 0)
2220 for (j = pointer + 1; j <= pointer + length; j++) {
2221 if (hw->eeprom.ops.read(hw, j, &word)) {
2222 DEBUGOUT("EEPROM read failed\n");
2223 return IXGBE_ERR_EEPROM;
2229 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2231 return (s32)checksum;
2235 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2236 * @hw: pointer to hardware structure
2237 * @checksum_val: calculated checksum
2239 * Performs checksum calculation and validates the EEPROM checksum. If the
2240 * caller does not need checksum_val, the value can be NULL.
2242 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2247 u16 read_checksum = 0;
2249 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
2251 /* Read the first word from the EEPROM. If this times out or fails, do
2252 * not continue or we could be in for a very long wait while every
2255 status = hw->eeprom.ops.read(hw, 0, &checksum);
2257 DEBUGOUT("EEPROM read failed\n");
2261 status = hw->eeprom.ops.calc_checksum(hw);
2265 checksum = (u16)(status & 0xffff);
2267 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2269 DEBUGOUT("EEPROM read failed\n");
2273 /* Verify read checksum from EEPROM is the same as
2274 * calculated checksum
2276 if (read_checksum != checksum)
2277 status = IXGBE_ERR_EEPROM_CHECKSUM;
2279 /* If the user cares, return the calculated checksum */
2281 *checksum_val = checksum;
2287 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2288 * @hw: pointer to hardware structure
2290 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2295 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
2297 /* Read the first word from the EEPROM. If this times out or fails, do
2298 * not continue or we could be in for a very long wait while every
2301 status = hw->eeprom.ops.read(hw, 0, &checksum);
2303 DEBUGOUT("EEPROM read failed\n");
2307 status = hw->eeprom.ops.calc_checksum(hw);
2311 checksum = (u16)(status & 0xffff);
2313 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
2319 * ixgbe_validate_mac_addr - Validate MAC address
2320 * @mac_addr: pointer to MAC address.
2322 * Tests a MAC address to ensure it is a valid Individual Address.
2324 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
2326 s32 status = IXGBE_SUCCESS;
2328 DEBUGFUNC("ixgbe_validate_mac_addr");
2330 /* Make sure it is not a multicast address */
2331 if (IXGBE_IS_MULTICAST(mac_addr)) {
2332 status = IXGBE_ERR_INVALID_MAC_ADDR;
2333 /* Not a broadcast address */
2334 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
2335 status = IXGBE_ERR_INVALID_MAC_ADDR;
2336 /* Reject the zero address */
2337 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
2338 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
2339 status = IXGBE_ERR_INVALID_MAC_ADDR;
2345 * ixgbe_set_rar_generic - Set Rx address register
2346 * @hw: pointer to hardware structure
2347 * @index: Receive address register to write
2348 * @addr: Address to put into receive address register
2349 * @vmdq: VMDq "set" or "pool" index
2350 * @enable_addr: set flag that address is active
2352 * Puts an ethernet address into a receive address register.
2354 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2357 u32 rar_low, rar_high;
2358 u32 rar_entries = hw->mac.num_rar_entries;
2360 DEBUGFUNC("ixgbe_set_rar_generic");
2362 /* Make sure we are using a valid rar index range */
2363 if (index >= rar_entries) {
2364 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2365 "RAR index %d is out of range.\n", index);
2366 return IXGBE_ERR_INVALID_ARGUMENT;
2369 /* setup VMDq pool selection before this RAR gets enabled */
2370 hw->mac.ops.set_vmdq(hw, index, vmdq);
2373 * HW expects these in little endian so we reverse the byte
2374 * order from network order (big endian) to little endian
2376 rar_low = ((u32)addr[0] |
2377 ((u32)addr[1] << 8) |
2378 ((u32)addr[2] << 16) |
2379 ((u32)addr[3] << 24));
2381 * Some parts put the VMDq setting in the extra RAH bits,
2382 * so save everything except the lower 16 bits that hold part
2383 * of the address and the address valid bit.
2385 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2386 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2387 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2389 if (enable_addr != 0)
2390 rar_high |= IXGBE_RAH_AV;
2392 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2393 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2395 return IXGBE_SUCCESS;
2399 * ixgbe_clear_rar_generic - Remove Rx address register
2400 * @hw: pointer to hardware structure
2401 * @index: Receive address register to write
2403 * Clears an ethernet address from a receive address register.
2405 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2408 u32 rar_entries = hw->mac.num_rar_entries;
2410 DEBUGFUNC("ixgbe_clear_rar_generic");
2412 /* Make sure we are using a valid rar index range */
2413 if (index >= rar_entries) {
2414 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2415 "RAR index %d is out of range.\n", index);
2416 return IXGBE_ERR_INVALID_ARGUMENT;
2420 * Some parts put the VMDq setting in the extra RAH bits,
2421 * so save everything except the lower 16 bits that hold part
2422 * of the address and the address valid bit.
2424 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2425 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2427 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2428 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2430 /* clear VMDq pool/queue selection for this RAR */
2431 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2433 return IXGBE_SUCCESS;
2437 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2438 * @hw: pointer to hardware structure
2440 * Places the MAC address in receive address register 0 and clears the rest
2441 * of the receive address registers. Clears the multicast table. Assumes
2442 * the receiver is in reset when the routine is called.
2444 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2447 u32 rar_entries = hw->mac.num_rar_entries;
2449 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2452 * If the current mac address is valid, assume it is a software override
2453 * to the permanent address.
2454 * Otherwise, use the permanent address from the eeprom.
2456 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2457 IXGBE_ERR_INVALID_MAC_ADDR) {
2458 /* Get the MAC address from the RAR0 for later reference */
2459 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2461 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2462 hw->mac.addr[0], hw->mac.addr[1],
2464 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2465 hw->mac.addr[4], hw->mac.addr[5]);
2467 /* Setup the receive address. */
2468 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2469 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2470 hw->mac.addr[0], hw->mac.addr[1],
2472 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2473 hw->mac.addr[4], hw->mac.addr[5]);
2475 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2478 /* clear VMDq pool/queue selection for RAR 0 */
2479 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2481 hw->addr_ctrl.overflow_promisc = 0;
2483 hw->addr_ctrl.rar_used_count = 1;
2485 /* Zero out the other receive addresses. */
2486 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2487 for (i = 1; i < rar_entries; i++) {
2488 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2489 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2493 hw->addr_ctrl.mta_in_use = 0;
2494 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2496 DEBUGOUT(" Clearing MTA\n");
2497 for (i = 0; i < hw->mac.mcft_size; i++)
2498 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2500 ixgbe_init_uta_tables(hw);
2502 return IXGBE_SUCCESS;
2506 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2507 * @hw: pointer to hardware structure
2508 * @addr: new address
2509 * @vmdq: VMDq "set" or "pool" index
2511 * Adds it to unused receive address register or goes into promiscuous mode.
2513 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2515 u32 rar_entries = hw->mac.num_rar_entries;
2518 DEBUGFUNC("ixgbe_add_uc_addr");
2520 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2521 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2524 * Place this address in the RAR if there is room,
2525 * else put the controller into promiscuous mode
2527 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2528 rar = hw->addr_ctrl.rar_used_count;
2529 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2530 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2531 hw->addr_ctrl.rar_used_count++;
2533 hw->addr_ctrl.overflow_promisc++;
2536 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2540 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2541 * @hw: pointer to hardware structure
2542 * @addr_list: the list of new addresses
2543 * @addr_count: number of addresses
2544 * @next: iterator function to walk the address list
2546 * The given list replaces any existing list. Clears the secondary addrs from
2547 * receive address registers. Uses unused receive address registers for the
2548 * first secondary addresses, and falls back to promiscuous mode as needed.
2550 * Drivers using secondary unicast addresses must set user_set_promisc when
2551 * manually putting the device into promiscuous mode.
2553 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2554 u32 addr_count, ixgbe_mc_addr_itr next)
2558 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2563 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2566 * Clear accounting of old secondary address list,
2567 * don't count RAR[0]
2569 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2570 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2571 hw->addr_ctrl.overflow_promisc = 0;
2573 /* Zero out the other receive addresses */
2574 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2575 for (i = 0; i < uc_addr_in_use; i++) {
2576 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2577 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2580 /* Add the new addresses */
2581 for (i = 0; i < addr_count; i++) {
2582 DEBUGOUT(" Adding the secondary addresses:\n");
2583 addr = next(hw, &addr_list, &vmdq);
2584 ixgbe_add_uc_addr(hw, addr, vmdq);
2587 if (hw->addr_ctrl.overflow_promisc) {
2588 /* enable promisc if not already in overflow or set by user */
2589 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2590 DEBUGOUT(" Entering address overflow promisc mode\n");
2591 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2592 fctrl |= IXGBE_FCTRL_UPE;
2593 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2596 /* only disable if set by overflow, not by user */
2597 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2598 DEBUGOUT(" Leaving address overflow promisc mode\n");
2599 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2600 fctrl &= ~IXGBE_FCTRL_UPE;
2601 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2605 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2606 return IXGBE_SUCCESS;
2610 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2611 * @hw: pointer to hardware structure
2612 * @mc_addr: the multicast address
2614 * Extracts the 12 bits, from a multicast address, to determine which
2615 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2616 * incoming rx multicast addresses, to determine the bit-vector to check in
2617 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2618 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2619 * to mc_filter_type.
2621 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2625 DEBUGFUNC("ixgbe_mta_vector");
2627 switch (hw->mac.mc_filter_type) {
2628 case 0: /* use bits [47:36] of the address */
2629 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2631 case 1: /* use bits [46:35] of the address */
2632 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2634 case 2: /* use bits [45:34] of the address */
2635 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2637 case 3: /* use bits [43:32] of the address */
2638 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2640 default: /* Invalid mc_filter_type */
2641 DEBUGOUT("MC filter type param set incorrectly\n");
2646 /* vector can only be 12-bits or boundary will be exceeded */
2652 * ixgbe_set_mta - Set bit-vector in multicast table
2653 * @hw: pointer to hardware structure
2654 * @mc_addr: Multicast address
2656 * Sets the bit-vector in the multicast table.
2658 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2664 DEBUGFUNC("ixgbe_set_mta");
2666 hw->addr_ctrl.mta_in_use++;
2668 vector = ixgbe_mta_vector(hw, mc_addr);
2669 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2672 * The MTA is a register array of 128 32-bit registers. It is treated
2673 * like an array of 4096 bits. We want to set bit
2674 * BitArray[vector_value]. So we figure out what register the bit is
2675 * in, read it, OR in the new bit, then write back the new value. The
2676 * register is determined by the upper 7 bits of the vector value and
2677 * the bit within that register are determined by the lower 5 bits of
2680 vector_reg = (vector >> 5) & 0x7F;
2681 vector_bit = vector & 0x1F;
2682 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2686 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2687 * @hw: pointer to hardware structure
2688 * @mc_addr_list: the list of new multicast addresses
2689 * @mc_addr_count: number of addresses
2690 * @next: iterator function to walk the multicast address list
2691 * @clear: flag, when set clears the table beforehand
2693 * When the clear flag is set, the given list replaces any existing list.
2694 * Hashes the given addresses into the multicast table.
2696 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2697 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2703 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2706 * Set the new number of MC addresses that we are being requested to
2709 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2710 hw->addr_ctrl.mta_in_use = 0;
2712 /* Clear mta_shadow */
2714 DEBUGOUT(" Clearing MTA\n");
2715 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2718 /* Update mta_shadow */
2719 for (i = 0; i < mc_addr_count; i++) {
2720 DEBUGOUT(" Adding the multicast addresses:\n");
2721 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2725 for (i = 0; i < hw->mac.mcft_size; i++)
2726 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2727 hw->mac.mta_shadow[i]);
2729 if (hw->addr_ctrl.mta_in_use > 0)
2730 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2731 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2733 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2734 return IXGBE_SUCCESS;
2738 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2739 * @hw: pointer to hardware structure
2741 * Enables multicast address in RAR and the use of the multicast hash table.
2743 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2745 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2747 DEBUGFUNC("ixgbe_enable_mc_generic");
2749 if (a->mta_in_use > 0)
2750 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2751 hw->mac.mc_filter_type);
2753 return IXGBE_SUCCESS;
2757 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2758 * @hw: pointer to hardware structure
2760 * Disables multicast address in RAR and the use of the multicast hash table.
2762 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2764 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2766 DEBUGFUNC("ixgbe_disable_mc_generic");
2768 if (a->mta_in_use > 0)
2769 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2771 return IXGBE_SUCCESS;
2775 * ixgbe_fc_enable_generic - Enable flow control
2776 * @hw: pointer to hardware structure
2778 * Enable flow control according to the current settings.
2780 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2782 s32 ret_val = IXGBE_SUCCESS;
2783 u32 mflcn_reg, fccfg_reg;
2788 DEBUGFUNC("ixgbe_fc_enable_generic");
2790 /* Validate the water mark configuration */
2791 if (!hw->fc.pause_time) {
2792 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2796 /* Low water mark of zero causes XOFF floods */
2797 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2798 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2799 hw->fc.high_water[i]) {
2800 if (!hw->fc.low_water[i] ||
2801 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2802 DEBUGOUT("Invalid water mark configuration\n");
2803 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2809 /* Negotiate the fc mode to use */
2810 hw->mac.ops.fc_autoneg(hw);
2812 /* Disable any previous flow control settings */
2813 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2814 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2816 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2817 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2820 * The possible values of fc.current_mode are:
2821 * 0: Flow control is completely disabled
2822 * 1: Rx flow control is enabled (we can receive pause frames,
2823 * but not send pause frames).
2824 * 2: Tx flow control is enabled (we can send pause frames but
2825 * we do not support receiving pause frames).
2826 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2829 switch (hw->fc.current_mode) {
2832 * Flow control is disabled by software override or autoneg.
2833 * The code below will actually disable it in the HW.
2836 case ixgbe_fc_rx_pause:
2838 * Rx Flow control is enabled and Tx Flow control is
2839 * disabled by software override. Since there really
2840 * isn't a way to advertise that we are capable of RX
2841 * Pause ONLY, we will advertise that we support both
2842 * symmetric and asymmetric Rx PAUSE. Later, we will
2843 * disable the adapter's ability to send PAUSE frames.
2845 mflcn_reg |= IXGBE_MFLCN_RFCE;
2847 case ixgbe_fc_tx_pause:
2849 * Tx Flow control is enabled, and Rx Flow control is
2850 * disabled by software override.
2852 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2855 /* Flow control (both Rx and Tx) is enabled by SW override. */
2856 mflcn_reg |= IXGBE_MFLCN_RFCE;
2857 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2860 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2861 "Flow control param set incorrectly\n");
2862 ret_val = IXGBE_ERR_CONFIG;
2867 /* Set 802.3x based flow control settings. */
2868 mflcn_reg |= IXGBE_MFLCN_DPF;
2869 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2870 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2873 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2874 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2875 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2876 hw->fc.high_water[i]) {
2877 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2878 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2879 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2881 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2883 * In order to prevent Tx hangs when the internal Tx
2884 * switch is enabled we must set the high water mark
2885 * to the Rx packet buffer size - 24KB. This allows
2886 * the Tx switch to function even under heavy Rx
2889 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2892 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2895 /* Configure pause time (2 TCs per register) */
2896 reg = hw->fc.pause_time * 0x00010001;
2897 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2898 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2900 /* Configure flow control refresh threshold value */
2901 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2908 * ixgbe_negotiate_fc - Negotiate flow control
2909 * @hw: pointer to hardware structure
2910 * @adv_reg: flow control advertised settings
2911 * @lp_reg: link partner's flow control settings
2912 * @adv_sym: symmetric pause bit in advertisement
2913 * @adv_asm: asymmetric pause bit in advertisement
2914 * @lp_sym: symmetric pause bit in link partner advertisement
2915 * @lp_asm: asymmetric pause bit in link partner advertisement
2917 * Find the intersection between advertised settings and link partner's
2918 * advertised settings
2920 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2921 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2923 if ((!(adv_reg)) || (!(lp_reg))) {
2924 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
2925 "Local or link partner's advertised flow control "
2926 "settings are NULL. Local: %x, link partner: %x\n",
2928 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2931 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2933 * Now we need to check if the user selected Rx ONLY
2934 * of pause frames. In this case, we had to advertise
2935 * FULL flow control because we could not advertise RX
2936 * ONLY. Hence, we must now check to see if we need to
2937 * turn OFF the TRANSMISSION of PAUSE frames.
2939 if (hw->fc.requested_mode == ixgbe_fc_full) {
2940 hw->fc.current_mode = ixgbe_fc_full;
2941 DEBUGOUT("Flow Control = FULL.\n");
2943 hw->fc.current_mode = ixgbe_fc_rx_pause;
2944 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2946 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2947 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2948 hw->fc.current_mode = ixgbe_fc_tx_pause;
2949 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2950 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2951 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2952 hw->fc.current_mode = ixgbe_fc_rx_pause;
2953 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2955 hw->fc.current_mode = ixgbe_fc_none;
2956 DEBUGOUT("Flow Control = NONE.\n");
2958 return IXGBE_SUCCESS;
2962 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2963 * @hw: pointer to hardware structure
2965 * Enable flow control according on 1 gig fiber.
2967 STATIC s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2969 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2970 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2973 * On multispeed fiber at 1g, bail out if
2974 * - link is up but AN did not complete, or if
2975 * - link is up and AN completed but timed out
2978 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2979 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2980 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
2981 DEBUGOUT("Auto-Negotiation did not complete or timed out\n");
2985 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2986 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2988 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2989 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2990 IXGBE_PCS1GANA_ASM_PAUSE,
2991 IXGBE_PCS1GANA_SYM_PAUSE,
2992 IXGBE_PCS1GANA_ASM_PAUSE);
2999 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
3000 * @hw: pointer to hardware structure
3002 * Enable flow control according to IEEE clause 37.
3004 STATIC s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
3006 u32 links2, anlp1_reg, autoc_reg, links;
3007 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3010 * On backplane, bail out if
3011 * - backplane autoneg was not completed, or if
3012 * - we are 82599 and link partner is not AN enabled
3014 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
3015 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
3016 DEBUGOUT("Auto-Negotiation did not complete\n");
3020 if (hw->mac.type == ixgbe_mac_82599EB) {
3021 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
3022 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
3023 DEBUGOUT("Link partner is not AN enabled\n");
3028 * Read the 10g AN autoc and LP ability registers and resolve
3029 * local flow control settings accordingly
3031 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3032 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
3034 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
3035 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
3036 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
3043 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
3044 * @hw: pointer to hardware structure
3046 * Enable flow control according to IEEE clause 37.
3048 STATIC s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
3050 u16 technology_ability_reg = 0;
3051 u16 lp_technology_ability_reg = 0;
3053 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
3054 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3055 &technology_ability_reg);
3056 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
3057 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3058 &lp_technology_ability_reg);
3060 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
3061 (u32)lp_technology_ability_reg,
3062 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
3063 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
3067 * ixgbe_fc_autoneg - Configure flow control
3068 * @hw: pointer to hardware structure
3070 * Compares our advertised flow control capabilities to those advertised by
3071 * our link partner, and determines the proper flow control mode to use.
3073 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
3075 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3076 ixgbe_link_speed speed;
3079 DEBUGFUNC("ixgbe_fc_autoneg");
3082 * AN should have completed when the cable was plugged in.
3083 * Look for reasons to bail out. Bail out if:
3084 * - FC autoneg is disabled, or if
3087 if (hw->fc.disable_fc_autoneg) {
3088 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3089 "Flow control autoneg is disabled");
3093 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3095 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3099 switch (hw->phy.media_type) {
3100 /* Autoneg flow control on fiber adapters */
3101 case ixgbe_media_type_fiber_fixed:
3102 case ixgbe_media_type_fiber_qsfp:
3103 case ixgbe_media_type_fiber:
3104 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
3105 ret_val = ixgbe_fc_autoneg_fiber(hw);
3108 /* Autoneg flow control on backplane adapters */
3109 case ixgbe_media_type_backplane:
3110 ret_val = ixgbe_fc_autoneg_backplane(hw);
3113 /* Autoneg flow control on copper adapters */
3114 case ixgbe_media_type_copper:
3115 if (ixgbe_device_supports_autoneg_fc(hw))
3116 ret_val = ixgbe_fc_autoneg_copper(hw);
3124 if (ret_val == IXGBE_SUCCESS) {
3125 hw->fc.fc_was_autonegged = true;
3127 hw->fc.fc_was_autonegged = false;
3128 hw->fc.current_mode = hw->fc.requested_mode;
3133 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3134 * @hw: pointer to hardware structure
3136 * System-wide timeout range is encoded in PCIe Device Control2 register.
3138 * Add 10% to specified maximum and return the number of times to poll for
3139 * completion timeout, in units of 100 microsec. Never return less than
3140 * 800 = 80 millisec.
3142 STATIC u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3147 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3148 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
3151 case IXGBE_PCIDEVCTRL2_65_130ms:
3152 pollcnt = 1300; /* 130 millisec */
3154 case IXGBE_PCIDEVCTRL2_260_520ms:
3155 pollcnt = 5200; /* 520 millisec */
3157 case IXGBE_PCIDEVCTRL2_1_2s:
3158 pollcnt = 20000; /* 2 sec */
3160 case IXGBE_PCIDEVCTRL2_4_8s:
3161 pollcnt = 80000; /* 8 sec */
3163 case IXGBE_PCIDEVCTRL2_17_34s:
3164 pollcnt = 34000; /* 34 sec */
3166 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
3167 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
3168 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
3169 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
3171 pollcnt = 800; /* 80 millisec minimum */
3175 /* add 10% to spec maximum */
3176 return (pollcnt * 11) / 10;
3180 * ixgbe_disable_pcie_master - Disable PCI-express master access
3181 * @hw: pointer to hardware structure
3183 * Disables PCI-Express master access and verifies there are no pending
3184 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
3185 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
3186 * is returned signifying master requests disabled.
3188 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
3190 s32 status = IXGBE_SUCCESS;
3194 DEBUGFUNC("ixgbe_disable_pcie_master");
3196 /* Always set this bit to ensure any future transactions are blocked */
3197 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3199 /* Exit if master requests are blocked */
3200 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3201 IXGBE_REMOVED(hw->hw_addr))
3204 /* Poll for master request bit to clear */
3205 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
3207 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3212 * Two consecutive resets are required via CTRL.RST per datasheet
3213 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
3214 * of this need. The first reset prevents new master requests from
3215 * being issued by our device. We then must wait 1usec or more for any
3216 * remaining completions from the PCIe bus to trickle in, and then reset
3217 * again to clear out any effects they may have had on our device.
3219 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
3220 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3222 if (hw->mac.type >= ixgbe_mac_X550)
3226 * Before proceeding, make sure that the PCIe block does not have
3227 * transactions pending.
3229 poll = ixgbe_pcie_timeout_poll(hw);
3230 for (i = 0; i < poll; i++) {
3232 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3233 if (IXGBE_REMOVED(hw->hw_addr))
3235 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3239 ERROR_REPORT1(IXGBE_ERROR_POLLING,
3240 "PCIe transaction pending bit also did not clear.\n");
3241 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
3248 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3249 * @hw: pointer to hardware structure
3250 * @mask: Mask to specify which semaphore to acquire
3252 * Acquires the SWFW semaphore through the GSSR register for the specified
3253 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3255 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3259 u32 fwmask = mask << 5;
3263 DEBUGFUNC("ixgbe_acquire_swfw_sync");
3265 for (i = 0; i < timeout; i++) {
3267 * SW NVM semaphore bit is used for access to all
3268 * SW_FW_SYNC bits (not just NVM)
3270 if (ixgbe_get_eeprom_semaphore(hw))
3271 return IXGBE_ERR_SWFW_SYNC;
3273 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3274 if (!(gssr & (fwmask | swmask))) {
3276 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3277 ixgbe_release_eeprom_semaphore(hw);
3278 return IXGBE_SUCCESS;
3280 /* Resource is currently in use by FW or SW */
3281 ixgbe_release_eeprom_semaphore(hw);
3286 /* If time expired clear the bits holding the lock and retry */
3287 if (gssr & (fwmask | swmask))
3288 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
3291 return IXGBE_ERR_SWFW_SYNC;
3295 * ixgbe_release_swfw_sync - Release SWFW semaphore
3296 * @hw: pointer to hardware structure
3297 * @mask: Mask to specify which semaphore to release
3299 * Releases the SWFW semaphore through the GSSR register for the specified
3300 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3302 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3307 DEBUGFUNC("ixgbe_release_swfw_sync");
3309 ixgbe_get_eeprom_semaphore(hw);
3311 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3313 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3315 ixgbe_release_eeprom_semaphore(hw);
3319 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3320 * @hw: pointer to hardware structure
3322 * Stops the receive data path and waits for the HW to internally empty
3323 * the Rx security block
3325 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3327 #define IXGBE_MAX_SECRX_POLL 4000
3332 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
3335 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3336 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
3337 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3338 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
3339 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3340 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
3343 /* Use interrupt-safe sleep just in case */
3347 /* For informational purposes only */
3348 if (i >= IXGBE_MAX_SECRX_POLL)
3349 DEBUGOUT("Rx unit being enabled before security "
3350 "path fully disabled. Continuing with init.\n");
3352 return IXGBE_SUCCESS;
3356 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3357 * @hw: pointer to hardware structure
3358 * @locked: bool to indicate whether the SW/FW lock was taken
3359 * @reg_val: Value we read from AUTOC
3361 * The default case requires no protection so just to the register read.
3363 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3366 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3367 return IXGBE_SUCCESS;
3371 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
3372 * @hw: pointer to hardware structure
3373 * @reg_val: value to write to AUTOC
3374 * @locked: bool to indicate whether the SW/FW lock was already taken by
3377 * The default case requires no protection so just to the register write.
3379 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
3381 UNREFERENCED_1PARAMETER(locked);
3383 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
3384 return IXGBE_SUCCESS;
3388 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3389 * @hw: pointer to hardware structure
3391 * Enables the receive data path.
3393 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3397 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
3399 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3400 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
3401 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3402 IXGBE_WRITE_FLUSH(hw);
3404 return IXGBE_SUCCESS;
3408 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3409 * @hw: pointer to hardware structure
3410 * @regval: register value to write to RXCTRL
3412 * Enables the Rx DMA unit
3414 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3416 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
3418 if (regval & IXGBE_RXCTRL_RXEN)
3419 ixgbe_enable_rx(hw);
3421 ixgbe_disable_rx(hw);
3423 return IXGBE_SUCCESS;
3427 * ixgbe_blink_led_start_generic - Blink LED based on index.
3428 * @hw: pointer to hardware structure
3429 * @index: led number to blink
3431 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3433 ixgbe_link_speed speed = 0;
3436 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3437 s32 ret_val = IXGBE_SUCCESS;
3438 bool locked = false;
3440 DEBUGFUNC("ixgbe_blink_led_start_generic");
3443 return IXGBE_ERR_PARAM;
3446 * Link must be up to auto-blink the LEDs;
3447 * Force it if link is down.
3449 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3452 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3453 if (ret_val != IXGBE_SUCCESS)
3456 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3457 autoc_reg |= IXGBE_AUTOC_FLU;
3459 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3460 if (ret_val != IXGBE_SUCCESS)
3463 IXGBE_WRITE_FLUSH(hw);
3467 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3468 led_reg |= IXGBE_LED_BLINK(index);
3469 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3470 IXGBE_WRITE_FLUSH(hw);
3477 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3478 * @hw: pointer to hardware structure
3479 * @index: led number to stop blinking
3481 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3484 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3485 s32 ret_val = IXGBE_SUCCESS;
3486 bool locked = false;
3488 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3491 return IXGBE_ERR_PARAM;
3494 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3495 if (ret_val != IXGBE_SUCCESS)
3498 autoc_reg &= ~IXGBE_AUTOC_FLU;
3499 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3501 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3502 if (ret_val != IXGBE_SUCCESS)
3505 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3506 led_reg &= ~IXGBE_LED_BLINK(index);
3507 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3508 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3509 IXGBE_WRITE_FLUSH(hw);
3516 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3517 * @hw: pointer to hardware structure
3518 * @san_mac_offset: SAN MAC address offset
3520 * This function will read the EEPROM location for the SAN MAC address
3521 * pointer, and returns the value at that location. This is used in both
3522 * get and set mac_addr routines.
3524 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3525 u16 *san_mac_offset)
3529 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3532 * First read the EEPROM pointer to see if the MAC addresses are
3535 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3538 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3539 "eeprom at offset %d failed",
3540 IXGBE_SAN_MAC_ADDR_PTR);
3547 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3548 * @hw: pointer to hardware structure
3549 * @san_mac_addr: SAN MAC address
3551 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3552 * per-port, so set_lan_id() must be called before reading the addresses.
3553 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3554 * upon for non-SFP connections, so we must call it here.
3556 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3558 u16 san_mac_data, san_mac_offset;
3562 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3565 * First read the EEPROM pointer to see if the MAC addresses are
3566 * available. If they're not, no point in calling set_lan_id() here.
3568 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3569 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3570 goto san_mac_addr_out;
3572 /* make sure we know which port we need to program */
3573 hw->mac.ops.set_lan_id(hw);
3574 /* apply the port offset to the address offset */
3575 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3576 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3577 for (i = 0; i < 3; i++) {
3578 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3581 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3582 "eeprom read at offset %d failed",
3584 goto san_mac_addr_out;
3586 san_mac_addr[i * 2] = (u8)(san_mac_data);
3587 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3590 return IXGBE_SUCCESS;
3594 * No addresses available in this EEPROM. It's not an
3595 * error though, so just wipe the local address and return.
3597 for (i = 0; i < 6; i++)
3598 san_mac_addr[i] = 0xFF;
3599 return IXGBE_SUCCESS;
3603 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3604 * @hw: pointer to hardware structure
3605 * @san_mac_addr: SAN MAC address
3607 * Write a SAN MAC address to the EEPROM.
3609 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3612 u16 san_mac_data, san_mac_offset;
3615 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3617 /* Look for SAN mac address pointer. If not defined, return */
3618 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3619 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3620 return IXGBE_ERR_NO_SAN_ADDR_PTR;
3622 /* Make sure we know which port we need to write */
3623 hw->mac.ops.set_lan_id(hw);
3624 /* Apply the port offset to the address offset */
3625 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3626 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3628 for (i = 0; i < 3; i++) {
3629 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3630 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3631 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3635 return IXGBE_SUCCESS;
3639 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3640 * @hw: pointer to hardware structure
3642 * Read PCIe configuration space, and get the MSI-X vector count from
3643 * the capabilities table.
3645 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3651 switch (hw->mac.type) {
3652 case ixgbe_mac_82598EB:
3653 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3654 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3656 case ixgbe_mac_82599EB:
3657 case ixgbe_mac_X540:
3658 case ixgbe_mac_X550:
3659 case ixgbe_mac_X550EM_x:
3660 case ixgbe_mac_X550EM_a:
3661 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3662 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3668 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3669 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3670 if (IXGBE_REMOVED(hw->hw_addr))
3672 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3674 /* MSI-X count is zero-based in HW */
3677 if (msix_count > max_msix_count)
3678 msix_count = max_msix_count;
3684 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3685 * @hw: pointer to hardware structure
3686 * @addr: Address to put into receive address register
3687 * @vmdq: VMDq pool to assign
3689 * Puts an ethernet address into a receive address register, or
3690 * finds the rar that it is aleady in; adds to the pool list
3692 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3694 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3695 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3697 u32 rar_low, rar_high;
3698 u32 addr_low, addr_high;
3700 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3702 /* swap bytes for HW little endian */
3703 addr_low = addr[0] | (addr[1] << 8)
3706 addr_high = addr[4] | (addr[5] << 8);
3709 * Either find the mac_id in rar or find the first empty space.
3710 * rar_highwater points to just after the highest currently used
3711 * rar in order to shorten the search. It grows when we add a new
3714 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3715 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3717 if (((IXGBE_RAH_AV & rar_high) == 0)
3718 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3719 first_empty_rar = rar;
3720 } else if ((rar_high & 0xFFFF) == addr_high) {
3721 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3722 if (rar_low == addr_low)
3723 break; /* found it already in the rars */
3727 if (rar < hw->mac.rar_highwater) {
3728 /* already there so just add to the pool bits */
3729 ixgbe_set_vmdq(hw, rar, vmdq);
3730 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3731 /* stick it into first empty RAR slot we found */
3732 rar = first_empty_rar;
3733 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3734 } else if (rar == hw->mac.rar_highwater) {
3735 /* add it to the top of the list and inc the highwater mark */
3736 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3737 hw->mac.rar_highwater++;
3738 } else if (rar >= hw->mac.num_rar_entries) {
3739 return IXGBE_ERR_INVALID_MAC_ADDR;
3743 * If we found rar[0], make sure the default pool bit (we use pool 0)
3744 * remains cleared to be sure default pool packets will get delivered
3747 ixgbe_clear_vmdq(hw, rar, 0);
3753 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3754 * @hw: pointer to hardware struct
3755 * @rar: receive address register index to disassociate
3756 * @vmdq: VMDq pool index to remove from the rar
3758 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3760 u32 mpsar_lo, mpsar_hi;
3761 u32 rar_entries = hw->mac.num_rar_entries;
3763 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3765 /* Make sure we are using a valid rar index range */
3766 if (rar >= rar_entries) {
3767 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3768 "RAR index %d is out of range.\n", rar);
3769 return IXGBE_ERR_INVALID_ARGUMENT;
3772 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3773 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3775 if (IXGBE_REMOVED(hw->hw_addr))
3778 if (!mpsar_lo && !mpsar_hi)
3781 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3783 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3787 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3790 } else if (vmdq < 32) {
3791 mpsar_lo &= ~(1 << vmdq);
3792 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3794 mpsar_hi &= ~(1 << (vmdq - 32));
3795 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3798 /* was that the last pool using this rar? */
3799 if (mpsar_lo == 0 && mpsar_hi == 0 &&
3800 rar != 0 && rar != hw->mac.san_mac_rar_index)
3801 hw->mac.ops.clear_rar(hw, rar);
3803 return IXGBE_SUCCESS;
3807 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3808 * @hw: pointer to hardware struct
3809 * @rar: receive address register index to associate with a VMDq index
3810 * @vmdq: VMDq pool index
3812 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3815 u32 rar_entries = hw->mac.num_rar_entries;
3817 DEBUGFUNC("ixgbe_set_vmdq_generic");
3819 /* Make sure we are using a valid rar index range */
3820 if (rar >= rar_entries) {
3821 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3822 "RAR index %d is out of range.\n", rar);
3823 return IXGBE_ERR_INVALID_ARGUMENT;
3827 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3829 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3831 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3832 mpsar |= 1 << (vmdq - 32);
3833 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3835 return IXGBE_SUCCESS;
3839 * This function should only be involved in the IOV mode.
3840 * In IOV mode, Default pool is next pool after the number of
3841 * VFs advertized and not 0.
3842 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3844 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3845 * @hw: pointer to hardware struct
3846 * @vmdq: VMDq pool index
3848 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3850 u32 rar = hw->mac.san_mac_rar_index;
3852 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3855 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3856 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3858 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3859 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3862 return IXGBE_SUCCESS;
3866 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3867 * @hw: pointer to hardware structure
3869 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3873 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3874 DEBUGOUT(" Clearing UTA\n");
3876 for (i = 0; i < 128; i++)
3877 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3879 return IXGBE_SUCCESS;
3883 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3884 * @hw: pointer to hardware structure
3885 * @vlan: VLAN id to write to VLAN filter
3886 * @vlvf_bypass: true to find vlanid only, false returns first empty slot if
3890 * return the VLVF index where this VLAN id should be placed
3893 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)
3895 s32 regindex, first_empty_slot;
3898 /* short cut the special case */
3902 /* if vlvf_bypass is set we don't want to use an empty slot, we
3903 * will simply bypass the VLVF if there are no entries present in the
3904 * VLVF that contain our VLAN
3906 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0;
3908 /* add VLAN enable bit for comparison */
3909 vlan |= IXGBE_VLVF_VIEN;
3911 /* Search for the vlan id in the VLVF entries. Save off the first empty
3912 * slot found along the way.
3914 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1
3916 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) {
3917 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3920 if (!first_empty_slot && !bits)
3921 first_empty_slot = regindex;
3924 /* If we are here then we didn't find the VLAN. Return first empty
3925 * slot we found during our search, else error.
3927 if (!first_empty_slot)
3928 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "No space in VLVF.\n");
3930 return first_empty_slot ? first_empty_slot : IXGBE_ERR_NO_SPACE;
3934 * ixgbe_set_vfta_generic - Set VLAN filter table
3935 * @hw: pointer to hardware structure
3936 * @vlan: VLAN id to write to VLAN filter
3937 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
3938 * @vlan_on: boolean flag to turn on/off VLAN
3939 * @vlvf_bypass: boolean flag indicating updating default pool is okay
3941 * Turn on/off specified VLAN in the VLAN filter table.
3943 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3944 bool vlan_on, bool vlvf_bypass)
3946 u32 regidx, vfta_delta, vfta;
3949 DEBUGFUNC("ixgbe_set_vfta_generic");
3951 if (vlan > 4095 || vind > 63)
3952 return IXGBE_ERR_PARAM;
3955 * this is a 2 part operation - first the VFTA, then the
3956 * VLVF and VLVFB if VT Mode is set
3957 * We don't write the VFTA until we know the VLVF part succeeded.
3961 * The VFTA is a bitstring made up of 128 32-bit registers
3962 * that enable the particular VLAN id, much like the MTA:
3963 * bits[11-5]: which register
3964 * bits[4-0]: which bit in the register
3967 vfta_delta = 1 << (vlan % 32);
3968 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx));
3971 * vfta_delta represents the difference between the current value
3972 * of vfta and the value we want in the register. Since the diff
3973 * is an XOR mask we can just update the vfta using an XOR
3975 vfta_delta &= vlan_on ? ~vfta : vfta;
3979 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
3981 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta,
3983 if (ret_val != IXGBE_SUCCESS) {
3990 /* Update VFTA now that we are ready for traffic */
3992 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta);
3994 return IXGBE_SUCCESS;
3998 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
3999 * @hw: pointer to hardware structure
4000 * @vlan: VLAN id to write to VLAN filter
4001 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
4002 * @vlan_on: boolean flag to turn on/off VLAN in VLVF
4003 * @vfta_delta: pointer to the difference between the current value of VFTA
4004 * and the desired value
4005 * @vfta: the desired value of the VFTA
4006 * @vlvf_bypass: boolean flag indicating updating default pool is okay
4008 * Turn on/off specified bit in VLVF table.
4010 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
4011 bool vlan_on, u32 *vfta_delta, u32 vfta,
4017 DEBUGFUNC("ixgbe_set_vlvf_generic");
4019 if (vlan > 4095 || vind > 63)
4020 return IXGBE_ERR_PARAM;
4022 /* If VT Mode is set
4024 * make sure the vlan is in VLVF
4025 * set the vind bit in the matching VLVFB
4027 * clear the pool bit and possibly the vind
4029 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE))
4030 return IXGBE_SUCCESS;
4032 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
4036 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32));
4038 /* set the pool bit */
4039 bits |= 1 << (vind % 32);
4043 /* clear the pool bit */
4044 bits ^= 1 << (vind % 32);
4047 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) {
4048 /* Clear VFTA first, then disable VLVF. Otherwise
4049 * we run the risk of stray packets leaking into
4050 * the PF via the default pool
4053 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta);
4055 /* disable VLVF and clear remaining bit from pool */
4056 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
4057 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0);
4059 return IXGBE_SUCCESS;
4062 /* If there are still bits set in the VLVFB registers
4063 * for the VLAN ID indicated we need to see if the
4064 * caller is requesting that we clear the VFTA entry bit.
4065 * If the caller has requested that we clear the VFTA
4066 * entry bit but there are still pools/VFs using this VLAN
4067 * ID entry then ignore the request. We're not worried
4068 * about the case where we're turning the VFTA VLAN ID
4069 * entry bit on, only when requested to turn it off as
4070 * there may be multiple pools and/or VFs using the
4071 * VLAN ID entry. In that case we cannot clear the
4072 * VFTA bit until all pools/VFs using that VLAN ID have also
4073 * been cleared. This will be indicated by "bits" being
4079 /* record pool change and enable VLAN ID if not already enabled */
4080 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits);
4081 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan);
4083 return IXGBE_SUCCESS;
4087 * ixgbe_clear_vfta_generic - Clear VLAN filter table
4088 * @hw: pointer to hardware structure
4090 * Clears the VLAN filer table, and the VMDq index associated with the filter
4092 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
4096 DEBUGFUNC("ixgbe_clear_vfta_generic");
4098 for (offset = 0; offset < hw->mac.vft_size; offset++)
4099 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
4101 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
4102 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
4103 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
4104 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0);
4107 return IXGBE_SUCCESS;
4111 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
4112 * @hw: pointer to hardware structure
4114 * Contains the logic to identify if we need to verify link for the
4117 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw)
4120 /* Does FW say we need the fix */
4121 if (!hw->need_crosstalk_fix)
4124 /* Only consider SFP+ PHYs i.e. media type fiber */
4125 switch (hw->mac.ops.get_media_type(hw)) {
4126 case ixgbe_media_type_fiber:
4127 case ixgbe_media_type_fiber_qsfp:
4137 * ixgbe_check_mac_link_generic - Determine link and speed status
4138 * @hw: pointer to hardware structure
4139 * @speed: pointer to link speed
4140 * @link_up: true when link is up
4141 * @link_up_wait_to_complete: bool used to wait for link up or not
4143 * Reads the links register to determine if link is up and the current speed
4145 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4146 bool *link_up, bool link_up_wait_to_complete)
4148 u32 links_reg, links_orig;
4151 DEBUGFUNC("ixgbe_check_mac_link_generic");
4153 /* If Crosstalk fix enabled do the sanity check of making sure
4154 * the SFP+ cage is full.
4156 if (ixgbe_need_crosstalk_fix(hw)) {
4159 switch (hw->mac.type) {
4160 case ixgbe_mac_82599EB:
4161 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4164 case ixgbe_mac_X550EM_x:
4165 case ixgbe_mac_X550EM_a:
4166 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4170 /* sanity check - No SFP+ devices here */
4171 sfp_cage_full = false;
4175 if (!sfp_cage_full) {
4177 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4178 return IXGBE_SUCCESS;
4182 /* clear the old state */
4183 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
4185 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4187 if (links_orig != links_reg) {
4188 DEBUGOUT2("LINKS changed from %08X to %08X\n",
4189 links_orig, links_reg);
4192 if (link_up_wait_to_complete) {
4193 for (i = 0; i < hw->mac.max_link_up_time; i++) {
4194 if (links_reg & IXGBE_LINKS_UP) {
4201 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4204 if (links_reg & IXGBE_LINKS_UP)
4210 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4211 case IXGBE_LINKS_SPEED_10G_82599:
4212 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4213 if (hw->mac.type >= ixgbe_mac_X550) {
4214 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4215 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4218 case IXGBE_LINKS_SPEED_1G_82599:
4219 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4221 case IXGBE_LINKS_SPEED_100_82599:
4222 *speed = IXGBE_LINK_SPEED_100_FULL;
4223 if (hw->mac.type == ixgbe_mac_X550) {
4224 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4225 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4228 case IXGBE_LINKS_SPEED_10_X550EM_A:
4229 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4230 #ifdef PREBOOT_SUPPORT
4231 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4232 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L ||
4233 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
4234 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
4235 *speed = IXGBE_LINK_SPEED_10_FULL;
4237 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4238 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4239 *speed = IXGBE_LINK_SPEED_10_FULL;
4240 #endif /* PREBOOT_SUPPORT */
4243 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4246 return IXGBE_SUCCESS;
4250 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4252 * @hw: pointer to hardware structure
4253 * @wwnn_prefix: the alternative WWNN prefix
4254 * @wwpn_prefix: the alternative WWPN prefix
4256 * This function will read the EEPROM from the alternative SAN MAC address
4257 * block to check the support for the alternative WWNN/WWPN prefix support.
4259 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4263 u16 alt_san_mac_blk_offset;
4265 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
4267 /* clear output first */
4268 *wwnn_prefix = 0xFFFF;
4269 *wwpn_prefix = 0xFFFF;
4271 /* check if alternative SAN MAC is supported */
4272 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
4273 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4274 goto wwn_prefix_err;
4276 if ((alt_san_mac_blk_offset == 0) ||
4277 (alt_san_mac_blk_offset == 0xFFFF))
4278 goto wwn_prefix_out;
4280 /* check capability in alternative san mac address block */
4281 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
4282 if (hw->eeprom.ops.read(hw, offset, &caps))
4283 goto wwn_prefix_err;
4284 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
4285 goto wwn_prefix_out;
4287 /* get the corresponding prefix for WWNN/WWPN */
4288 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
4289 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4290 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4291 "eeprom read at offset %d failed", offset);
4294 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
4295 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4296 goto wwn_prefix_err;
4299 return IXGBE_SUCCESS;
4302 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4303 "eeprom read at offset %d failed", offset);
4304 return IXGBE_SUCCESS;
4308 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4309 * @hw: pointer to hardware structure
4310 * @bs: the fcoe boot status
4312 * This function will read the FCOE boot status from the iSCSI FCOE block
4314 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4316 u16 offset, caps, flags;
4319 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
4321 /* clear output first */
4322 *bs = ixgbe_fcoe_bootstatus_unavailable;
4324 /* check if FCOE IBA block is present */
4325 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
4326 status = hw->eeprom.ops.read(hw, offset, &caps);
4327 if (status != IXGBE_SUCCESS)
4330 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
4333 /* check if iSCSI FCOE block is populated */
4334 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4335 if (status != IXGBE_SUCCESS)
4338 if ((offset == 0) || (offset == 0xFFFF))
4341 /* read fcoe flags in iSCSI FCOE block */
4342 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
4343 status = hw->eeprom.ops.read(hw, offset, &flags);
4344 if (status != IXGBE_SUCCESS)
4347 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
4348 *bs = ixgbe_fcoe_bootstatus_enabled;
4350 *bs = ixgbe_fcoe_bootstatus_disabled;
4357 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4358 * @hw: pointer to hardware structure
4359 * @enable: enable or disable switch for MAC anti-spoofing
4360 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
4363 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4365 int vf_target_reg = vf >> 3;
4366 int vf_target_shift = vf % 8;
4369 if (hw->mac.type == ixgbe_mac_82598EB)
4372 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4374 pfvfspoof |= (1 << vf_target_shift);
4376 pfvfspoof &= ~(1 << vf_target_shift);
4377 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4381 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4382 * @hw: pointer to hardware structure
4383 * @enable: enable or disable switch for VLAN anti-spoofing
4384 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4387 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4389 int vf_target_reg = vf >> 3;
4390 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
4393 if (hw->mac.type == ixgbe_mac_82598EB)
4396 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4398 pfvfspoof |= (1 << vf_target_shift);
4400 pfvfspoof &= ~(1 << vf_target_shift);
4401 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4405 * ixgbe_get_device_caps_generic - Get additional device capabilities
4406 * @hw: pointer to hardware structure
4407 * @device_caps: the EEPROM word with the extra device capabilities
4409 * This function will read the EEPROM location for the device capabilities,
4410 * and return the word through device_caps.
4412 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4414 DEBUGFUNC("ixgbe_get_device_caps_generic");
4416 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4418 return IXGBE_SUCCESS;
4422 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4423 * @hw: pointer to hardware structure
4426 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4431 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
4433 /* Enable relaxed ordering */
4434 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4435 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4436 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4437 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4440 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4441 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4442 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
4443 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4444 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4450 * ixgbe_calculate_checksum - Calculate checksum for buffer
4451 * @buffer: pointer to EEPROM
4452 * @length: size of EEPROM to calculate a checksum for
4453 * Calculates the checksum for some buffer on a specified length. The
4454 * checksum calculated is returned.
4456 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4461 DEBUGFUNC("ixgbe_calculate_checksum");
4466 for (i = 0; i < length; i++)
4469 return (u8) (0 - sum);
4473 * ixgbe_hic_unlocked - Issue command to manageability block unlocked
4474 * @hw: pointer to the HW structure
4475 * @buffer: command to write and where the return status will be placed
4476 * @length: length of buffer, must be multiple of 4 bytes
4477 * @timeout: time in ms to wait for command completion
4479 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4480 * else returns semaphore error when encountering an error acquiring
4481 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4483 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held
4486 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length,
4492 DEBUGFUNC("ixgbe_hic_unlocked");
4494 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4495 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4496 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4499 /* Set bit 9 of FWSTS clearing FW reset indication */
4500 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
4501 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
4503 /* Check that the host interface is enabled. */
4504 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4505 if (!(hicr & IXGBE_HICR_EN)) {
4506 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
4507 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4510 /* Calculate length in DWORDs. We must be DWORD aligned */
4511 if (length % sizeof(u32)) {
4512 DEBUGOUT("Buffer length failure, not aligned to dword");
4513 return IXGBE_ERR_INVALID_ARGUMENT;
4516 dword_len = length >> 2;
4518 /* The device driver writes the relevant command block
4519 * into the ram area.
4521 for (i = 0; i < dword_len; i++)
4522 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4523 i, IXGBE_CPU_TO_LE32(buffer[i]));
4525 /* Setting this bit tells the ARC that a new command is pending. */
4526 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4528 for (i = 0; i < timeout; i++) {
4529 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4530 if (!(hicr & IXGBE_HICR_C))
4535 /* Check command completion */
4536 if ((timeout && i == timeout) ||
4537 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
4538 ERROR_REPORT1(IXGBE_ERROR_CAUTION,
4539 "Command has failed with no status valid.\n");
4540 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4543 return IXGBE_SUCCESS;
4547 * ixgbe_host_interface_command - Issue command to manageability block
4548 * @hw: pointer to the HW structure
4549 * @buffer: contains the command to write and where the return status will
4551 * @length: length of buffer, must be multiple of 4 bytes
4552 * @timeout: time in ms to wait for command completion
4553 * @return_data: read and return data from the buffer (true) or not (false)
4554 * Needed because FW structures are big endian and decoding of
4555 * these fields can be 8 bit or 16 bit based on command. Decoding
4556 * is not easily understood without making a table of commands.
4557 * So we will leave this up to the caller to read back the data
4560 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4561 * else returns semaphore error when encountering an error acquiring
4562 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4564 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4565 u32 length, u32 timeout, bool return_data)
4567 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4568 struct ixgbe_hic_hdr *resp = (struct ixgbe_hic_hdr *)buffer;
4574 DEBUGFUNC("ixgbe_host_interface_command");
4576 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4577 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4578 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4581 /* Take management host interface semaphore */
4582 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4586 status = ixgbe_hic_unlocked(hw, buffer, length, timeout);
4593 /* Calculate length in DWORDs */
4594 dword_len = hdr_size >> 2;
4596 /* first pull in the header so we know the buffer length */
4597 for (bi = 0; bi < dword_len; bi++) {
4598 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4599 IXGBE_LE32_TO_CPUS((uintptr_t)&buffer[bi]);
4603 * If there is any thing in data position pull it in
4604 * Read Flash command requires reading buffer length from
4605 * two byes instead of one byte
4607 if (resp->cmd == 0x30) {
4608 for (; bi < dword_len + 2; bi++) {
4609 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4611 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4613 buf_len = (((u16)(resp->cmd_or_resp.ret_status) << 3)
4614 & 0xF00) | resp->buf_len;
4615 hdr_size += (2 << 2);
4617 buf_len = resp->buf_len;
4622 if (length < buf_len + hdr_size) {
4623 DEBUGOUT("Buffer not large enough for reply message.\n");
4624 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4628 /* Calculate length in DWORDs, add 3 for odd lengths */
4629 dword_len = (buf_len + 3) >> 2;
4631 /* Pull in the rest of the buffer (bi is where we left off) */
4632 for (; bi <= dword_len; bi++) {
4633 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4634 IXGBE_LE32_TO_CPUS((uintptr_t)&buffer[bi]);
4638 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4644 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4645 * @hw: pointer to the HW structure
4646 * @maj: driver version major number
4647 * @min: driver version minor number
4648 * @build: driver version build number
4649 * @sub: driver version sub build number
4651 * @driver_ver: unused
4653 * Sends driver version number to firmware through the manageability
4654 * block. On success return IXGBE_SUCCESS
4655 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4656 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4658 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4659 u8 build, u8 sub, u16 len,
4660 const char *driver_ver)
4662 struct ixgbe_hic_drv_info fw_cmd;
4664 s32 ret_val = IXGBE_SUCCESS;
4666 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4667 UNREFERENCED_2PARAMETER(len, driver_ver);
4669 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4670 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4671 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4672 fw_cmd.port_num = (u8)hw->bus.func;
4673 fw_cmd.ver_maj = maj;
4674 fw_cmd.ver_min = min;
4675 fw_cmd.ver_build = build;
4676 fw_cmd.ver_sub = sub;
4677 fw_cmd.hdr.checksum = 0;
4680 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4681 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4683 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4684 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4686 IXGBE_HI_COMMAND_TIMEOUT,
4688 if (ret_val != IXGBE_SUCCESS)
4691 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4692 FW_CEM_RESP_STATUS_SUCCESS)
4693 ret_val = IXGBE_SUCCESS;
4695 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4704 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4705 * @hw: pointer to hardware structure
4706 * @num_pb: number of packet buffers to allocate
4707 * @headroom: reserve n KB of headroom
4708 * @strategy: packet buffer allocation strategy
4710 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4713 u32 pbsize = hw->mac.rx_pb_size;
4715 u32 rxpktsize, txpktsize, txpbthresh;
4717 /* Reserve headroom */
4723 /* Divide remaining packet buffer space amongst the number of packet
4724 * buffers requested using supplied strategy.
4727 case PBA_STRATEGY_WEIGHTED:
4728 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4729 * buffer with 5/8 of the packet buffer space.
4731 rxpktsize = (pbsize * 5) / (num_pb * 4);
4732 pbsize -= rxpktsize * (num_pb / 2);
4733 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4734 for (; i < (num_pb / 2); i++)
4735 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4736 /* fall through - configure remaining packet buffers */
4737 case PBA_STRATEGY_EQUAL:
4738 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4739 for (; i < num_pb; i++)
4740 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4746 /* Only support an equally distributed Tx packet buffer strategy. */
4747 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4748 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4749 for (i = 0; i < num_pb; i++) {
4750 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4751 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4754 /* Clear unused TCs, if any, to zero buffer size*/
4755 for (; i < IXGBE_MAX_PB; i++) {
4756 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4757 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4758 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4763 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4764 * @hw: pointer to the hardware structure
4766 * The 82599 and x540 MACs can experience issues if TX work is still pending
4767 * when a reset occurs. This function prevents this by flushing the PCIe
4768 * buffers on the system.
4770 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4772 u32 gcr_ext, hlreg0, i, poll;
4776 * If double reset is not requested then all transactions should
4777 * already be clear and as such there is no work to do
4779 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4783 * Set loopback enable to prevent any transmits from being sent
4784 * should the link come up. This assumes that the RXCTRL.RXEN bit
4785 * has already been cleared.
4787 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4788 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4790 /* Wait for a last completion before clearing buffers */
4791 IXGBE_WRITE_FLUSH(hw);
4795 * Before proceeding, make sure that the PCIe block does not have
4796 * transactions pending.
4798 poll = ixgbe_pcie_timeout_poll(hw);
4799 for (i = 0; i < poll; i++) {
4801 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
4802 if (IXGBE_REMOVED(hw->hw_addr))
4804 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
4809 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4810 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4811 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4812 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4814 /* Flush all writes and allow 20usec for all transactions to clear */
4815 IXGBE_WRITE_FLUSH(hw);
4818 /* restore previous register values */
4819 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4820 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4823 STATIC const u8 ixgbe_emc_temp_data[4] = {
4824 IXGBE_EMC_INTERNAL_DATA,
4825 IXGBE_EMC_DIODE1_DATA,
4826 IXGBE_EMC_DIODE2_DATA,
4827 IXGBE_EMC_DIODE3_DATA
4829 STATIC const u8 ixgbe_emc_therm_limit[4] = {
4830 IXGBE_EMC_INTERNAL_THERM_LIMIT,
4831 IXGBE_EMC_DIODE1_THERM_LIMIT,
4832 IXGBE_EMC_DIODE2_THERM_LIMIT,
4833 IXGBE_EMC_DIODE3_THERM_LIMIT
4837 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
4838 * @hw: pointer to hardware structure
4840 * Returns the thermal sensor data structure
4842 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
4844 s32 status = IXGBE_SUCCESS;
4852 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4854 DEBUGFUNC("ixgbe_get_thermal_sensor_data_generic");
4856 /* Only support thermal sensors attached to 82599 physical port 0 */
4857 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4858 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
4859 status = IXGBE_NOT_IMPLEMENTED;
4863 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);
4867 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) {
4868 status = IXGBE_NOT_IMPLEMENTED;
4872 status = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);
4876 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4877 != IXGBE_ETS_TYPE_EMC) {
4878 status = IXGBE_NOT_IMPLEMENTED;
4882 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4883 if (num_sensors > IXGBE_MAX_SENSORS)
4884 num_sensors = IXGBE_MAX_SENSORS;
4886 for (i = 0; i < num_sensors; i++) {
4887 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
4892 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4893 IXGBE_ETS_DATA_INDEX_SHIFT);
4894 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4895 IXGBE_ETS_DATA_LOC_SHIFT);
4897 if (sensor_location != 0) {
4898 status = hw->phy.ops.read_i2c_byte(hw,
4899 ixgbe_emc_temp_data[sensor_index],
4900 IXGBE_I2C_THERMAL_SENSOR_ADDR,
4901 &data->sensor[i].temp);
4911 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
4912 * @hw: pointer to hardware structure
4914 * Inits the thermal sensor thresholds according to the NVM map
4915 * and save off the threshold and location values into mac.thermal_sensor_data
4917 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
4919 s32 status = IXGBE_SUCCESS;
4924 u8 low_thresh_delta;
4930 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4932 DEBUGFUNC("ixgbe_init_thermal_sensor_thresh_generic");
4934 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
4936 /* Only support thermal sensors attached to 82599 physical port 0 */
4937 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4938 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
4939 return IXGBE_NOT_IMPLEMENTED;
4941 offset = IXGBE_ETS_CFG;
4942 if (hw->eeprom.ops.read(hw, offset, &ets_offset))
4944 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
4945 return IXGBE_NOT_IMPLEMENTED;
4947 offset = ets_offset;
4948 if (hw->eeprom.ops.read(hw, offset, &ets_cfg))
4950 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4951 != IXGBE_ETS_TYPE_EMC)
4952 return IXGBE_NOT_IMPLEMENTED;
4954 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
4955 IXGBE_ETS_LTHRES_DELTA_SHIFT);
4956 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4958 for (i = 0; i < num_sensors; i++) {
4959 offset = ets_offset + 1 + i;
4960 if (hw->eeprom.ops.read(hw, offset, &ets_sensor)) {
4961 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4962 "eeprom read at offset %d failed",
4966 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4967 IXGBE_ETS_DATA_INDEX_SHIFT);
4968 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4969 IXGBE_ETS_DATA_LOC_SHIFT);
4970 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
4972 hw->phy.ops.write_i2c_byte(hw,
4973 ixgbe_emc_therm_limit[sensor_index],
4974 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
4976 if ((i < IXGBE_MAX_SENSORS) && (sensor_location != 0)) {
4977 data->sensor[i].location = sensor_location;
4978 data->sensor[i].caution_thresh = therm_limit;
4979 data->sensor[i].max_op_thresh = therm_limit -
4986 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4987 "eeprom read at offset %d failed", offset);
4988 return IXGBE_NOT_IMPLEMENTED;
4992 * ixgbe_get_orom_version - Return option ROM from EEPROM
4994 * @hw: pointer to hardware structure
4995 * @nvm_ver: pointer to output structure
4997 * if valid option ROM version, nvm_ver->or_valid set to true
4998 * else nvm_ver->or_valid is false.
5000 void ixgbe_get_orom_version(struct ixgbe_hw *hw,
5001 struct ixgbe_nvm_version *nvm_ver)
5003 u16 offset, eeprom_cfg_blkh, eeprom_cfg_blkl;
5005 nvm_ver->or_valid = false;
5006 /* Option Rom may or may not be present. Start with pointer */
5007 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset);
5009 /* make sure offset is valid */
5010 if ((offset == 0x0) || (offset == NVM_INVALID_PTR))
5013 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh);
5014 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl);
5016 /* option rom exists and is valid */
5017 if ((eeprom_cfg_blkl | eeprom_cfg_blkh) == 0x0 ||
5018 eeprom_cfg_blkl == NVM_VER_INVALID ||
5019 eeprom_cfg_blkh == NVM_VER_INVALID)
5022 nvm_ver->or_valid = true;
5023 nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT;
5024 nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) |
5025 (eeprom_cfg_blkh >> NVM_OROM_SHIFT);
5026 nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK;
5030 * ixgbe_get_oem_prod_version - Return OEM Product version
5032 * @hw: pointer to hardware structure
5033 * @nvm_ver: pointer to output structure
5035 * if valid OEM product version, nvm_ver->oem_valid set to true
5036 * else nvm_ver->oem_valid is false.
5038 void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw,
5039 struct ixgbe_nvm_version *nvm_ver)
5041 u16 rel_num, prod_ver, mod_len, cap, offset;
5043 nvm_ver->oem_valid = false;
5044 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset);
5046 /* Return is offset to OEM Product Version block is invalid */
5047 if (offset == 0x0 && offset == NVM_INVALID_PTR)
5050 /* Read product version block */
5051 hw->eeprom.ops.read(hw, offset, &mod_len);
5052 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap);
5054 /* Return if OEM product version block is invalid */
5055 if (mod_len != NVM_OEM_PROD_VER_MOD_LEN ||
5056 (cap & NVM_OEM_PROD_VER_CAP_MASK) != 0x0)
5059 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver);
5060 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num);
5062 /* Return if version is invalid */
5063 if ((rel_num | prod_ver) == 0x0 ||
5064 rel_num == NVM_VER_INVALID || prod_ver == NVM_VER_INVALID)
5067 nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT;
5068 nvm_ver->oem_minor = prod_ver & NVM_VER_MASK;
5069 nvm_ver->oem_release = rel_num;
5070 nvm_ver->oem_valid = true;
5074 * ixgbe_get_etk_id - Return Etrack ID from EEPROM
5076 * @hw: pointer to hardware structure
5077 * @nvm_ver: pointer to output structure
5079 * word read errors will return 0xFFFF
5081 void ixgbe_get_etk_id(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver)
5083 u16 etk_id_l, etk_id_h;
5085 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l))
5086 etk_id_l = NVM_VER_INVALID;
5087 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h))
5088 etk_id_h = NVM_VER_INVALID;
5090 /* The word order for the version format is determined by high order
5093 if ((etk_id_h & NVM_ETK_VALID) == 0) {
5094 nvm_ver->etk_id = etk_id_h;
5095 nvm_ver->etk_id |= (etk_id_l << NVM_ETK_SHIFT);
5097 nvm_ver->etk_id = etk_id_l;
5098 nvm_ver->etk_id |= (etk_id_h << NVM_ETK_SHIFT);
5104 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
5105 * @hw: pointer to hardware structure
5106 * @map: pointer to u8 arr for returning map
5108 * Read the rtrup2tc HW register and resolve its content into map
5110 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
5114 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
5115 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
5116 map[i] = IXGBE_RTRUP2TC_UP_MASK &
5117 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
5121 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
5126 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5127 if (rxctrl & IXGBE_RXCTRL_RXEN) {
5128 if (hw->mac.type != ixgbe_mac_82598EB) {
5129 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5130 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
5131 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
5132 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
5133 hw->mac.set_lben = true;
5135 hw->mac.set_lben = false;
5138 rxctrl &= ~IXGBE_RXCTRL_RXEN;
5139 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
5143 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
5148 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5149 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
5151 if (hw->mac.type != ixgbe_mac_82598EB) {
5152 if (hw->mac.set_lben) {
5153 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5154 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
5155 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
5156 hw->mac.set_lben = false;
5162 * ixgbe_mng_present - returns true when management capability is present
5163 * @hw: pointer to hardware structure
5165 bool ixgbe_mng_present(struct ixgbe_hw *hw)
5169 if (hw->mac.type < ixgbe_mac_82599EB)
5172 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5174 return !!(fwsm & IXGBE_FWSM_FW_MODE_PT);
5178 * ixgbe_mng_enabled - Is the manageability engine enabled?
5179 * @hw: pointer to hardware structure
5181 * Returns true if the manageability engine is enabled.
5183 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
5185 u32 fwsm, manc, factps;
5187 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5188 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
5191 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
5192 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
5195 if (hw->mac.type <= ixgbe_mac_X540) {
5196 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
5197 if (factps & IXGBE_FACTPS_MNGCG)
5205 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
5206 * @hw: pointer to hardware structure
5207 * @speed: new link speed
5208 * @autoneg_wait_to_complete: true when waiting for completion is needed
5210 * Set the link speed in the MAC and/or PHY register and restarts link.
5212 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
5213 ixgbe_link_speed speed,
5214 bool autoneg_wait_to_complete)
5216 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
5217 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
5218 s32 status = IXGBE_SUCCESS;
5221 bool autoneg, link_up = false;
5223 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
5225 /* Mask off requested but non-supported speeds */
5226 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
5227 if (status != IXGBE_SUCCESS)
5230 speed &= link_speed;
5232 /* Try each speed one by one, highest priority first. We do this in
5233 * software because 10Gb fiber doesn't support speed autonegotiation.
5235 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
5237 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5239 /* Set the module link speed */
5240 switch (hw->phy.media_type) {
5241 case ixgbe_media_type_fiber_fixed:
5242 case ixgbe_media_type_fiber:
5243 ixgbe_set_rate_select_speed(hw,
5244 IXGBE_LINK_SPEED_10GB_FULL);
5246 case ixgbe_media_type_fiber_qsfp:
5247 /* QSFP module automatically detects MAC link speed */
5250 DEBUGOUT("Unexpected media type.\n");
5254 /* Allow module to change analog characteristics (1G->10G) */
5257 status = ixgbe_setup_mac_link(hw,
5258 IXGBE_LINK_SPEED_10GB_FULL,
5259 autoneg_wait_to_complete);
5260 if (status != IXGBE_SUCCESS)
5263 /* Flap the Tx laser if it has not already been done */
5264 ixgbe_flap_tx_laser(hw);
5266 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
5267 * Section 73.10.2, we may have to wait up to 500ms if KR is
5268 * attempted. 82599 uses the same timing for 10g SFI.
5270 for (i = 0; i < 5; i++) {
5271 /* Wait for the link partner to also set speed */
5274 /* If we have link, just jump out */
5275 status = ixgbe_check_link(hw, &link_speed,
5277 if (status != IXGBE_SUCCESS)
5285 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
5287 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
5288 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
5290 /* Set the module link speed */
5291 switch (hw->phy.media_type) {
5292 case ixgbe_media_type_fiber_fixed:
5293 case ixgbe_media_type_fiber:
5294 ixgbe_set_rate_select_speed(hw,
5295 IXGBE_LINK_SPEED_1GB_FULL);
5297 case ixgbe_media_type_fiber_qsfp:
5298 /* QSFP module automatically detects link speed */
5301 DEBUGOUT("Unexpected media type.\n");
5305 /* Allow module to change analog characteristics (10G->1G) */
5308 status = ixgbe_setup_mac_link(hw,
5309 IXGBE_LINK_SPEED_1GB_FULL,
5310 autoneg_wait_to_complete);
5311 if (status != IXGBE_SUCCESS)
5314 /* Flap the Tx laser if it has not already been done */
5315 ixgbe_flap_tx_laser(hw);
5317 /* Wait for the link partner to also set speed */
5320 /* If we have link, just jump out */
5321 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
5322 if (status != IXGBE_SUCCESS)
5329 /* We didn't get link. Configure back to the highest speed we tried,
5330 * (if there was more than one). We call ourselves back with just the
5331 * single highest speed that the user requested.
5334 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
5336 autoneg_wait_to_complete);
5339 /* Set autoneg_advertised value based on input link speed */
5340 hw->phy.autoneg_advertised = 0;
5342 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
5343 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
5345 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
5346 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
5352 * ixgbe_set_soft_rate_select_speed - Set module link speed
5353 * @hw: pointer to hardware structure
5354 * @speed: link speed to set
5356 * Set module link speed via the soft rate select.
5358 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
5359 ixgbe_link_speed speed)
5365 case IXGBE_LINK_SPEED_10GB_FULL:
5366 /* one bit mask same as setting on */
5367 rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
5369 case IXGBE_LINK_SPEED_1GB_FULL:
5370 rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
5373 DEBUGOUT("Invalid fixed module speed\n");
5378 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5379 IXGBE_I2C_EEPROM_DEV_ADDR2,
5382 DEBUGOUT("Failed to read Rx Rate Select RS0\n");
5386 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5388 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5389 IXGBE_I2C_EEPROM_DEV_ADDR2,
5392 DEBUGOUT("Failed to write Rx Rate Select RS0\n");
5397 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5398 IXGBE_I2C_EEPROM_DEV_ADDR2,
5401 DEBUGOUT("Failed to read Rx Rate Select RS1\n");
5405 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5407 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5408 IXGBE_I2C_EEPROM_DEV_ADDR2,
5411 DEBUGOUT("Failed to write Rx Rate Select RS1\n");