1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
36 #include "ixgbe_dcb.h"
37 #include "ixgbe_dcb_82599.h"
38 #include "ixgbe_api.h"
40 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
41 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
42 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
43 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
44 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
45 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
47 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
48 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
49 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
50 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw);
52 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
53 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
55 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
56 u16 words, u16 *data);
57 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
58 u16 words, u16 *data);
59 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
63 * ixgbe_init_ops_generic - Inits function ptrs
64 * @hw: pointer to the hardware structure
66 * Initialize the function pointers.
68 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
70 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
71 struct ixgbe_mac_info *mac = &hw->mac;
72 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
74 DEBUGFUNC("ixgbe_init_ops_generic");
77 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic;
78 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
79 if (eec & IXGBE_EEC_PRES) {
80 eeprom->ops.read = ixgbe_read_eerd_generic;
81 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic;
83 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic;
84 eeprom->ops.read_buffer =
85 ixgbe_read_eeprom_buffer_bit_bang_generic;
87 eeprom->ops.write = ixgbe_write_eeprom_generic;
88 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic;
89 eeprom->ops.validate_checksum =
90 ixgbe_validate_eeprom_checksum_generic;
91 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic;
92 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic;
95 mac->ops.init_hw = ixgbe_init_hw_generic;
96 mac->ops.reset_hw = NULL;
97 mac->ops.start_hw = ixgbe_start_hw_generic;
98 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic;
99 mac->ops.get_media_type = NULL;
100 mac->ops.get_supported_physical_layer = NULL;
101 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic;
102 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic;
103 mac->ops.stop_adapter = ixgbe_stop_adapter_generic;
104 mac->ops.get_bus_info = ixgbe_get_bus_info_generic;
105 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie;
106 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync;
107 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync;
108 mac->ops.prot_autoc_read = prot_autoc_read_generic;
109 mac->ops.prot_autoc_write = prot_autoc_write_generic;
112 mac->ops.led_on = ixgbe_led_on_generic;
113 mac->ops.led_off = ixgbe_led_off_generic;
114 mac->ops.blink_led_start = ixgbe_blink_led_start_generic;
115 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic;
117 /* RAR, Multicast, VLAN */
118 mac->ops.set_rar = ixgbe_set_rar_generic;
119 mac->ops.clear_rar = ixgbe_clear_rar_generic;
120 mac->ops.insert_mac_addr = NULL;
121 mac->ops.set_vmdq = NULL;
122 mac->ops.clear_vmdq = NULL;
123 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic;
124 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic;
125 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic;
126 mac->ops.enable_mc = ixgbe_enable_mc_generic;
127 mac->ops.disable_mc = ixgbe_disable_mc_generic;
128 mac->ops.clear_vfta = NULL;
129 mac->ops.set_vfta = NULL;
130 mac->ops.set_vlvf = NULL;
131 mac->ops.init_uta_tables = NULL;
132 mac->ops.enable_rx = ixgbe_enable_rx_generic;
133 mac->ops.disable_rx = ixgbe_disable_rx_generic;
136 mac->ops.fc_enable = ixgbe_fc_enable_generic;
137 mac->ops.setup_fc = ixgbe_setup_fc_generic;
140 mac->ops.get_link_capabilities = NULL;
141 mac->ops.setup_link = NULL;
142 mac->ops.check_link = NULL;
143 mac->ops.dmac_config = NULL;
144 mac->ops.dmac_update_tcs = NULL;
145 mac->ops.dmac_config_tcs = NULL;
147 return IXGBE_SUCCESS;
151 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
153 * @hw: pointer to hardware structure
155 * This function returns true if the device supports flow control
156 * autonegotiation, and false if it does not.
159 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
161 bool supported = false;
162 ixgbe_link_speed speed;
165 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
167 switch (hw->phy.media_type) {
168 case ixgbe_media_type_fiber_qsfp:
169 case ixgbe_media_type_fiber:
170 hw->mac.ops.check_link(hw, &speed, &link_up, false);
171 /* if link is down, assume supported */
173 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
178 case ixgbe_media_type_backplane:
181 case ixgbe_media_type_copper:
182 /* only some copper devices support flow control autoneg */
183 switch (hw->device_id) {
184 case IXGBE_DEV_ID_82599_T3_LOM:
185 case IXGBE_DEV_ID_X540T:
186 case IXGBE_DEV_ID_X540T1:
187 case IXGBE_DEV_ID_X550T:
188 case IXGBE_DEV_ID_X550T1:
189 case IXGBE_DEV_ID_X550EM_X_10G_T:
199 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
200 "Device %x does not support flow control autoneg",
206 * ixgbe_setup_fc_generic - Set up flow control
207 * @hw: pointer to hardware structure
209 * Called at init time to set up flow control.
211 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
213 s32 ret_val = IXGBE_SUCCESS;
214 u32 reg = 0, reg_bp = 0;
218 DEBUGFUNC("ixgbe_setup_fc_generic");
220 /* Validate the requested mode */
221 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
222 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
223 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
224 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
229 * 10gig parts do not have a word in the EEPROM to determine the
230 * default flow control setting, so we explicitly set it to full.
232 if (hw->fc.requested_mode == ixgbe_fc_default)
233 hw->fc.requested_mode = ixgbe_fc_full;
236 * Set up the 1G and 10G flow control advertisement registers so the
237 * HW will be able to do fc autoneg once the cable is plugged in. If
238 * we link at 10G, the 1G advertisement is harmless and vice versa.
240 switch (hw->phy.media_type) {
241 case ixgbe_media_type_backplane:
242 /* some MAC's need RMW protection on AUTOC */
243 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
244 if (ret_val != IXGBE_SUCCESS)
247 /* only backplane uses autoc so fall though */
248 case ixgbe_media_type_fiber_qsfp:
249 case ixgbe_media_type_fiber:
250 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
253 case ixgbe_media_type_copper:
254 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
255 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
262 * The possible values of fc.requested_mode are:
263 * 0: Flow control is completely disabled
264 * 1: Rx flow control is enabled (we can receive pause frames,
265 * but not send pause frames).
266 * 2: Tx flow control is enabled (we can send pause frames but
267 * we do not support receiving pause frames).
268 * 3: Both Rx and Tx flow control (symmetric) are enabled.
271 switch (hw->fc.requested_mode) {
273 /* Flow control completely disabled by software override. */
274 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
275 if (hw->phy.media_type == ixgbe_media_type_backplane)
276 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
277 IXGBE_AUTOC_ASM_PAUSE);
278 else if (hw->phy.media_type == ixgbe_media_type_copper)
279 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
281 case ixgbe_fc_tx_pause:
283 * Tx Flow control is enabled, and Rx Flow control is
284 * disabled by software override.
286 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
287 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
288 if (hw->phy.media_type == ixgbe_media_type_backplane) {
289 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
290 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
291 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
292 reg_cu |= IXGBE_TAF_ASM_PAUSE;
293 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
296 case ixgbe_fc_rx_pause:
298 * Rx Flow control is enabled and Tx Flow control is
299 * disabled by software override. Since there really
300 * isn't a way to advertise that we are capable of RX
301 * Pause ONLY, we will advertise that we support both
302 * symmetric and asymmetric Rx PAUSE, as such we fall
303 * through to the fc_full statement. Later, we will
304 * disable the adapter's ability to send PAUSE frames.
307 /* Flow control (both Rx and Tx) is enabled by SW override. */
308 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
309 if (hw->phy.media_type == ixgbe_media_type_backplane)
310 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
311 IXGBE_AUTOC_ASM_PAUSE;
312 else if (hw->phy.media_type == ixgbe_media_type_copper)
313 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
316 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
317 "Flow control param set incorrectly\n");
318 ret_val = IXGBE_ERR_CONFIG;
323 if (hw->mac.type < ixgbe_mac_X540) {
325 * Enable auto-negotiation between the MAC & PHY;
326 * the MAC will advertise clause 37 flow control.
328 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
329 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
331 /* Disable AN timeout */
332 if (hw->fc.strict_ieee)
333 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
335 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
336 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
340 * AUTOC restart handles negotiation of 1G and 10G on backplane
341 * and copper. There is no need to set the PCS1GCTL register.
344 if (hw->phy.media_type == ixgbe_media_type_backplane) {
345 reg_bp |= IXGBE_AUTOC_AN_RESTART;
346 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
349 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
350 (ixgbe_device_supports_autoneg_fc(hw))) {
351 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
352 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
355 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
361 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
362 * @hw: pointer to hardware structure
364 * Starts the hardware by filling the bus info structure and media type, clears
365 * all on chip counters, initializes receive address registers, multicast
366 * table, VLAN filter table, calls routine to set up link and flow control
367 * settings, and leaves transmit and receive units disabled and uninitialized
369 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
374 DEBUGFUNC("ixgbe_start_hw_generic");
376 /* Set the media type */
377 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
379 /* PHY ops initialization must be done in reset_hw() */
381 /* Clear the VLAN filter table */
382 hw->mac.ops.clear_vfta(hw);
384 /* Clear statistics registers */
385 hw->mac.ops.clear_hw_cntrs(hw);
387 /* Set No Snoop Disable */
388 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
389 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
390 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
391 IXGBE_WRITE_FLUSH(hw);
393 /* Setup flow control */
394 ret_val = ixgbe_setup_fc(hw);
395 if (ret_val != IXGBE_SUCCESS)
398 /* Clear adapter stopped flag */
399 hw->adapter_stopped = false;
406 * ixgbe_start_hw_gen2 - Init sequence for common device family
407 * @hw: pointer to hw structure
409 * Performs the init sequence common to the second generation
411 * Devices in the second generation:
415 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
420 /* Clear the rate limiters */
421 for (i = 0; i < hw->mac.max_tx_queues; i++) {
422 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
423 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
425 IXGBE_WRITE_FLUSH(hw);
427 /* Disable relaxed ordering */
428 for (i = 0; i < hw->mac.max_tx_queues; i++) {
429 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
430 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
431 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
434 for (i = 0; i < hw->mac.max_rx_queues; i++) {
435 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
436 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
437 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
438 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
441 return IXGBE_SUCCESS;
445 * ixgbe_init_hw_generic - Generic hardware initialization
446 * @hw: pointer to hardware structure
448 * Initialize the hardware by resetting the hardware, filling the bus info
449 * structure and media type, clears all on chip counters, initializes receive
450 * address registers, multicast table, VLAN filter table, calls routine to set
451 * up link and flow control settings, and leaves transmit and receive units
452 * disabled and uninitialized
454 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
458 DEBUGFUNC("ixgbe_init_hw_generic");
460 /* Reset the hardware */
461 status = hw->mac.ops.reset_hw(hw);
463 if (status == IXGBE_SUCCESS) {
465 status = hw->mac.ops.start_hw(hw);
472 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
473 * @hw: pointer to hardware structure
475 * Clears all hardware statistics counters by reading them from the hardware
476 * Statistics counters are clear on read.
478 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
482 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
484 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
485 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
486 IXGBE_READ_REG(hw, IXGBE_ERRBC);
487 IXGBE_READ_REG(hw, IXGBE_MSPDC);
488 for (i = 0; i < 8; i++)
489 IXGBE_READ_REG(hw, IXGBE_MPC(i));
491 IXGBE_READ_REG(hw, IXGBE_MLFC);
492 IXGBE_READ_REG(hw, IXGBE_MRFC);
493 IXGBE_READ_REG(hw, IXGBE_RLEC);
494 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
495 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
496 if (hw->mac.type >= ixgbe_mac_82599EB) {
497 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
498 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
500 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
501 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
504 for (i = 0; i < 8; i++) {
505 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
506 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
507 if (hw->mac.type >= ixgbe_mac_82599EB) {
508 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
509 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
511 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
512 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
515 if (hw->mac.type >= ixgbe_mac_82599EB)
516 for (i = 0; i < 8; i++)
517 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
518 IXGBE_READ_REG(hw, IXGBE_PRC64);
519 IXGBE_READ_REG(hw, IXGBE_PRC127);
520 IXGBE_READ_REG(hw, IXGBE_PRC255);
521 IXGBE_READ_REG(hw, IXGBE_PRC511);
522 IXGBE_READ_REG(hw, IXGBE_PRC1023);
523 IXGBE_READ_REG(hw, IXGBE_PRC1522);
524 IXGBE_READ_REG(hw, IXGBE_GPRC);
525 IXGBE_READ_REG(hw, IXGBE_BPRC);
526 IXGBE_READ_REG(hw, IXGBE_MPRC);
527 IXGBE_READ_REG(hw, IXGBE_GPTC);
528 IXGBE_READ_REG(hw, IXGBE_GORCL);
529 IXGBE_READ_REG(hw, IXGBE_GORCH);
530 IXGBE_READ_REG(hw, IXGBE_GOTCL);
531 IXGBE_READ_REG(hw, IXGBE_GOTCH);
532 if (hw->mac.type == ixgbe_mac_82598EB)
533 for (i = 0; i < 8; i++)
534 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
535 IXGBE_READ_REG(hw, IXGBE_RUC);
536 IXGBE_READ_REG(hw, IXGBE_RFC);
537 IXGBE_READ_REG(hw, IXGBE_ROC);
538 IXGBE_READ_REG(hw, IXGBE_RJC);
539 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
540 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
541 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
542 IXGBE_READ_REG(hw, IXGBE_TORL);
543 IXGBE_READ_REG(hw, IXGBE_TORH);
544 IXGBE_READ_REG(hw, IXGBE_TPR);
545 IXGBE_READ_REG(hw, IXGBE_TPT);
546 IXGBE_READ_REG(hw, IXGBE_PTC64);
547 IXGBE_READ_REG(hw, IXGBE_PTC127);
548 IXGBE_READ_REG(hw, IXGBE_PTC255);
549 IXGBE_READ_REG(hw, IXGBE_PTC511);
550 IXGBE_READ_REG(hw, IXGBE_PTC1023);
551 IXGBE_READ_REG(hw, IXGBE_PTC1522);
552 IXGBE_READ_REG(hw, IXGBE_MPTC);
553 IXGBE_READ_REG(hw, IXGBE_BPTC);
554 for (i = 0; i < 16; i++) {
555 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
556 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
557 if (hw->mac.type >= ixgbe_mac_82599EB) {
558 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
559 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
560 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
561 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
562 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
564 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
565 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
569 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
571 ixgbe_identify_phy(hw);
572 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
573 IXGBE_MDIO_PCS_DEV_TYPE, &i);
574 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
575 IXGBE_MDIO_PCS_DEV_TYPE, &i);
576 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
577 IXGBE_MDIO_PCS_DEV_TYPE, &i);
578 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
579 IXGBE_MDIO_PCS_DEV_TYPE, &i);
582 return IXGBE_SUCCESS;
586 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
587 * @hw: pointer to hardware structure
588 * @pba_num: stores the part number string from the EEPROM
589 * @pba_num_size: part number string buffer length
591 * Reads the part number string from the EEPROM.
593 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
602 DEBUGFUNC("ixgbe_read_pba_string_generic");
604 if (pba_num == NULL) {
605 DEBUGOUT("PBA string buffer was null\n");
606 return IXGBE_ERR_INVALID_ARGUMENT;
609 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
611 DEBUGOUT("NVM Read Error\n");
615 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
617 DEBUGOUT("NVM Read Error\n");
622 * if data is not ptr guard the PBA must be in legacy format which
623 * means pba_ptr is actually our second data word for the PBA number
624 * and we can decode it into an ascii string
626 if (data != IXGBE_PBANUM_PTR_GUARD) {
627 DEBUGOUT("NVM PBA number is not stored as string\n");
629 /* we will need 11 characters to store the PBA */
630 if (pba_num_size < 11) {
631 DEBUGOUT("PBA string buffer too small\n");
632 return IXGBE_ERR_NO_SPACE;
635 /* extract hex string from data and pba_ptr */
636 pba_num[0] = (data >> 12) & 0xF;
637 pba_num[1] = (data >> 8) & 0xF;
638 pba_num[2] = (data >> 4) & 0xF;
639 pba_num[3] = data & 0xF;
640 pba_num[4] = (pba_ptr >> 12) & 0xF;
641 pba_num[5] = (pba_ptr >> 8) & 0xF;
644 pba_num[8] = (pba_ptr >> 4) & 0xF;
645 pba_num[9] = pba_ptr & 0xF;
647 /* put a null character on the end of our string */
650 /* switch all the data but the '-' to hex char */
651 for (offset = 0; offset < 10; offset++) {
652 if (pba_num[offset] < 0xA)
653 pba_num[offset] += '0';
654 else if (pba_num[offset] < 0x10)
655 pba_num[offset] += 'A' - 0xA;
658 return IXGBE_SUCCESS;
661 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
663 DEBUGOUT("NVM Read Error\n");
667 if (length == 0xFFFF || length == 0) {
668 DEBUGOUT("NVM PBA number section invalid length\n");
669 return IXGBE_ERR_PBA_SECTION;
672 /* check if pba_num buffer is big enough */
673 if (pba_num_size < (((u32)length * 2) - 1)) {
674 DEBUGOUT("PBA string buffer too small\n");
675 return IXGBE_ERR_NO_SPACE;
678 /* trim pba length from start of string */
682 for (offset = 0; offset < length; offset++) {
683 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
685 DEBUGOUT("NVM Read Error\n");
688 pba_num[offset * 2] = (u8)(data >> 8);
689 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
691 pba_num[offset * 2] = '\0';
693 return IXGBE_SUCCESS;
697 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
698 * @hw: pointer to hardware structure
699 * @pba_num: stores the part number from the EEPROM
701 * Reads the part number from the EEPROM.
703 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
708 DEBUGFUNC("ixgbe_read_pba_num_generic");
710 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
712 DEBUGOUT("NVM Read Error\n");
714 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
715 DEBUGOUT("NVM Not supported\n");
716 return IXGBE_NOT_IMPLEMENTED;
718 *pba_num = (u32)(data << 16);
720 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
722 DEBUGOUT("NVM Read Error\n");
727 return IXGBE_SUCCESS;
732 * @hw: pointer to the HW structure
733 * @eeprom_buf: optional pointer to EEPROM image
734 * @eeprom_buf_size: size of EEPROM image in words
735 * @max_pba_block_size: PBA block size limit
736 * @pba: pointer to output PBA structure
738 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
739 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
742 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
743 u32 eeprom_buf_size, u16 max_pba_block_size,
744 struct ixgbe_pba *pba)
750 return IXGBE_ERR_PARAM;
752 if (eeprom_buf == NULL) {
753 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
758 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
759 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
760 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
762 return IXGBE_ERR_PARAM;
766 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
767 if (pba->pba_block == NULL)
768 return IXGBE_ERR_PARAM;
770 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
776 if (pba_block_size > max_pba_block_size)
777 return IXGBE_ERR_PARAM;
779 if (eeprom_buf == NULL) {
780 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
786 if (eeprom_buf_size > (u32)(pba->word[1] +
788 memcpy(pba->pba_block,
789 &eeprom_buf[pba->word[1]],
790 pba_block_size * sizeof(u16));
792 return IXGBE_ERR_PARAM;
797 return IXGBE_SUCCESS;
801 * ixgbe_write_pba_raw
802 * @hw: pointer to the HW structure
803 * @eeprom_buf: optional pointer to EEPROM image
804 * @eeprom_buf_size: size of EEPROM image in words
805 * @pba: pointer to PBA structure
807 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
808 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
811 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
812 u32 eeprom_buf_size, struct ixgbe_pba *pba)
817 return IXGBE_ERR_PARAM;
819 if (eeprom_buf == NULL) {
820 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
825 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
826 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
827 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
829 return IXGBE_ERR_PARAM;
833 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
834 if (pba->pba_block == NULL)
835 return IXGBE_ERR_PARAM;
837 if (eeprom_buf == NULL) {
838 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
844 if (eeprom_buf_size > (u32)(pba->word[1] +
845 pba->pba_block[0])) {
846 memcpy(&eeprom_buf[pba->word[1]],
848 pba->pba_block[0] * sizeof(u16));
850 return IXGBE_ERR_PARAM;
855 return IXGBE_SUCCESS;
859 * ixgbe_get_pba_block_size
860 * @hw: pointer to the HW structure
861 * @eeprom_buf: optional pointer to EEPROM image
862 * @eeprom_buf_size: size of EEPROM image in words
863 * @pba_data_size: pointer to output variable
865 * Returns the size of the PBA block in words. Function operates on EEPROM
866 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
870 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
871 u32 eeprom_buf_size, u16 *pba_block_size)
877 DEBUGFUNC("ixgbe_get_pba_block_size");
879 if (eeprom_buf == NULL) {
880 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
885 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
886 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
887 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
889 return IXGBE_ERR_PARAM;
893 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
894 if (eeprom_buf == NULL) {
895 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
900 if (eeprom_buf_size > pba_word[1])
901 length = eeprom_buf[pba_word[1] + 0];
903 return IXGBE_ERR_PARAM;
906 if (length == 0xFFFF || length == 0)
907 return IXGBE_ERR_PBA_SECTION;
909 /* PBA number in legacy format, there is no PBA Block. */
913 if (pba_block_size != NULL)
914 *pba_block_size = length;
916 return IXGBE_SUCCESS;
920 * ixgbe_get_mac_addr_generic - Generic get MAC address
921 * @hw: pointer to hardware structure
922 * @mac_addr: Adapter MAC address
924 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
925 * A reset of the adapter must be performed prior to calling this function
926 * in order for the MAC address to have been loaded from the EEPROM into RAR0
928 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
934 DEBUGFUNC("ixgbe_get_mac_addr_generic");
936 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
937 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
939 for (i = 0; i < 4; i++)
940 mac_addr[i] = (u8)(rar_low >> (i*8));
942 for (i = 0; i < 2; i++)
943 mac_addr[i+4] = (u8)(rar_high >> (i*8));
945 return IXGBE_SUCCESS;
949 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
950 * @hw: pointer to hardware structure
951 * @link_status: the link status returned by the PCI config space
953 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
955 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
957 struct ixgbe_mac_info *mac = &hw->mac;
959 if (hw->bus.type == ixgbe_bus_type_unknown)
960 hw->bus.type = ixgbe_bus_type_pci_express;
962 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
963 case IXGBE_PCI_LINK_WIDTH_1:
964 hw->bus.width = ixgbe_bus_width_pcie_x1;
966 case IXGBE_PCI_LINK_WIDTH_2:
967 hw->bus.width = ixgbe_bus_width_pcie_x2;
969 case IXGBE_PCI_LINK_WIDTH_4:
970 hw->bus.width = ixgbe_bus_width_pcie_x4;
972 case IXGBE_PCI_LINK_WIDTH_8:
973 hw->bus.width = ixgbe_bus_width_pcie_x8;
976 hw->bus.width = ixgbe_bus_width_unknown;
980 switch (link_status & IXGBE_PCI_LINK_SPEED) {
981 case IXGBE_PCI_LINK_SPEED_2500:
982 hw->bus.speed = ixgbe_bus_speed_2500;
984 case IXGBE_PCI_LINK_SPEED_5000:
985 hw->bus.speed = ixgbe_bus_speed_5000;
987 case IXGBE_PCI_LINK_SPEED_8000:
988 hw->bus.speed = ixgbe_bus_speed_8000;
991 hw->bus.speed = ixgbe_bus_speed_unknown;
995 mac->ops.set_lan_id(hw);
999 * ixgbe_get_bus_info_generic - Generic set PCI bus info
1000 * @hw: pointer to hardware structure
1002 * Gets the PCI bus info (speed, width, type) then calls helper function to
1003 * store this data within the ixgbe_hw structure.
1005 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
1009 DEBUGFUNC("ixgbe_get_bus_info_generic");
1011 /* Get the negotiated link width and speed from PCI config space */
1012 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
1014 ixgbe_set_pci_config_data_generic(hw, link_status);
1016 return IXGBE_SUCCESS;
1020 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
1021 * @hw: pointer to the HW structure
1023 * Determines the LAN function id by reading memory-mapped registers
1024 * and swaps the port value if requested.
1026 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
1028 struct ixgbe_bus_info *bus = &hw->bus;
1031 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
1033 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
1034 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
1035 bus->lan_id = bus->func;
1037 /* check for a port swap */
1038 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
1039 if (reg & IXGBE_FACTPS_LFS)
1044 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1045 * @hw: pointer to hardware structure
1047 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
1048 * disables transmit and receive units. The adapter_stopped flag is used by
1049 * the shared code and drivers to determine if the adapter is in a stopped
1050 * state and should not touch the hardware.
1052 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1057 DEBUGFUNC("ixgbe_stop_adapter_generic");
1060 * Set the adapter_stopped flag so other driver functions stop touching
1063 hw->adapter_stopped = true;
1065 /* Disable the receive unit */
1066 ixgbe_disable_rx(hw);
1068 /* Clear interrupt mask to stop interrupts from being generated */
1069 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1071 /* Clear any pending interrupts, flush previous writes */
1072 IXGBE_READ_REG(hw, IXGBE_EICR);
1074 /* Disable the transmit unit. Each queue must be disabled. */
1075 for (i = 0; i < hw->mac.max_tx_queues; i++)
1076 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1078 /* Disable the receive unit by stopping each queue */
1079 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1080 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1081 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1082 reg_val |= IXGBE_RXDCTL_SWFLSH;
1083 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1086 /* flush all queues disables */
1087 IXGBE_WRITE_FLUSH(hw);
1091 * Prevent the PCI-E bus from hanging by disabling PCI-E master
1092 * access and verify no pending requests
1094 return ixgbe_disable_pcie_master(hw);
1098 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1099 * @hw: pointer to hardware structure
1100 * @index: led number to turn on
1102 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1104 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1106 DEBUGFUNC("ixgbe_led_on_generic");
1108 /* To turn on the LED, set mode to ON. */
1109 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1110 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
1111 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1112 IXGBE_WRITE_FLUSH(hw);
1114 return IXGBE_SUCCESS;
1118 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1119 * @hw: pointer to hardware structure
1120 * @index: led number to turn off
1122 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1124 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1126 DEBUGFUNC("ixgbe_led_off_generic");
1128 /* To turn off the LED, set mode to OFF. */
1129 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1130 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
1131 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1132 IXGBE_WRITE_FLUSH(hw);
1134 return IXGBE_SUCCESS;
1138 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1139 * @hw: pointer to hardware structure
1141 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1142 * ixgbe_hw struct in order to set up EEPROM access.
1144 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1146 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1150 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
1152 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1153 eeprom->type = ixgbe_eeprom_none;
1154 /* Set default semaphore delay to 10ms which is a well
1156 eeprom->semaphore_delay = 10;
1157 /* Clear EEPROM page size, it will be initialized as needed */
1158 eeprom->word_page_size = 0;
1161 * Check for EEPROM present first.
1162 * If not present leave as none
1164 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1165 if (eec & IXGBE_EEC_PRES) {
1166 eeprom->type = ixgbe_eeprom_spi;
1169 * SPI EEPROM is assumed here. This code would need to
1170 * change if a future EEPROM is not SPI.
1172 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1173 IXGBE_EEC_SIZE_SHIFT);
1174 eeprom->word_size = 1 << (eeprom_size +
1175 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1178 if (eec & IXGBE_EEC_ADDR_SIZE)
1179 eeprom->address_bits = 16;
1181 eeprom->address_bits = 8;
1182 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
1183 "%d\n", eeprom->type, eeprom->word_size,
1184 eeprom->address_bits);
1187 return IXGBE_SUCCESS;
1191 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1192 * @hw: pointer to hardware structure
1193 * @offset: offset within the EEPROM to write
1194 * @words: number of word(s)
1195 * @data: 16 bit word(s) to write to EEPROM
1197 * Reads 16 bit word(s) from EEPROM through bit-bang method
1199 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1200 u16 words, u16 *data)
1202 s32 status = IXGBE_SUCCESS;
1205 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
1207 hw->eeprom.ops.init_params(hw);
1210 status = IXGBE_ERR_INVALID_ARGUMENT;
1214 if (offset + words > hw->eeprom.word_size) {
1215 status = IXGBE_ERR_EEPROM;
1220 * The EEPROM page size cannot be queried from the chip. We do lazy
1221 * initialization. It is worth to do that when we write large buffer.
1223 if ((hw->eeprom.word_page_size == 0) &&
1224 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
1225 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1228 * We cannot hold synchronization semaphores for too long
1229 * to avoid other entity starvation. However it is more efficient
1230 * to read in bursts than synchronizing access for each word.
1232 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1233 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1234 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1235 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1238 if (status != IXGBE_SUCCESS)
1247 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1248 * @hw: pointer to hardware structure
1249 * @offset: offset within the EEPROM to be written to
1250 * @words: number of word(s)
1251 * @data: 16 bit word(s) to be written to the EEPROM
1253 * If ixgbe_eeprom_update_checksum is not called after this function, the
1254 * EEPROM will most likely contain an invalid checksum.
1256 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1257 u16 words, u16 *data)
1263 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1265 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1267 /* Prepare the EEPROM for writing */
1268 status = ixgbe_acquire_eeprom(hw);
1270 if (status == IXGBE_SUCCESS) {
1271 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1272 ixgbe_release_eeprom(hw);
1273 status = IXGBE_ERR_EEPROM;
1277 if (status == IXGBE_SUCCESS) {
1278 for (i = 0; i < words; i++) {
1279 ixgbe_standby_eeprom(hw);
1281 /* Send the WRITE ENABLE command (8 bit opcode ) */
1282 ixgbe_shift_out_eeprom_bits(hw,
1283 IXGBE_EEPROM_WREN_OPCODE_SPI,
1284 IXGBE_EEPROM_OPCODE_BITS);
1286 ixgbe_standby_eeprom(hw);
1289 * Some SPI eeproms use the 8th address bit embedded
1292 if ((hw->eeprom.address_bits == 8) &&
1293 ((offset + i) >= 128))
1294 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1296 /* Send the Write command (8-bit opcode + addr) */
1297 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1298 IXGBE_EEPROM_OPCODE_BITS);
1299 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1300 hw->eeprom.address_bits);
1302 page_size = hw->eeprom.word_page_size;
1304 /* Send the data in burst via SPI*/
1307 word = (word >> 8) | (word << 8);
1308 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1313 /* do not wrap around page */
1314 if (((offset + i) & (page_size - 1)) ==
1317 } while (++i < words);
1319 ixgbe_standby_eeprom(hw);
1322 /* Done with writing - release the EEPROM */
1323 ixgbe_release_eeprom(hw);
1330 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1331 * @hw: pointer to hardware structure
1332 * @offset: offset within the EEPROM to be written to
1333 * @data: 16 bit word to be written to the EEPROM
1335 * If ixgbe_eeprom_update_checksum is not called after this function, the
1336 * EEPROM will most likely contain an invalid checksum.
1338 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1342 DEBUGFUNC("ixgbe_write_eeprom_generic");
1344 hw->eeprom.ops.init_params(hw);
1346 if (offset >= hw->eeprom.word_size) {
1347 status = IXGBE_ERR_EEPROM;
1351 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1358 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1359 * @hw: pointer to hardware structure
1360 * @offset: offset within the EEPROM to be read
1361 * @data: read 16 bit words(s) from EEPROM
1362 * @words: number of word(s)
1364 * Reads 16 bit word(s) from EEPROM through bit-bang method
1366 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1367 u16 words, u16 *data)
1369 s32 status = IXGBE_SUCCESS;
1372 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1374 hw->eeprom.ops.init_params(hw);
1377 status = IXGBE_ERR_INVALID_ARGUMENT;
1381 if (offset + words > hw->eeprom.word_size) {
1382 status = IXGBE_ERR_EEPROM;
1387 * We cannot hold synchronization semaphores for too long
1388 * to avoid other entity starvation. However it is more efficient
1389 * to read in bursts than synchronizing access for each word.
1391 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1392 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1393 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1395 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1398 if (status != IXGBE_SUCCESS)
1407 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1408 * @hw: pointer to hardware structure
1409 * @offset: offset within the EEPROM to be read
1410 * @words: number of word(s)
1411 * @data: read 16 bit word(s) from EEPROM
1413 * Reads 16 bit word(s) from EEPROM through bit-bang method
1415 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1416 u16 words, u16 *data)
1420 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1423 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1425 /* Prepare the EEPROM for reading */
1426 status = ixgbe_acquire_eeprom(hw);
1428 if (status == IXGBE_SUCCESS) {
1429 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1430 ixgbe_release_eeprom(hw);
1431 status = IXGBE_ERR_EEPROM;
1435 if (status == IXGBE_SUCCESS) {
1436 for (i = 0; i < words; i++) {
1437 ixgbe_standby_eeprom(hw);
1439 * Some SPI eeproms use the 8th address bit embedded
1442 if ((hw->eeprom.address_bits == 8) &&
1443 ((offset + i) >= 128))
1444 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1446 /* Send the READ command (opcode + addr) */
1447 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1448 IXGBE_EEPROM_OPCODE_BITS);
1449 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1450 hw->eeprom.address_bits);
1452 /* Read the data. */
1453 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1454 data[i] = (word_in >> 8) | (word_in << 8);
1457 /* End this read operation */
1458 ixgbe_release_eeprom(hw);
1465 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1466 * @hw: pointer to hardware structure
1467 * @offset: offset within the EEPROM to be read
1468 * @data: read 16 bit value from EEPROM
1470 * Reads 16 bit value from EEPROM through bit-bang method
1472 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1477 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1479 hw->eeprom.ops.init_params(hw);
1481 if (offset >= hw->eeprom.word_size) {
1482 status = IXGBE_ERR_EEPROM;
1486 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1493 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1494 * @hw: pointer to hardware structure
1495 * @offset: offset of word in the EEPROM to read
1496 * @words: number of word(s)
1497 * @data: 16 bit word(s) from the EEPROM
1499 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1501 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1502 u16 words, u16 *data)
1505 s32 status = IXGBE_SUCCESS;
1508 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1510 hw->eeprom.ops.init_params(hw);
1513 status = IXGBE_ERR_INVALID_ARGUMENT;
1514 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1518 if (offset >= hw->eeprom.word_size) {
1519 status = IXGBE_ERR_EEPROM;
1520 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1524 for (i = 0; i < words; i++) {
1525 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1526 IXGBE_EEPROM_RW_REG_START;
1528 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1529 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1531 if (status == IXGBE_SUCCESS) {
1532 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1533 IXGBE_EEPROM_RW_REG_DATA);
1535 DEBUGOUT("Eeprom read timed out\n");
1544 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1545 * @hw: pointer to hardware structure
1546 * @offset: offset within the EEPROM to be used as a scratch pad
1548 * Discover EEPROM page size by writing marching data at given offset.
1549 * This function is called only when we are writing a new large buffer
1550 * at given offset so the data would be overwritten anyway.
1552 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1555 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1556 s32 status = IXGBE_SUCCESS;
1559 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1561 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1564 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1565 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1566 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1567 hw->eeprom.word_page_size = 0;
1568 if (status != IXGBE_SUCCESS)
1571 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1572 if (status != IXGBE_SUCCESS)
1576 * When writing in burst more than the actual page size
1577 * EEPROM address wraps around current page.
1579 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1581 DEBUGOUT1("Detected EEPROM page size = %d words.",
1582 hw->eeprom.word_page_size);
1588 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1589 * @hw: pointer to hardware structure
1590 * @offset: offset of word in the EEPROM to read
1591 * @data: word read from the EEPROM
1593 * Reads a 16 bit word from the EEPROM using the EERD register.
1595 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1597 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1601 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1602 * @hw: pointer to hardware structure
1603 * @offset: offset of word in the EEPROM to write
1604 * @words: number of word(s)
1605 * @data: word(s) write to the EEPROM
1607 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1609 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1610 u16 words, u16 *data)
1613 s32 status = IXGBE_SUCCESS;
1616 DEBUGFUNC("ixgbe_write_eewr_generic");
1618 hw->eeprom.ops.init_params(hw);
1621 status = IXGBE_ERR_INVALID_ARGUMENT;
1622 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1626 if (offset >= hw->eeprom.word_size) {
1627 status = IXGBE_ERR_EEPROM;
1628 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1632 for (i = 0; i < words; i++) {
1633 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1634 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1635 IXGBE_EEPROM_RW_REG_START;
1637 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1638 if (status != IXGBE_SUCCESS) {
1639 DEBUGOUT("Eeprom write EEWR timed out\n");
1643 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1645 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1646 if (status != IXGBE_SUCCESS) {
1647 DEBUGOUT("Eeprom write EEWR timed out\n");
1657 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1658 * @hw: pointer to hardware structure
1659 * @offset: offset of word in the EEPROM to write
1660 * @data: word write to the EEPROM
1662 * Write a 16 bit word to the EEPROM using the EEWR register.
1664 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1666 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1670 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1671 * @hw: pointer to hardware structure
1672 * @ee_reg: EEPROM flag for polling
1674 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1675 * read or write is done respectively.
1677 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1681 s32 status = IXGBE_ERR_EEPROM;
1683 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1685 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1686 if (ee_reg == IXGBE_NVM_POLL_READ)
1687 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1689 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1691 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1692 status = IXGBE_SUCCESS;
1698 if (i == IXGBE_EERD_EEWR_ATTEMPTS)
1699 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1700 "EEPROM read/write done polling timed out");
1706 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1707 * @hw: pointer to hardware structure
1709 * Prepares EEPROM for access using bit-bang method. This function should
1710 * be called before issuing a command to the EEPROM.
1712 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1714 s32 status = IXGBE_SUCCESS;
1718 DEBUGFUNC("ixgbe_acquire_eeprom");
1720 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1722 status = IXGBE_ERR_SWFW_SYNC;
1724 if (status == IXGBE_SUCCESS) {
1725 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1727 /* Request EEPROM Access */
1728 eec |= IXGBE_EEC_REQ;
1729 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1731 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1732 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1733 if (eec & IXGBE_EEC_GNT)
1738 /* Release if grant not acquired */
1739 if (!(eec & IXGBE_EEC_GNT)) {
1740 eec &= ~IXGBE_EEC_REQ;
1741 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1742 DEBUGOUT("Could not acquire EEPROM grant\n");
1744 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1745 status = IXGBE_ERR_EEPROM;
1748 /* Setup EEPROM for Read/Write */
1749 if (status == IXGBE_SUCCESS) {
1750 /* Clear CS and SK */
1751 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1752 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1753 IXGBE_WRITE_FLUSH(hw);
1761 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1762 * @hw: pointer to hardware structure
1764 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1766 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1768 s32 status = IXGBE_ERR_EEPROM;
1773 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1776 /* Get SMBI software semaphore between device drivers first */
1777 for (i = 0; i < timeout; i++) {
1779 * If the SMBI bit is 0 when we read it, then the bit will be
1780 * set and we have the semaphore
1782 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1783 if (!(swsm & IXGBE_SWSM_SMBI)) {
1784 status = IXGBE_SUCCESS;
1791 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1794 * this release is particularly important because our attempts
1795 * above to get the semaphore may have succeeded, and if there
1796 * was a timeout, we should unconditionally clear the semaphore
1797 * bits to free the driver to make progress
1799 ixgbe_release_eeprom_semaphore(hw);
1804 * If the SMBI bit is 0 when we read it, then the bit will be
1805 * set and we have the semaphore
1807 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1808 if (!(swsm & IXGBE_SWSM_SMBI))
1809 status = IXGBE_SUCCESS;
1812 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1813 if (status == IXGBE_SUCCESS) {
1814 for (i = 0; i < timeout; i++) {
1815 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1817 /* Set the SW EEPROM semaphore bit to request access */
1818 swsm |= IXGBE_SWSM_SWESMBI;
1819 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
1822 * If we set the bit successfully then we got the
1825 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1826 if (swsm & IXGBE_SWSM_SWESMBI)
1833 * Release semaphores and return error if SW EEPROM semaphore
1834 * was not granted because we don't have access to the EEPROM
1837 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1838 "SWESMBI Software EEPROM semaphore not granted.\n");
1839 ixgbe_release_eeprom_semaphore(hw);
1840 status = IXGBE_ERR_EEPROM;
1843 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1844 "Software semaphore SMBI between device drivers "
1852 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1853 * @hw: pointer to hardware structure
1855 * This function clears hardware semaphore bits.
1857 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1861 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1863 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1865 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1866 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1867 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1868 IXGBE_WRITE_FLUSH(hw);
1872 * ixgbe_ready_eeprom - Polls for EEPROM ready
1873 * @hw: pointer to hardware structure
1875 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1877 s32 status = IXGBE_SUCCESS;
1881 DEBUGFUNC("ixgbe_ready_eeprom");
1884 * Read "Status Register" repeatedly until the LSB is cleared. The
1885 * EEPROM will signal that the command has been completed by clearing
1886 * bit 0 of the internal status register. If it's not cleared within
1887 * 5 milliseconds, then error out.
1889 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1890 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1891 IXGBE_EEPROM_OPCODE_BITS);
1892 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1893 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1897 ixgbe_standby_eeprom(hw);
1901 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1902 * devices (and only 0-5mSec on 5V devices)
1904 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1905 DEBUGOUT("SPI EEPROM Status error\n");
1906 status = IXGBE_ERR_EEPROM;
1913 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1914 * @hw: pointer to hardware structure
1916 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1920 DEBUGFUNC("ixgbe_standby_eeprom");
1922 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1924 /* Toggle CS to flush commands */
1925 eec |= IXGBE_EEC_CS;
1926 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1927 IXGBE_WRITE_FLUSH(hw);
1929 eec &= ~IXGBE_EEC_CS;
1930 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1931 IXGBE_WRITE_FLUSH(hw);
1936 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1937 * @hw: pointer to hardware structure
1938 * @data: data to send to the EEPROM
1939 * @count: number of bits to shift out
1941 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1948 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
1950 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1953 * Mask is used to shift "count" bits of "data" out to the EEPROM
1954 * one bit at a time. Determine the starting bit based on count
1956 mask = 0x01 << (count - 1);
1958 for (i = 0; i < count; i++) {
1960 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1961 * "1", and then raising and then lowering the clock (the SK
1962 * bit controls the clock input to the EEPROM). A "0" is
1963 * shifted out to the EEPROM by setting "DI" to "0" and then
1964 * raising and then lowering the clock.
1967 eec |= IXGBE_EEC_DI;
1969 eec &= ~IXGBE_EEC_DI;
1971 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1972 IXGBE_WRITE_FLUSH(hw);
1976 ixgbe_raise_eeprom_clk(hw, &eec);
1977 ixgbe_lower_eeprom_clk(hw, &eec);
1980 * Shift mask to signify next bit of data to shift in to the
1986 /* We leave the "DI" bit set to "0" when we leave this routine. */
1987 eec &= ~IXGBE_EEC_DI;
1988 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1989 IXGBE_WRITE_FLUSH(hw);
1993 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1994 * @hw: pointer to hardware structure
1996 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
2002 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
2005 * In order to read a register from the EEPROM, we need to shift
2006 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
2007 * the clock input to the EEPROM (setting the SK bit), and then reading
2008 * the value of the "DO" bit. During this "shifting in" process the
2009 * "DI" bit should always be clear.
2011 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2013 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
2015 for (i = 0; i < count; i++) {
2017 ixgbe_raise_eeprom_clk(hw, &eec);
2019 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2021 eec &= ~(IXGBE_EEC_DI);
2022 if (eec & IXGBE_EEC_DO)
2025 ixgbe_lower_eeprom_clk(hw, &eec);
2032 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
2033 * @hw: pointer to hardware structure
2034 * @eec: EEC register's current value
2036 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2038 DEBUGFUNC("ixgbe_raise_eeprom_clk");
2041 * Raise the clock input to the EEPROM
2042 * (setting the SK bit), then delay
2044 *eec = *eec | IXGBE_EEC_SK;
2045 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2046 IXGBE_WRITE_FLUSH(hw);
2051 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2052 * @hw: pointer to hardware structure
2053 * @eecd: EECD's current value
2055 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2057 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2060 * Lower the clock input to the EEPROM (clearing the SK bit), then
2063 *eec = *eec & ~IXGBE_EEC_SK;
2064 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2065 IXGBE_WRITE_FLUSH(hw);
2070 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2071 * @hw: pointer to hardware structure
2073 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2077 DEBUGFUNC("ixgbe_release_eeprom");
2079 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2081 eec |= IXGBE_EEC_CS; /* Pull CS high */
2082 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
2084 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2085 IXGBE_WRITE_FLUSH(hw);
2089 /* Stop requesting EEPROM access */
2090 eec &= ~IXGBE_EEC_REQ;
2091 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2093 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2095 /* Delay before attempt to obtain semaphore again to allow FW access */
2096 msec_delay(hw->eeprom.semaphore_delay);
2100 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2101 * @hw: pointer to hardware structure
2103 * Returns a negative error code on error, or the 16-bit checksum
2105 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2114 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
2116 /* Include 0x0-0x3F in the checksum */
2117 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
2118 if (hw->eeprom.ops.read(hw, i, &word)) {
2119 DEBUGOUT("EEPROM read failed\n");
2120 return IXGBE_ERR_EEPROM;
2125 /* Include all data from pointers except for the fw pointer */
2126 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
2127 if (hw->eeprom.ops.read(hw, i, &pointer)) {
2128 DEBUGOUT("EEPROM read failed\n");
2129 return IXGBE_ERR_EEPROM;
2132 /* If the pointer seems invalid */
2133 if (pointer == 0xFFFF || pointer == 0)
2136 if (hw->eeprom.ops.read(hw, pointer, &length)) {
2137 DEBUGOUT("EEPROM read failed\n");
2138 return IXGBE_ERR_EEPROM;
2141 if (length == 0xFFFF || length == 0)
2144 for (j = pointer + 1; j <= pointer + length; j++) {
2145 if (hw->eeprom.ops.read(hw, j, &word)) {
2146 DEBUGOUT("EEPROM read failed\n");
2147 return IXGBE_ERR_EEPROM;
2153 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2155 return (s32)checksum;
2159 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2160 * @hw: pointer to hardware structure
2161 * @checksum_val: calculated checksum
2163 * Performs checksum calculation and validates the EEPROM checksum. If the
2164 * caller does not need checksum_val, the value can be NULL.
2166 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2171 u16 read_checksum = 0;
2173 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
2175 /* Read the first word from the EEPROM. If this times out or fails, do
2176 * not continue or we could be in for a very long wait while every
2179 status = hw->eeprom.ops.read(hw, 0, &checksum);
2181 DEBUGOUT("EEPROM read failed\n");
2185 status = hw->eeprom.ops.calc_checksum(hw);
2189 checksum = (u16)(status & 0xffff);
2191 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2193 DEBUGOUT("EEPROM read failed\n");
2197 /* Verify read checksum from EEPROM is the same as
2198 * calculated checksum
2200 if (read_checksum != checksum)
2201 status = IXGBE_ERR_EEPROM_CHECKSUM;
2203 /* If the user cares, return the calculated checksum */
2205 *checksum_val = checksum;
2211 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2212 * @hw: pointer to hardware structure
2214 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2219 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
2221 /* Read the first word from the EEPROM. If this times out or fails, do
2222 * not continue or we could be in for a very long wait while every
2225 status = hw->eeprom.ops.read(hw, 0, &checksum);
2227 DEBUGOUT("EEPROM read failed\n");
2231 status = hw->eeprom.ops.calc_checksum(hw);
2235 checksum = (u16)(status & 0xffff);
2237 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
2243 * ixgbe_validate_mac_addr - Validate MAC address
2244 * @mac_addr: pointer to MAC address.
2246 * Tests a MAC address to ensure it is a valid Individual Address.
2248 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
2250 s32 status = IXGBE_SUCCESS;
2252 DEBUGFUNC("ixgbe_validate_mac_addr");
2254 /* Make sure it is not a multicast address */
2255 if (IXGBE_IS_MULTICAST(mac_addr)) {
2256 status = IXGBE_ERR_INVALID_MAC_ADDR;
2257 /* Not a broadcast address */
2258 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
2259 status = IXGBE_ERR_INVALID_MAC_ADDR;
2260 /* Reject the zero address */
2261 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
2262 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
2263 status = IXGBE_ERR_INVALID_MAC_ADDR;
2269 * ixgbe_set_rar_generic - Set Rx address register
2270 * @hw: pointer to hardware structure
2271 * @index: Receive address register to write
2272 * @addr: Address to put into receive address register
2273 * @vmdq: VMDq "set" or "pool" index
2274 * @enable_addr: set flag that address is active
2276 * Puts an ethernet address into a receive address register.
2278 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2281 u32 rar_low, rar_high;
2282 u32 rar_entries = hw->mac.num_rar_entries;
2284 DEBUGFUNC("ixgbe_set_rar_generic");
2286 /* Make sure we are using a valid rar index range */
2287 if (index >= rar_entries) {
2288 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2289 "RAR index %d is out of range.\n", index);
2290 return IXGBE_ERR_INVALID_ARGUMENT;
2293 /* setup VMDq pool selection before this RAR gets enabled */
2294 hw->mac.ops.set_vmdq(hw, index, vmdq);
2297 * HW expects these in little endian so we reverse the byte
2298 * order from network order (big endian) to little endian
2300 rar_low = ((u32)addr[0] |
2301 ((u32)addr[1] << 8) |
2302 ((u32)addr[2] << 16) |
2303 ((u32)addr[3] << 24));
2305 * Some parts put the VMDq setting in the extra RAH bits,
2306 * so save everything except the lower 16 bits that hold part
2307 * of the address and the address valid bit.
2309 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2310 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2311 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2313 if (enable_addr != 0)
2314 rar_high |= IXGBE_RAH_AV;
2316 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2317 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2319 return IXGBE_SUCCESS;
2323 * ixgbe_clear_rar_generic - Remove Rx address register
2324 * @hw: pointer to hardware structure
2325 * @index: Receive address register to write
2327 * Clears an ethernet address from a receive address register.
2329 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2332 u32 rar_entries = hw->mac.num_rar_entries;
2334 DEBUGFUNC("ixgbe_clear_rar_generic");
2336 /* Make sure we are using a valid rar index range */
2337 if (index >= rar_entries) {
2338 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2339 "RAR index %d is out of range.\n", index);
2340 return IXGBE_ERR_INVALID_ARGUMENT;
2344 * Some parts put the VMDq setting in the extra RAH bits,
2345 * so save everything except the lower 16 bits that hold part
2346 * of the address and the address valid bit.
2348 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2349 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2351 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2352 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2354 /* clear VMDq pool/queue selection for this RAR */
2355 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2357 return IXGBE_SUCCESS;
2361 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2362 * @hw: pointer to hardware structure
2364 * Places the MAC address in receive address register 0 and clears the rest
2365 * of the receive address registers. Clears the multicast table. Assumes
2366 * the receiver is in reset when the routine is called.
2368 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2371 u32 rar_entries = hw->mac.num_rar_entries;
2373 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2376 * If the current mac address is valid, assume it is a software override
2377 * to the permanent address.
2378 * Otherwise, use the permanent address from the eeprom.
2380 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2381 IXGBE_ERR_INVALID_MAC_ADDR) {
2382 /* Get the MAC address from the RAR0 for later reference */
2383 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2385 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2386 hw->mac.addr[0], hw->mac.addr[1],
2388 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2389 hw->mac.addr[4], hw->mac.addr[5]);
2391 /* Setup the receive address. */
2392 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2393 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2394 hw->mac.addr[0], hw->mac.addr[1],
2396 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2397 hw->mac.addr[4], hw->mac.addr[5]);
2399 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2401 /* clear VMDq pool/queue selection for RAR 0 */
2402 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2404 hw->addr_ctrl.overflow_promisc = 0;
2406 hw->addr_ctrl.rar_used_count = 1;
2408 /* Zero out the other receive addresses. */
2409 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2410 for (i = 1; i < rar_entries; i++) {
2411 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2412 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2416 hw->addr_ctrl.mta_in_use = 0;
2417 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2419 DEBUGOUT(" Clearing MTA\n");
2420 for (i = 0; i < hw->mac.mcft_size; i++)
2421 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2423 ixgbe_init_uta_tables(hw);
2425 return IXGBE_SUCCESS;
2429 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2430 * @hw: pointer to hardware structure
2431 * @addr: new address
2433 * Adds it to unused receive address register or goes into promiscuous mode.
2435 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2437 u32 rar_entries = hw->mac.num_rar_entries;
2440 DEBUGFUNC("ixgbe_add_uc_addr");
2442 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2443 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2446 * Place this address in the RAR if there is room,
2447 * else put the controller into promiscuous mode
2449 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2450 rar = hw->addr_ctrl.rar_used_count;
2451 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2452 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2453 hw->addr_ctrl.rar_used_count++;
2455 hw->addr_ctrl.overflow_promisc++;
2458 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2462 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2463 * @hw: pointer to hardware structure
2464 * @addr_list: the list of new addresses
2465 * @addr_count: number of addresses
2466 * @next: iterator function to walk the address list
2468 * The given list replaces any existing list. Clears the secondary addrs from
2469 * receive address registers. Uses unused receive address registers for the
2470 * first secondary addresses, and falls back to promiscuous mode as needed.
2472 * Drivers using secondary unicast addresses must set user_set_promisc when
2473 * manually putting the device into promiscuous mode.
2475 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2476 u32 addr_count, ixgbe_mc_addr_itr next)
2480 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2485 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2488 * Clear accounting of old secondary address list,
2489 * don't count RAR[0]
2491 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2492 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2493 hw->addr_ctrl.overflow_promisc = 0;
2495 /* Zero out the other receive addresses */
2496 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2497 for (i = 0; i < uc_addr_in_use; i++) {
2498 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2499 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2502 /* Add the new addresses */
2503 for (i = 0; i < addr_count; i++) {
2504 DEBUGOUT(" Adding the secondary addresses:\n");
2505 addr = next(hw, &addr_list, &vmdq);
2506 ixgbe_add_uc_addr(hw, addr, vmdq);
2509 if (hw->addr_ctrl.overflow_promisc) {
2510 /* enable promisc if not already in overflow or set by user */
2511 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2512 DEBUGOUT(" Entering address overflow promisc mode\n");
2513 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2514 fctrl |= IXGBE_FCTRL_UPE;
2515 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2518 /* only disable if set by overflow, not by user */
2519 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2520 DEBUGOUT(" Leaving address overflow promisc mode\n");
2521 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2522 fctrl &= ~IXGBE_FCTRL_UPE;
2523 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2527 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2528 return IXGBE_SUCCESS;
2532 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2533 * @hw: pointer to hardware structure
2534 * @mc_addr: the multicast address
2536 * Extracts the 12 bits, from a multicast address, to determine which
2537 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2538 * incoming rx multicast addresses, to determine the bit-vector to check in
2539 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2540 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2541 * to mc_filter_type.
2543 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2547 DEBUGFUNC("ixgbe_mta_vector");
2549 switch (hw->mac.mc_filter_type) {
2550 case 0: /* use bits [47:36] of the address */
2551 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2553 case 1: /* use bits [46:35] of the address */
2554 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2556 case 2: /* use bits [45:34] of the address */
2557 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2559 case 3: /* use bits [43:32] of the address */
2560 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2562 default: /* Invalid mc_filter_type */
2563 DEBUGOUT("MC filter type param set incorrectly\n");
2568 /* vector can only be 12-bits or boundary will be exceeded */
2574 * ixgbe_set_mta - Set bit-vector in multicast table
2575 * @hw: pointer to hardware structure
2576 * @hash_value: Multicast address hash value
2578 * Sets the bit-vector in the multicast table.
2580 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2586 DEBUGFUNC("ixgbe_set_mta");
2588 hw->addr_ctrl.mta_in_use++;
2590 vector = ixgbe_mta_vector(hw, mc_addr);
2591 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2594 * The MTA is a register array of 128 32-bit registers. It is treated
2595 * like an array of 4096 bits. We want to set bit
2596 * BitArray[vector_value]. So we figure out what register the bit is
2597 * in, read it, OR in the new bit, then write back the new value. The
2598 * register is determined by the upper 7 bits of the vector value and
2599 * the bit within that register are determined by the lower 5 bits of
2602 vector_reg = (vector >> 5) & 0x7F;
2603 vector_bit = vector & 0x1F;
2604 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2608 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2609 * @hw: pointer to hardware structure
2610 * @mc_addr_list: the list of new multicast addresses
2611 * @mc_addr_count: number of addresses
2612 * @next: iterator function to walk the multicast address list
2613 * @clear: flag, when set clears the table beforehand
2615 * When the clear flag is set, the given list replaces any existing list.
2616 * Hashes the given addresses into the multicast table.
2618 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2619 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2625 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2628 * Set the new number of MC addresses that we are being requested to
2631 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2632 hw->addr_ctrl.mta_in_use = 0;
2634 /* Clear mta_shadow */
2636 DEBUGOUT(" Clearing MTA\n");
2637 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2640 /* Update mta_shadow */
2641 for (i = 0; i < mc_addr_count; i++) {
2642 DEBUGOUT(" Adding the multicast addresses:\n");
2643 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2647 for (i = 0; i < hw->mac.mcft_size; i++)
2648 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2649 hw->mac.mta_shadow[i]);
2651 if (hw->addr_ctrl.mta_in_use > 0)
2652 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2653 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2655 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2656 return IXGBE_SUCCESS;
2660 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2661 * @hw: pointer to hardware structure
2663 * Enables multicast address in RAR and the use of the multicast hash table.
2665 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2667 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2669 DEBUGFUNC("ixgbe_enable_mc_generic");
2671 if (a->mta_in_use > 0)
2672 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2673 hw->mac.mc_filter_type);
2675 return IXGBE_SUCCESS;
2679 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2680 * @hw: pointer to hardware structure
2682 * Disables multicast address in RAR and the use of the multicast hash table.
2684 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2686 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2688 DEBUGFUNC("ixgbe_disable_mc_generic");
2690 if (a->mta_in_use > 0)
2691 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2693 return IXGBE_SUCCESS;
2697 * ixgbe_fc_enable_generic - Enable flow control
2698 * @hw: pointer to hardware structure
2700 * Enable flow control according to the current settings.
2702 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2704 s32 ret_val = IXGBE_SUCCESS;
2705 u32 mflcn_reg, fccfg_reg;
2710 DEBUGFUNC("ixgbe_fc_enable_generic");
2712 /* Validate the water mark configuration */
2713 if (!hw->fc.pause_time) {
2714 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2718 /* Low water mark of zero causes XOFF floods */
2719 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2720 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2721 hw->fc.high_water[i]) {
2722 if (!hw->fc.low_water[i] ||
2723 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2724 DEBUGOUT("Invalid water mark configuration\n");
2725 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2731 /* Negotiate the fc mode to use */
2732 ixgbe_fc_autoneg(hw);
2734 /* Disable any previous flow control settings */
2735 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2736 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2738 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2739 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2742 * The possible values of fc.current_mode are:
2743 * 0: Flow control is completely disabled
2744 * 1: Rx flow control is enabled (we can receive pause frames,
2745 * but not send pause frames).
2746 * 2: Tx flow control is enabled (we can send pause frames but
2747 * we do not support receiving pause frames).
2748 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2751 switch (hw->fc.current_mode) {
2754 * Flow control is disabled by software override or autoneg.
2755 * The code below will actually disable it in the HW.
2758 case ixgbe_fc_rx_pause:
2760 * Rx Flow control is enabled and Tx Flow control is
2761 * disabled by software override. Since there really
2762 * isn't a way to advertise that we are capable of RX
2763 * Pause ONLY, we will advertise that we support both
2764 * symmetric and asymmetric Rx PAUSE. Later, we will
2765 * disable the adapter's ability to send PAUSE frames.
2767 mflcn_reg |= IXGBE_MFLCN_RFCE;
2769 case ixgbe_fc_tx_pause:
2771 * Tx Flow control is enabled, and Rx Flow control is
2772 * disabled by software override.
2774 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2777 /* Flow control (both Rx and Tx) is enabled by SW override. */
2778 mflcn_reg |= IXGBE_MFLCN_RFCE;
2779 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2782 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2783 "Flow control param set incorrectly\n");
2784 ret_val = IXGBE_ERR_CONFIG;
2789 /* Set 802.3x based flow control settings. */
2790 mflcn_reg |= IXGBE_MFLCN_DPF;
2791 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2792 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2795 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2796 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2797 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2798 hw->fc.high_water[i]) {
2799 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2800 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2801 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2803 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2805 * In order to prevent Tx hangs when the internal Tx
2806 * switch is enabled we must set the high water mark
2807 * to the Rx packet buffer size - 24KB. This allows
2808 * the Tx switch to function even under heavy Rx
2811 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2814 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2817 /* Configure pause time (2 TCs per register) */
2818 reg = hw->fc.pause_time * 0x00010001;
2819 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2820 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2822 /* Configure flow control refresh threshold value */
2823 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2830 * ixgbe_negotiate_fc - Negotiate flow control
2831 * @hw: pointer to hardware structure
2832 * @adv_reg: flow control advertised settings
2833 * @lp_reg: link partner's flow control settings
2834 * @adv_sym: symmetric pause bit in advertisement
2835 * @adv_asm: asymmetric pause bit in advertisement
2836 * @lp_sym: symmetric pause bit in link partner advertisement
2837 * @lp_asm: asymmetric pause bit in link partner advertisement
2839 * Find the intersection between advertised settings and link partner's
2840 * advertised settings
2842 STATIC s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2843 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2845 if ((!(adv_reg)) || (!(lp_reg))) {
2846 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
2847 "Local or link partner's advertised flow control "
2848 "settings are NULL. Local: %x, link partner: %x\n",
2850 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2853 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2855 * Now we need to check if the user selected Rx ONLY
2856 * of pause frames. In this case, we had to advertise
2857 * FULL flow control because we could not advertise RX
2858 * ONLY. Hence, we must now check to see if we need to
2859 * turn OFF the TRANSMISSION of PAUSE frames.
2861 if (hw->fc.requested_mode == ixgbe_fc_full) {
2862 hw->fc.current_mode = ixgbe_fc_full;
2863 DEBUGOUT("Flow Control = FULL.\n");
2865 hw->fc.current_mode = ixgbe_fc_rx_pause;
2866 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2868 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2869 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2870 hw->fc.current_mode = ixgbe_fc_tx_pause;
2871 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2872 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2873 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2874 hw->fc.current_mode = ixgbe_fc_rx_pause;
2875 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2877 hw->fc.current_mode = ixgbe_fc_none;
2878 DEBUGOUT("Flow Control = NONE.\n");
2880 return IXGBE_SUCCESS;
2884 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2885 * @hw: pointer to hardware structure
2887 * Enable flow control according on 1 gig fiber.
2889 STATIC s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2891 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2892 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2895 * On multispeed fiber at 1g, bail out if
2896 * - link is up but AN did not complete, or if
2897 * - link is up and AN completed but timed out
2900 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2901 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2902 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
2903 DEBUGOUT("Auto-Negotiation did not complete or timed out\n");
2907 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2908 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2910 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2911 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2912 IXGBE_PCS1GANA_ASM_PAUSE,
2913 IXGBE_PCS1GANA_SYM_PAUSE,
2914 IXGBE_PCS1GANA_ASM_PAUSE);
2921 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2922 * @hw: pointer to hardware structure
2924 * Enable flow control according to IEEE clause 37.
2926 STATIC s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2928 u32 links2, anlp1_reg, autoc_reg, links;
2929 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2932 * On backplane, bail out if
2933 * - backplane autoneg was not completed, or if
2934 * - we are 82599 and link partner is not AN enabled
2936 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2937 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
2938 DEBUGOUT("Auto-Negotiation did not complete\n");
2942 if (hw->mac.type == ixgbe_mac_82599EB) {
2943 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2944 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
2945 DEBUGOUT("Link partner is not AN enabled\n");
2950 * Read the 10g AN autoc and LP ability registers and resolve
2951 * local flow control settings accordingly
2953 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2954 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2956 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2957 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2958 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2965 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2966 * @hw: pointer to hardware structure
2968 * Enable flow control according to IEEE clause 37.
2970 STATIC s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2972 u16 technology_ability_reg = 0;
2973 u16 lp_technology_ability_reg = 0;
2975 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
2976 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2977 &technology_ability_reg);
2978 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
2979 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2980 &lp_technology_ability_reg);
2982 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2983 (u32)lp_technology_ability_reg,
2984 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2985 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2989 * ixgbe_fc_autoneg - Configure flow control
2990 * @hw: pointer to hardware structure
2992 * Compares our advertised flow control capabilities to those advertised by
2993 * our link partner, and determines the proper flow control mode to use.
2995 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2997 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2998 ixgbe_link_speed speed;
3001 DEBUGFUNC("ixgbe_fc_autoneg");
3004 * AN should have completed when the cable was plugged in.
3005 * Look for reasons to bail out. Bail out if:
3006 * - FC autoneg is disabled, or if
3009 if (hw->fc.disable_fc_autoneg) {
3010 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3011 "Flow control autoneg is disabled");
3015 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3017 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3021 switch (hw->phy.media_type) {
3022 /* Autoneg flow control on fiber adapters */
3023 case ixgbe_media_type_fiber_qsfp:
3024 case ixgbe_media_type_fiber:
3025 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
3026 ret_val = ixgbe_fc_autoneg_fiber(hw);
3029 /* Autoneg flow control on backplane adapters */
3030 case ixgbe_media_type_backplane:
3031 ret_val = ixgbe_fc_autoneg_backplane(hw);
3034 /* Autoneg flow control on copper adapters */
3035 case ixgbe_media_type_copper:
3036 if (ixgbe_device_supports_autoneg_fc(hw))
3037 ret_val = ixgbe_fc_autoneg_copper(hw);
3045 if (ret_val == IXGBE_SUCCESS) {
3046 hw->fc.fc_was_autonegged = true;
3048 hw->fc.fc_was_autonegged = false;
3049 hw->fc.current_mode = hw->fc.requested_mode;
3054 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3055 * @hw: pointer to hardware structure
3057 * System-wide timeout range is encoded in PCIe Device Control2 register.
3059 * Add 10% to specified maximum and return the number of times to poll for
3060 * completion timeout, in units of 100 microsec. Never return less than
3061 * 800 = 80 millisec.
3063 STATIC u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3068 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3069 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
3072 case IXGBE_PCIDEVCTRL2_65_130ms:
3073 pollcnt = 1300; /* 130 millisec */
3075 case IXGBE_PCIDEVCTRL2_260_520ms:
3076 pollcnt = 5200; /* 520 millisec */
3078 case IXGBE_PCIDEVCTRL2_1_2s:
3079 pollcnt = 20000; /* 2 sec */
3081 case IXGBE_PCIDEVCTRL2_4_8s:
3082 pollcnt = 80000; /* 8 sec */
3084 case IXGBE_PCIDEVCTRL2_17_34s:
3085 pollcnt = 34000; /* 34 sec */
3087 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
3088 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
3089 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
3090 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
3092 pollcnt = 800; /* 80 millisec minimum */
3096 /* add 10% to spec maximum */
3097 return (pollcnt * 11) / 10;
3101 * ixgbe_disable_pcie_master - Disable PCI-express master access
3102 * @hw: pointer to hardware structure
3104 * Disables PCI-Express master access and verifies there are no pending
3105 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
3106 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
3107 * is returned signifying master requests disabled.
3109 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
3111 s32 status = IXGBE_SUCCESS;
3115 DEBUGFUNC("ixgbe_disable_pcie_master");
3117 /* Always set this bit to ensure any future transactions are blocked */
3118 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3120 /* Exit if master requests are blocked */
3121 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3122 IXGBE_REMOVED(hw->hw_addr))
3125 /* Poll for master request bit to clear */
3126 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
3128 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3133 * Two consecutive resets are required via CTRL.RST per datasheet
3134 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
3135 * of this need. The first reset prevents new master requests from
3136 * being issued by our device. We then must wait 1usec or more for any
3137 * remaining completions from the PCIe bus to trickle in, and then reset
3138 * again to clear out any effects they may have had on our device.
3140 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
3141 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3143 if (hw->mac.type >= ixgbe_mac_X550)
3147 * Before proceeding, make sure that the PCIe block does not have
3148 * transactions pending.
3150 poll = ixgbe_pcie_timeout_poll(hw);
3151 for (i = 0; i < poll; i++) {
3153 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3154 if (IXGBE_REMOVED(hw->hw_addr))
3156 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3160 ERROR_REPORT1(IXGBE_ERROR_POLLING,
3161 "PCIe transaction pending bit also did not clear.\n");
3162 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
3169 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3170 * @hw: pointer to hardware structure
3171 * @mask: Mask to specify which semaphore to acquire
3173 * Acquires the SWFW semaphore through the GSSR register for the specified
3174 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3176 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3180 u32 fwmask = mask << 5;
3184 DEBUGFUNC("ixgbe_acquire_swfw_sync");
3186 for (i = 0; i < timeout; i++) {
3188 * SW NVM semaphore bit is used for access to all
3189 * SW_FW_SYNC bits (not just NVM)
3191 if (ixgbe_get_eeprom_semaphore(hw))
3192 return IXGBE_ERR_SWFW_SYNC;
3194 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3195 if (!(gssr & (fwmask | swmask))) {
3197 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3198 ixgbe_release_eeprom_semaphore(hw);
3199 return IXGBE_SUCCESS;
3201 /* Resource is currently in use by FW or SW */
3202 ixgbe_release_eeprom_semaphore(hw);
3207 /* If time expired clear the bits holding the lock and retry */
3208 if (gssr & (fwmask | swmask))
3209 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
3212 return IXGBE_ERR_SWFW_SYNC;
3216 * ixgbe_release_swfw_sync - Release SWFW semaphore
3217 * @hw: pointer to hardware structure
3218 * @mask: Mask to specify which semaphore to release
3220 * Releases the SWFW semaphore through the GSSR register for the specified
3221 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3223 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3228 DEBUGFUNC("ixgbe_release_swfw_sync");
3230 ixgbe_get_eeprom_semaphore(hw);
3232 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3234 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3236 ixgbe_release_eeprom_semaphore(hw);
3240 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3241 * @hw: pointer to hardware structure
3243 * Stops the receive data path and waits for the HW to internally empty
3244 * the Rx security block
3246 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3248 #define IXGBE_MAX_SECRX_POLL 40
3253 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
3256 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3257 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
3258 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3259 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
3260 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3261 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
3264 /* Use interrupt-safe sleep just in case */
3268 /* For informational purposes only */
3269 if (i >= IXGBE_MAX_SECRX_POLL)
3270 DEBUGOUT("Rx unit being enabled before security "
3271 "path fully disabled. Continuing with init.\n");
3273 return IXGBE_SUCCESS;
3277 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3278 * @hw: pointer to hardware structure
3279 * @reg_val: Value we read from AUTOC
3281 * The default case requires no protection so just to the register read.
3283 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3286 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3287 return IXGBE_SUCCESS;
3291 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
3292 * @hw: pointer to hardware structure
3293 * @reg_val: value to write to AUTOC
3294 * @locked: bool to indicate whether the SW/FW lock was already taken by
3297 * The default case requires no protection so just to the register write.
3299 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
3301 UNREFERENCED_1PARAMETER(locked);
3303 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
3304 return IXGBE_SUCCESS;
3308 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3309 * @hw: pointer to hardware structure
3311 * Enables the receive data path.
3313 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3317 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
3319 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3320 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
3321 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3322 IXGBE_WRITE_FLUSH(hw);
3324 return IXGBE_SUCCESS;
3328 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3329 * @hw: pointer to hardware structure
3330 * @regval: register value to write to RXCTRL
3332 * Enables the Rx DMA unit
3334 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3336 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
3338 if (regval & IXGBE_RXCTRL_RXEN)
3339 ixgbe_enable_rx(hw);
3341 ixgbe_disable_rx(hw);
3343 return IXGBE_SUCCESS;
3347 * ixgbe_blink_led_start_generic - Blink LED based on index.
3348 * @hw: pointer to hardware structure
3349 * @index: led number to blink
3351 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3353 ixgbe_link_speed speed = 0;
3356 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3357 s32 ret_val = IXGBE_SUCCESS;
3358 bool locked = false;
3360 DEBUGFUNC("ixgbe_blink_led_start_generic");
3363 * Link must be up to auto-blink the LEDs;
3364 * Force it if link is down.
3366 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3369 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3370 if (ret_val != IXGBE_SUCCESS)
3373 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3374 autoc_reg |= IXGBE_AUTOC_FLU;
3376 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3377 if (ret_val != IXGBE_SUCCESS)
3380 IXGBE_WRITE_FLUSH(hw);
3384 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3385 led_reg |= IXGBE_LED_BLINK(index);
3386 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3387 IXGBE_WRITE_FLUSH(hw);
3394 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3395 * @hw: pointer to hardware structure
3396 * @index: led number to stop blinking
3398 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3401 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3402 s32 ret_val = IXGBE_SUCCESS;
3403 bool locked = false;
3405 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3407 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3408 if (ret_val != IXGBE_SUCCESS)
3411 autoc_reg &= ~IXGBE_AUTOC_FLU;
3412 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3414 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3415 if (ret_val != IXGBE_SUCCESS)
3418 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3419 led_reg &= ~IXGBE_LED_BLINK(index);
3420 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3421 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3422 IXGBE_WRITE_FLUSH(hw);
3429 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3430 * @hw: pointer to hardware structure
3431 * @san_mac_offset: SAN MAC address offset
3433 * This function will read the EEPROM location for the SAN MAC address
3434 * pointer, and returns the value at that location. This is used in both
3435 * get and set mac_addr routines.
3437 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3438 u16 *san_mac_offset)
3442 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3445 * First read the EEPROM pointer to see if the MAC addresses are
3448 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3451 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3452 "eeprom at offset %d failed",
3453 IXGBE_SAN_MAC_ADDR_PTR);
3460 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3461 * @hw: pointer to hardware structure
3462 * @san_mac_addr: SAN MAC address
3464 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3465 * per-port, so set_lan_id() must be called before reading the addresses.
3466 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3467 * upon for non-SFP connections, so we must call it here.
3469 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3471 u16 san_mac_data, san_mac_offset;
3475 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3478 * First read the EEPROM pointer to see if the MAC addresses are
3479 * available. If they're not, no point in calling set_lan_id() here.
3481 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3482 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3483 goto san_mac_addr_out;
3485 /* make sure we know which port we need to program */
3486 hw->mac.ops.set_lan_id(hw);
3487 /* apply the port offset to the address offset */
3488 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3489 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3490 for (i = 0; i < 3; i++) {
3491 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3494 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3495 "eeprom read at offset %d failed",
3497 goto san_mac_addr_out;
3499 san_mac_addr[i * 2] = (u8)(san_mac_data);
3500 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3503 return IXGBE_SUCCESS;
3507 * No addresses available in this EEPROM. It's not an
3508 * error though, so just wipe the local address and return.
3510 for (i = 0; i < 6; i++)
3511 san_mac_addr[i] = 0xFF;
3512 return IXGBE_SUCCESS;
3516 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3517 * @hw: pointer to hardware structure
3518 * @san_mac_addr: SAN MAC address
3520 * Write a SAN MAC address to the EEPROM.
3522 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3525 u16 san_mac_data, san_mac_offset;
3528 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3530 /* Look for SAN mac address pointer. If not defined, return */
3531 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3532 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3533 return IXGBE_ERR_NO_SAN_ADDR_PTR;
3535 /* Make sure we know which port we need to write */
3536 hw->mac.ops.set_lan_id(hw);
3537 /* Apply the port offset to the address offset */
3538 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3539 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3541 for (i = 0; i < 3; i++) {
3542 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3543 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3544 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3548 return IXGBE_SUCCESS;
3552 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3553 * @hw: pointer to hardware structure
3555 * Read PCIe configuration space, and get the MSI-X vector count from
3556 * the capabilities table.
3558 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3564 switch (hw->mac.type) {
3565 case ixgbe_mac_82598EB:
3566 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3567 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3569 case ixgbe_mac_82599EB:
3570 case ixgbe_mac_X540:
3571 case ixgbe_mac_X550:
3572 case ixgbe_mac_X550EM_x:
3573 case ixgbe_mac_X550EM_a:
3574 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3575 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3581 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3582 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3583 if (IXGBE_REMOVED(hw->hw_addr))
3585 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3587 /* MSI-X count is zero-based in HW */
3590 if (msix_count > max_msix_count)
3591 msix_count = max_msix_count;
3597 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3598 * @hw: pointer to hardware structure
3599 * @addr: Address to put into receive address register
3600 * @vmdq: VMDq pool to assign
3602 * Puts an ethernet address into a receive address register, or
3603 * finds the rar that it is aleady in; adds to the pool list
3605 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3607 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3608 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3610 u32 rar_low, rar_high;
3611 u32 addr_low, addr_high;
3613 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3615 /* swap bytes for HW little endian */
3616 addr_low = addr[0] | (addr[1] << 8)
3619 addr_high = addr[4] | (addr[5] << 8);
3622 * Either find the mac_id in rar or find the first empty space.
3623 * rar_highwater points to just after the highest currently used
3624 * rar in order to shorten the search. It grows when we add a new
3627 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3628 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3630 if (((IXGBE_RAH_AV & rar_high) == 0)
3631 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3632 first_empty_rar = rar;
3633 } else if ((rar_high & 0xFFFF) == addr_high) {
3634 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3635 if (rar_low == addr_low)
3636 break; /* found it already in the rars */
3640 if (rar < hw->mac.rar_highwater) {
3641 /* already there so just add to the pool bits */
3642 ixgbe_set_vmdq(hw, rar, vmdq);
3643 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3644 /* stick it into first empty RAR slot we found */
3645 rar = first_empty_rar;
3646 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3647 } else if (rar == hw->mac.rar_highwater) {
3648 /* add it to the top of the list and inc the highwater mark */
3649 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3650 hw->mac.rar_highwater++;
3651 } else if (rar >= hw->mac.num_rar_entries) {
3652 return IXGBE_ERR_INVALID_MAC_ADDR;
3656 * If we found rar[0], make sure the default pool bit (we use pool 0)
3657 * remains cleared to be sure default pool packets will get delivered
3660 ixgbe_clear_vmdq(hw, rar, 0);
3666 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3667 * @hw: pointer to hardware struct
3668 * @rar: receive address register index to disassociate
3669 * @vmdq: VMDq pool index to remove from the rar
3671 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3673 u32 mpsar_lo, mpsar_hi;
3674 u32 rar_entries = hw->mac.num_rar_entries;
3676 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3678 /* Make sure we are using a valid rar index range */
3679 if (rar >= rar_entries) {
3680 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3681 "RAR index %d is out of range.\n", rar);
3682 return IXGBE_ERR_INVALID_ARGUMENT;
3685 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3686 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3688 if (IXGBE_REMOVED(hw->hw_addr))
3691 if (!mpsar_lo && !mpsar_hi)
3694 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3696 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3700 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3703 } else if (vmdq < 32) {
3704 mpsar_lo &= ~(1 << vmdq);
3705 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3707 mpsar_hi &= ~(1 << (vmdq - 32));
3708 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3711 /* was that the last pool using this rar? */
3712 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
3713 hw->mac.ops.clear_rar(hw, rar);
3715 return IXGBE_SUCCESS;
3719 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3720 * @hw: pointer to hardware struct
3721 * @rar: receive address register index to associate with a VMDq index
3722 * @vmdq: VMDq pool index
3724 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3727 u32 rar_entries = hw->mac.num_rar_entries;
3729 DEBUGFUNC("ixgbe_set_vmdq_generic");
3731 /* Make sure we are using a valid rar index range */
3732 if (rar >= rar_entries) {
3733 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3734 "RAR index %d is out of range.\n", rar);
3735 return IXGBE_ERR_INVALID_ARGUMENT;
3739 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3741 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3743 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3744 mpsar |= 1 << (vmdq - 32);
3745 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3747 return IXGBE_SUCCESS;
3751 * This function should only be involved in the IOV mode.
3752 * In IOV mode, Default pool is next pool after the number of
3753 * VFs advertized and not 0.
3754 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3756 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3757 * @hw: pointer to hardware struct
3758 * @vmdq: VMDq pool index
3760 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3762 u32 rar = hw->mac.san_mac_rar_index;
3764 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3767 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3768 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3770 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3771 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3774 return IXGBE_SUCCESS;
3778 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3779 * @hw: pointer to hardware structure
3781 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3785 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3786 DEBUGOUT(" Clearing UTA\n");
3788 for (i = 0; i < 128; i++)
3789 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3791 return IXGBE_SUCCESS;
3795 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3796 * @hw: pointer to hardware structure
3797 * @vlan: VLAN id to write to VLAN filter
3799 * return the VLVF index where this VLAN id should be placed
3802 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
3805 u32 first_empty_slot = 0;
3808 /* short cut the special case */
3813 * Search for the vlan id in the VLVF entries. Save off the first empty
3814 * slot found along the way
3816 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
3817 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3818 if (!bits && !(first_empty_slot))
3819 first_empty_slot = regindex;
3820 else if ((bits & 0x0FFF) == vlan)
3825 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
3826 * in the VLVF. Else use the first empty VLVF register for this
3829 if (regindex >= IXGBE_VLVF_ENTRIES) {
3830 if (first_empty_slot)
3831 regindex = first_empty_slot;
3833 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
3834 "No space in VLVF.\n");
3835 regindex = IXGBE_ERR_NO_SPACE;
3843 * ixgbe_set_vfta_generic - Set VLAN filter table
3844 * @hw: pointer to hardware structure
3845 * @vlan: VLAN id to write to VLAN filter
3846 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3847 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3849 * Turn on/off specified VLAN in the VLAN filter table.
3851 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3858 s32 ret_val = IXGBE_SUCCESS;
3859 bool vfta_changed = false;
3861 DEBUGFUNC("ixgbe_set_vfta_generic");
3864 return IXGBE_ERR_PARAM;
3867 * this is a 2 part operation - first the VFTA, then the
3868 * VLVF and VLVFB if VT Mode is set
3869 * We don't write the VFTA until we know the VLVF part succeeded.
3873 * The VFTA is a bitstring made up of 128 32-bit registers
3874 * that enable the particular VLAN id, much like the MTA:
3875 * bits[11-5]: which register
3876 * bits[4-0]: which bit in the register
3878 regindex = (vlan >> 5) & 0x7F;
3879 bitindex = vlan & 0x1F;
3880 targetbit = (1 << bitindex);
3881 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3884 if (!(vfta & targetbit)) {
3886 vfta_changed = true;
3889 if ((vfta & targetbit)) {
3891 vfta_changed = true;
3896 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
3898 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on,
3900 if (ret_val != IXGBE_SUCCESS)
3904 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3906 return IXGBE_SUCCESS;
3910 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
3911 * @hw: pointer to hardware structure
3912 * @vlan: VLAN id to write to VLAN filter
3913 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3914 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3915 * @vfta_changed: pointer to boolean flag which indicates whether VFTA
3918 * Turn on/off specified bit in VLVF table.
3920 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3921 bool vlan_on, bool *vfta_changed)
3925 DEBUGFUNC("ixgbe_set_vlvf_generic");
3928 return IXGBE_ERR_PARAM;
3930 /* If VT Mode is set
3932 * make sure the vlan is in VLVF
3933 * set the vind bit in the matching VLVFB
3935 * clear the pool bit and possibly the vind
3937 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3938 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3942 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3947 /* set the pool bit */
3949 bits = IXGBE_READ_REG(hw,
3950 IXGBE_VLVFB(vlvf_index * 2));
3951 bits |= (1 << vind);
3953 IXGBE_VLVFB(vlvf_index * 2),
3956 bits = IXGBE_READ_REG(hw,
3957 IXGBE_VLVFB((vlvf_index * 2) + 1));
3958 bits |= (1 << (vind - 32));
3960 IXGBE_VLVFB((vlvf_index * 2) + 1),
3964 /* clear the pool bit */
3966 bits = IXGBE_READ_REG(hw,
3967 IXGBE_VLVFB(vlvf_index * 2));
3968 bits &= ~(1 << vind);
3970 IXGBE_VLVFB(vlvf_index * 2),
3972 bits |= IXGBE_READ_REG(hw,
3973 IXGBE_VLVFB((vlvf_index * 2) + 1));
3975 bits = IXGBE_READ_REG(hw,
3976 IXGBE_VLVFB((vlvf_index * 2) + 1));
3977 bits &= ~(1 << (vind - 32));
3979 IXGBE_VLVFB((vlvf_index * 2) + 1),
3981 bits |= IXGBE_READ_REG(hw,
3982 IXGBE_VLVFB(vlvf_index * 2));
3987 * If there are still bits set in the VLVFB registers
3988 * for the VLAN ID indicated we need to see if the
3989 * caller is requesting that we clear the VFTA entry bit.
3990 * If the caller has requested that we clear the VFTA
3991 * entry bit but there are still pools/VFs using this VLAN
3992 * ID entry then ignore the request. We're not worried
3993 * about the case where we're turning the VFTA VLAN ID
3994 * entry bit on, only when requested to turn it off as
3995 * there may be multiple pools and/or VFs using the
3996 * VLAN ID entry. In that case we cannot clear the
3997 * VFTA bit until all pools/VFs using that VLAN ID have also
3998 * been cleared. This will be indicated by "bits" being
4002 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
4003 (IXGBE_VLVF_VIEN | vlan));
4004 if ((!vlan_on) && (vfta_changed != NULL)) {
4005 /* someone wants to clear the vfta entry
4006 * but some pools/VFs are still using it.
4008 *vfta_changed = false;
4011 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
4014 return IXGBE_SUCCESS;
4018 * ixgbe_clear_vfta_generic - Clear VLAN filter table
4019 * @hw: pointer to hardware structure
4021 * Clears the VLAN filer table, and the VMDq index associated with the filter
4023 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
4027 DEBUGFUNC("ixgbe_clear_vfta_generic");
4029 for (offset = 0; offset < hw->mac.vft_size; offset++)
4030 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
4032 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
4033 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
4034 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
4035 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
4038 return IXGBE_SUCCESS;
4042 * ixgbe_check_mac_link_generic - Determine link and speed status
4043 * @hw: pointer to hardware structure
4044 * @speed: pointer to link speed
4045 * @link_up: true when link is up
4046 * @link_up_wait_to_complete: bool used to wait for link up or not
4048 * Reads the links register to determine if link is up and the current speed
4050 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4051 bool *link_up, bool link_up_wait_to_complete)
4053 u32 links_reg, links_orig;
4056 DEBUGFUNC("ixgbe_check_mac_link_generic");
4058 /* clear the old state */
4059 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
4061 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4063 if (links_orig != links_reg) {
4064 DEBUGOUT2("LINKS changed from %08X to %08X\n",
4065 links_orig, links_reg);
4068 if (link_up_wait_to_complete) {
4069 for (i = 0; i < hw->mac.max_link_up_time; i++) {
4070 if (links_reg & IXGBE_LINKS_UP) {
4077 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4080 if (links_reg & IXGBE_LINKS_UP)
4086 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4087 case IXGBE_LINKS_SPEED_10G_82599:
4088 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4089 if (hw->mac.type >= ixgbe_mac_X550) {
4090 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4091 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4094 case IXGBE_LINKS_SPEED_1G_82599:
4095 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4097 case IXGBE_LINKS_SPEED_100_82599:
4098 *speed = IXGBE_LINK_SPEED_100_FULL;
4099 if (hw->mac.type >= ixgbe_mac_X550) {
4100 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4101 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4105 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4108 return IXGBE_SUCCESS;
4112 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4114 * @hw: pointer to hardware structure
4115 * @wwnn_prefix: the alternative WWNN prefix
4116 * @wwpn_prefix: the alternative WWPN prefix
4118 * This function will read the EEPROM from the alternative SAN MAC address
4119 * block to check the support for the alternative WWNN/WWPN prefix support.
4121 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4125 u16 alt_san_mac_blk_offset;
4127 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
4129 /* clear output first */
4130 *wwnn_prefix = 0xFFFF;
4131 *wwpn_prefix = 0xFFFF;
4133 /* check if alternative SAN MAC is supported */
4134 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
4135 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4136 goto wwn_prefix_err;
4138 if ((alt_san_mac_blk_offset == 0) ||
4139 (alt_san_mac_blk_offset == 0xFFFF))
4140 goto wwn_prefix_out;
4142 /* check capability in alternative san mac address block */
4143 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
4144 if (hw->eeprom.ops.read(hw, offset, &caps))
4145 goto wwn_prefix_err;
4146 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
4147 goto wwn_prefix_out;
4149 /* get the corresponding prefix for WWNN/WWPN */
4150 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
4151 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4152 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4153 "eeprom read at offset %d failed", offset);
4156 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
4157 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4158 goto wwn_prefix_err;
4161 return IXGBE_SUCCESS;
4164 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4165 "eeprom read at offset %d failed", offset);
4166 return IXGBE_SUCCESS;
4170 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4171 * @hw: pointer to hardware structure
4172 * @bs: the fcoe boot status
4174 * This function will read the FCOE boot status from the iSCSI FCOE block
4176 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4178 u16 offset, caps, flags;
4181 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
4183 /* clear output first */
4184 *bs = ixgbe_fcoe_bootstatus_unavailable;
4186 /* check if FCOE IBA block is present */
4187 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
4188 status = hw->eeprom.ops.read(hw, offset, &caps);
4189 if (status != IXGBE_SUCCESS)
4192 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
4195 /* check if iSCSI FCOE block is populated */
4196 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4197 if (status != IXGBE_SUCCESS)
4200 if ((offset == 0) || (offset == 0xFFFF))
4203 /* read fcoe flags in iSCSI FCOE block */
4204 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
4205 status = hw->eeprom.ops.read(hw, offset, &flags);
4206 if (status != IXGBE_SUCCESS)
4209 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
4210 *bs = ixgbe_fcoe_bootstatus_enabled;
4212 *bs = ixgbe_fcoe_bootstatus_disabled;
4219 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4220 * @hw: pointer to hardware structure
4221 * @enable: enable or disable switch for anti-spoofing
4222 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
4225 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
4228 int pf_target_reg = pf >> 3;
4229 int pf_target_shift = pf % 8;
4232 if (hw->mac.type == ixgbe_mac_82598EB)
4236 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
4239 * PFVFSPOOF register array is size 8 with 8 bits assigned to
4240 * MAC anti-spoof enables in each register array element.
4242 for (j = 0; j < pf_target_reg; j++)
4243 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
4246 * The PF should be allowed to spoof so that it can support
4247 * emulation mode NICs. Do not set the bits assigned to the PF
4249 pfvfspoof &= (1 << pf_target_shift) - 1;
4250 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
4253 * Remaining pools belong to the PF so they do not need to have
4254 * anti-spoofing enabled.
4256 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
4257 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
4261 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4262 * @hw: pointer to hardware structure
4263 * @enable: enable or disable switch for VLAN anti-spoofing
4264 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4267 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4269 int vf_target_reg = vf >> 3;
4270 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
4273 if (hw->mac.type == ixgbe_mac_82598EB)
4276 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4278 pfvfspoof |= (1 << vf_target_shift);
4280 pfvfspoof &= ~(1 << vf_target_shift);
4281 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4285 * ixgbe_get_device_caps_generic - Get additional device capabilities
4286 * @hw: pointer to hardware structure
4287 * @device_caps: the EEPROM word with the extra device capabilities
4289 * This function will read the EEPROM location for the device capabilities,
4290 * and return the word through device_caps.
4292 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4294 DEBUGFUNC("ixgbe_get_device_caps_generic");
4296 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4298 return IXGBE_SUCCESS;
4302 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4303 * @hw: pointer to hardware structure
4306 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4311 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
4313 /* Enable relaxed ordering */
4314 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4315 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4316 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4317 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4320 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4321 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4322 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
4323 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4324 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4330 * ixgbe_calculate_checksum - Calculate checksum for buffer
4331 * @buffer: pointer to EEPROM
4332 * @length: size of EEPROM to calculate a checksum for
4333 * Calculates the checksum for some buffer on a specified length. The
4334 * checksum calculated is returned.
4336 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4341 DEBUGFUNC("ixgbe_calculate_checksum");
4346 for (i = 0; i < length; i++)
4349 return (u8) (0 - sum);
4353 * ixgbe_host_interface_command - Issue command to manageability block
4354 * @hw: pointer to the HW structure
4355 * @buffer: contains the command to write and where the return status will
4357 * @length: length of buffer, must be multiple of 4 bytes
4358 * @timeout: time in ms to wait for command completion
4359 * @return_data: read and return data from the buffer (true) or not (false)
4360 * Needed because FW structures are big endian and decoding of
4361 * these fields can be 8 bit or 16 bit based on command. Decoding
4362 * is not easily understood without making a table of commands.
4363 * So we will leave this up to the caller to read back the data
4366 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4367 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
4369 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4370 u32 length, u32 timeout, bool return_data)
4372 u32 hicr, i, bi, fwsts;
4373 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4377 DEBUGFUNC("ixgbe_host_interface_command");
4379 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4380 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4381 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4383 /* Set bit 9 of FWSTS clearing FW reset indication */
4384 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
4385 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
4387 /* Check that the host interface is enabled. */
4388 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4389 if ((hicr & IXGBE_HICR_EN) == 0) {
4390 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
4391 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4394 /* Calculate length in DWORDs. We must be DWORD aligned */
4395 if ((length % (sizeof(u32))) != 0) {
4396 DEBUGOUT("Buffer length failure, not aligned to dword");
4397 return IXGBE_ERR_INVALID_ARGUMENT;
4400 dword_len = length >> 2;
4402 /* The device driver writes the relevant command block
4403 * into the ram area.
4405 for (i = 0; i < dword_len; i++)
4406 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4407 i, IXGBE_CPU_TO_LE32(buffer[i]));
4409 /* Setting this bit tells the ARC that a new command is pending. */
4410 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4412 for (i = 0; i < timeout; i++) {
4413 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4414 if (!(hicr & IXGBE_HICR_C))
4419 /* Check command completion */
4420 if ((timeout != 0 && i == timeout) ||
4421 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
4422 ERROR_REPORT1(IXGBE_ERROR_CAUTION,
4423 "Command has failed with no status valid.\n");
4424 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4430 /* Calculate length in DWORDs */
4431 dword_len = hdr_size >> 2;
4433 /* first pull in the header so we know the buffer length */
4434 for (bi = 0; bi < dword_len; bi++) {
4435 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4436 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4439 /* If there is any thing in data position pull it in */
4440 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
4444 if (length < buf_len + hdr_size) {
4445 DEBUGOUT("Buffer not large enough for reply message.\n");
4446 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4449 /* Calculate length in DWORDs, add 3 for odd lengths */
4450 dword_len = (buf_len + 3) >> 2;
4452 /* Pull in the rest of the buffer (bi is where we left off) */
4453 for (; bi <= dword_len; bi++) {
4454 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4455 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4462 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4463 * @hw: pointer to the HW structure
4464 * @maj: driver version major number
4465 * @min: driver version minor number
4466 * @build: driver version build number
4467 * @sub: driver version sub build number
4469 * Sends driver version number to firmware through the manageability
4470 * block. On success return IXGBE_SUCCESS
4471 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4472 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4474 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4477 struct ixgbe_hic_drv_info fw_cmd;
4479 s32 ret_val = IXGBE_SUCCESS;
4481 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4483 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM)
4485 ret_val = IXGBE_ERR_SWFW_SYNC;
4489 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4490 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4491 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4492 fw_cmd.port_num = (u8)hw->bus.func;
4493 fw_cmd.ver_maj = maj;
4494 fw_cmd.ver_min = min;
4495 fw_cmd.ver_build = build;
4496 fw_cmd.ver_sub = sub;
4497 fw_cmd.hdr.checksum = 0;
4498 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4499 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4503 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4504 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4506 IXGBE_HI_COMMAND_TIMEOUT,
4508 if (ret_val != IXGBE_SUCCESS)
4511 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4512 FW_CEM_RESP_STATUS_SUCCESS)
4513 ret_val = IXGBE_SUCCESS;
4515 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4520 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4526 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4527 * @hw: pointer to hardware structure
4528 * @num_pb: number of packet buffers to allocate
4529 * @headroom: reserve n KB of headroom
4530 * @strategy: packet buffer allocation strategy
4532 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4535 u32 pbsize = hw->mac.rx_pb_size;
4537 u32 rxpktsize, txpktsize, txpbthresh;
4539 /* Reserve headroom */
4545 /* Divide remaining packet buffer space amongst the number of packet
4546 * buffers requested using supplied strategy.
4549 case PBA_STRATEGY_WEIGHTED:
4550 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4551 * buffer with 5/8 of the packet buffer space.
4553 rxpktsize = (pbsize * 5) / (num_pb * 4);
4554 pbsize -= rxpktsize * (num_pb / 2);
4555 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4556 for (; i < (num_pb / 2); i++)
4557 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4558 /* Fall through to configure remaining packet buffers */
4559 case PBA_STRATEGY_EQUAL:
4560 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4561 for (; i < num_pb; i++)
4562 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4568 /* Only support an equally distributed Tx packet buffer strategy. */
4569 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4570 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4571 for (i = 0; i < num_pb; i++) {
4572 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4573 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4576 /* Clear unused TCs, if any, to zero buffer size*/
4577 for (; i < IXGBE_MAX_PB; i++) {
4578 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4579 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4580 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4585 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4586 * @hw: pointer to the hardware structure
4588 * The 82599 and x540 MACs can experience issues if TX work is still pending
4589 * when a reset occurs. This function prevents this by flushing the PCIe
4590 * buffers on the system.
4592 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4594 u32 gcr_ext, hlreg0, i, poll;
4598 * If double reset is not requested then all transactions should
4599 * already be clear and as such there is no work to do
4601 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4605 * Set loopback enable to prevent any transmits from being sent
4606 * should the link come up. This assumes that the RXCTRL.RXEN bit
4607 * has already been cleared.
4609 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4610 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4612 /* Wait for a last completion before clearing buffers */
4613 IXGBE_WRITE_FLUSH(hw);
4617 * Before proceeding, make sure that the PCIe block does not have
4618 * transactions pending.
4620 poll = ixgbe_pcie_timeout_poll(hw);
4621 for (i = 0; i < poll; i++) {
4623 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
4624 if (IXGBE_REMOVED(hw->hw_addr))
4626 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
4631 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4632 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4633 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4634 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4636 /* Flush all writes and allow 20usec for all transactions to clear */
4637 IXGBE_WRITE_FLUSH(hw);
4640 /* restore previous register values */
4641 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4642 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4645 STATIC const u8 ixgbe_emc_temp_data[4] = {
4646 IXGBE_EMC_INTERNAL_DATA,
4647 IXGBE_EMC_DIODE1_DATA,
4648 IXGBE_EMC_DIODE2_DATA,
4649 IXGBE_EMC_DIODE3_DATA
4651 STATIC const u8 ixgbe_emc_therm_limit[4] = {
4652 IXGBE_EMC_INTERNAL_THERM_LIMIT,
4653 IXGBE_EMC_DIODE1_THERM_LIMIT,
4654 IXGBE_EMC_DIODE2_THERM_LIMIT,
4655 IXGBE_EMC_DIODE3_THERM_LIMIT
4659 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
4660 * @hw: pointer to hardware structure
4661 * @data: pointer to the thermal sensor data structure
4663 * Returns the thermal sensor data structure
4665 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
4667 s32 status = IXGBE_SUCCESS;
4675 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4677 DEBUGFUNC("ixgbe_get_thermal_sensor_data_generic");
4679 /* Only support thermal sensors attached to 82599 physical port 0 */
4680 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4681 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
4682 status = IXGBE_NOT_IMPLEMENTED;
4686 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);
4690 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) {
4691 status = IXGBE_NOT_IMPLEMENTED;
4695 status = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);
4699 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4700 != IXGBE_ETS_TYPE_EMC) {
4701 status = IXGBE_NOT_IMPLEMENTED;
4705 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4706 if (num_sensors > IXGBE_MAX_SENSORS)
4707 num_sensors = IXGBE_MAX_SENSORS;
4709 for (i = 0; i < num_sensors; i++) {
4710 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
4715 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4716 IXGBE_ETS_DATA_INDEX_SHIFT);
4717 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4718 IXGBE_ETS_DATA_LOC_SHIFT);
4720 if (sensor_location != 0) {
4721 status = hw->phy.ops.read_i2c_byte(hw,
4722 ixgbe_emc_temp_data[sensor_index],
4723 IXGBE_I2C_THERMAL_SENSOR_ADDR,
4724 &data->sensor[i].temp);
4734 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
4735 * @hw: pointer to hardware structure
4737 * Inits the thermal sensor thresholds according to the NVM map
4738 * and save off the threshold and location values into mac.thermal_sensor_data
4740 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
4742 s32 status = IXGBE_SUCCESS;
4747 u8 low_thresh_delta;
4753 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4755 DEBUGFUNC("ixgbe_init_thermal_sensor_thresh_generic");
4757 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
4759 /* Only support thermal sensors attached to 82599 physical port 0 */
4760 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4761 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
4762 return IXGBE_NOT_IMPLEMENTED;
4764 offset = IXGBE_ETS_CFG;
4765 if (hw->eeprom.ops.read(hw, offset, &ets_offset))
4767 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
4768 return IXGBE_NOT_IMPLEMENTED;
4770 offset = ets_offset;
4771 if (hw->eeprom.ops.read(hw, offset, &ets_cfg))
4773 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4774 != IXGBE_ETS_TYPE_EMC)
4775 return IXGBE_NOT_IMPLEMENTED;
4777 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
4778 IXGBE_ETS_LTHRES_DELTA_SHIFT);
4779 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4781 for (i = 0; i < num_sensors; i++) {
4782 offset = ets_offset + 1 + i;
4783 if (hw->eeprom.ops.read(hw, offset, &ets_sensor)) {
4784 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4785 "eeprom read at offset %d failed",
4789 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4790 IXGBE_ETS_DATA_INDEX_SHIFT);
4791 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4792 IXGBE_ETS_DATA_LOC_SHIFT);
4793 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
4795 hw->phy.ops.write_i2c_byte(hw,
4796 ixgbe_emc_therm_limit[sensor_index],
4797 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
4799 if ((i < IXGBE_MAX_SENSORS) && (sensor_location != 0)) {
4800 data->sensor[i].location = sensor_location;
4801 data->sensor[i].caution_thresh = therm_limit;
4802 data->sensor[i].max_op_thresh = therm_limit -
4809 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4810 "eeprom read at offset %d failed", offset);
4811 return IXGBE_NOT_IMPLEMENTED;
4816 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
4817 * @hw: pointer to hardware structure
4818 * @map: pointer to u8 arr for returning map
4820 * Read the rtrup2tc HW register and resolve its content into map
4822 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
4826 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
4827 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
4828 map[i] = IXGBE_RTRUP2TC_UP_MASK &
4829 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
4833 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
4838 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4839 if (rxctrl & IXGBE_RXCTRL_RXEN) {
4840 if (hw->mac.type != ixgbe_mac_82598EB) {
4841 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4842 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
4843 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4844 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4845 hw->mac.set_lben = true;
4847 hw->mac.set_lben = false;
4850 rxctrl &= ~IXGBE_RXCTRL_RXEN;
4851 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
4855 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
4860 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4861 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
4863 if (hw->mac.type != ixgbe_mac_82598EB) {
4864 if (hw->mac.set_lben) {
4865 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4866 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
4867 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4868 hw->mac.set_lben = false;
4874 * ixgbe_mng_present - returns true when management capability is present
4875 * @hw: pointer to hardware structure
4877 bool ixgbe_mng_present(struct ixgbe_hw *hw)
4881 if (hw->mac.type < ixgbe_mac_82599EB)
4884 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
4885 fwsm &= IXGBE_FWSM_MODE_MASK;
4886 return fwsm == IXGBE_FWSM_FW_MODE_PT;
4890 * ixgbe_mng_enabled - Is the manageability engine enabled?
4891 * @hw: pointer to hardware structure
4893 * Returns true if the manageability engine is enabled.
4895 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
4897 u32 fwsm, manc, factps;
4899 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
4900 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
4903 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
4904 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
4907 if (hw->mac.type <= ixgbe_mac_X540) {
4908 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
4909 if (factps & IXGBE_FACTPS_MNGCG)
4917 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
4918 * @hw: pointer to hardware structure
4919 * @speed: new link speed
4920 * @autoneg_wait_to_complete: true when waiting for completion is needed
4922 * Set the link speed in the MAC and/or PHY register and restarts link.
4924 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
4925 ixgbe_link_speed speed,
4926 bool autoneg_wait_to_complete)
4928 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4929 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4930 s32 status = IXGBE_SUCCESS;
4933 bool autoneg, link_up = false;
4935 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
4937 /* Mask off requested but non-supported speeds */
4938 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
4939 if (status != IXGBE_SUCCESS)
4942 speed &= link_speed;
4944 /* Try each speed one by one, highest priority first. We do this in
4945 * software because 10Gb fiber doesn't support speed autonegotiation.
4947 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
4949 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
4951 /* If we already have link at this speed, just jump out */
4952 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
4953 if (status != IXGBE_SUCCESS)
4956 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
4959 /* Set the module link speed */
4960 switch (hw->phy.media_type) {
4961 case ixgbe_media_type_fiber:
4962 ixgbe_set_rate_select_speed(hw,
4963 IXGBE_LINK_SPEED_10GB_FULL);
4965 case ixgbe_media_type_fiber_qsfp:
4966 /* QSFP module automatically detects MAC link speed */
4969 DEBUGOUT("Unexpected media type.\n");
4973 /* Allow module to change analog characteristics (1G->10G) */
4976 status = ixgbe_setup_mac_link(hw,
4977 IXGBE_LINK_SPEED_10GB_FULL,
4978 autoneg_wait_to_complete);
4979 if (status != IXGBE_SUCCESS)
4982 /* Flap the Tx laser if it has not already been done */
4983 ixgbe_flap_tx_laser(hw);
4985 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
4986 * Section 73.10.2, we may have to wait up to 500ms if KR is
4987 * attempted. 82599 uses the same timing for 10g SFI.
4989 for (i = 0; i < 5; i++) {
4990 /* Wait for the link partner to also set speed */
4993 /* If we have link, just jump out */
4994 status = ixgbe_check_link(hw, &link_speed,
4996 if (status != IXGBE_SUCCESS)
5004 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
5006 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
5007 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
5009 /* If we already have link at this speed, just jump out */
5010 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
5011 if (status != IXGBE_SUCCESS)
5014 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
5017 /* Set the module link speed */
5018 switch (hw->phy.media_type) {
5019 case ixgbe_media_type_fiber:
5020 ixgbe_set_rate_select_speed(hw,
5021 IXGBE_LINK_SPEED_1GB_FULL);
5023 case ixgbe_media_type_fiber_qsfp:
5024 /* QSFP module automatically detects link speed */
5027 DEBUGOUT("Unexpected media type.\n");
5031 /* Allow module to change analog characteristics (10G->1G) */
5034 status = ixgbe_setup_mac_link(hw,
5035 IXGBE_LINK_SPEED_1GB_FULL,
5036 autoneg_wait_to_complete);
5037 if (status != IXGBE_SUCCESS)
5040 /* Flap the Tx laser if it has not already been done */
5041 ixgbe_flap_tx_laser(hw);
5043 /* Wait for the link partner to also set speed */
5046 /* If we have link, just jump out */
5047 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
5048 if (status != IXGBE_SUCCESS)
5055 /* We didn't get link. Configure back to the highest speed we tried,
5056 * (if there was more than one). We call ourselves back with just the
5057 * single highest speed that the user requested.
5060 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
5062 autoneg_wait_to_complete);
5065 /* Set autoneg_advertised value based on input link speed */
5066 hw->phy.autoneg_advertised = 0;
5068 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
5069 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
5071 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
5072 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
5078 * ixgbe_set_soft_rate_select_speed - Set module link speed
5079 * @hw: pointer to hardware structure
5080 * @speed: link speed to set
5082 * Set module link speed via the soft rate select.
5084 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
5085 ixgbe_link_speed speed)
5091 case IXGBE_LINK_SPEED_10GB_FULL:
5092 /* one bit mask same as setting on */
5093 rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
5095 case IXGBE_LINK_SPEED_1GB_FULL:
5096 rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
5099 DEBUGOUT("Invalid fixed module speed\n");
5104 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5105 IXGBE_I2C_EEPROM_DEV_ADDR2,
5108 DEBUGOUT("Failed to read Rx Rate Select RS0\n");
5112 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5114 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5115 IXGBE_I2C_EEPROM_DEV_ADDR2,
5118 DEBUGOUT("Failed to write Rx Rate Select RS0\n");
5123 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5124 IXGBE_I2C_EEPROM_DEV_ADDR2,
5127 DEBUGOUT("Failed to read Rx Rate Select RS1\n");
5131 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5133 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5134 IXGBE_I2C_EEPROM_DEV_ADDR2,
5137 DEBUGOUT("Failed to write Rx Rate Select RS1\n");