1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
36 #include "ixgbe_dcb.h"
37 #include "ixgbe_dcb_82599.h"
38 #include "ixgbe_api.h"
40 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
41 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
42 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
43 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
44 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
45 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
47 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
48 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
49 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
50 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw);
52 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
53 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
55 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
56 u16 words, u16 *data);
57 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
58 u16 words, u16 *data);
59 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
63 * ixgbe_init_ops_generic - Inits function ptrs
64 * @hw: pointer to the hardware structure
66 * Initialize the function pointers.
68 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
70 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
71 struct ixgbe_mac_info *mac = &hw->mac;
72 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
74 DEBUGFUNC("ixgbe_init_ops_generic");
77 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic;
78 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
79 if (eec & IXGBE_EEC_PRES) {
80 eeprom->ops.read = ixgbe_read_eerd_generic;
81 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic;
83 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic;
84 eeprom->ops.read_buffer =
85 ixgbe_read_eeprom_buffer_bit_bang_generic;
87 eeprom->ops.write = ixgbe_write_eeprom_generic;
88 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic;
89 eeprom->ops.validate_checksum =
90 ixgbe_validate_eeprom_checksum_generic;
91 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic;
92 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic;
95 mac->ops.init_hw = ixgbe_init_hw_generic;
96 mac->ops.reset_hw = NULL;
97 mac->ops.start_hw = ixgbe_start_hw_generic;
98 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic;
99 mac->ops.get_media_type = NULL;
100 mac->ops.get_supported_physical_layer = NULL;
101 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic;
102 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic;
103 mac->ops.stop_adapter = ixgbe_stop_adapter_generic;
104 mac->ops.get_bus_info = ixgbe_get_bus_info_generic;
105 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie;
106 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync;
107 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync;
108 mac->ops.prot_autoc_read = prot_autoc_read_generic;
109 mac->ops.prot_autoc_write = prot_autoc_write_generic;
112 mac->ops.led_on = ixgbe_led_on_generic;
113 mac->ops.led_off = ixgbe_led_off_generic;
114 mac->ops.blink_led_start = ixgbe_blink_led_start_generic;
115 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic;
117 /* RAR, Multicast, VLAN */
118 mac->ops.set_rar = ixgbe_set_rar_generic;
119 mac->ops.clear_rar = ixgbe_clear_rar_generic;
120 mac->ops.insert_mac_addr = NULL;
121 mac->ops.set_vmdq = NULL;
122 mac->ops.clear_vmdq = NULL;
123 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic;
124 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic;
125 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic;
126 mac->ops.enable_mc = ixgbe_enable_mc_generic;
127 mac->ops.disable_mc = ixgbe_disable_mc_generic;
128 mac->ops.clear_vfta = NULL;
129 mac->ops.set_vfta = NULL;
130 mac->ops.set_vlvf = NULL;
131 mac->ops.init_uta_tables = NULL;
132 mac->ops.enable_rx = ixgbe_enable_rx_generic;
133 mac->ops.disable_rx = ixgbe_disable_rx_generic;
136 mac->ops.fc_enable = ixgbe_fc_enable_generic;
137 mac->ops.setup_fc = ixgbe_setup_fc_generic;
138 mac->ops.fc_autoneg = ixgbe_fc_autoneg;
141 mac->ops.get_link_capabilities = NULL;
142 mac->ops.setup_link = NULL;
143 mac->ops.check_link = NULL;
144 mac->ops.dmac_config = NULL;
145 mac->ops.dmac_update_tcs = NULL;
146 mac->ops.dmac_config_tcs = NULL;
148 return IXGBE_SUCCESS;
152 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
154 * @hw: pointer to hardware structure
156 * This function returns true if the device supports flow control
157 * autonegotiation, and false if it does not.
160 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
162 bool supported = false;
163 ixgbe_link_speed speed;
166 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
168 switch (hw->phy.media_type) {
169 case ixgbe_media_type_fiber_qsfp:
170 case ixgbe_media_type_fiber:
171 /* flow control autoneg black list */
172 switch (hw->device_id) {
173 case IXGBE_DEV_ID_X550EM_A_SFP:
174 case IXGBE_DEV_ID_X550EM_A_SFP_N:
175 case IXGBE_DEV_ID_X550EM_A_QSFP:
176 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
180 hw->mac.ops.check_link(hw, &speed, &link_up, false);
181 /* if link is down, assume supported */
183 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
190 case ixgbe_media_type_backplane:
193 case ixgbe_media_type_copper:
194 /* only some copper devices support flow control autoneg */
195 switch (hw->device_id) {
196 case IXGBE_DEV_ID_82599_T3_LOM:
197 case IXGBE_DEV_ID_X540T:
198 case IXGBE_DEV_ID_X540T1:
199 case IXGBE_DEV_ID_X550T:
200 case IXGBE_DEV_ID_X550T1:
201 case IXGBE_DEV_ID_X550EM_X_10G_T:
202 case IXGBE_DEV_ID_X550EM_A_10G_T:
203 case IXGBE_DEV_ID_X550EM_A_1G_T:
204 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
215 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
216 "Device %x does not support flow control autoneg",
222 * ixgbe_setup_fc_generic - Set up flow control
223 * @hw: pointer to hardware structure
225 * Called at init time to set up flow control.
227 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
229 s32 ret_val = IXGBE_SUCCESS;
230 u32 reg = 0, reg_bp = 0;
234 DEBUGFUNC("ixgbe_setup_fc_generic");
236 /* Validate the requested mode */
237 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
238 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
239 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
240 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
245 * 10gig parts do not have a word in the EEPROM to determine the
246 * default flow control setting, so we explicitly set it to full.
248 if (hw->fc.requested_mode == ixgbe_fc_default)
249 hw->fc.requested_mode = ixgbe_fc_full;
252 * Set up the 1G and 10G flow control advertisement registers so the
253 * HW will be able to do fc autoneg once the cable is plugged in. If
254 * we link at 10G, the 1G advertisement is harmless and vice versa.
256 switch (hw->phy.media_type) {
257 case ixgbe_media_type_backplane:
258 /* some MAC's need RMW protection on AUTOC */
259 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
260 if (ret_val != IXGBE_SUCCESS)
263 /* only backplane uses autoc so fall though */
264 case ixgbe_media_type_fiber_qsfp:
265 case ixgbe_media_type_fiber:
266 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
269 case ixgbe_media_type_copper:
270 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
271 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
278 * The possible values of fc.requested_mode are:
279 * 0: Flow control is completely disabled
280 * 1: Rx flow control is enabled (we can receive pause frames,
281 * but not send pause frames).
282 * 2: Tx flow control is enabled (we can send pause frames but
283 * we do not support receiving pause frames).
284 * 3: Both Rx and Tx flow control (symmetric) are enabled.
287 switch (hw->fc.requested_mode) {
289 /* Flow control completely disabled by software override. */
290 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
291 if (hw->phy.media_type == ixgbe_media_type_backplane)
292 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
293 IXGBE_AUTOC_ASM_PAUSE);
294 else if (hw->phy.media_type == ixgbe_media_type_copper)
295 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
297 case ixgbe_fc_tx_pause:
299 * Tx Flow control is enabled, and Rx Flow control is
300 * disabled by software override.
302 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
303 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
304 if (hw->phy.media_type == ixgbe_media_type_backplane) {
305 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
306 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
307 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
308 reg_cu |= IXGBE_TAF_ASM_PAUSE;
309 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
312 case ixgbe_fc_rx_pause:
314 * Rx Flow control is enabled and Tx Flow control is
315 * disabled by software override. Since there really
316 * isn't a way to advertise that we are capable of RX
317 * Pause ONLY, we will advertise that we support both
318 * symmetric and asymmetric Rx PAUSE, as such we fall
319 * through to the fc_full statement. Later, we will
320 * disable the adapter's ability to send PAUSE frames.
323 /* Flow control (both Rx and Tx) is enabled by SW override. */
324 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
325 if (hw->phy.media_type == ixgbe_media_type_backplane)
326 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
327 IXGBE_AUTOC_ASM_PAUSE;
328 else if (hw->phy.media_type == ixgbe_media_type_copper)
329 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
332 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
333 "Flow control param set incorrectly\n");
334 ret_val = IXGBE_ERR_CONFIG;
339 if (hw->mac.type < ixgbe_mac_X540) {
341 * Enable auto-negotiation between the MAC & PHY;
342 * the MAC will advertise clause 37 flow control.
344 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
345 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
347 /* Disable AN timeout */
348 if (hw->fc.strict_ieee)
349 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
351 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
352 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
356 * AUTOC restart handles negotiation of 1G and 10G on backplane
357 * and copper. There is no need to set the PCS1GCTL register.
360 if (hw->phy.media_type == ixgbe_media_type_backplane) {
361 reg_bp |= IXGBE_AUTOC_AN_RESTART;
362 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
365 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
366 (ixgbe_device_supports_autoneg_fc(hw))) {
367 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
368 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
371 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
377 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
378 * @hw: pointer to hardware structure
380 * Starts the hardware by filling the bus info structure and media type, clears
381 * all on chip counters, initializes receive address registers, multicast
382 * table, VLAN filter table, calls routine to set up link and flow control
383 * settings, and leaves transmit and receive units disabled and uninitialized
385 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
391 DEBUGFUNC("ixgbe_start_hw_generic");
393 /* Set the media type */
394 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
396 /* PHY ops initialization must be done in reset_hw() */
398 /* Clear the VLAN filter table */
399 hw->mac.ops.clear_vfta(hw);
401 /* Clear statistics registers */
402 hw->mac.ops.clear_hw_cntrs(hw);
404 /* Set No Snoop Disable */
405 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
406 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
407 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
408 IXGBE_WRITE_FLUSH(hw);
410 /* Setup flow control */
411 ret_val = ixgbe_setup_fc(hw);
412 if (ret_val != IXGBE_SUCCESS && ret_val != IXGBE_NOT_IMPLEMENTED)
415 /* Cache bit indicating need for crosstalk fix */
416 switch (hw->mac.type) {
417 case ixgbe_mac_82599EB:
418 case ixgbe_mac_X550EM_x:
419 case ixgbe_mac_X550EM_a:
420 hw->mac.ops.get_device_caps(hw, &device_caps);
421 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
422 hw->need_crosstalk_fix = false;
424 hw->need_crosstalk_fix = true;
427 hw->need_crosstalk_fix = false;
431 /* Clear adapter stopped flag */
432 hw->adapter_stopped = false;
434 return IXGBE_SUCCESS;
438 * ixgbe_start_hw_gen2 - Init sequence for common device family
439 * @hw: pointer to hw structure
441 * Performs the init sequence common to the second generation
443 * Devices in the second generation:
447 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
452 /* Clear the rate limiters */
453 for (i = 0; i < hw->mac.max_tx_queues; i++) {
454 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
455 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
457 IXGBE_WRITE_FLUSH(hw);
459 /* Disable relaxed ordering */
460 for (i = 0; i < hw->mac.max_tx_queues; i++) {
461 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
462 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
463 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
466 for (i = 0; i < hw->mac.max_rx_queues; i++) {
467 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
468 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
469 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
470 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
473 return IXGBE_SUCCESS;
477 * ixgbe_init_hw_generic - Generic hardware initialization
478 * @hw: pointer to hardware structure
480 * Initialize the hardware by resetting the hardware, filling the bus info
481 * structure and media type, clears all on chip counters, initializes receive
482 * address registers, multicast table, VLAN filter table, calls routine to set
483 * up link and flow control settings, and leaves transmit and receive units
484 * disabled and uninitialized
486 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
490 DEBUGFUNC("ixgbe_init_hw_generic");
492 /* Reset the hardware */
493 status = hw->mac.ops.reset_hw(hw);
495 if (status == IXGBE_SUCCESS) {
497 status = hw->mac.ops.start_hw(hw);
504 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
505 * @hw: pointer to hardware structure
507 * Clears all hardware statistics counters by reading them from the hardware
508 * Statistics counters are clear on read.
510 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
514 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
516 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
517 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
518 IXGBE_READ_REG(hw, IXGBE_ERRBC);
519 IXGBE_READ_REG(hw, IXGBE_MSPDC);
520 for (i = 0; i < 8; i++)
521 IXGBE_READ_REG(hw, IXGBE_MPC(i));
523 IXGBE_READ_REG(hw, IXGBE_MLFC);
524 IXGBE_READ_REG(hw, IXGBE_MRFC);
525 IXGBE_READ_REG(hw, IXGBE_RLEC);
526 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
527 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
528 if (hw->mac.type >= ixgbe_mac_82599EB) {
529 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
530 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
532 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
533 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
536 for (i = 0; i < 8; i++) {
537 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
538 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
539 if (hw->mac.type >= ixgbe_mac_82599EB) {
540 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
541 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
543 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
544 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
547 if (hw->mac.type >= ixgbe_mac_82599EB)
548 for (i = 0; i < 8; i++)
549 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
550 IXGBE_READ_REG(hw, IXGBE_PRC64);
551 IXGBE_READ_REG(hw, IXGBE_PRC127);
552 IXGBE_READ_REG(hw, IXGBE_PRC255);
553 IXGBE_READ_REG(hw, IXGBE_PRC511);
554 IXGBE_READ_REG(hw, IXGBE_PRC1023);
555 IXGBE_READ_REG(hw, IXGBE_PRC1522);
556 IXGBE_READ_REG(hw, IXGBE_GPRC);
557 IXGBE_READ_REG(hw, IXGBE_BPRC);
558 IXGBE_READ_REG(hw, IXGBE_MPRC);
559 IXGBE_READ_REG(hw, IXGBE_GPTC);
560 IXGBE_READ_REG(hw, IXGBE_GORCL);
561 IXGBE_READ_REG(hw, IXGBE_GORCH);
562 IXGBE_READ_REG(hw, IXGBE_GOTCL);
563 IXGBE_READ_REG(hw, IXGBE_GOTCH);
564 if (hw->mac.type == ixgbe_mac_82598EB)
565 for (i = 0; i < 8; i++)
566 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
567 IXGBE_READ_REG(hw, IXGBE_RUC);
568 IXGBE_READ_REG(hw, IXGBE_RFC);
569 IXGBE_READ_REG(hw, IXGBE_ROC);
570 IXGBE_READ_REG(hw, IXGBE_RJC);
571 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
572 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
573 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
574 IXGBE_READ_REG(hw, IXGBE_TORL);
575 IXGBE_READ_REG(hw, IXGBE_TORH);
576 IXGBE_READ_REG(hw, IXGBE_TPR);
577 IXGBE_READ_REG(hw, IXGBE_TPT);
578 IXGBE_READ_REG(hw, IXGBE_PTC64);
579 IXGBE_READ_REG(hw, IXGBE_PTC127);
580 IXGBE_READ_REG(hw, IXGBE_PTC255);
581 IXGBE_READ_REG(hw, IXGBE_PTC511);
582 IXGBE_READ_REG(hw, IXGBE_PTC1023);
583 IXGBE_READ_REG(hw, IXGBE_PTC1522);
584 IXGBE_READ_REG(hw, IXGBE_MPTC);
585 IXGBE_READ_REG(hw, IXGBE_BPTC);
586 for (i = 0; i < 16; i++) {
587 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
588 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
589 if (hw->mac.type >= ixgbe_mac_82599EB) {
590 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
591 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
592 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
593 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
594 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
596 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
597 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
601 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
603 ixgbe_identify_phy(hw);
604 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
605 IXGBE_MDIO_PCS_DEV_TYPE, &i);
606 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
607 IXGBE_MDIO_PCS_DEV_TYPE, &i);
608 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
609 IXGBE_MDIO_PCS_DEV_TYPE, &i);
610 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
611 IXGBE_MDIO_PCS_DEV_TYPE, &i);
614 return IXGBE_SUCCESS;
618 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
619 * @hw: pointer to hardware structure
620 * @pba_num: stores the part number string from the EEPROM
621 * @pba_num_size: part number string buffer length
623 * Reads the part number string from the EEPROM.
625 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
634 DEBUGFUNC("ixgbe_read_pba_string_generic");
636 if (pba_num == NULL) {
637 DEBUGOUT("PBA string buffer was null\n");
638 return IXGBE_ERR_INVALID_ARGUMENT;
641 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
643 DEBUGOUT("NVM Read Error\n");
647 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
649 DEBUGOUT("NVM Read Error\n");
654 * if data is not ptr guard the PBA must be in legacy format which
655 * means pba_ptr is actually our second data word for the PBA number
656 * and we can decode it into an ascii string
658 if (data != IXGBE_PBANUM_PTR_GUARD) {
659 DEBUGOUT("NVM PBA number is not stored as string\n");
661 /* we will need 11 characters to store the PBA */
662 if (pba_num_size < 11) {
663 DEBUGOUT("PBA string buffer too small\n");
664 return IXGBE_ERR_NO_SPACE;
667 /* extract hex string from data and pba_ptr */
668 pba_num[0] = (data >> 12) & 0xF;
669 pba_num[1] = (data >> 8) & 0xF;
670 pba_num[2] = (data >> 4) & 0xF;
671 pba_num[3] = data & 0xF;
672 pba_num[4] = (pba_ptr >> 12) & 0xF;
673 pba_num[5] = (pba_ptr >> 8) & 0xF;
676 pba_num[8] = (pba_ptr >> 4) & 0xF;
677 pba_num[9] = pba_ptr & 0xF;
679 /* put a null character on the end of our string */
682 /* switch all the data but the '-' to hex char */
683 for (offset = 0; offset < 10; offset++) {
684 if (pba_num[offset] < 0xA)
685 pba_num[offset] += '0';
686 else if (pba_num[offset] < 0x10)
687 pba_num[offset] += 'A' - 0xA;
690 return IXGBE_SUCCESS;
693 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
695 DEBUGOUT("NVM Read Error\n");
699 if (length == 0xFFFF || length == 0) {
700 DEBUGOUT("NVM PBA number section invalid length\n");
701 return IXGBE_ERR_PBA_SECTION;
704 /* check if pba_num buffer is big enough */
705 if (pba_num_size < (((u32)length * 2) - 1)) {
706 DEBUGOUT("PBA string buffer too small\n");
707 return IXGBE_ERR_NO_SPACE;
710 /* trim pba length from start of string */
714 for (offset = 0; offset < length; offset++) {
715 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
717 DEBUGOUT("NVM Read Error\n");
720 pba_num[offset * 2] = (u8)(data >> 8);
721 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
723 pba_num[offset * 2] = '\0';
725 return IXGBE_SUCCESS;
729 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
730 * @hw: pointer to hardware structure
731 * @pba_num: stores the part number from the EEPROM
733 * Reads the part number from the EEPROM.
735 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
740 DEBUGFUNC("ixgbe_read_pba_num_generic");
742 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
744 DEBUGOUT("NVM Read Error\n");
746 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
747 DEBUGOUT("NVM Not supported\n");
748 return IXGBE_NOT_IMPLEMENTED;
750 *pba_num = (u32)(data << 16);
752 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
754 DEBUGOUT("NVM Read Error\n");
759 return IXGBE_SUCCESS;
764 * @hw: pointer to the HW structure
765 * @eeprom_buf: optional pointer to EEPROM image
766 * @eeprom_buf_size: size of EEPROM image in words
767 * @max_pba_block_size: PBA block size limit
768 * @pba: pointer to output PBA structure
770 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
771 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
774 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
775 u32 eeprom_buf_size, u16 max_pba_block_size,
776 struct ixgbe_pba *pba)
782 return IXGBE_ERR_PARAM;
784 if (eeprom_buf == NULL) {
785 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
790 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
791 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
792 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
794 return IXGBE_ERR_PARAM;
798 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
799 if (pba->pba_block == NULL)
800 return IXGBE_ERR_PARAM;
802 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
808 if (pba_block_size > max_pba_block_size)
809 return IXGBE_ERR_PARAM;
811 if (eeprom_buf == NULL) {
812 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
818 if (eeprom_buf_size > (u32)(pba->word[1] +
820 memcpy(pba->pba_block,
821 &eeprom_buf[pba->word[1]],
822 pba_block_size * sizeof(u16));
824 return IXGBE_ERR_PARAM;
829 return IXGBE_SUCCESS;
833 * ixgbe_write_pba_raw
834 * @hw: pointer to the HW structure
835 * @eeprom_buf: optional pointer to EEPROM image
836 * @eeprom_buf_size: size of EEPROM image in words
837 * @pba: pointer to PBA structure
839 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
840 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
843 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
844 u32 eeprom_buf_size, struct ixgbe_pba *pba)
849 return IXGBE_ERR_PARAM;
851 if (eeprom_buf == NULL) {
852 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
857 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
858 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
859 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
861 return IXGBE_ERR_PARAM;
865 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
866 if (pba->pba_block == NULL)
867 return IXGBE_ERR_PARAM;
869 if (eeprom_buf == NULL) {
870 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
876 if (eeprom_buf_size > (u32)(pba->word[1] +
877 pba->pba_block[0])) {
878 memcpy(&eeprom_buf[pba->word[1]],
880 pba->pba_block[0] * sizeof(u16));
882 return IXGBE_ERR_PARAM;
887 return IXGBE_SUCCESS;
891 * ixgbe_get_pba_block_size
892 * @hw: pointer to the HW structure
893 * @eeprom_buf: optional pointer to EEPROM image
894 * @eeprom_buf_size: size of EEPROM image in words
895 * @pba_data_size: pointer to output variable
897 * Returns the size of the PBA block in words. Function operates on EEPROM
898 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
902 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
903 u32 eeprom_buf_size, u16 *pba_block_size)
909 DEBUGFUNC("ixgbe_get_pba_block_size");
911 if (eeprom_buf == NULL) {
912 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
917 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
918 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
919 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
921 return IXGBE_ERR_PARAM;
925 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
926 if (eeprom_buf == NULL) {
927 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
932 if (eeprom_buf_size > pba_word[1])
933 length = eeprom_buf[pba_word[1] + 0];
935 return IXGBE_ERR_PARAM;
938 if (length == 0xFFFF || length == 0)
939 return IXGBE_ERR_PBA_SECTION;
941 /* PBA number in legacy format, there is no PBA Block. */
945 if (pba_block_size != NULL)
946 *pba_block_size = length;
948 return IXGBE_SUCCESS;
952 * ixgbe_get_mac_addr_generic - Generic get MAC address
953 * @hw: pointer to hardware structure
954 * @mac_addr: Adapter MAC address
956 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
957 * A reset of the adapter must be performed prior to calling this function
958 * in order for the MAC address to have been loaded from the EEPROM into RAR0
960 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
966 DEBUGFUNC("ixgbe_get_mac_addr_generic");
968 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
969 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
971 for (i = 0; i < 4; i++)
972 mac_addr[i] = (u8)(rar_low >> (i*8));
974 for (i = 0; i < 2; i++)
975 mac_addr[i+4] = (u8)(rar_high >> (i*8));
977 return IXGBE_SUCCESS;
981 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
982 * @hw: pointer to hardware structure
983 * @link_status: the link status returned by the PCI config space
985 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
987 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
989 struct ixgbe_mac_info *mac = &hw->mac;
991 if (hw->bus.type == ixgbe_bus_type_unknown)
992 hw->bus.type = ixgbe_bus_type_pci_express;
994 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
995 case IXGBE_PCI_LINK_WIDTH_1:
996 hw->bus.width = ixgbe_bus_width_pcie_x1;
998 case IXGBE_PCI_LINK_WIDTH_2:
999 hw->bus.width = ixgbe_bus_width_pcie_x2;
1001 case IXGBE_PCI_LINK_WIDTH_4:
1002 hw->bus.width = ixgbe_bus_width_pcie_x4;
1004 case IXGBE_PCI_LINK_WIDTH_8:
1005 hw->bus.width = ixgbe_bus_width_pcie_x8;
1008 hw->bus.width = ixgbe_bus_width_unknown;
1012 switch (link_status & IXGBE_PCI_LINK_SPEED) {
1013 case IXGBE_PCI_LINK_SPEED_2500:
1014 hw->bus.speed = ixgbe_bus_speed_2500;
1016 case IXGBE_PCI_LINK_SPEED_5000:
1017 hw->bus.speed = ixgbe_bus_speed_5000;
1019 case IXGBE_PCI_LINK_SPEED_8000:
1020 hw->bus.speed = ixgbe_bus_speed_8000;
1023 hw->bus.speed = ixgbe_bus_speed_unknown;
1027 mac->ops.set_lan_id(hw);
1031 * ixgbe_get_bus_info_generic - Generic set PCI bus info
1032 * @hw: pointer to hardware structure
1034 * Gets the PCI bus info (speed, width, type) then calls helper function to
1035 * store this data within the ixgbe_hw structure.
1037 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
1041 DEBUGFUNC("ixgbe_get_bus_info_generic");
1043 /* Get the negotiated link width and speed from PCI config space */
1044 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
1046 ixgbe_set_pci_config_data_generic(hw, link_status);
1048 return IXGBE_SUCCESS;
1052 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
1053 * @hw: pointer to the HW structure
1055 * Determines the LAN function id by reading memory-mapped registers and swaps
1056 * the port value if requested, and set MAC instance for devices that share
1059 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
1061 struct ixgbe_bus_info *bus = &hw->bus;
1065 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
1067 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
1068 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
1069 bus->lan_id = (u8)bus->func;
1071 /* check for a port swap */
1072 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
1073 if (reg & IXGBE_FACTPS_LFS)
1076 /* Get MAC instance from EEPROM for configuring CS4227 */
1077 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) {
1078 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4);
1079 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >>
1080 IXGBE_EE_CTRL_4_INST_ID_SHIFT;
1085 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1086 * @hw: pointer to hardware structure
1088 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
1089 * disables transmit and receive units. The adapter_stopped flag is used by
1090 * the shared code and drivers to determine if the adapter is in a stopped
1091 * state and should not touch the hardware.
1093 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1098 DEBUGFUNC("ixgbe_stop_adapter_generic");
1101 * Set the adapter_stopped flag so other driver functions stop touching
1104 hw->adapter_stopped = true;
1106 /* Disable the receive unit */
1107 ixgbe_disable_rx(hw);
1109 /* Clear interrupt mask to stop interrupts from being generated */
1110 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1112 /* Clear any pending interrupts, flush previous writes */
1113 IXGBE_READ_REG(hw, IXGBE_EICR);
1115 /* Disable the transmit unit. Each queue must be disabled. */
1116 for (i = 0; i < hw->mac.max_tx_queues; i++)
1117 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1119 /* Disable the receive unit by stopping each queue */
1120 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1121 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1122 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1123 reg_val |= IXGBE_RXDCTL_SWFLSH;
1124 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1127 /* flush all queues disables */
1128 IXGBE_WRITE_FLUSH(hw);
1132 * Prevent the PCI-E bus from hanging by disabling PCI-E master
1133 * access and verify no pending requests
1135 return ixgbe_disable_pcie_master(hw);
1139 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1140 * @hw: pointer to hardware structure
1141 * @index: led number to turn on
1143 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1145 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1147 DEBUGFUNC("ixgbe_led_on_generic");
1150 return IXGBE_ERR_PARAM;
1152 /* To turn on the LED, set mode to ON. */
1153 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1154 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
1155 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1156 IXGBE_WRITE_FLUSH(hw);
1158 return IXGBE_SUCCESS;
1162 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1163 * @hw: pointer to hardware structure
1164 * @index: led number to turn off
1166 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1168 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1170 DEBUGFUNC("ixgbe_led_off_generic");
1173 return IXGBE_ERR_PARAM;
1175 /* To turn off the LED, set mode to OFF. */
1176 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1177 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
1178 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1179 IXGBE_WRITE_FLUSH(hw);
1181 return IXGBE_SUCCESS;
1185 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1186 * @hw: pointer to hardware structure
1188 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1189 * ixgbe_hw struct in order to set up EEPROM access.
1191 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1193 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1197 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
1199 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1200 eeprom->type = ixgbe_eeprom_none;
1201 /* Set default semaphore delay to 10ms which is a well
1203 eeprom->semaphore_delay = 10;
1204 /* Clear EEPROM page size, it will be initialized as needed */
1205 eeprom->word_page_size = 0;
1208 * Check for EEPROM present first.
1209 * If not present leave as none
1211 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1212 if (eec & IXGBE_EEC_PRES) {
1213 eeprom->type = ixgbe_eeprom_spi;
1216 * SPI EEPROM is assumed here. This code would need to
1217 * change if a future EEPROM is not SPI.
1219 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1220 IXGBE_EEC_SIZE_SHIFT);
1221 eeprom->word_size = 1 << (eeprom_size +
1222 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1225 if (eec & IXGBE_EEC_ADDR_SIZE)
1226 eeprom->address_bits = 16;
1228 eeprom->address_bits = 8;
1229 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
1230 "%d\n", eeprom->type, eeprom->word_size,
1231 eeprom->address_bits);
1234 return IXGBE_SUCCESS;
1238 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1239 * @hw: pointer to hardware structure
1240 * @offset: offset within the EEPROM to write
1241 * @words: number of word(s)
1242 * @data: 16 bit word(s) to write to EEPROM
1244 * Reads 16 bit word(s) from EEPROM through bit-bang method
1246 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1247 u16 words, u16 *data)
1249 s32 status = IXGBE_SUCCESS;
1252 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
1254 hw->eeprom.ops.init_params(hw);
1257 status = IXGBE_ERR_INVALID_ARGUMENT;
1261 if (offset + words > hw->eeprom.word_size) {
1262 status = IXGBE_ERR_EEPROM;
1267 * The EEPROM page size cannot be queried from the chip. We do lazy
1268 * initialization. It is worth to do that when we write large buffer.
1270 if ((hw->eeprom.word_page_size == 0) &&
1271 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
1272 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1275 * We cannot hold synchronization semaphores for too long
1276 * to avoid other entity starvation. However it is more efficient
1277 * to read in bursts than synchronizing access for each word.
1279 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1280 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1281 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1282 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1285 if (status != IXGBE_SUCCESS)
1294 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1295 * @hw: pointer to hardware structure
1296 * @offset: offset within the EEPROM to be written to
1297 * @words: number of word(s)
1298 * @data: 16 bit word(s) to be written to the EEPROM
1300 * If ixgbe_eeprom_update_checksum is not called after this function, the
1301 * EEPROM will most likely contain an invalid checksum.
1303 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1304 u16 words, u16 *data)
1310 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1312 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1314 /* Prepare the EEPROM for writing */
1315 status = ixgbe_acquire_eeprom(hw);
1317 if (status == IXGBE_SUCCESS) {
1318 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1319 ixgbe_release_eeprom(hw);
1320 status = IXGBE_ERR_EEPROM;
1324 if (status == IXGBE_SUCCESS) {
1325 for (i = 0; i < words; i++) {
1326 ixgbe_standby_eeprom(hw);
1328 /* Send the WRITE ENABLE command (8 bit opcode ) */
1329 ixgbe_shift_out_eeprom_bits(hw,
1330 IXGBE_EEPROM_WREN_OPCODE_SPI,
1331 IXGBE_EEPROM_OPCODE_BITS);
1333 ixgbe_standby_eeprom(hw);
1336 * Some SPI eeproms use the 8th address bit embedded
1339 if ((hw->eeprom.address_bits == 8) &&
1340 ((offset + i) >= 128))
1341 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1343 /* Send the Write command (8-bit opcode + addr) */
1344 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1345 IXGBE_EEPROM_OPCODE_BITS);
1346 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1347 hw->eeprom.address_bits);
1349 page_size = hw->eeprom.word_page_size;
1351 /* Send the data in burst via SPI*/
1354 word = (word >> 8) | (word << 8);
1355 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1360 /* do not wrap around page */
1361 if (((offset + i) & (page_size - 1)) ==
1364 } while (++i < words);
1366 ixgbe_standby_eeprom(hw);
1369 /* Done with writing - release the EEPROM */
1370 ixgbe_release_eeprom(hw);
1377 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1378 * @hw: pointer to hardware structure
1379 * @offset: offset within the EEPROM to be written to
1380 * @data: 16 bit word to be written to the EEPROM
1382 * If ixgbe_eeprom_update_checksum is not called after this function, the
1383 * EEPROM will most likely contain an invalid checksum.
1385 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1389 DEBUGFUNC("ixgbe_write_eeprom_generic");
1391 hw->eeprom.ops.init_params(hw);
1393 if (offset >= hw->eeprom.word_size) {
1394 status = IXGBE_ERR_EEPROM;
1398 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1405 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1406 * @hw: pointer to hardware structure
1407 * @offset: offset within the EEPROM to be read
1408 * @data: read 16 bit words(s) from EEPROM
1409 * @words: number of word(s)
1411 * Reads 16 bit word(s) from EEPROM through bit-bang method
1413 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1414 u16 words, u16 *data)
1416 s32 status = IXGBE_SUCCESS;
1419 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1421 hw->eeprom.ops.init_params(hw);
1424 status = IXGBE_ERR_INVALID_ARGUMENT;
1428 if (offset + words > hw->eeprom.word_size) {
1429 status = IXGBE_ERR_EEPROM;
1434 * We cannot hold synchronization semaphores for too long
1435 * to avoid other entity starvation. However it is more efficient
1436 * to read in bursts than synchronizing access for each word.
1438 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1439 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1440 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1442 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1445 if (status != IXGBE_SUCCESS)
1454 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1455 * @hw: pointer to hardware structure
1456 * @offset: offset within the EEPROM to be read
1457 * @words: number of word(s)
1458 * @data: read 16 bit word(s) from EEPROM
1460 * Reads 16 bit word(s) from EEPROM through bit-bang method
1462 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1463 u16 words, u16 *data)
1467 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1470 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1472 /* Prepare the EEPROM for reading */
1473 status = ixgbe_acquire_eeprom(hw);
1475 if (status == IXGBE_SUCCESS) {
1476 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1477 ixgbe_release_eeprom(hw);
1478 status = IXGBE_ERR_EEPROM;
1482 if (status == IXGBE_SUCCESS) {
1483 for (i = 0; i < words; i++) {
1484 ixgbe_standby_eeprom(hw);
1486 * Some SPI eeproms use the 8th address bit embedded
1489 if ((hw->eeprom.address_bits == 8) &&
1490 ((offset + i) >= 128))
1491 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1493 /* Send the READ command (opcode + addr) */
1494 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1495 IXGBE_EEPROM_OPCODE_BITS);
1496 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1497 hw->eeprom.address_bits);
1499 /* Read the data. */
1500 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1501 data[i] = (word_in >> 8) | (word_in << 8);
1504 /* End this read operation */
1505 ixgbe_release_eeprom(hw);
1512 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1513 * @hw: pointer to hardware structure
1514 * @offset: offset within the EEPROM to be read
1515 * @data: read 16 bit value from EEPROM
1517 * Reads 16 bit value from EEPROM through bit-bang method
1519 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1524 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1526 hw->eeprom.ops.init_params(hw);
1528 if (offset >= hw->eeprom.word_size) {
1529 status = IXGBE_ERR_EEPROM;
1533 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1540 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1541 * @hw: pointer to hardware structure
1542 * @offset: offset of word in the EEPROM to read
1543 * @words: number of word(s)
1544 * @data: 16 bit word(s) from the EEPROM
1546 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1548 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1549 u16 words, u16 *data)
1552 s32 status = IXGBE_SUCCESS;
1555 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1557 hw->eeprom.ops.init_params(hw);
1560 status = IXGBE_ERR_INVALID_ARGUMENT;
1561 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1565 if (offset >= hw->eeprom.word_size) {
1566 status = IXGBE_ERR_EEPROM;
1567 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1571 for (i = 0; i < words; i++) {
1572 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1573 IXGBE_EEPROM_RW_REG_START;
1575 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1576 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1578 if (status == IXGBE_SUCCESS) {
1579 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1580 IXGBE_EEPROM_RW_REG_DATA);
1582 DEBUGOUT("Eeprom read timed out\n");
1591 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1592 * @hw: pointer to hardware structure
1593 * @offset: offset within the EEPROM to be used as a scratch pad
1595 * Discover EEPROM page size by writing marching data at given offset.
1596 * This function is called only when we are writing a new large buffer
1597 * at given offset so the data would be overwritten anyway.
1599 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1602 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1603 s32 status = IXGBE_SUCCESS;
1606 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1608 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1611 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1612 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1613 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1614 hw->eeprom.word_page_size = 0;
1615 if (status != IXGBE_SUCCESS)
1618 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1619 if (status != IXGBE_SUCCESS)
1623 * When writing in burst more than the actual page size
1624 * EEPROM address wraps around current page.
1626 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1628 DEBUGOUT1("Detected EEPROM page size = %d words.",
1629 hw->eeprom.word_page_size);
1635 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1636 * @hw: pointer to hardware structure
1637 * @offset: offset of word in the EEPROM to read
1638 * @data: word read from the EEPROM
1640 * Reads a 16 bit word from the EEPROM using the EERD register.
1642 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1644 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1648 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1649 * @hw: pointer to hardware structure
1650 * @offset: offset of word in the EEPROM to write
1651 * @words: number of word(s)
1652 * @data: word(s) write to the EEPROM
1654 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1656 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1657 u16 words, u16 *data)
1660 s32 status = IXGBE_SUCCESS;
1663 DEBUGFUNC("ixgbe_write_eewr_generic");
1665 hw->eeprom.ops.init_params(hw);
1668 status = IXGBE_ERR_INVALID_ARGUMENT;
1669 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1673 if (offset >= hw->eeprom.word_size) {
1674 status = IXGBE_ERR_EEPROM;
1675 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1679 for (i = 0; i < words; i++) {
1680 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1681 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1682 IXGBE_EEPROM_RW_REG_START;
1684 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1685 if (status != IXGBE_SUCCESS) {
1686 DEBUGOUT("Eeprom write EEWR timed out\n");
1690 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1692 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1693 if (status != IXGBE_SUCCESS) {
1694 DEBUGOUT("Eeprom write EEWR timed out\n");
1704 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1705 * @hw: pointer to hardware structure
1706 * @offset: offset of word in the EEPROM to write
1707 * @data: word write to the EEPROM
1709 * Write a 16 bit word to the EEPROM using the EEWR register.
1711 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1713 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1717 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1718 * @hw: pointer to hardware structure
1719 * @ee_reg: EEPROM flag for polling
1721 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1722 * read or write is done respectively.
1724 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1728 s32 status = IXGBE_ERR_EEPROM;
1730 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1732 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1733 if (ee_reg == IXGBE_NVM_POLL_READ)
1734 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1736 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1738 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1739 status = IXGBE_SUCCESS;
1745 if (i == IXGBE_EERD_EEWR_ATTEMPTS)
1746 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1747 "EEPROM read/write done polling timed out");
1753 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1754 * @hw: pointer to hardware structure
1756 * Prepares EEPROM for access using bit-bang method. This function should
1757 * be called before issuing a command to the EEPROM.
1759 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1761 s32 status = IXGBE_SUCCESS;
1765 DEBUGFUNC("ixgbe_acquire_eeprom");
1767 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1769 status = IXGBE_ERR_SWFW_SYNC;
1771 if (status == IXGBE_SUCCESS) {
1772 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1774 /* Request EEPROM Access */
1775 eec |= IXGBE_EEC_REQ;
1776 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1778 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1779 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1780 if (eec & IXGBE_EEC_GNT)
1785 /* Release if grant not acquired */
1786 if (!(eec & IXGBE_EEC_GNT)) {
1787 eec &= ~IXGBE_EEC_REQ;
1788 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1789 DEBUGOUT("Could not acquire EEPROM grant\n");
1791 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1792 status = IXGBE_ERR_EEPROM;
1795 /* Setup EEPROM for Read/Write */
1796 if (status == IXGBE_SUCCESS) {
1797 /* Clear CS and SK */
1798 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1799 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1800 IXGBE_WRITE_FLUSH(hw);
1808 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1809 * @hw: pointer to hardware structure
1811 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1813 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1815 s32 status = IXGBE_ERR_EEPROM;
1820 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1823 /* Get SMBI software semaphore between device drivers first */
1824 for (i = 0; i < timeout; i++) {
1826 * If the SMBI bit is 0 when we read it, then the bit will be
1827 * set and we have the semaphore
1829 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1830 if (!(swsm & IXGBE_SWSM_SMBI)) {
1831 status = IXGBE_SUCCESS;
1838 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1841 * this release is particularly important because our attempts
1842 * above to get the semaphore may have succeeded, and if there
1843 * was a timeout, we should unconditionally clear the semaphore
1844 * bits to free the driver to make progress
1846 ixgbe_release_eeprom_semaphore(hw);
1851 * If the SMBI bit is 0 when we read it, then the bit will be
1852 * set and we have the semaphore
1854 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1855 if (!(swsm & IXGBE_SWSM_SMBI))
1856 status = IXGBE_SUCCESS;
1859 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1860 if (status == IXGBE_SUCCESS) {
1861 for (i = 0; i < timeout; i++) {
1862 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1864 /* Set the SW EEPROM semaphore bit to request access */
1865 swsm |= IXGBE_SWSM_SWESMBI;
1866 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
1869 * If we set the bit successfully then we got the
1872 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1873 if (swsm & IXGBE_SWSM_SWESMBI)
1880 * Release semaphores and return error if SW EEPROM semaphore
1881 * was not granted because we don't have access to the EEPROM
1884 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1885 "SWESMBI Software EEPROM semaphore not granted.\n");
1886 ixgbe_release_eeprom_semaphore(hw);
1887 status = IXGBE_ERR_EEPROM;
1890 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1891 "Software semaphore SMBI between device drivers "
1899 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1900 * @hw: pointer to hardware structure
1902 * This function clears hardware semaphore bits.
1904 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1908 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1910 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1912 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1913 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1914 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1915 IXGBE_WRITE_FLUSH(hw);
1919 * ixgbe_ready_eeprom - Polls for EEPROM ready
1920 * @hw: pointer to hardware structure
1922 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1924 s32 status = IXGBE_SUCCESS;
1928 DEBUGFUNC("ixgbe_ready_eeprom");
1931 * Read "Status Register" repeatedly until the LSB is cleared. The
1932 * EEPROM will signal that the command has been completed by clearing
1933 * bit 0 of the internal status register. If it's not cleared within
1934 * 5 milliseconds, then error out.
1936 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1937 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1938 IXGBE_EEPROM_OPCODE_BITS);
1939 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1940 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1944 ixgbe_standby_eeprom(hw);
1948 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1949 * devices (and only 0-5mSec on 5V devices)
1951 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1952 DEBUGOUT("SPI EEPROM Status error\n");
1953 status = IXGBE_ERR_EEPROM;
1960 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1961 * @hw: pointer to hardware structure
1963 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1967 DEBUGFUNC("ixgbe_standby_eeprom");
1969 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1971 /* Toggle CS to flush commands */
1972 eec |= IXGBE_EEC_CS;
1973 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1974 IXGBE_WRITE_FLUSH(hw);
1976 eec &= ~IXGBE_EEC_CS;
1977 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1978 IXGBE_WRITE_FLUSH(hw);
1983 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1984 * @hw: pointer to hardware structure
1985 * @data: data to send to the EEPROM
1986 * @count: number of bits to shift out
1988 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1995 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
1997 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2000 * Mask is used to shift "count" bits of "data" out to the EEPROM
2001 * one bit at a time. Determine the starting bit based on count
2003 mask = 0x01 << (count - 1);
2005 for (i = 0; i < count; i++) {
2007 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
2008 * "1", and then raising and then lowering the clock (the SK
2009 * bit controls the clock input to the EEPROM). A "0" is
2010 * shifted out to the EEPROM by setting "DI" to "0" and then
2011 * raising and then lowering the clock.
2014 eec |= IXGBE_EEC_DI;
2016 eec &= ~IXGBE_EEC_DI;
2018 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2019 IXGBE_WRITE_FLUSH(hw);
2023 ixgbe_raise_eeprom_clk(hw, &eec);
2024 ixgbe_lower_eeprom_clk(hw, &eec);
2027 * Shift mask to signify next bit of data to shift in to the
2033 /* We leave the "DI" bit set to "0" when we leave this routine. */
2034 eec &= ~IXGBE_EEC_DI;
2035 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2036 IXGBE_WRITE_FLUSH(hw);
2040 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
2041 * @hw: pointer to hardware structure
2043 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
2049 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
2052 * In order to read a register from the EEPROM, we need to shift
2053 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
2054 * the clock input to the EEPROM (setting the SK bit), and then reading
2055 * the value of the "DO" bit. During this "shifting in" process the
2056 * "DI" bit should always be clear.
2058 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2060 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
2062 for (i = 0; i < count; i++) {
2064 ixgbe_raise_eeprom_clk(hw, &eec);
2066 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2068 eec &= ~(IXGBE_EEC_DI);
2069 if (eec & IXGBE_EEC_DO)
2072 ixgbe_lower_eeprom_clk(hw, &eec);
2079 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
2080 * @hw: pointer to hardware structure
2081 * @eec: EEC register's current value
2083 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2085 DEBUGFUNC("ixgbe_raise_eeprom_clk");
2088 * Raise the clock input to the EEPROM
2089 * (setting the SK bit), then delay
2091 *eec = *eec | IXGBE_EEC_SK;
2092 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2093 IXGBE_WRITE_FLUSH(hw);
2098 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2099 * @hw: pointer to hardware structure
2100 * @eecd: EECD's current value
2102 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2104 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2107 * Lower the clock input to the EEPROM (clearing the SK bit), then
2110 *eec = *eec & ~IXGBE_EEC_SK;
2111 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2112 IXGBE_WRITE_FLUSH(hw);
2117 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2118 * @hw: pointer to hardware structure
2120 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2124 DEBUGFUNC("ixgbe_release_eeprom");
2126 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2128 eec |= IXGBE_EEC_CS; /* Pull CS high */
2129 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
2131 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2132 IXGBE_WRITE_FLUSH(hw);
2136 /* Stop requesting EEPROM access */
2137 eec &= ~IXGBE_EEC_REQ;
2138 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2140 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2142 /* Delay before attempt to obtain semaphore again to allow FW access */
2143 msec_delay(hw->eeprom.semaphore_delay);
2147 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2148 * @hw: pointer to hardware structure
2150 * Returns a negative error code on error, or the 16-bit checksum
2152 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2161 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
2163 /* Include 0x0-0x3F in the checksum */
2164 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
2165 if (hw->eeprom.ops.read(hw, i, &word)) {
2166 DEBUGOUT("EEPROM read failed\n");
2167 return IXGBE_ERR_EEPROM;
2172 /* Include all data from pointers except for the fw pointer */
2173 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
2174 if (hw->eeprom.ops.read(hw, i, &pointer)) {
2175 DEBUGOUT("EEPROM read failed\n");
2176 return IXGBE_ERR_EEPROM;
2179 /* If the pointer seems invalid */
2180 if (pointer == 0xFFFF || pointer == 0)
2183 if (hw->eeprom.ops.read(hw, pointer, &length)) {
2184 DEBUGOUT("EEPROM read failed\n");
2185 return IXGBE_ERR_EEPROM;
2188 if (length == 0xFFFF || length == 0)
2191 for (j = pointer + 1; j <= pointer + length; j++) {
2192 if (hw->eeprom.ops.read(hw, j, &word)) {
2193 DEBUGOUT("EEPROM read failed\n");
2194 return IXGBE_ERR_EEPROM;
2200 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2202 return (s32)checksum;
2206 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2207 * @hw: pointer to hardware structure
2208 * @checksum_val: calculated checksum
2210 * Performs checksum calculation and validates the EEPROM checksum. If the
2211 * caller does not need checksum_val, the value can be NULL.
2213 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2218 u16 read_checksum = 0;
2220 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
2222 /* Read the first word from the EEPROM. If this times out or fails, do
2223 * not continue or we could be in for a very long wait while every
2226 status = hw->eeprom.ops.read(hw, 0, &checksum);
2228 DEBUGOUT("EEPROM read failed\n");
2232 status = hw->eeprom.ops.calc_checksum(hw);
2236 checksum = (u16)(status & 0xffff);
2238 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2240 DEBUGOUT("EEPROM read failed\n");
2244 /* Verify read checksum from EEPROM is the same as
2245 * calculated checksum
2247 if (read_checksum != checksum)
2248 status = IXGBE_ERR_EEPROM_CHECKSUM;
2250 /* If the user cares, return the calculated checksum */
2252 *checksum_val = checksum;
2258 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2259 * @hw: pointer to hardware structure
2261 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2266 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
2268 /* Read the first word from the EEPROM. If this times out or fails, do
2269 * not continue or we could be in for a very long wait while every
2272 status = hw->eeprom.ops.read(hw, 0, &checksum);
2274 DEBUGOUT("EEPROM read failed\n");
2278 status = hw->eeprom.ops.calc_checksum(hw);
2282 checksum = (u16)(status & 0xffff);
2284 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
2290 * ixgbe_validate_mac_addr - Validate MAC address
2291 * @mac_addr: pointer to MAC address.
2293 * Tests a MAC address to ensure it is a valid Individual Address.
2295 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
2297 s32 status = IXGBE_SUCCESS;
2299 DEBUGFUNC("ixgbe_validate_mac_addr");
2301 /* Make sure it is not a multicast address */
2302 if (IXGBE_IS_MULTICAST(mac_addr)) {
2303 status = IXGBE_ERR_INVALID_MAC_ADDR;
2304 /* Not a broadcast address */
2305 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
2306 status = IXGBE_ERR_INVALID_MAC_ADDR;
2307 /* Reject the zero address */
2308 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
2309 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
2310 status = IXGBE_ERR_INVALID_MAC_ADDR;
2316 * ixgbe_set_rar_generic - Set Rx address register
2317 * @hw: pointer to hardware structure
2318 * @index: Receive address register to write
2319 * @addr: Address to put into receive address register
2320 * @vmdq: VMDq "set" or "pool" index
2321 * @enable_addr: set flag that address is active
2323 * Puts an ethernet address into a receive address register.
2325 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2328 u32 rar_low, rar_high;
2329 u32 rar_entries = hw->mac.num_rar_entries;
2331 DEBUGFUNC("ixgbe_set_rar_generic");
2333 /* Make sure we are using a valid rar index range */
2334 if (index >= rar_entries) {
2335 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2336 "RAR index %d is out of range.\n", index);
2337 return IXGBE_ERR_INVALID_ARGUMENT;
2340 /* setup VMDq pool selection before this RAR gets enabled */
2341 hw->mac.ops.set_vmdq(hw, index, vmdq);
2344 * HW expects these in little endian so we reverse the byte
2345 * order from network order (big endian) to little endian
2347 rar_low = ((u32)addr[0] |
2348 ((u32)addr[1] << 8) |
2349 ((u32)addr[2] << 16) |
2350 ((u32)addr[3] << 24));
2352 * Some parts put the VMDq setting in the extra RAH bits,
2353 * so save everything except the lower 16 bits that hold part
2354 * of the address and the address valid bit.
2356 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2357 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2358 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2360 if (enable_addr != 0)
2361 rar_high |= IXGBE_RAH_AV;
2363 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2364 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2366 return IXGBE_SUCCESS;
2370 * ixgbe_clear_rar_generic - Remove Rx address register
2371 * @hw: pointer to hardware structure
2372 * @index: Receive address register to write
2374 * Clears an ethernet address from a receive address register.
2376 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2379 u32 rar_entries = hw->mac.num_rar_entries;
2381 DEBUGFUNC("ixgbe_clear_rar_generic");
2383 /* Make sure we are using a valid rar index range */
2384 if (index >= rar_entries) {
2385 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2386 "RAR index %d is out of range.\n", index);
2387 return IXGBE_ERR_INVALID_ARGUMENT;
2391 * Some parts put the VMDq setting in the extra RAH bits,
2392 * so save everything except the lower 16 bits that hold part
2393 * of the address and the address valid bit.
2395 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2396 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2398 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2399 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2401 /* clear VMDq pool/queue selection for this RAR */
2402 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2404 return IXGBE_SUCCESS;
2408 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2409 * @hw: pointer to hardware structure
2411 * Places the MAC address in receive address register 0 and clears the rest
2412 * of the receive address registers. Clears the multicast table. Assumes
2413 * the receiver is in reset when the routine is called.
2415 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2418 u32 rar_entries = hw->mac.num_rar_entries;
2420 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2423 * If the current mac address is valid, assume it is a software override
2424 * to the permanent address.
2425 * Otherwise, use the permanent address from the eeprom.
2427 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2428 IXGBE_ERR_INVALID_MAC_ADDR) {
2429 /* Get the MAC address from the RAR0 for later reference */
2430 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2432 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2433 hw->mac.addr[0], hw->mac.addr[1],
2435 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2436 hw->mac.addr[4], hw->mac.addr[5]);
2438 /* Setup the receive address. */
2439 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2440 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2441 hw->mac.addr[0], hw->mac.addr[1],
2443 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2444 hw->mac.addr[4], hw->mac.addr[5]);
2446 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2449 /* clear VMDq pool/queue selection for RAR 0 */
2450 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2452 hw->addr_ctrl.overflow_promisc = 0;
2454 hw->addr_ctrl.rar_used_count = 1;
2456 /* Zero out the other receive addresses. */
2457 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2458 for (i = 1; i < rar_entries; i++) {
2459 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2460 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2464 hw->addr_ctrl.mta_in_use = 0;
2465 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2467 DEBUGOUT(" Clearing MTA\n");
2468 for (i = 0; i < hw->mac.mcft_size; i++)
2469 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2471 ixgbe_init_uta_tables(hw);
2473 return IXGBE_SUCCESS;
2477 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2478 * @hw: pointer to hardware structure
2479 * @addr: new address
2481 * Adds it to unused receive address register or goes into promiscuous mode.
2483 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2485 u32 rar_entries = hw->mac.num_rar_entries;
2488 DEBUGFUNC("ixgbe_add_uc_addr");
2490 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2491 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2494 * Place this address in the RAR if there is room,
2495 * else put the controller into promiscuous mode
2497 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2498 rar = hw->addr_ctrl.rar_used_count;
2499 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2500 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2501 hw->addr_ctrl.rar_used_count++;
2503 hw->addr_ctrl.overflow_promisc++;
2506 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2510 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2511 * @hw: pointer to hardware structure
2512 * @addr_list: the list of new addresses
2513 * @addr_count: number of addresses
2514 * @next: iterator function to walk the address list
2516 * The given list replaces any existing list. Clears the secondary addrs from
2517 * receive address registers. Uses unused receive address registers for the
2518 * first secondary addresses, and falls back to promiscuous mode as needed.
2520 * Drivers using secondary unicast addresses must set user_set_promisc when
2521 * manually putting the device into promiscuous mode.
2523 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2524 u32 addr_count, ixgbe_mc_addr_itr next)
2528 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2533 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2536 * Clear accounting of old secondary address list,
2537 * don't count RAR[0]
2539 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2540 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2541 hw->addr_ctrl.overflow_promisc = 0;
2543 /* Zero out the other receive addresses */
2544 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2545 for (i = 0; i < uc_addr_in_use; i++) {
2546 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2547 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2550 /* Add the new addresses */
2551 for (i = 0; i < addr_count; i++) {
2552 DEBUGOUT(" Adding the secondary addresses:\n");
2553 addr = next(hw, &addr_list, &vmdq);
2554 ixgbe_add_uc_addr(hw, addr, vmdq);
2557 if (hw->addr_ctrl.overflow_promisc) {
2558 /* enable promisc if not already in overflow or set by user */
2559 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2560 DEBUGOUT(" Entering address overflow promisc mode\n");
2561 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2562 fctrl |= IXGBE_FCTRL_UPE;
2563 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2566 /* only disable if set by overflow, not by user */
2567 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2568 DEBUGOUT(" Leaving address overflow promisc mode\n");
2569 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2570 fctrl &= ~IXGBE_FCTRL_UPE;
2571 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2575 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2576 return IXGBE_SUCCESS;
2580 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2581 * @hw: pointer to hardware structure
2582 * @mc_addr: the multicast address
2584 * Extracts the 12 bits, from a multicast address, to determine which
2585 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2586 * incoming rx multicast addresses, to determine the bit-vector to check in
2587 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2588 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2589 * to mc_filter_type.
2591 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2595 DEBUGFUNC("ixgbe_mta_vector");
2597 switch (hw->mac.mc_filter_type) {
2598 case 0: /* use bits [47:36] of the address */
2599 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2601 case 1: /* use bits [46:35] of the address */
2602 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2604 case 2: /* use bits [45:34] of the address */
2605 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2607 case 3: /* use bits [43:32] of the address */
2608 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2610 default: /* Invalid mc_filter_type */
2611 DEBUGOUT("MC filter type param set incorrectly\n");
2616 /* vector can only be 12-bits or boundary will be exceeded */
2622 * ixgbe_set_mta - Set bit-vector in multicast table
2623 * @hw: pointer to hardware structure
2624 * @hash_value: Multicast address hash value
2626 * Sets the bit-vector in the multicast table.
2628 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2634 DEBUGFUNC("ixgbe_set_mta");
2636 hw->addr_ctrl.mta_in_use++;
2638 vector = ixgbe_mta_vector(hw, mc_addr);
2639 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2642 * The MTA is a register array of 128 32-bit registers. It is treated
2643 * like an array of 4096 bits. We want to set bit
2644 * BitArray[vector_value]. So we figure out what register the bit is
2645 * in, read it, OR in the new bit, then write back the new value. The
2646 * register is determined by the upper 7 bits of the vector value and
2647 * the bit within that register are determined by the lower 5 bits of
2650 vector_reg = (vector >> 5) & 0x7F;
2651 vector_bit = vector & 0x1F;
2652 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2656 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2657 * @hw: pointer to hardware structure
2658 * @mc_addr_list: the list of new multicast addresses
2659 * @mc_addr_count: number of addresses
2660 * @next: iterator function to walk the multicast address list
2661 * @clear: flag, when set clears the table beforehand
2663 * When the clear flag is set, the given list replaces any existing list.
2664 * Hashes the given addresses into the multicast table.
2666 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2667 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2673 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2676 * Set the new number of MC addresses that we are being requested to
2679 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2680 hw->addr_ctrl.mta_in_use = 0;
2682 /* Clear mta_shadow */
2684 DEBUGOUT(" Clearing MTA\n");
2685 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2688 /* Update mta_shadow */
2689 for (i = 0; i < mc_addr_count; i++) {
2690 DEBUGOUT(" Adding the multicast addresses:\n");
2691 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2695 for (i = 0; i < hw->mac.mcft_size; i++)
2696 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2697 hw->mac.mta_shadow[i]);
2699 if (hw->addr_ctrl.mta_in_use > 0)
2700 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2701 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2703 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2704 return IXGBE_SUCCESS;
2708 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2709 * @hw: pointer to hardware structure
2711 * Enables multicast address in RAR and the use of the multicast hash table.
2713 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2715 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2717 DEBUGFUNC("ixgbe_enable_mc_generic");
2719 if (a->mta_in_use > 0)
2720 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2721 hw->mac.mc_filter_type);
2723 return IXGBE_SUCCESS;
2727 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2728 * @hw: pointer to hardware structure
2730 * Disables multicast address in RAR and the use of the multicast hash table.
2732 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2734 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2736 DEBUGFUNC("ixgbe_disable_mc_generic");
2738 if (a->mta_in_use > 0)
2739 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2741 return IXGBE_SUCCESS;
2745 * ixgbe_fc_enable_generic - Enable flow control
2746 * @hw: pointer to hardware structure
2748 * Enable flow control according to the current settings.
2750 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2752 s32 ret_val = IXGBE_SUCCESS;
2753 u32 mflcn_reg, fccfg_reg;
2758 DEBUGFUNC("ixgbe_fc_enable_generic");
2760 /* Validate the water mark configuration */
2761 if (!hw->fc.pause_time) {
2762 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2766 /* Low water mark of zero causes XOFF floods */
2767 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2768 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2769 hw->fc.high_water[i]) {
2770 if (!hw->fc.low_water[i] ||
2771 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2772 DEBUGOUT("Invalid water mark configuration\n");
2773 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2779 /* Negotiate the fc mode to use */
2780 hw->mac.ops.fc_autoneg(hw);
2782 /* Disable any previous flow control settings */
2783 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2784 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2786 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2787 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2790 * The possible values of fc.current_mode are:
2791 * 0: Flow control is completely disabled
2792 * 1: Rx flow control is enabled (we can receive pause frames,
2793 * but not send pause frames).
2794 * 2: Tx flow control is enabled (we can send pause frames but
2795 * we do not support receiving pause frames).
2796 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2799 switch (hw->fc.current_mode) {
2802 * Flow control is disabled by software override or autoneg.
2803 * The code below will actually disable it in the HW.
2806 case ixgbe_fc_rx_pause:
2808 * Rx Flow control is enabled and Tx Flow control is
2809 * disabled by software override. Since there really
2810 * isn't a way to advertise that we are capable of RX
2811 * Pause ONLY, we will advertise that we support both
2812 * symmetric and asymmetric Rx PAUSE. Later, we will
2813 * disable the adapter's ability to send PAUSE frames.
2815 mflcn_reg |= IXGBE_MFLCN_RFCE;
2817 case ixgbe_fc_tx_pause:
2819 * Tx Flow control is enabled, and Rx Flow control is
2820 * disabled by software override.
2822 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2825 /* Flow control (both Rx and Tx) is enabled by SW override. */
2826 mflcn_reg |= IXGBE_MFLCN_RFCE;
2827 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2830 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2831 "Flow control param set incorrectly\n");
2832 ret_val = IXGBE_ERR_CONFIG;
2837 /* Set 802.3x based flow control settings. */
2838 mflcn_reg |= IXGBE_MFLCN_DPF;
2839 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2840 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2843 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2844 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2845 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2846 hw->fc.high_water[i]) {
2847 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2848 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2849 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2851 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2853 * In order to prevent Tx hangs when the internal Tx
2854 * switch is enabled we must set the high water mark
2855 * to the Rx packet buffer size - 24KB. This allows
2856 * the Tx switch to function even under heavy Rx
2859 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2862 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2865 /* Configure pause time (2 TCs per register) */
2866 reg = hw->fc.pause_time * 0x00010001;
2867 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2868 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2870 /* Configure flow control refresh threshold value */
2871 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2878 * ixgbe_negotiate_fc - Negotiate flow control
2879 * @hw: pointer to hardware structure
2880 * @adv_reg: flow control advertised settings
2881 * @lp_reg: link partner's flow control settings
2882 * @adv_sym: symmetric pause bit in advertisement
2883 * @adv_asm: asymmetric pause bit in advertisement
2884 * @lp_sym: symmetric pause bit in link partner advertisement
2885 * @lp_asm: asymmetric pause bit in link partner advertisement
2887 * Find the intersection between advertised settings and link partner's
2888 * advertised settings
2890 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2891 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2893 if ((!(adv_reg)) || (!(lp_reg))) {
2894 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
2895 "Local or link partner's advertised flow control "
2896 "settings are NULL. Local: %x, link partner: %x\n",
2898 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2901 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2903 * Now we need to check if the user selected Rx ONLY
2904 * of pause frames. In this case, we had to advertise
2905 * FULL flow control because we could not advertise RX
2906 * ONLY. Hence, we must now check to see if we need to
2907 * turn OFF the TRANSMISSION of PAUSE frames.
2909 if (hw->fc.requested_mode == ixgbe_fc_full) {
2910 hw->fc.current_mode = ixgbe_fc_full;
2911 DEBUGOUT("Flow Control = FULL.\n");
2913 hw->fc.current_mode = ixgbe_fc_rx_pause;
2914 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2916 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2917 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2918 hw->fc.current_mode = ixgbe_fc_tx_pause;
2919 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2920 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2921 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2922 hw->fc.current_mode = ixgbe_fc_rx_pause;
2923 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2925 hw->fc.current_mode = ixgbe_fc_none;
2926 DEBUGOUT("Flow Control = NONE.\n");
2928 return IXGBE_SUCCESS;
2932 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2933 * @hw: pointer to hardware structure
2935 * Enable flow control according on 1 gig fiber.
2937 STATIC s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2939 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2940 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2943 * On multispeed fiber at 1g, bail out if
2944 * - link is up but AN did not complete, or if
2945 * - link is up and AN completed but timed out
2948 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2949 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2950 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
2951 DEBUGOUT("Auto-Negotiation did not complete or timed out\n");
2955 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2956 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2958 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2959 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2960 IXGBE_PCS1GANA_ASM_PAUSE,
2961 IXGBE_PCS1GANA_SYM_PAUSE,
2962 IXGBE_PCS1GANA_ASM_PAUSE);
2969 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2970 * @hw: pointer to hardware structure
2972 * Enable flow control according to IEEE clause 37.
2974 STATIC s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2976 u32 links2, anlp1_reg, autoc_reg, links;
2977 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2980 * On backplane, bail out if
2981 * - backplane autoneg was not completed, or if
2982 * - we are 82599 and link partner is not AN enabled
2984 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2985 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
2986 DEBUGOUT("Auto-Negotiation did not complete\n");
2990 if (hw->mac.type == ixgbe_mac_82599EB) {
2991 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2992 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
2993 DEBUGOUT("Link partner is not AN enabled\n");
2998 * Read the 10g AN autoc and LP ability registers and resolve
2999 * local flow control settings accordingly
3001 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3002 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
3004 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
3005 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
3006 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
3013 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
3014 * @hw: pointer to hardware structure
3016 * Enable flow control according to IEEE clause 37.
3018 STATIC s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
3020 u16 technology_ability_reg = 0;
3021 u16 lp_technology_ability_reg = 0;
3023 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
3024 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3025 &technology_ability_reg);
3026 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
3027 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3028 &lp_technology_ability_reg);
3030 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
3031 (u32)lp_technology_ability_reg,
3032 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
3033 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
3037 * ixgbe_fc_autoneg - Configure flow control
3038 * @hw: pointer to hardware structure
3040 * Compares our advertised flow control capabilities to those advertised by
3041 * our link partner, and determines the proper flow control mode to use.
3043 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
3045 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3046 ixgbe_link_speed speed;
3049 DEBUGFUNC("ixgbe_fc_autoneg");
3052 * AN should have completed when the cable was plugged in.
3053 * Look for reasons to bail out. Bail out if:
3054 * - FC autoneg is disabled, or if
3057 if (hw->fc.disable_fc_autoneg) {
3058 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3059 "Flow control autoneg is disabled");
3063 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3065 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3069 switch (hw->phy.media_type) {
3070 /* Autoneg flow control on fiber adapters */
3071 case ixgbe_media_type_fiber_qsfp:
3072 case ixgbe_media_type_fiber:
3073 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
3074 ret_val = ixgbe_fc_autoneg_fiber(hw);
3077 /* Autoneg flow control on backplane adapters */
3078 case ixgbe_media_type_backplane:
3079 ret_val = ixgbe_fc_autoneg_backplane(hw);
3082 /* Autoneg flow control on copper adapters */
3083 case ixgbe_media_type_copper:
3084 if (ixgbe_device_supports_autoneg_fc(hw))
3085 ret_val = ixgbe_fc_autoneg_copper(hw);
3093 if (ret_val == IXGBE_SUCCESS) {
3094 hw->fc.fc_was_autonegged = true;
3096 hw->fc.fc_was_autonegged = false;
3097 hw->fc.current_mode = hw->fc.requested_mode;
3102 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3103 * @hw: pointer to hardware structure
3105 * System-wide timeout range is encoded in PCIe Device Control2 register.
3107 * Add 10% to specified maximum and return the number of times to poll for
3108 * completion timeout, in units of 100 microsec. Never return less than
3109 * 800 = 80 millisec.
3111 STATIC u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3116 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3117 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
3120 case IXGBE_PCIDEVCTRL2_65_130ms:
3121 pollcnt = 1300; /* 130 millisec */
3123 case IXGBE_PCIDEVCTRL2_260_520ms:
3124 pollcnt = 5200; /* 520 millisec */
3126 case IXGBE_PCIDEVCTRL2_1_2s:
3127 pollcnt = 20000; /* 2 sec */
3129 case IXGBE_PCIDEVCTRL2_4_8s:
3130 pollcnt = 80000; /* 8 sec */
3132 case IXGBE_PCIDEVCTRL2_17_34s:
3133 pollcnt = 34000; /* 34 sec */
3135 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
3136 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
3137 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
3138 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
3140 pollcnt = 800; /* 80 millisec minimum */
3144 /* add 10% to spec maximum */
3145 return (pollcnt * 11) / 10;
3149 * ixgbe_disable_pcie_master - Disable PCI-express master access
3150 * @hw: pointer to hardware structure
3152 * Disables PCI-Express master access and verifies there are no pending
3153 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
3154 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
3155 * is returned signifying master requests disabled.
3157 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
3159 s32 status = IXGBE_SUCCESS;
3163 DEBUGFUNC("ixgbe_disable_pcie_master");
3165 /* Always set this bit to ensure any future transactions are blocked */
3166 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3168 /* Exit if master requests are blocked */
3169 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3170 IXGBE_REMOVED(hw->hw_addr))
3173 /* Poll for master request bit to clear */
3174 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
3176 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3181 * Two consecutive resets are required via CTRL.RST per datasheet
3182 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
3183 * of this need. The first reset prevents new master requests from
3184 * being issued by our device. We then must wait 1usec or more for any
3185 * remaining completions from the PCIe bus to trickle in, and then reset
3186 * again to clear out any effects they may have had on our device.
3188 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
3189 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3191 if (hw->mac.type >= ixgbe_mac_X550)
3195 * Before proceeding, make sure that the PCIe block does not have
3196 * transactions pending.
3198 poll = ixgbe_pcie_timeout_poll(hw);
3199 for (i = 0; i < poll; i++) {
3201 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3202 if (IXGBE_REMOVED(hw->hw_addr))
3204 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3208 ERROR_REPORT1(IXGBE_ERROR_POLLING,
3209 "PCIe transaction pending bit also did not clear.\n");
3210 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
3217 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3218 * @hw: pointer to hardware structure
3219 * @mask: Mask to specify which semaphore to acquire
3221 * Acquires the SWFW semaphore through the GSSR register for the specified
3222 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3224 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3228 u32 fwmask = mask << 5;
3232 DEBUGFUNC("ixgbe_acquire_swfw_sync");
3234 for (i = 0; i < timeout; i++) {
3236 * SW NVM semaphore bit is used for access to all
3237 * SW_FW_SYNC bits (not just NVM)
3239 if (ixgbe_get_eeprom_semaphore(hw))
3240 return IXGBE_ERR_SWFW_SYNC;
3242 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3243 if (!(gssr & (fwmask | swmask))) {
3245 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3246 ixgbe_release_eeprom_semaphore(hw);
3247 return IXGBE_SUCCESS;
3249 /* Resource is currently in use by FW or SW */
3250 ixgbe_release_eeprom_semaphore(hw);
3255 /* If time expired clear the bits holding the lock and retry */
3256 if (gssr & (fwmask | swmask))
3257 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
3260 return IXGBE_ERR_SWFW_SYNC;
3264 * ixgbe_release_swfw_sync - Release SWFW semaphore
3265 * @hw: pointer to hardware structure
3266 * @mask: Mask to specify which semaphore to release
3268 * Releases the SWFW semaphore through the GSSR register for the specified
3269 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3271 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3276 DEBUGFUNC("ixgbe_release_swfw_sync");
3278 ixgbe_get_eeprom_semaphore(hw);
3280 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3282 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3284 ixgbe_release_eeprom_semaphore(hw);
3288 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3289 * @hw: pointer to hardware structure
3291 * Stops the receive data path and waits for the HW to internally empty
3292 * the Rx security block
3294 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3296 #define IXGBE_MAX_SECRX_POLL 40
3301 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
3304 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3305 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
3306 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3307 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
3308 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3309 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
3312 /* Use interrupt-safe sleep just in case */
3316 /* For informational purposes only */
3317 if (i >= IXGBE_MAX_SECRX_POLL)
3318 DEBUGOUT("Rx unit being enabled before security "
3319 "path fully disabled. Continuing with init.\n");
3321 return IXGBE_SUCCESS;
3325 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3326 * @hw: pointer to hardware structure
3327 * @reg_val: Value we read from AUTOC
3329 * The default case requires no protection so just to the register read.
3331 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3334 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3335 return IXGBE_SUCCESS;
3339 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
3340 * @hw: pointer to hardware structure
3341 * @reg_val: value to write to AUTOC
3342 * @locked: bool to indicate whether the SW/FW lock was already taken by
3345 * The default case requires no protection so just to the register write.
3347 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
3349 UNREFERENCED_1PARAMETER(locked);
3351 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
3352 return IXGBE_SUCCESS;
3356 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3357 * @hw: pointer to hardware structure
3359 * Enables the receive data path.
3361 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3365 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
3367 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3368 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
3369 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3370 IXGBE_WRITE_FLUSH(hw);
3372 return IXGBE_SUCCESS;
3376 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3377 * @hw: pointer to hardware structure
3378 * @regval: register value to write to RXCTRL
3380 * Enables the Rx DMA unit
3382 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3384 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
3386 if (regval & IXGBE_RXCTRL_RXEN)
3387 ixgbe_enable_rx(hw);
3389 ixgbe_disable_rx(hw);
3391 return IXGBE_SUCCESS;
3395 * ixgbe_blink_led_start_generic - Blink LED based on index.
3396 * @hw: pointer to hardware structure
3397 * @index: led number to blink
3399 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3401 ixgbe_link_speed speed = 0;
3404 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3405 s32 ret_val = IXGBE_SUCCESS;
3406 bool locked = false;
3408 DEBUGFUNC("ixgbe_blink_led_start_generic");
3411 return IXGBE_ERR_PARAM;
3414 * Link must be up to auto-blink the LEDs;
3415 * Force it if link is down.
3417 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3420 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3421 if (ret_val != IXGBE_SUCCESS)
3424 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3425 autoc_reg |= IXGBE_AUTOC_FLU;
3427 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3428 if (ret_val != IXGBE_SUCCESS)
3431 IXGBE_WRITE_FLUSH(hw);
3435 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3436 led_reg |= IXGBE_LED_BLINK(index);
3437 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3438 IXGBE_WRITE_FLUSH(hw);
3445 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3446 * @hw: pointer to hardware structure
3447 * @index: led number to stop blinking
3449 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3452 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3453 s32 ret_val = IXGBE_SUCCESS;
3454 bool locked = false;
3456 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3459 return IXGBE_ERR_PARAM;
3462 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3463 if (ret_val != IXGBE_SUCCESS)
3466 autoc_reg &= ~IXGBE_AUTOC_FLU;
3467 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3469 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3470 if (ret_val != IXGBE_SUCCESS)
3473 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3474 led_reg &= ~IXGBE_LED_BLINK(index);
3475 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3476 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3477 IXGBE_WRITE_FLUSH(hw);
3484 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3485 * @hw: pointer to hardware structure
3486 * @san_mac_offset: SAN MAC address offset
3488 * This function will read the EEPROM location for the SAN MAC address
3489 * pointer, and returns the value at that location. This is used in both
3490 * get and set mac_addr routines.
3492 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3493 u16 *san_mac_offset)
3497 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3500 * First read the EEPROM pointer to see if the MAC addresses are
3503 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3506 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3507 "eeprom at offset %d failed",
3508 IXGBE_SAN_MAC_ADDR_PTR);
3515 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3516 * @hw: pointer to hardware structure
3517 * @san_mac_addr: SAN MAC address
3519 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3520 * per-port, so set_lan_id() must be called before reading the addresses.
3521 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3522 * upon for non-SFP connections, so we must call it here.
3524 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3526 u16 san_mac_data, san_mac_offset;
3530 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3533 * First read the EEPROM pointer to see if the MAC addresses are
3534 * available. If they're not, no point in calling set_lan_id() here.
3536 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3537 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3538 goto san_mac_addr_out;
3540 /* make sure we know which port we need to program */
3541 hw->mac.ops.set_lan_id(hw);
3542 /* apply the port offset to the address offset */
3543 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3544 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3545 for (i = 0; i < 3; i++) {
3546 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3549 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3550 "eeprom read at offset %d failed",
3552 goto san_mac_addr_out;
3554 san_mac_addr[i * 2] = (u8)(san_mac_data);
3555 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3558 return IXGBE_SUCCESS;
3562 * No addresses available in this EEPROM. It's not an
3563 * error though, so just wipe the local address and return.
3565 for (i = 0; i < 6; i++)
3566 san_mac_addr[i] = 0xFF;
3567 return IXGBE_SUCCESS;
3571 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3572 * @hw: pointer to hardware structure
3573 * @san_mac_addr: SAN MAC address
3575 * Write a SAN MAC address to the EEPROM.
3577 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3580 u16 san_mac_data, san_mac_offset;
3583 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3585 /* Look for SAN mac address pointer. If not defined, return */
3586 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3587 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3588 return IXGBE_ERR_NO_SAN_ADDR_PTR;
3590 /* Make sure we know which port we need to write */
3591 hw->mac.ops.set_lan_id(hw);
3592 /* Apply the port offset to the address offset */
3593 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3594 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3596 for (i = 0; i < 3; i++) {
3597 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3598 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3599 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3603 return IXGBE_SUCCESS;
3607 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3608 * @hw: pointer to hardware structure
3610 * Read PCIe configuration space, and get the MSI-X vector count from
3611 * the capabilities table.
3613 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3619 switch (hw->mac.type) {
3620 case ixgbe_mac_82598EB:
3621 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3622 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3624 case ixgbe_mac_82599EB:
3625 case ixgbe_mac_X540:
3626 case ixgbe_mac_X550:
3627 case ixgbe_mac_X550EM_x:
3628 case ixgbe_mac_X550EM_a:
3629 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3630 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3636 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3637 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3638 if (IXGBE_REMOVED(hw->hw_addr))
3640 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3642 /* MSI-X count is zero-based in HW */
3645 if (msix_count > max_msix_count)
3646 msix_count = max_msix_count;
3652 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3653 * @hw: pointer to hardware structure
3654 * @addr: Address to put into receive address register
3655 * @vmdq: VMDq pool to assign
3657 * Puts an ethernet address into a receive address register, or
3658 * finds the rar that it is aleady in; adds to the pool list
3660 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3662 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3663 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3665 u32 rar_low, rar_high;
3666 u32 addr_low, addr_high;
3668 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3670 /* swap bytes for HW little endian */
3671 addr_low = addr[0] | (addr[1] << 8)
3674 addr_high = addr[4] | (addr[5] << 8);
3677 * Either find the mac_id in rar or find the first empty space.
3678 * rar_highwater points to just after the highest currently used
3679 * rar in order to shorten the search. It grows when we add a new
3682 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3683 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3685 if (((IXGBE_RAH_AV & rar_high) == 0)
3686 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3687 first_empty_rar = rar;
3688 } else if ((rar_high & 0xFFFF) == addr_high) {
3689 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3690 if (rar_low == addr_low)
3691 break; /* found it already in the rars */
3695 if (rar < hw->mac.rar_highwater) {
3696 /* already there so just add to the pool bits */
3697 ixgbe_set_vmdq(hw, rar, vmdq);
3698 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3699 /* stick it into first empty RAR slot we found */
3700 rar = first_empty_rar;
3701 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3702 } else if (rar == hw->mac.rar_highwater) {
3703 /* add it to the top of the list and inc the highwater mark */
3704 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3705 hw->mac.rar_highwater++;
3706 } else if (rar >= hw->mac.num_rar_entries) {
3707 return IXGBE_ERR_INVALID_MAC_ADDR;
3711 * If we found rar[0], make sure the default pool bit (we use pool 0)
3712 * remains cleared to be sure default pool packets will get delivered
3715 ixgbe_clear_vmdq(hw, rar, 0);
3721 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3722 * @hw: pointer to hardware struct
3723 * @rar: receive address register index to disassociate
3724 * @vmdq: VMDq pool index to remove from the rar
3726 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3728 u32 mpsar_lo, mpsar_hi;
3729 u32 rar_entries = hw->mac.num_rar_entries;
3731 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3733 /* Make sure we are using a valid rar index range */
3734 if (rar >= rar_entries) {
3735 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3736 "RAR index %d is out of range.\n", rar);
3737 return IXGBE_ERR_INVALID_ARGUMENT;
3740 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3741 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3743 if (IXGBE_REMOVED(hw->hw_addr))
3746 if (!mpsar_lo && !mpsar_hi)
3749 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3751 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3755 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3758 } else if (vmdq < 32) {
3759 mpsar_lo &= ~(1 << vmdq);
3760 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3762 mpsar_hi &= ~(1 << (vmdq - 32));
3763 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3766 /* was that the last pool using this rar? */
3767 if (mpsar_lo == 0 && mpsar_hi == 0 &&
3768 rar != 0 && rar != hw->mac.san_mac_rar_index)
3769 hw->mac.ops.clear_rar(hw, rar);
3771 return IXGBE_SUCCESS;
3775 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3776 * @hw: pointer to hardware struct
3777 * @rar: receive address register index to associate with a VMDq index
3778 * @vmdq: VMDq pool index
3780 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3783 u32 rar_entries = hw->mac.num_rar_entries;
3785 DEBUGFUNC("ixgbe_set_vmdq_generic");
3787 /* Make sure we are using a valid rar index range */
3788 if (rar >= rar_entries) {
3789 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3790 "RAR index %d is out of range.\n", rar);
3791 return IXGBE_ERR_INVALID_ARGUMENT;
3795 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3797 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3799 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3800 mpsar |= 1 << (vmdq - 32);
3801 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3803 return IXGBE_SUCCESS;
3807 * This function should only be involved in the IOV mode.
3808 * In IOV mode, Default pool is next pool after the number of
3809 * VFs advertized and not 0.
3810 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3812 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3813 * @hw: pointer to hardware struct
3814 * @vmdq: VMDq pool index
3816 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3818 u32 rar = hw->mac.san_mac_rar_index;
3820 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3823 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3824 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3826 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3827 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3830 return IXGBE_SUCCESS;
3834 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3835 * @hw: pointer to hardware structure
3837 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3841 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3842 DEBUGOUT(" Clearing UTA\n");
3844 for (i = 0; i < 128; i++)
3845 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3847 return IXGBE_SUCCESS;
3851 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3852 * @hw: pointer to hardware structure
3853 * @vlan: VLAN id to write to VLAN filter
3855 * return the VLVF index where this VLAN id should be placed
3858 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)
3860 s32 regindex, first_empty_slot;
3863 /* short cut the special case */
3867 /* if vlvf_bypass is set we don't want to use an empty slot, we
3868 * will simply bypass the VLVF if there are no entries present in the
3869 * VLVF that contain our VLAN
3871 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0;
3873 /* add VLAN enable bit for comparison */
3874 vlan |= IXGBE_VLVF_VIEN;
3876 /* Search for the vlan id in the VLVF entries. Save off the first empty
3877 * slot found along the way.
3879 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1
3881 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) {
3882 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3885 if (!first_empty_slot && !bits)
3886 first_empty_slot = regindex;
3889 /* If we are here then we didn't find the VLAN. Return first empty
3890 * slot we found during our search, else error.
3892 if (!first_empty_slot)
3893 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "No space in VLVF.\n");
3895 return first_empty_slot ? first_empty_slot : IXGBE_ERR_NO_SPACE;
3899 * ixgbe_set_vfta_generic - Set VLAN filter table
3900 * @hw: pointer to hardware structure
3901 * @vlan: VLAN id to write to VLAN filter
3902 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
3903 * @vlan_on: boolean flag to turn on/off VLAN
3904 * @vlvf_bypass: boolean flag indicating updating default pool is okay
3906 * Turn on/off specified VLAN in the VLAN filter table.
3908 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3909 bool vlan_on, bool vlvf_bypass)
3911 u32 regidx, vfta_delta, vfta;
3914 DEBUGFUNC("ixgbe_set_vfta_generic");
3916 if (vlan > 4095 || vind > 63)
3917 return IXGBE_ERR_PARAM;
3920 * this is a 2 part operation - first the VFTA, then the
3921 * VLVF and VLVFB if VT Mode is set
3922 * We don't write the VFTA until we know the VLVF part succeeded.
3926 * The VFTA is a bitstring made up of 128 32-bit registers
3927 * that enable the particular VLAN id, much like the MTA:
3928 * bits[11-5]: which register
3929 * bits[4-0]: which bit in the register
3932 vfta_delta = 1 << (vlan % 32);
3933 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx));
3936 * vfta_delta represents the difference between the current value
3937 * of vfta and the value we want in the register. Since the diff
3938 * is an XOR mask we can just update the vfta using an XOR
3940 vfta_delta &= vlan_on ? ~vfta : vfta;
3944 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
3946 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta,
3948 if (ret_val != IXGBE_SUCCESS) {
3955 /* Update VFTA now that we are ready for traffic */
3957 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta);
3959 return IXGBE_SUCCESS;
3963 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
3964 * @hw: pointer to hardware structure
3965 * @vlan: VLAN id to write to VLAN filter
3966 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
3967 * @vlan_on: boolean flag to turn on/off VLAN in VLVF
3968 * @vfta_delta: pointer to the difference between the current value of VFTA
3969 * and the desired value
3970 * @vfta: the desired value of the VFTA
3971 * @vlvf_bypass: boolean flag indicating updating default pool is okay
3973 * Turn on/off specified bit in VLVF table.
3975 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3976 bool vlan_on, u32 *vfta_delta, u32 vfta,
3982 DEBUGFUNC("ixgbe_set_vlvf_generic");
3984 if (vlan > 4095 || vind > 63)
3985 return IXGBE_ERR_PARAM;
3987 /* If VT Mode is set
3989 * make sure the vlan is in VLVF
3990 * set the vind bit in the matching VLVFB
3992 * clear the pool bit and possibly the vind
3994 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE))
3995 return IXGBE_SUCCESS;
3997 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
4001 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32));
4003 /* set the pool bit */
4004 bits |= 1 << (vind % 32);
4008 /* clear the pool bit */
4009 bits ^= 1 << (vind % 32);
4012 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) {
4013 /* Clear VFTA first, then disable VLVF. Otherwise
4014 * we run the risk of stray packets leaking into
4015 * the PF via the default pool
4018 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta);
4020 /* disable VLVF and clear remaining bit from pool */
4021 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
4022 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0);
4024 return IXGBE_SUCCESS;
4027 /* If there are still bits set in the VLVFB registers
4028 * for the VLAN ID indicated we need to see if the
4029 * caller is requesting that we clear the VFTA entry bit.
4030 * If the caller has requested that we clear the VFTA
4031 * entry bit but there are still pools/VFs using this VLAN
4032 * ID entry then ignore the request. We're not worried
4033 * about the case where we're turning the VFTA VLAN ID
4034 * entry bit on, only when requested to turn it off as
4035 * there may be multiple pools and/or VFs using the
4036 * VLAN ID entry. In that case we cannot clear the
4037 * VFTA bit until all pools/VFs using that VLAN ID have also
4038 * been cleared. This will be indicated by "bits" being
4044 /* record pool change and enable VLAN ID if not already enabled */
4045 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits);
4046 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan);
4048 return IXGBE_SUCCESS;
4052 * ixgbe_clear_vfta_generic - Clear VLAN filter table
4053 * @hw: pointer to hardware structure
4055 * Clears the VLAN filer table, and the VMDq index associated with the filter
4057 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
4061 DEBUGFUNC("ixgbe_clear_vfta_generic");
4063 for (offset = 0; offset < hw->mac.vft_size; offset++)
4064 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
4066 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
4067 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
4068 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
4069 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0);
4072 return IXGBE_SUCCESS;
4076 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
4077 * @hw: pointer to hardware structure
4079 * Contains the logic to identify if we need to verify link for the
4082 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw)
4085 /* Does FW say we need the fix */
4086 if (!hw->need_crosstalk_fix)
4089 /* Only consider SFP+ PHYs i.e. media type fiber */
4090 switch (hw->mac.ops.get_media_type(hw)) {
4091 case ixgbe_media_type_fiber:
4092 case ixgbe_media_type_fiber_qsfp:
4102 * ixgbe_check_mac_link_generic - Determine link and speed status
4103 * @hw: pointer to hardware structure
4104 * @speed: pointer to link speed
4105 * @link_up: true when link is up
4106 * @link_up_wait_to_complete: bool used to wait for link up or not
4108 * Reads the links register to determine if link is up and the current speed
4110 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4111 bool *link_up, bool link_up_wait_to_complete)
4113 u32 links_reg, links_orig;
4116 DEBUGFUNC("ixgbe_check_mac_link_generic");
4118 /* If Crosstalk fix enabled do the sanity check of making sure
4119 * the SFP+ cage is full.
4121 if (ixgbe_need_crosstalk_fix(hw)) {
4124 switch (hw->mac.type) {
4125 case ixgbe_mac_82599EB:
4126 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4129 case ixgbe_mac_X550EM_x:
4130 case ixgbe_mac_X550EM_a:
4131 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4135 /* sanity check - No SFP+ devices here */
4136 sfp_cage_full = false;
4140 if (!sfp_cage_full) {
4142 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4143 return IXGBE_SUCCESS;
4147 /* clear the old state */
4148 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
4150 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4152 if (links_orig != links_reg) {
4153 DEBUGOUT2("LINKS changed from %08X to %08X\n",
4154 links_orig, links_reg);
4157 if (link_up_wait_to_complete) {
4158 for (i = 0; i < hw->mac.max_link_up_time; i++) {
4159 if (links_reg & IXGBE_LINKS_UP) {
4166 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4169 if (links_reg & IXGBE_LINKS_UP)
4175 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4176 case IXGBE_LINKS_SPEED_10G_82599:
4177 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4178 if (hw->mac.type >= ixgbe_mac_X550) {
4179 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4180 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4183 case IXGBE_LINKS_SPEED_1G_82599:
4184 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4186 case IXGBE_LINKS_SPEED_100_82599:
4187 *speed = IXGBE_LINK_SPEED_100_FULL;
4188 if (hw->mac.type >= ixgbe_mac_X550) {
4189 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4190 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4193 case IXGBE_LINKS_SPEED_10_X550EM_A:
4194 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4195 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4196 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
4197 *speed = IXGBE_LINK_SPEED_10_FULL;
4201 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4204 return IXGBE_SUCCESS;
4208 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4210 * @hw: pointer to hardware structure
4211 * @wwnn_prefix: the alternative WWNN prefix
4212 * @wwpn_prefix: the alternative WWPN prefix
4214 * This function will read the EEPROM from the alternative SAN MAC address
4215 * block to check the support for the alternative WWNN/WWPN prefix support.
4217 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4221 u16 alt_san_mac_blk_offset;
4223 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
4225 /* clear output first */
4226 *wwnn_prefix = 0xFFFF;
4227 *wwpn_prefix = 0xFFFF;
4229 /* check if alternative SAN MAC is supported */
4230 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
4231 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4232 goto wwn_prefix_err;
4234 if ((alt_san_mac_blk_offset == 0) ||
4235 (alt_san_mac_blk_offset == 0xFFFF))
4236 goto wwn_prefix_out;
4238 /* check capability in alternative san mac address block */
4239 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
4240 if (hw->eeprom.ops.read(hw, offset, &caps))
4241 goto wwn_prefix_err;
4242 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
4243 goto wwn_prefix_out;
4245 /* get the corresponding prefix for WWNN/WWPN */
4246 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
4247 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4248 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4249 "eeprom read at offset %d failed", offset);
4252 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
4253 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4254 goto wwn_prefix_err;
4257 return IXGBE_SUCCESS;
4260 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4261 "eeprom read at offset %d failed", offset);
4262 return IXGBE_SUCCESS;
4266 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4267 * @hw: pointer to hardware structure
4268 * @bs: the fcoe boot status
4270 * This function will read the FCOE boot status from the iSCSI FCOE block
4272 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4274 u16 offset, caps, flags;
4277 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
4279 /* clear output first */
4280 *bs = ixgbe_fcoe_bootstatus_unavailable;
4282 /* check if FCOE IBA block is present */
4283 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
4284 status = hw->eeprom.ops.read(hw, offset, &caps);
4285 if (status != IXGBE_SUCCESS)
4288 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
4291 /* check if iSCSI FCOE block is populated */
4292 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4293 if (status != IXGBE_SUCCESS)
4296 if ((offset == 0) || (offset == 0xFFFF))
4299 /* read fcoe flags in iSCSI FCOE block */
4300 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
4301 status = hw->eeprom.ops.read(hw, offset, &flags);
4302 if (status != IXGBE_SUCCESS)
4305 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
4306 *bs = ixgbe_fcoe_bootstatus_enabled;
4308 *bs = ixgbe_fcoe_bootstatus_disabled;
4315 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4316 * @hw: pointer to hardware structure
4317 * @enable: enable or disable switch for MAC anti-spoofing
4318 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
4321 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4323 int vf_target_reg = vf >> 3;
4324 int vf_target_shift = vf % 8;
4327 if (hw->mac.type == ixgbe_mac_82598EB)
4330 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4332 pfvfspoof |= (1 << vf_target_shift);
4334 pfvfspoof &= ~(1 << vf_target_shift);
4335 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4339 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4340 * @hw: pointer to hardware structure
4341 * @enable: enable or disable switch for VLAN anti-spoofing
4342 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4345 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4347 int vf_target_reg = vf >> 3;
4348 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
4351 if (hw->mac.type == ixgbe_mac_82598EB)
4354 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4356 pfvfspoof |= (1 << vf_target_shift);
4358 pfvfspoof &= ~(1 << vf_target_shift);
4359 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4363 * ixgbe_get_device_caps_generic - Get additional device capabilities
4364 * @hw: pointer to hardware structure
4365 * @device_caps: the EEPROM word with the extra device capabilities
4367 * This function will read the EEPROM location for the device capabilities,
4368 * and return the word through device_caps.
4370 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4372 DEBUGFUNC("ixgbe_get_device_caps_generic");
4374 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4376 return IXGBE_SUCCESS;
4380 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4381 * @hw: pointer to hardware structure
4384 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4389 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
4391 /* Enable relaxed ordering */
4392 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4393 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4394 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4395 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4398 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4399 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4400 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
4401 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4402 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4408 * ixgbe_calculate_checksum - Calculate checksum for buffer
4409 * @buffer: pointer to EEPROM
4410 * @length: size of EEPROM to calculate a checksum for
4411 * Calculates the checksum for some buffer on a specified length. The
4412 * checksum calculated is returned.
4414 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4419 DEBUGFUNC("ixgbe_calculate_checksum");
4424 for (i = 0; i < length; i++)
4427 return (u8) (0 - sum);
4431 * ixgbe_hic_unlocked - Issue command to manageability block unlocked
4432 * @hw: pointer to the HW structure
4433 * @buffer: command to write and where the return status will be placed
4434 * @length: length of buffer, must be multiple of 4 bytes
4435 * @timeout: time in ms to wait for command completion
4437 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4438 * else returns semaphore error when encountering an error acquiring
4439 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4441 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held
4444 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length,
4450 DEBUGFUNC("ixgbe_hic_unlocked");
4452 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4453 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4454 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4457 /* Set bit 9 of FWSTS clearing FW reset indication */
4458 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
4459 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
4461 /* Check that the host interface is enabled. */
4462 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4463 if (!(hicr & IXGBE_HICR_EN)) {
4464 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
4465 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4468 /* Calculate length in DWORDs. We must be DWORD aligned */
4469 if (length % sizeof(u32)) {
4470 DEBUGOUT("Buffer length failure, not aligned to dword");
4471 return IXGBE_ERR_INVALID_ARGUMENT;
4474 dword_len = length >> 2;
4476 /* The device driver writes the relevant command block
4477 * into the ram area.
4479 for (i = 0; i < dword_len; i++)
4480 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4481 i, IXGBE_CPU_TO_LE32(buffer[i]));
4483 /* Setting this bit tells the ARC that a new command is pending. */
4484 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4486 for (i = 0; i < timeout; i++) {
4487 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4488 if (!(hicr & IXGBE_HICR_C))
4493 /* Check command completion */
4494 if ((timeout && i == timeout) ||
4495 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
4496 ERROR_REPORT1(IXGBE_ERROR_CAUTION,
4497 "Command has failed with no status valid.\n");
4498 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4501 return IXGBE_SUCCESS;
4505 * ixgbe_host_interface_command - Issue command to manageability block
4506 * @hw: pointer to the HW structure
4507 * @buffer: contains the command to write and where the return status will
4509 * @length: length of buffer, must be multiple of 4 bytes
4510 * @timeout: time in ms to wait for command completion
4511 * @return_data: read and return data from the buffer (true) or not (false)
4512 * Needed because FW structures are big endian and decoding of
4513 * these fields can be 8 bit or 16 bit based on command. Decoding
4514 * is not easily understood without making a table of commands.
4515 * So we will leave this up to the caller to read back the data
4518 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4519 * else returns semaphore error when encountering an error acquiring
4520 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4522 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4523 u32 length, u32 timeout, bool return_data)
4525 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4531 DEBUGFUNC("ixgbe_host_interface_command");
4533 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4534 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4535 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4538 /* Take management host interface semaphore */
4539 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4543 status = ixgbe_hic_unlocked(hw, buffer, length, timeout);
4550 /* Calculate length in DWORDs */
4551 dword_len = hdr_size >> 2;
4553 /* first pull in the header so we know the buffer length */
4554 for (bi = 0; bi < dword_len; bi++) {
4555 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4556 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4559 /* If there is any thing in data position pull it in */
4560 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
4564 if (length < buf_len + hdr_size) {
4565 DEBUGOUT("Buffer not large enough for reply message.\n");
4566 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4570 /* Calculate length in DWORDs, add 3 for odd lengths */
4571 dword_len = (buf_len + 3) >> 2;
4573 /* Pull in the rest of the buffer (bi is where we left off) */
4574 for (; bi <= dword_len; bi++) {
4575 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4576 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4580 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4586 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4587 * @hw: pointer to the HW structure
4588 * @maj: driver version major number
4589 * @min: driver version minor number
4590 * @build: driver version build number
4591 * @sub: driver version sub build number
4593 * Sends driver version number to firmware through the manageability
4594 * block. On success return IXGBE_SUCCESS
4595 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4596 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4598 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4601 struct ixgbe_hic_drv_info fw_cmd;
4603 s32 ret_val = IXGBE_SUCCESS;
4605 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4607 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4608 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4609 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4610 fw_cmd.port_num = (u8)hw->bus.func;
4611 fw_cmd.ver_maj = maj;
4612 fw_cmd.ver_min = min;
4613 fw_cmd.ver_build = build;
4614 fw_cmd.ver_sub = sub;
4615 fw_cmd.hdr.checksum = 0;
4616 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4617 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4621 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4622 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4624 IXGBE_HI_COMMAND_TIMEOUT,
4626 if (ret_val != IXGBE_SUCCESS)
4629 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4630 FW_CEM_RESP_STATUS_SUCCESS)
4631 ret_val = IXGBE_SUCCESS;
4633 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4642 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4643 * @hw: pointer to hardware structure
4644 * @num_pb: number of packet buffers to allocate
4645 * @headroom: reserve n KB of headroom
4646 * @strategy: packet buffer allocation strategy
4648 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4651 u32 pbsize = hw->mac.rx_pb_size;
4653 u32 rxpktsize, txpktsize, txpbthresh;
4655 /* Reserve headroom */
4661 /* Divide remaining packet buffer space amongst the number of packet
4662 * buffers requested using supplied strategy.
4665 case PBA_STRATEGY_WEIGHTED:
4666 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4667 * buffer with 5/8 of the packet buffer space.
4669 rxpktsize = (pbsize * 5) / (num_pb * 4);
4670 pbsize -= rxpktsize * (num_pb / 2);
4671 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4672 for (; i < (num_pb / 2); i++)
4673 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4674 /* Fall through to configure remaining packet buffers */
4675 case PBA_STRATEGY_EQUAL:
4676 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4677 for (; i < num_pb; i++)
4678 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4684 /* Only support an equally distributed Tx packet buffer strategy. */
4685 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4686 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4687 for (i = 0; i < num_pb; i++) {
4688 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4689 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4692 /* Clear unused TCs, if any, to zero buffer size*/
4693 for (; i < IXGBE_MAX_PB; i++) {
4694 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4695 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4696 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4701 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4702 * @hw: pointer to the hardware structure
4704 * The 82599 and x540 MACs can experience issues if TX work is still pending
4705 * when a reset occurs. This function prevents this by flushing the PCIe
4706 * buffers on the system.
4708 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4710 u32 gcr_ext, hlreg0, i, poll;
4714 * If double reset is not requested then all transactions should
4715 * already be clear and as such there is no work to do
4717 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4721 * Set loopback enable to prevent any transmits from being sent
4722 * should the link come up. This assumes that the RXCTRL.RXEN bit
4723 * has already been cleared.
4725 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4726 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4728 /* Wait for a last completion before clearing buffers */
4729 IXGBE_WRITE_FLUSH(hw);
4733 * Before proceeding, make sure that the PCIe block does not have
4734 * transactions pending.
4736 poll = ixgbe_pcie_timeout_poll(hw);
4737 for (i = 0; i < poll; i++) {
4739 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
4740 if (IXGBE_REMOVED(hw->hw_addr))
4742 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
4747 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4748 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4749 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4750 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4752 /* Flush all writes and allow 20usec for all transactions to clear */
4753 IXGBE_WRITE_FLUSH(hw);
4756 /* restore previous register values */
4757 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4758 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4761 STATIC const u8 ixgbe_emc_temp_data[4] = {
4762 IXGBE_EMC_INTERNAL_DATA,
4763 IXGBE_EMC_DIODE1_DATA,
4764 IXGBE_EMC_DIODE2_DATA,
4765 IXGBE_EMC_DIODE3_DATA
4767 STATIC const u8 ixgbe_emc_therm_limit[4] = {
4768 IXGBE_EMC_INTERNAL_THERM_LIMIT,
4769 IXGBE_EMC_DIODE1_THERM_LIMIT,
4770 IXGBE_EMC_DIODE2_THERM_LIMIT,
4771 IXGBE_EMC_DIODE3_THERM_LIMIT
4775 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
4776 * @hw: pointer to hardware structure
4777 * @data: pointer to the thermal sensor data structure
4779 * Returns the thermal sensor data structure
4781 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
4783 s32 status = IXGBE_SUCCESS;
4791 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4793 DEBUGFUNC("ixgbe_get_thermal_sensor_data_generic");
4795 /* Only support thermal sensors attached to 82599 physical port 0 */
4796 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4797 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
4798 status = IXGBE_NOT_IMPLEMENTED;
4802 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);
4806 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) {
4807 status = IXGBE_NOT_IMPLEMENTED;
4811 status = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);
4815 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4816 != IXGBE_ETS_TYPE_EMC) {
4817 status = IXGBE_NOT_IMPLEMENTED;
4821 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4822 if (num_sensors > IXGBE_MAX_SENSORS)
4823 num_sensors = IXGBE_MAX_SENSORS;
4825 for (i = 0; i < num_sensors; i++) {
4826 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
4831 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4832 IXGBE_ETS_DATA_INDEX_SHIFT);
4833 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4834 IXGBE_ETS_DATA_LOC_SHIFT);
4836 if (sensor_location != 0) {
4837 status = hw->phy.ops.read_i2c_byte(hw,
4838 ixgbe_emc_temp_data[sensor_index],
4839 IXGBE_I2C_THERMAL_SENSOR_ADDR,
4840 &data->sensor[i].temp);
4850 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
4851 * @hw: pointer to hardware structure
4853 * Inits the thermal sensor thresholds according to the NVM map
4854 * and save off the threshold and location values into mac.thermal_sensor_data
4856 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
4858 s32 status = IXGBE_SUCCESS;
4863 u8 low_thresh_delta;
4869 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4871 DEBUGFUNC("ixgbe_init_thermal_sensor_thresh_generic");
4873 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
4875 /* Only support thermal sensors attached to 82599 physical port 0 */
4876 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4877 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
4878 return IXGBE_NOT_IMPLEMENTED;
4880 offset = IXGBE_ETS_CFG;
4881 if (hw->eeprom.ops.read(hw, offset, &ets_offset))
4883 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
4884 return IXGBE_NOT_IMPLEMENTED;
4886 offset = ets_offset;
4887 if (hw->eeprom.ops.read(hw, offset, &ets_cfg))
4889 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4890 != IXGBE_ETS_TYPE_EMC)
4891 return IXGBE_NOT_IMPLEMENTED;
4893 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
4894 IXGBE_ETS_LTHRES_DELTA_SHIFT);
4895 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4897 for (i = 0; i < num_sensors; i++) {
4898 offset = ets_offset + 1 + i;
4899 if (hw->eeprom.ops.read(hw, offset, &ets_sensor)) {
4900 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4901 "eeprom read at offset %d failed",
4905 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4906 IXGBE_ETS_DATA_INDEX_SHIFT);
4907 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4908 IXGBE_ETS_DATA_LOC_SHIFT);
4909 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
4911 hw->phy.ops.write_i2c_byte(hw,
4912 ixgbe_emc_therm_limit[sensor_index],
4913 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
4915 if ((i < IXGBE_MAX_SENSORS) && (sensor_location != 0)) {
4916 data->sensor[i].location = sensor_location;
4917 data->sensor[i].caution_thresh = therm_limit;
4918 data->sensor[i].max_op_thresh = therm_limit -
4925 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4926 "eeprom read at offset %d failed", offset);
4927 return IXGBE_NOT_IMPLEMENTED;
4932 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
4933 * @hw: pointer to hardware structure
4934 * @map: pointer to u8 arr for returning map
4936 * Read the rtrup2tc HW register and resolve its content into map
4938 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
4942 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
4943 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
4944 map[i] = IXGBE_RTRUP2TC_UP_MASK &
4945 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
4949 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
4954 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4955 if (rxctrl & IXGBE_RXCTRL_RXEN) {
4956 if (hw->mac.type != ixgbe_mac_82598EB) {
4957 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4958 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
4959 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4960 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4961 hw->mac.set_lben = true;
4963 hw->mac.set_lben = false;
4966 rxctrl &= ~IXGBE_RXCTRL_RXEN;
4967 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
4971 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
4976 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4977 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
4979 if (hw->mac.type != ixgbe_mac_82598EB) {
4980 if (hw->mac.set_lben) {
4981 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4982 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
4983 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4984 hw->mac.set_lben = false;
4990 * ixgbe_mng_present - returns true when management capability is present
4991 * @hw: pointer to hardware structure
4993 bool ixgbe_mng_present(struct ixgbe_hw *hw)
4997 if (hw->mac.type < ixgbe_mac_82599EB)
5000 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5001 fwsm &= IXGBE_FWSM_MODE_MASK;
5002 return fwsm == IXGBE_FWSM_FW_MODE_PT;
5006 * ixgbe_mng_enabled - Is the manageability engine enabled?
5007 * @hw: pointer to hardware structure
5009 * Returns true if the manageability engine is enabled.
5011 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
5013 u32 fwsm, manc, factps;
5015 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5016 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
5019 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
5020 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
5023 if (hw->mac.type <= ixgbe_mac_X540) {
5024 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
5025 if (factps & IXGBE_FACTPS_MNGCG)
5033 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
5034 * @hw: pointer to hardware structure
5035 * @speed: new link speed
5036 * @autoneg_wait_to_complete: true when waiting for completion is needed
5038 * Set the link speed in the MAC and/or PHY register and restarts link.
5040 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
5041 ixgbe_link_speed speed,
5042 bool autoneg_wait_to_complete)
5044 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
5045 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
5046 s32 status = IXGBE_SUCCESS;
5049 bool autoneg, link_up = false;
5051 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
5053 /* Mask off requested but non-supported speeds */
5054 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
5055 if (status != IXGBE_SUCCESS)
5058 speed &= link_speed;
5060 /* Try each speed one by one, highest priority first. We do this in
5061 * software because 10Gb fiber doesn't support speed autonegotiation.
5063 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
5065 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5067 /* Set the module link speed */
5068 switch (hw->phy.media_type) {
5069 case ixgbe_media_type_fiber:
5070 ixgbe_set_rate_select_speed(hw,
5071 IXGBE_LINK_SPEED_10GB_FULL);
5073 case ixgbe_media_type_fiber_qsfp:
5074 /* QSFP module automatically detects MAC link speed */
5077 DEBUGOUT("Unexpected media type.\n");
5081 /* Allow module to change analog characteristics (1G->10G) */
5084 status = ixgbe_setup_mac_link(hw,
5085 IXGBE_LINK_SPEED_10GB_FULL,
5086 autoneg_wait_to_complete);
5087 if (status != IXGBE_SUCCESS)
5090 /* Flap the Tx laser if it has not already been done */
5091 ixgbe_flap_tx_laser(hw);
5093 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
5094 * Section 73.10.2, we may have to wait up to 500ms if KR is
5095 * attempted. 82599 uses the same timing for 10g SFI.
5097 for (i = 0; i < 5; i++) {
5098 /* Wait for the link partner to also set speed */
5101 /* If we have link, just jump out */
5102 status = ixgbe_check_link(hw, &link_speed,
5104 if (status != IXGBE_SUCCESS)
5112 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
5114 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
5115 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
5117 /* Set the module link speed */
5118 switch (hw->phy.media_type) {
5119 case ixgbe_media_type_fiber:
5120 ixgbe_set_rate_select_speed(hw,
5121 IXGBE_LINK_SPEED_1GB_FULL);
5123 case ixgbe_media_type_fiber_qsfp:
5124 /* QSFP module automatically detects link speed */
5127 DEBUGOUT("Unexpected media type.\n");
5131 /* Allow module to change analog characteristics (10G->1G) */
5134 status = ixgbe_setup_mac_link(hw,
5135 IXGBE_LINK_SPEED_1GB_FULL,
5136 autoneg_wait_to_complete);
5137 if (status != IXGBE_SUCCESS)
5140 /* Flap the Tx laser if it has not already been done */
5141 ixgbe_flap_tx_laser(hw);
5143 /* Wait for the link partner to also set speed */
5146 /* If we have link, just jump out */
5147 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
5148 if (status != IXGBE_SUCCESS)
5155 /* We didn't get link. Configure back to the highest speed we tried,
5156 * (if there was more than one). We call ourselves back with just the
5157 * single highest speed that the user requested.
5160 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
5162 autoneg_wait_to_complete);
5165 /* Set autoneg_advertised value based on input link speed */
5166 hw->phy.autoneg_advertised = 0;
5168 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
5169 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
5171 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
5172 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
5178 * ixgbe_set_soft_rate_select_speed - Set module link speed
5179 * @hw: pointer to hardware structure
5180 * @speed: link speed to set
5182 * Set module link speed via the soft rate select.
5184 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
5185 ixgbe_link_speed speed)
5191 case IXGBE_LINK_SPEED_10GB_FULL:
5192 /* one bit mask same as setting on */
5193 rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
5195 case IXGBE_LINK_SPEED_1GB_FULL:
5196 rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
5199 DEBUGOUT("Invalid fixed module speed\n");
5204 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5205 IXGBE_I2C_EEPROM_DEV_ADDR2,
5208 DEBUGOUT("Failed to read Rx Rate Select RS0\n");
5212 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5214 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5215 IXGBE_I2C_EEPROM_DEV_ADDR2,
5218 DEBUGOUT("Failed to write Rx Rate Select RS0\n");
5223 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5224 IXGBE_I2C_EEPROM_DEV_ADDR2,
5227 DEBUGOUT("Failed to read Rx Rate Select RS1\n");
5231 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5233 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5234 IXGBE_I2C_EEPROM_DEV_ADDR2,
5237 DEBUGOUT("Failed to write Rx Rate Select RS1\n");