1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
36 #include "ixgbe_dcb.h"
37 #include "ixgbe_dcb_82599.h"
38 #include "ixgbe_api.h"
40 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
41 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
42 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
43 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
44 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
45 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
47 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
48 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
49 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
50 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw);
52 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
53 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
55 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
56 u16 words, u16 *data);
57 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
58 u16 words, u16 *data);
59 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
63 * ixgbe_init_ops_generic - Inits function ptrs
64 * @hw: pointer to the hardware structure
66 * Initialize the function pointers.
68 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
70 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
71 struct ixgbe_mac_info *mac = &hw->mac;
72 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
74 DEBUGFUNC("ixgbe_init_ops_generic");
77 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic;
78 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
79 if (eec & IXGBE_EEC_PRES) {
80 eeprom->ops.read = ixgbe_read_eerd_generic;
81 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic;
83 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic;
84 eeprom->ops.read_buffer =
85 ixgbe_read_eeprom_buffer_bit_bang_generic;
87 eeprom->ops.write = ixgbe_write_eeprom_generic;
88 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic;
89 eeprom->ops.validate_checksum =
90 ixgbe_validate_eeprom_checksum_generic;
91 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic;
92 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic;
95 mac->ops.init_hw = ixgbe_init_hw_generic;
96 mac->ops.reset_hw = NULL;
97 mac->ops.start_hw = ixgbe_start_hw_generic;
98 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic;
99 mac->ops.get_media_type = NULL;
100 mac->ops.get_supported_physical_layer = NULL;
101 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic;
102 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic;
103 mac->ops.stop_adapter = ixgbe_stop_adapter_generic;
104 mac->ops.get_bus_info = ixgbe_get_bus_info_generic;
105 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie;
106 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync;
107 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync;
108 mac->ops.prot_autoc_read = prot_autoc_read_generic;
109 mac->ops.prot_autoc_write = prot_autoc_write_generic;
112 mac->ops.led_on = ixgbe_led_on_generic;
113 mac->ops.led_off = ixgbe_led_off_generic;
114 mac->ops.blink_led_start = ixgbe_blink_led_start_generic;
115 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic;
117 /* RAR, Multicast, VLAN */
118 mac->ops.set_rar = ixgbe_set_rar_generic;
119 mac->ops.clear_rar = ixgbe_clear_rar_generic;
120 mac->ops.insert_mac_addr = NULL;
121 mac->ops.set_vmdq = NULL;
122 mac->ops.clear_vmdq = NULL;
123 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic;
124 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic;
125 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic;
126 mac->ops.enable_mc = ixgbe_enable_mc_generic;
127 mac->ops.disable_mc = ixgbe_disable_mc_generic;
128 mac->ops.clear_vfta = NULL;
129 mac->ops.set_vfta = NULL;
130 mac->ops.set_vlvf = NULL;
131 mac->ops.init_uta_tables = NULL;
132 mac->ops.enable_rx = ixgbe_enable_rx_generic;
133 mac->ops.disable_rx = ixgbe_disable_rx_generic;
136 mac->ops.fc_enable = ixgbe_fc_enable_generic;
137 mac->ops.setup_fc = ixgbe_setup_fc_generic;
140 mac->ops.get_link_capabilities = NULL;
141 mac->ops.setup_link = NULL;
142 mac->ops.check_link = NULL;
143 mac->ops.dmac_config = NULL;
144 mac->ops.dmac_update_tcs = NULL;
145 mac->ops.dmac_config_tcs = NULL;
147 return IXGBE_SUCCESS;
151 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
153 * @hw: pointer to hardware structure
155 * This function returns true if the device supports flow control
156 * autonegotiation, and false if it does not.
159 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
161 bool supported = false;
162 ixgbe_link_speed speed;
165 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
167 switch (hw->phy.media_type) {
168 case ixgbe_media_type_fiber_qsfp:
169 case ixgbe_media_type_fiber:
170 hw->mac.ops.check_link(hw, &speed, &link_up, false);
171 /* if link is down, assume supported */
173 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
178 case ixgbe_media_type_backplane:
181 case ixgbe_media_type_copper:
182 /* only some copper devices support flow control autoneg */
183 switch (hw->device_id) {
184 case IXGBE_DEV_ID_82599_T3_LOM:
185 case IXGBE_DEV_ID_X540T:
186 case IXGBE_DEV_ID_X540T1:
187 case IXGBE_DEV_ID_X550T:
188 case IXGBE_DEV_ID_X550T1:
189 case IXGBE_DEV_ID_X550EM_X_10G_T:
199 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
200 "Device %x does not support flow control autoneg",
206 * ixgbe_setup_fc_generic - Set up flow control
207 * @hw: pointer to hardware structure
209 * Called at init time to set up flow control.
211 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
213 s32 ret_val = IXGBE_SUCCESS;
214 u32 reg = 0, reg_bp = 0;
218 DEBUGFUNC("ixgbe_setup_fc_generic");
220 /* Validate the requested mode */
221 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
222 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
223 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
224 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
229 * 10gig parts do not have a word in the EEPROM to determine the
230 * default flow control setting, so we explicitly set it to full.
232 if (hw->fc.requested_mode == ixgbe_fc_default)
233 hw->fc.requested_mode = ixgbe_fc_full;
236 * Set up the 1G and 10G flow control advertisement registers so the
237 * HW will be able to do fc autoneg once the cable is plugged in. If
238 * we link at 10G, the 1G advertisement is harmless and vice versa.
240 switch (hw->phy.media_type) {
241 case ixgbe_media_type_backplane:
242 /* some MAC's need RMW protection on AUTOC */
243 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
244 if (ret_val != IXGBE_SUCCESS)
247 /* only backplane uses autoc so fall though */
248 case ixgbe_media_type_fiber_qsfp:
249 case ixgbe_media_type_fiber:
250 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
253 case ixgbe_media_type_copper:
254 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
255 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
262 * The possible values of fc.requested_mode are:
263 * 0: Flow control is completely disabled
264 * 1: Rx flow control is enabled (we can receive pause frames,
265 * but not send pause frames).
266 * 2: Tx flow control is enabled (we can send pause frames but
267 * we do not support receiving pause frames).
268 * 3: Both Rx and Tx flow control (symmetric) are enabled.
271 switch (hw->fc.requested_mode) {
273 /* Flow control completely disabled by software override. */
274 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
275 if (hw->phy.media_type == ixgbe_media_type_backplane)
276 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
277 IXGBE_AUTOC_ASM_PAUSE);
278 else if (hw->phy.media_type == ixgbe_media_type_copper)
279 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
281 case ixgbe_fc_tx_pause:
283 * Tx Flow control is enabled, and Rx Flow control is
284 * disabled by software override.
286 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
287 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
288 if (hw->phy.media_type == ixgbe_media_type_backplane) {
289 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
290 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
291 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
292 reg_cu |= IXGBE_TAF_ASM_PAUSE;
293 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
296 case ixgbe_fc_rx_pause:
298 * Rx Flow control is enabled and Tx Flow control is
299 * disabled by software override. Since there really
300 * isn't a way to advertise that we are capable of RX
301 * Pause ONLY, we will advertise that we support both
302 * symmetric and asymmetric Rx PAUSE, as such we fall
303 * through to the fc_full statement. Later, we will
304 * disable the adapter's ability to send PAUSE frames.
307 /* Flow control (both Rx and Tx) is enabled by SW override. */
308 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
309 if (hw->phy.media_type == ixgbe_media_type_backplane)
310 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
311 IXGBE_AUTOC_ASM_PAUSE;
312 else if (hw->phy.media_type == ixgbe_media_type_copper)
313 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
316 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
317 "Flow control param set incorrectly\n");
318 ret_val = IXGBE_ERR_CONFIG;
323 if (hw->mac.type < ixgbe_mac_X540) {
325 * Enable auto-negotiation between the MAC & PHY;
326 * the MAC will advertise clause 37 flow control.
328 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
329 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
331 /* Disable AN timeout */
332 if (hw->fc.strict_ieee)
333 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
335 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
336 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
340 * AUTOC restart handles negotiation of 1G and 10G on backplane
341 * and copper. There is no need to set the PCS1GCTL register.
344 if (hw->phy.media_type == ixgbe_media_type_backplane) {
345 reg_bp |= IXGBE_AUTOC_AN_RESTART;
346 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
349 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
350 (ixgbe_device_supports_autoneg_fc(hw))) {
351 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
352 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
355 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
361 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
362 * @hw: pointer to hardware structure
364 * Starts the hardware by filling the bus info structure and media type, clears
365 * all on chip counters, initializes receive address registers, multicast
366 * table, VLAN filter table, calls routine to set up link and flow control
367 * settings, and leaves transmit and receive units disabled and uninitialized
369 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
374 DEBUGFUNC("ixgbe_start_hw_generic");
376 /* Set the media type */
377 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
379 /* PHY ops initialization must be done in reset_hw() */
381 /* Clear the VLAN filter table */
382 hw->mac.ops.clear_vfta(hw);
384 /* Clear statistics registers */
385 hw->mac.ops.clear_hw_cntrs(hw);
387 /* Set No Snoop Disable */
388 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
389 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
390 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
391 IXGBE_WRITE_FLUSH(hw);
393 /* Setup flow control */
394 ret_val = ixgbe_setup_fc(hw);
395 if (ret_val != IXGBE_SUCCESS)
398 /* Clear adapter stopped flag */
399 hw->adapter_stopped = false;
406 * ixgbe_start_hw_gen2 - Init sequence for common device family
407 * @hw: pointer to hw structure
409 * Performs the init sequence common to the second generation
411 * Devices in the second generation:
415 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
420 /* Clear the rate limiters */
421 for (i = 0; i < hw->mac.max_tx_queues; i++) {
422 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
423 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
425 IXGBE_WRITE_FLUSH(hw);
427 /* Disable relaxed ordering */
428 for (i = 0; i < hw->mac.max_tx_queues; i++) {
429 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
430 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
431 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
434 for (i = 0; i < hw->mac.max_rx_queues; i++) {
435 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
436 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
437 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
438 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
441 return IXGBE_SUCCESS;
445 * ixgbe_init_hw_generic - Generic hardware initialization
446 * @hw: pointer to hardware structure
448 * Initialize the hardware by resetting the hardware, filling the bus info
449 * structure and media type, clears all on chip counters, initializes receive
450 * address registers, multicast table, VLAN filter table, calls routine to set
451 * up link and flow control settings, and leaves transmit and receive units
452 * disabled and uninitialized
454 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
458 DEBUGFUNC("ixgbe_init_hw_generic");
460 /* Reset the hardware */
461 status = hw->mac.ops.reset_hw(hw);
463 if (status == IXGBE_SUCCESS) {
465 status = hw->mac.ops.start_hw(hw);
472 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
473 * @hw: pointer to hardware structure
475 * Clears all hardware statistics counters by reading them from the hardware
476 * Statistics counters are clear on read.
478 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
482 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
484 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
485 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
486 IXGBE_READ_REG(hw, IXGBE_ERRBC);
487 IXGBE_READ_REG(hw, IXGBE_MSPDC);
488 for (i = 0; i < 8; i++)
489 IXGBE_READ_REG(hw, IXGBE_MPC(i));
491 IXGBE_READ_REG(hw, IXGBE_MLFC);
492 IXGBE_READ_REG(hw, IXGBE_MRFC);
493 IXGBE_READ_REG(hw, IXGBE_RLEC);
494 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
495 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
496 if (hw->mac.type >= ixgbe_mac_82599EB) {
497 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
498 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
500 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
501 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
504 for (i = 0; i < 8; i++) {
505 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
506 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
507 if (hw->mac.type >= ixgbe_mac_82599EB) {
508 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
509 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
511 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
512 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
515 if (hw->mac.type >= ixgbe_mac_82599EB)
516 for (i = 0; i < 8; i++)
517 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
518 IXGBE_READ_REG(hw, IXGBE_PRC64);
519 IXGBE_READ_REG(hw, IXGBE_PRC127);
520 IXGBE_READ_REG(hw, IXGBE_PRC255);
521 IXGBE_READ_REG(hw, IXGBE_PRC511);
522 IXGBE_READ_REG(hw, IXGBE_PRC1023);
523 IXGBE_READ_REG(hw, IXGBE_PRC1522);
524 IXGBE_READ_REG(hw, IXGBE_GPRC);
525 IXGBE_READ_REG(hw, IXGBE_BPRC);
526 IXGBE_READ_REG(hw, IXGBE_MPRC);
527 IXGBE_READ_REG(hw, IXGBE_GPTC);
528 IXGBE_READ_REG(hw, IXGBE_GORCL);
529 IXGBE_READ_REG(hw, IXGBE_GORCH);
530 IXGBE_READ_REG(hw, IXGBE_GOTCL);
531 IXGBE_READ_REG(hw, IXGBE_GOTCH);
532 if (hw->mac.type == ixgbe_mac_82598EB)
533 for (i = 0; i < 8; i++)
534 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
535 IXGBE_READ_REG(hw, IXGBE_RUC);
536 IXGBE_READ_REG(hw, IXGBE_RFC);
537 IXGBE_READ_REG(hw, IXGBE_ROC);
538 IXGBE_READ_REG(hw, IXGBE_RJC);
539 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
540 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
541 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
542 IXGBE_READ_REG(hw, IXGBE_TORL);
543 IXGBE_READ_REG(hw, IXGBE_TORH);
544 IXGBE_READ_REG(hw, IXGBE_TPR);
545 IXGBE_READ_REG(hw, IXGBE_TPT);
546 IXGBE_READ_REG(hw, IXGBE_PTC64);
547 IXGBE_READ_REG(hw, IXGBE_PTC127);
548 IXGBE_READ_REG(hw, IXGBE_PTC255);
549 IXGBE_READ_REG(hw, IXGBE_PTC511);
550 IXGBE_READ_REG(hw, IXGBE_PTC1023);
551 IXGBE_READ_REG(hw, IXGBE_PTC1522);
552 IXGBE_READ_REG(hw, IXGBE_MPTC);
553 IXGBE_READ_REG(hw, IXGBE_BPTC);
554 for (i = 0; i < 16; i++) {
555 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
556 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
557 if (hw->mac.type >= ixgbe_mac_82599EB) {
558 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
559 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
560 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
561 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
562 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
564 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
565 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
569 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
571 ixgbe_identify_phy(hw);
572 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
573 IXGBE_MDIO_PCS_DEV_TYPE, &i);
574 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
575 IXGBE_MDIO_PCS_DEV_TYPE, &i);
576 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
577 IXGBE_MDIO_PCS_DEV_TYPE, &i);
578 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
579 IXGBE_MDIO_PCS_DEV_TYPE, &i);
582 return IXGBE_SUCCESS;
586 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
587 * @hw: pointer to hardware structure
588 * @pba_num: stores the part number string from the EEPROM
589 * @pba_num_size: part number string buffer length
591 * Reads the part number string from the EEPROM.
593 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
602 DEBUGFUNC("ixgbe_read_pba_string_generic");
604 if (pba_num == NULL) {
605 DEBUGOUT("PBA string buffer was null\n");
606 return IXGBE_ERR_INVALID_ARGUMENT;
609 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
611 DEBUGOUT("NVM Read Error\n");
615 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
617 DEBUGOUT("NVM Read Error\n");
622 * if data is not ptr guard the PBA must be in legacy format which
623 * means pba_ptr is actually our second data word for the PBA number
624 * and we can decode it into an ascii string
626 if (data != IXGBE_PBANUM_PTR_GUARD) {
627 DEBUGOUT("NVM PBA number is not stored as string\n");
629 /* we will need 11 characters to store the PBA */
630 if (pba_num_size < 11) {
631 DEBUGOUT("PBA string buffer too small\n");
632 return IXGBE_ERR_NO_SPACE;
635 /* extract hex string from data and pba_ptr */
636 pba_num[0] = (data >> 12) & 0xF;
637 pba_num[1] = (data >> 8) & 0xF;
638 pba_num[2] = (data >> 4) & 0xF;
639 pba_num[3] = data & 0xF;
640 pba_num[4] = (pba_ptr >> 12) & 0xF;
641 pba_num[5] = (pba_ptr >> 8) & 0xF;
644 pba_num[8] = (pba_ptr >> 4) & 0xF;
645 pba_num[9] = pba_ptr & 0xF;
647 /* put a null character on the end of our string */
650 /* switch all the data but the '-' to hex char */
651 for (offset = 0; offset < 10; offset++) {
652 if (pba_num[offset] < 0xA)
653 pba_num[offset] += '0';
654 else if (pba_num[offset] < 0x10)
655 pba_num[offset] += 'A' - 0xA;
658 return IXGBE_SUCCESS;
661 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
663 DEBUGOUT("NVM Read Error\n");
667 if (length == 0xFFFF || length == 0) {
668 DEBUGOUT("NVM PBA number section invalid length\n");
669 return IXGBE_ERR_PBA_SECTION;
672 /* check if pba_num buffer is big enough */
673 if (pba_num_size < (((u32)length * 2) - 1)) {
674 DEBUGOUT("PBA string buffer too small\n");
675 return IXGBE_ERR_NO_SPACE;
678 /* trim pba length from start of string */
682 for (offset = 0; offset < length; offset++) {
683 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
685 DEBUGOUT("NVM Read Error\n");
688 pba_num[offset * 2] = (u8)(data >> 8);
689 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
691 pba_num[offset * 2] = '\0';
693 return IXGBE_SUCCESS;
697 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
698 * @hw: pointer to hardware structure
699 * @pba_num: stores the part number from the EEPROM
701 * Reads the part number from the EEPROM.
703 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
708 DEBUGFUNC("ixgbe_read_pba_num_generic");
710 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
712 DEBUGOUT("NVM Read Error\n");
714 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
715 DEBUGOUT("NVM Not supported\n");
716 return IXGBE_NOT_IMPLEMENTED;
718 *pba_num = (u32)(data << 16);
720 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
722 DEBUGOUT("NVM Read Error\n");
727 return IXGBE_SUCCESS;
732 * @hw: pointer to the HW structure
733 * @eeprom_buf: optional pointer to EEPROM image
734 * @eeprom_buf_size: size of EEPROM image in words
735 * @max_pba_block_size: PBA block size limit
736 * @pba: pointer to output PBA structure
738 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
739 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
742 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
743 u32 eeprom_buf_size, u16 max_pba_block_size,
744 struct ixgbe_pba *pba)
750 return IXGBE_ERR_PARAM;
752 if (eeprom_buf == NULL) {
753 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
758 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
759 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
760 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
762 return IXGBE_ERR_PARAM;
766 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
767 if (pba->pba_block == NULL)
768 return IXGBE_ERR_PARAM;
770 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
776 if (pba_block_size > max_pba_block_size)
777 return IXGBE_ERR_PARAM;
779 if (eeprom_buf == NULL) {
780 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
786 if (eeprom_buf_size > (u32)(pba->word[1] +
788 memcpy(pba->pba_block,
789 &eeprom_buf[pba->word[1]],
790 pba_block_size * sizeof(u16));
792 return IXGBE_ERR_PARAM;
797 return IXGBE_SUCCESS;
801 * ixgbe_write_pba_raw
802 * @hw: pointer to the HW structure
803 * @eeprom_buf: optional pointer to EEPROM image
804 * @eeprom_buf_size: size of EEPROM image in words
805 * @pba: pointer to PBA structure
807 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
808 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
811 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
812 u32 eeprom_buf_size, struct ixgbe_pba *pba)
817 return IXGBE_ERR_PARAM;
819 if (eeprom_buf == NULL) {
820 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
825 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
826 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
827 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
829 return IXGBE_ERR_PARAM;
833 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
834 if (pba->pba_block == NULL)
835 return IXGBE_ERR_PARAM;
837 if (eeprom_buf == NULL) {
838 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
844 if (eeprom_buf_size > (u32)(pba->word[1] +
845 pba->pba_block[0])) {
846 memcpy(&eeprom_buf[pba->word[1]],
848 pba->pba_block[0] * sizeof(u16));
850 return IXGBE_ERR_PARAM;
855 return IXGBE_SUCCESS;
859 * ixgbe_get_pba_block_size
860 * @hw: pointer to the HW structure
861 * @eeprom_buf: optional pointer to EEPROM image
862 * @eeprom_buf_size: size of EEPROM image in words
863 * @pba_data_size: pointer to output variable
865 * Returns the size of the PBA block in words. Function operates on EEPROM
866 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
870 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
871 u32 eeprom_buf_size, u16 *pba_block_size)
877 DEBUGFUNC("ixgbe_get_pba_block_size");
879 if (eeprom_buf == NULL) {
880 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
885 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
886 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
887 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
889 return IXGBE_ERR_PARAM;
893 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
894 if (eeprom_buf == NULL) {
895 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
900 if (eeprom_buf_size > pba_word[1])
901 length = eeprom_buf[pba_word[1] + 0];
903 return IXGBE_ERR_PARAM;
906 if (length == 0xFFFF || length == 0)
907 return IXGBE_ERR_PBA_SECTION;
909 /* PBA number in legacy format, there is no PBA Block. */
913 if (pba_block_size != NULL)
914 *pba_block_size = length;
916 return IXGBE_SUCCESS;
920 * ixgbe_get_mac_addr_generic - Generic get MAC address
921 * @hw: pointer to hardware structure
922 * @mac_addr: Adapter MAC address
924 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
925 * A reset of the adapter must be performed prior to calling this function
926 * in order for the MAC address to have been loaded from the EEPROM into RAR0
928 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
934 DEBUGFUNC("ixgbe_get_mac_addr_generic");
936 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
937 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
939 for (i = 0; i < 4; i++)
940 mac_addr[i] = (u8)(rar_low >> (i*8));
942 for (i = 0; i < 2; i++)
943 mac_addr[i+4] = (u8)(rar_high >> (i*8));
945 return IXGBE_SUCCESS;
949 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
950 * @hw: pointer to hardware structure
951 * @link_status: the link status returned by the PCI config space
953 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
955 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
957 struct ixgbe_mac_info *mac = &hw->mac;
959 if (hw->bus.type == ixgbe_bus_type_unknown)
960 hw->bus.type = ixgbe_bus_type_pci_express;
962 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
963 case IXGBE_PCI_LINK_WIDTH_1:
964 hw->bus.width = ixgbe_bus_width_pcie_x1;
966 case IXGBE_PCI_LINK_WIDTH_2:
967 hw->bus.width = ixgbe_bus_width_pcie_x2;
969 case IXGBE_PCI_LINK_WIDTH_4:
970 hw->bus.width = ixgbe_bus_width_pcie_x4;
972 case IXGBE_PCI_LINK_WIDTH_8:
973 hw->bus.width = ixgbe_bus_width_pcie_x8;
976 hw->bus.width = ixgbe_bus_width_unknown;
980 switch (link_status & IXGBE_PCI_LINK_SPEED) {
981 case IXGBE_PCI_LINK_SPEED_2500:
982 hw->bus.speed = ixgbe_bus_speed_2500;
984 case IXGBE_PCI_LINK_SPEED_5000:
985 hw->bus.speed = ixgbe_bus_speed_5000;
987 case IXGBE_PCI_LINK_SPEED_8000:
988 hw->bus.speed = ixgbe_bus_speed_8000;
991 hw->bus.speed = ixgbe_bus_speed_unknown;
995 mac->ops.set_lan_id(hw);
999 * ixgbe_get_bus_info_generic - Generic set PCI bus info
1000 * @hw: pointer to hardware structure
1002 * Gets the PCI bus info (speed, width, type) then calls helper function to
1003 * store this data within the ixgbe_hw structure.
1005 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
1009 DEBUGFUNC("ixgbe_get_bus_info_generic");
1011 /* Get the negotiated link width and speed from PCI config space */
1012 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
1014 ixgbe_set_pci_config_data_generic(hw, link_status);
1016 return IXGBE_SUCCESS;
1020 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
1021 * @hw: pointer to the HW structure
1023 * Determines the LAN function id by reading memory-mapped registers
1024 * and swaps the port value if requested.
1026 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
1028 struct ixgbe_bus_info *bus = &hw->bus;
1031 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
1033 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
1034 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
1035 bus->lan_id = bus->func;
1037 /* check for a port swap */
1038 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
1039 if (reg & IXGBE_FACTPS_LFS)
1044 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1045 * @hw: pointer to hardware structure
1047 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
1048 * disables transmit and receive units. The adapter_stopped flag is used by
1049 * the shared code and drivers to determine if the adapter is in a stopped
1050 * state and should not touch the hardware.
1052 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1057 DEBUGFUNC("ixgbe_stop_adapter_generic");
1060 * Set the adapter_stopped flag so other driver functions stop touching
1063 hw->adapter_stopped = true;
1065 /* Disable the receive unit */
1066 ixgbe_disable_rx(hw);
1068 /* Clear interrupt mask to stop interrupts from being generated */
1069 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1071 /* Clear any pending interrupts, flush previous writes */
1072 IXGBE_READ_REG(hw, IXGBE_EICR);
1074 /* Disable the transmit unit. Each queue must be disabled. */
1075 for (i = 0; i < hw->mac.max_tx_queues; i++)
1076 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1078 /* Disable the receive unit by stopping each queue */
1079 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1080 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1081 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1082 reg_val |= IXGBE_RXDCTL_SWFLSH;
1083 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1086 /* flush all queues disables */
1087 IXGBE_WRITE_FLUSH(hw);
1091 * Prevent the PCI-E bus from hanging by disabling PCI-E master
1092 * access and verify no pending requests
1094 return ixgbe_disable_pcie_master(hw);
1098 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1099 * @hw: pointer to hardware structure
1100 * @index: led number to turn on
1102 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1104 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1106 DEBUGFUNC("ixgbe_led_on_generic");
1108 /* To turn on the LED, set mode to ON. */
1109 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1110 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
1111 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1112 IXGBE_WRITE_FLUSH(hw);
1114 return IXGBE_SUCCESS;
1118 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1119 * @hw: pointer to hardware structure
1120 * @index: led number to turn off
1122 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1124 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1126 DEBUGFUNC("ixgbe_led_off_generic");
1128 /* To turn off the LED, set mode to OFF. */
1129 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1130 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
1131 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1132 IXGBE_WRITE_FLUSH(hw);
1134 return IXGBE_SUCCESS;
1138 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1139 * @hw: pointer to hardware structure
1141 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1142 * ixgbe_hw struct in order to set up EEPROM access.
1144 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1146 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1150 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
1152 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1153 eeprom->type = ixgbe_eeprom_none;
1154 /* Set default semaphore delay to 10ms which is a well
1156 eeprom->semaphore_delay = 10;
1157 /* Clear EEPROM page size, it will be initialized as needed */
1158 eeprom->word_page_size = 0;
1161 * Check for EEPROM present first.
1162 * If not present leave as none
1164 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1165 if (eec & IXGBE_EEC_PRES) {
1166 eeprom->type = ixgbe_eeprom_spi;
1169 * SPI EEPROM is assumed here. This code would need to
1170 * change if a future EEPROM is not SPI.
1172 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1173 IXGBE_EEC_SIZE_SHIFT);
1174 eeprom->word_size = 1 << (eeprom_size +
1175 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1178 if (eec & IXGBE_EEC_ADDR_SIZE)
1179 eeprom->address_bits = 16;
1181 eeprom->address_bits = 8;
1182 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
1183 "%d\n", eeprom->type, eeprom->word_size,
1184 eeprom->address_bits);
1187 return IXGBE_SUCCESS;
1191 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1192 * @hw: pointer to hardware structure
1193 * @offset: offset within the EEPROM to write
1194 * @words: number of word(s)
1195 * @data: 16 bit word(s) to write to EEPROM
1197 * Reads 16 bit word(s) from EEPROM through bit-bang method
1199 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1200 u16 words, u16 *data)
1202 s32 status = IXGBE_SUCCESS;
1205 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
1207 hw->eeprom.ops.init_params(hw);
1210 status = IXGBE_ERR_INVALID_ARGUMENT;
1214 if (offset + words > hw->eeprom.word_size) {
1215 status = IXGBE_ERR_EEPROM;
1220 * The EEPROM page size cannot be queried from the chip. We do lazy
1221 * initialization. It is worth to do that when we write large buffer.
1223 if ((hw->eeprom.word_page_size == 0) &&
1224 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
1225 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1228 * We cannot hold synchronization semaphores for too long
1229 * to avoid other entity starvation. However it is more efficient
1230 * to read in bursts than synchronizing access for each word.
1232 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1233 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1234 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1235 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1238 if (status != IXGBE_SUCCESS)
1247 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1248 * @hw: pointer to hardware structure
1249 * @offset: offset within the EEPROM to be written to
1250 * @words: number of word(s)
1251 * @data: 16 bit word(s) to be written to the EEPROM
1253 * If ixgbe_eeprom_update_checksum is not called after this function, the
1254 * EEPROM will most likely contain an invalid checksum.
1256 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1257 u16 words, u16 *data)
1263 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1265 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1267 /* Prepare the EEPROM for writing */
1268 status = ixgbe_acquire_eeprom(hw);
1270 if (status == IXGBE_SUCCESS) {
1271 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1272 ixgbe_release_eeprom(hw);
1273 status = IXGBE_ERR_EEPROM;
1277 if (status == IXGBE_SUCCESS) {
1278 for (i = 0; i < words; i++) {
1279 ixgbe_standby_eeprom(hw);
1281 /* Send the WRITE ENABLE command (8 bit opcode ) */
1282 ixgbe_shift_out_eeprom_bits(hw,
1283 IXGBE_EEPROM_WREN_OPCODE_SPI,
1284 IXGBE_EEPROM_OPCODE_BITS);
1286 ixgbe_standby_eeprom(hw);
1289 * Some SPI eeproms use the 8th address bit embedded
1292 if ((hw->eeprom.address_bits == 8) &&
1293 ((offset + i) >= 128))
1294 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1296 /* Send the Write command (8-bit opcode + addr) */
1297 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1298 IXGBE_EEPROM_OPCODE_BITS);
1299 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1300 hw->eeprom.address_bits);
1302 page_size = hw->eeprom.word_page_size;
1304 /* Send the data in burst via SPI*/
1307 word = (word >> 8) | (word << 8);
1308 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1313 /* do not wrap around page */
1314 if (((offset + i) & (page_size - 1)) ==
1317 } while (++i < words);
1319 ixgbe_standby_eeprom(hw);
1322 /* Done with writing - release the EEPROM */
1323 ixgbe_release_eeprom(hw);
1330 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1331 * @hw: pointer to hardware structure
1332 * @offset: offset within the EEPROM to be written to
1333 * @data: 16 bit word to be written to the EEPROM
1335 * If ixgbe_eeprom_update_checksum is not called after this function, the
1336 * EEPROM will most likely contain an invalid checksum.
1338 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1342 DEBUGFUNC("ixgbe_write_eeprom_generic");
1344 hw->eeprom.ops.init_params(hw);
1346 if (offset >= hw->eeprom.word_size) {
1347 status = IXGBE_ERR_EEPROM;
1351 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1358 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1359 * @hw: pointer to hardware structure
1360 * @offset: offset within the EEPROM to be read
1361 * @data: read 16 bit words(s) from EEPROM
1362 * @words: number of word(s)
1364 * Reads 16 bit word(s) from EEPROM through bit-bang method
1366 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1367 u16 words, u16 *data)
1369 s32 status = IXGBE_SUCCESS;
1372 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1374 hw->eeprom.ops.init_params(hw);
1377 status = IXGBE_ERR_INVALID_ARGUMENT;
1381 if (offset + words > hw->eeprom.word_size) {
1382 status = IXGBE_ERR_EEPROM;
1387 * We cannot hold synchronization semaphores for too long
1388 * to avoid other entity starvation. However it is more efficient
1389 * to read in bursts than synchronizing access for each word.
1391 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1392 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1393 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1395 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1398 if (status != IXGBE_SUCCESS)
1407 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1408 * @hw: pointer to hardware structure
1409 * @offset: offset within the EEPROM to be read
1410 * @words: number of word(s)
1411 * @data: read 16 bit word(s) from EEPROM
1413 * Reads 16 bit word(s) from EEPROM through bit-bang method
1415 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1416 u16 words, u16 *data)
1420 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1423 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1425 /* Prepare the EEPROM for reading */
1426 status = ixgbe_acquire_eeprom(hw);
1428 if (status == IXGBE_SUCCESS) {
1429 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1430 ixgbe_release_eeprom(hw);
1431 status = IXGBE_ERR_EEPROM;
1435 if (status == IXGBE_SUCCESS) {
1436 for (i = 0; i < words; i++) {
1437 ixgbe_standby_eeprom(hw);
1439 * Some SPI eeproms use the 8th address bit embedded
1442 if ((hw->eeprom.address_bits == 8) &&
1443 ((offset + i) >= 128))
1444 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1446 /* Send the READ command (opcode + addr) */
1447 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1448 IXGBE_EEPROM_OPCODE_BITS);
1449 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1450 hw->eeprom.address_bits);
1452 /* Read the data. */
1453 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1454 data[i] = (word_in >> 8) | (word_in << 8);
1457 /* End this read operation */
1458 ixgbe_release_eeprom(hw);
1465 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1466 * @hw: pointer to hardware structure
1467 * @offset: offset within the EEPROM to be read
1468 * @data: read 16 bit value from EEPROM
1470 * Reads 16 bit value from EEPROM through bit-bang method
1472 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1477 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1479 hw->eeprom.ops.init_params(hw);
1481 if (offset >= hw->eeprom.word_size) {
1482 status = IXGBE_ERR_EEPROM;
1486 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1493 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1494 * @hw: pointer to hardware structure
1495 * @offset: offset of word in the EEPROM to read
1496 * @words: number of word(s)
1497 * @data: 16 bit word(s) from the EEPROM
1499 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1501 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1502 u16 words, u16 *data)
1505 s32 status = IXGBE_SUCCESS;
1508 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1510 hw->eeprom.ops.init_params(hw);
1513 status = IXGBE_ERR_INVALID_ARGUMENT;
1514 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1518 if (offset >= hw->eeprom.word_size) {
1519 status = IXGBE_ERR_EEPROM;
1520 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1524 for (i = 0; i < words; i++) {
1525 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1526 IXGBE_EEPROM_RW_REG_START;
1528 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1529 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1531 if (status == IXGBE_SUCCESS) {
1532 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1533 IXGBE_EEPROM_RW_REG_DATA);
1535 DEBUGOUT("Eeprom read timed out\n");
1544 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1545 * @hw: pointer to hardware structure
1546 * @offset: offset within the EEPROM to be used as a scratch pad
1548 * Discover EEPROM page size by writing marching data at given offset.
1549 * This function is called only when we are writing a new large buffer
1550 * at given offset so the data would be overwritten anyway.
1552 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1555 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1556 s32 status = IXGBE_SUCCESS;
1559 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1561 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1564 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1565 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1566 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1567 hw->eeprom.word_page_size = 0;
1568 if (status != IXGBE_SUCCESS)
1571 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1572 if (status != IXGBE_SUCCESS)
1576 * When writing in burst more than the actual page size
1577 * EEPROM address wraps around current page.
1579 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1581 DEBUGOUT1("Detected EEPROM page size = %d words.",
1582 hw->eeprom.word_page_size);
1588 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1589 * @hw: pointer to hardware structure
1590 * @offset: offset of word in the EEPROM to read
1591 * @data: word read from the EEPROM
1593 * Reads a 16 bit word from the EEPROM using the EERD register.
1595 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1597 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1601 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1602 * @hw: pointer to hardware structure
1603 * @offset: offset of word in the EEPROM to write
1604 * @words: number of word(s)
1605 * @data: word(s) write to the EEPROM
1607 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1609 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1610 u16 words, u16 *data)
1613 s32 status = IXGBE_SUCCESS;
1616 DEBUGFUNC("ixgbe_write_eewr_generic");
1618 hw->eeprom.ops.init_params(hw);
1621 status = IXGBE_ERR_INVALID_ARGUMENT;
1622 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1626 if (offset >= hw->eeprom.word_size) {
1627 status = IXGBE_ERR_EEPROM;
1628 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1632 for (i = 0; i < words; i++) {
1633 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1634 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1635 IXGBE_EEPROM_RW_REG_START;
1637 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1638 if (status != IXGBE_SUCCESS) {
1639 DEBUGOUT("Eeprom write EEWR timed out\n");
1643 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1645 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1646 if (status != IXGBE_SUCCESS) {
1647 DEBUGOUT("Eeprom write EEWR timed out\n");
1657 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1658 * @hw: pointer to hardware structure
1659 * @offset: offset of word in the EEPROM to write
1660 * @data: word write to the EEPROM
1662 * Write a 16 bit word to the EEPROM using the EEWR register.
1664 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1666 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1670 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1671 * @hw: pointer to hardware structure
1672 * @ee_reg: EEPROM flag for polling
1674 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1675 * read or write is done respectively.
1677 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1681 s32 status = IXGBE_ERR_EEPROM;
1683 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1685 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1686 if (ee_reg == IXGBE_NVM_POLL_READ)
1687 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1689 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1691 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1692 status = IXGBE_SUCCESS;
1698 if (i == IXGBE_EERD_EEWR_ATTEMPTS)
1699 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1700 "EEPROM read/write done polling timed out");
1706 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1707 * @hw: pointer to hardware structure
1709 * Prepares EEPROM for access using bit-bang method. This function should
1710 * be called before issuing a command to the EEPROM.
1712 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1714 s32 status = IXGBE_SUCCESS;
1718 DEBUGFUNC("ixgbe_acquire_eeprom");
1720 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1722 status = IXGBE_ERR_SWFW_SYNC;
1724 if (status == IXGBE_SUCCESS) {
1725 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1727 /* Request EEPROM Access */
1728 eec |= IXGBE_EEC_REQ;
1729 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1731 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1732 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1733 if (eec & IXGBE_EEC_GNT)
1738 /* Release if grant not acquired */
1739 if (!(eec & IXGBE_EEC_GNT)) {
1740 eec &= ~IXGBE_EEC_REQ;
1741 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1742 DEBUGOUT("Could not acquire EEPROM grant\n");
1744 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1745 status = IXGBE_ERR_EEPROM;
1748 /* Setup EEPROM for Read/Write */
1749 if (status == IXGBE_SUCCESS) {
1750 /* Clear CS and SK */
1751 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1752 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1753 IXGBE_WRITE_FLUSH(hw);
1761 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1762 * @hw: pointer to hardware structure
1764 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1766 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1768 s32 status = IXGBE_ERR_EEPROM;
1773 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1776 /* Get SMBI software semaphore between device drivers first */
1777 for (i = 0; i < timeout; i++) {
1779 * If the SMBI bit is 0 when we read it, then the bit will be
1780 * set and we have the semaphore
1782 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1783 if (!(swsm & IXGBE_SWSM_SMBI)) {
1784 status = IXGBE_SUCCESS;
1791 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1794 * this release is particularly important because our attempts
1795 * above to get the semaphore may have succeeded, and if there
1796 * was a timeout, we should unconditionally clear the semaphore
1797 * bits to free the driver to make progress
1799 ixgbe_release_eeprom_semaphore(hw);
1804 * If the SMBI bit is 0 when we read it, then the bit will be
1805 * set and we have the semaphore
1807 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1808 if (!(swsm & IXGBE_SWSM_SMBI))
1809 status = IXGBE_SUCCESS;
1812 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1813 if (status == IXGBE_SUCCESS) {
1814 for (i = 0; i < timeout; i++) {
1815 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1817 /* Set the SW EEPROM semaphore bit to request access */
1818 swsm |= IXGBE_SWSM_SWESMBI;
1819 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
1822 * If we set the bit successfully then we got the
1825 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1826 if (swsm & IXGBE_SWSM_SWESMBI)
1833 * Release semaphores and return error if SW EEPROM semaphore
1834 * was not granted because we don't have access to the EEPROM
1837 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1838 "SWESMBI Software EEPROM semaphore not granted.\n");
1839 ixgbe_release_eeprom_semaphore(hw);
1840 status = IXGBE_ERR_EEPROM;
1843 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1844 "Software semaphore SMBI between device drivers "
1852 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1853 * @hw: pointer to hardware structure
1855 * This function clears hardware semaphore bits.
1857 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1861 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1863 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1865 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1866 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1867 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1868 IXGBE_WRITE_FLUSH(hw);
1872 * ixgbe_ready_eeprom - Polls for EEPROM ready
1873 * @hw: pointer to hardware structure
1875 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1877 s32 status = IXGBE_SUCCESS;
1881 DEBUGFUNC("ixgbe_ready_eeprom");
1884 * Read "Status Register" repeatedly until the LSB is cleared. The
1885 * EEPROM will signal that the command has been completed by clearing
1886 * bit 0 of the internal status register. If it's not cleared within
1887 * 5 milliseconds, then error out.
1889 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1890 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1891 IXGBE_EEPROM_OPCODE_BITS);
1892 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1893 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1897 ixgbe_standby_eeprom(hw);
1901 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1902 * devices (and only 0-5mSec on 5V devices)
1904 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1905 DEBUGOUT("SPI EEPROM Status error\n");
1906 status = IXGBE_ERR_EEPROM;
1913 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1914 * @hw: pointer to hardware structure
1916 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1920 DEBUGFUNC("ixgbe_standby_eeprom");
1922 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1924 /* Toggle CS to flush commands */
1925 eec |= IXGBE_EEC_CS;
1926 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1927 IXGBE_WRITE_FLUSH(hw);
1929 eec &= ~IXGBE_EEC_CS;
1930 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1931 IXGBE_WRITE_FLUSH(hw);
1936 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1937 * @hw: pointer to hardware structure
1938 * @data: data to send to the EEPROM
1939 * @count: number of bits to shift out
1941 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1948 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
1950 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1953 * Mask is used to shift "count" bits of "data" out to the EEPROM
1954 * one bit at a time. Determine the starting bit based on count
1956 mask = 0x01 << (count - 1);
1958 for (i = 0; i < count; i++) {
1960 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1961 * "1", and then raising and then lowering the clock (the SK
1962 * bit controls the clock input to the EEPROM). A "0" is
1963 * shifted out to the EEPROM by setting "DI" to "0" and then
1964 * raising and then lowering the clock.
1967 eec |= IXGBE_EEC_DI;
1969 eec &= ~IXGBE_EEC_DI;
1971 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1972 IXGBE_WRITE_FLUSH(hw);
1976 ixgbe_raise_eeprom_clk(hw, &eec);
1977 ixgbe_lower_eeprom_clk(hw, &eec);
1980 * Shift mask to signify next bit of data to shift in to the
1986 /* We leave the "DI" bit set to "0" when we leave this routine. */
1987 eec &= ~IXGBE_EEC_DI;
1988 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1989 IXGBE_WRITE_FLUSH(hw);
1993 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1994 * @hw: pointer to hardware structure
1996 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
2002 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
2005 * In order to read a register from the EEPROM, we need to shift
2006 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
2007 * the clock input to the EEPROM (setting the SK bit), and then reading
2008 * the value of the "DO" bit. During this "shifting in" process the
2009 * "DI" bit should always be clear.
2011 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2013 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
2015 for (i = 0; i < count; i++) {
2017 ixgbe_raise_eeprom_clk(hw, &eec);
2019 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2021 eec &= ~(IXGBE_EEC_DI);
2022 if (eec & IXGBE_EEC_DO)
2025 ixgbe_lower_eeprom_clk(hw, &eec);
2032 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
2033 * @hw: pointer to hardware structure
2034 * @eec: EEC register's current value
2036 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2038 DEBUGFUNC("ixgbe_raise_eeprom_clk");
2041 * Raise the clock input to the EEPROM
2042 * (setting the SK bit), then delay
2044 *eec = *eec | IXGBE_EEC_SK;
2045 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2046 IXGBE_WRITE_FLUSH(hw);
2051 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2052 * @hw: pointer to hardware structure
2053 * @eecd: EECD's current value
2055 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2057 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2060 * Lower the clock input to the EEPROM (clearing the SK bit), then
2063 *eec = *eec & ~IXGBE_EEC_SK;
2064 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2065 IXGBE_WRITE_FLUSH(hw);
2070 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2071 * @hw: pointer to hardware structure
2073 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2077 DEBUGFUNC("ixgbe_release_eeprom");
2079 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2081 eec |= IXGBE_EEC_CS; /* Pull CS high */
2082 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
2084 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2085 IXGBE_WRITE_FLUSH(hw);
2089 /* Stop requesting EEPROM access */
2090 eec &= ~IXGBE_EEC_REQ;
2091 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2093 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2095 /* Delay before attempt to obtain semaphore again to allow FW access */
2096 msec_delay(hw->eeprom.semaphore_delay);
2100 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2101 * @hw: pointer to hardware structure
2103 * Returns a negative error code on error, or the 16-bit checksum
2105 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2114 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
2116 /* Include 0x0-0x3F in the checksum */
2117 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
2118 if (hw->eeprom.ops.read(hw, i, &word)) {
2119 DEBUGOUT("EEPROM read failed\n");
2120 return IXGBE_ERR_EEPROM;
2125 /* Include all data from pointers except for the fw pointer */
2126 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
2127 if (hw->eeprom.ops.read(hw, i, &pointer)) {
2128 DEBUGOUT("EEPROM read failed\n");
2129 return IXGBE_ERR_EEPROM;
2132 /* If the pointer seems invalid */
2133 if (pointer == 0xFFFF || pointer == 0)
2136 if (hw->eeprom.ops.read(hw, pointer, &length)) {
2137 DEBUGOUT("EEPROM read failed\n");
2138 return IXGBE_ERR_EEPROM;
2141 if (length == 0xFFFF || length == 0)
2144 for (j = pointer + 1; j <= pointer + length; j++) {
2145 if (hw->eeprom.ops.read(hw, j, &word)) {
2146 DEBUGOUT("EEPROM read failed\n");
2147 return IXGBE_ERR_EEPROM;
2153 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2155 return (s32)checksum;
2159 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2160 * @hw: pointer to hardware structure
2161 * @checksum_val: calculated checksum
2163 * Performs checksum calculation and validates the EEPROM checksum. If the
2164 * caller does not need checksum_val, the value can be NULL.
2166 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2171 u16 read_checksum = 0;
2173 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
2175 /* Read the first word from the EEPROM. If this times out or fails, do
2176 * not continue or we could be in for a very long wait while every
2179 status = hw->eeprom.ops.read(hw, 0, &checksum);
2181 DEBUGOUT("EEPROM read failed\n");
2185 status = hw->eeprom.ops.calc_checksum(hw);
2189 checksum = (u16)(status & 0xffff);
2191 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2193 DEBUGOUT("EEPROM read failed\n");
2197 /* Verify read checksum from EEPROM is the same as
2198 * calculated checksum
2200 if (read_checksum != checksum)
2201 status = IXGBE_ERR_EEPROM_CHECKSUM;
2203 /* If the user cares, return the calculated checksum */
2205 *checksum_val = checksum;
2211 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2212 * @hw: pointer to hardware structure
2214 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2219 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
2221 /* Read the first word from the EEPROM. If this times out or fails, do
2222 * not continue or we could be in for a very long wait while every
2225 status = hw->eeprom.ops.read(hw, 0, &checksum);
2227 DEBUGOUT("EEPROM read failed\n");
2231 status = hw->eeprom.ops.calc_checksum(hw);
2235 checksum = (u16)(status & 0xffff);
2237 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
2243 * ixgbe_validate_mac_addr - Validate MAC address
2244 * @mac_addr: pointer to MAC address.
2246 * Tests a MAC address to ensure it is a valid Individual Address
2248 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
2250 s32 status = IXGBE_SUCCESS;
2252 DEBUGFUNC("ixgbe_validate_mac_addr");
2254 /* Make sure it is not a multicast address */
2255 if (IXGBE_IS_MULTICAST(mac_addr)) {
2256 DEBUGOUT("MAC address is multicast\n");
2257 status = IXGBE_ERR_INVALID_MAC_ADDR;
2258 /* Not a broadcast address */
2259 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
2260 DEBUGOUT("MAC address is broadcast\n");
2261 status = IXGBE_ERR_INVALID_MAC_ADDR;
2262 /* Reject the zero address */
2263 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
2264 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
2265 DEBUGOUT("MAC address is all zeros\n");
2266 status = IXGBE_ERR_INVALID_MAC_ADDR;
2272 * ixgbe_set_rar_generic - Set Rx address register
2273 * @hw: pointer to hardware structure
2274 * @index: Receive address register to write
2275 * @addr: Address to put into receive address register
2276 * @vmdq: VMDq "set" or "pool" index
2277 * @enable_addr: set flag that address is active
2279 * Puts an ethernet address into a receive address register.
2281 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2284 u32 rar_low, rar_high;
2285 u32 rar_entries = hw->mac.num_rar_entries;
2287 DEBUGFUNC("ixgbe_set_rar_generic");
2289 /* Make sure we are using a valid rar index range */
2290 if (index >= rar_entries) {
2291 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2292 "RAR index %d is out of range.\n", index);
2293 return IXGBE_ERR_INVALID_ARGUMENT;
2296 /* setup VMDq pool selection before this RAR gets enabled */
2297 hw->mac.ops.set_vmdq(hw, index, vmdq);
2300 * HW expects these in little endian so we reverse the byte
2301 * order from network order (big endian) to little endian
2303 rar_low = ((u32)addr[0] |
2304 ((u32)addr[1] << 8) |
2305 ((u32)addr[2] << 16) |
2306 ((u32)addr[3] << 24));
2308 * Some parts put the VMDq setting in the extra RAH bits,
2309 * so save everything except the lower 16 bits that hold part
2310 * of the address and the address valid bit.
2312 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2313 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2314 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2316 if (enable_addr != 0)
2317 rar_high |= IXGBE_RAH_AV;
2319 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2320 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2322 return IXGBE_SUCCESS;
2326 * ixgbe_clear_rar_generic - Remove Rx address register
2327 * @hw: pointer to hardware structure
2328 * @index: Receive address register to write
2330 * Clears an ethernet address from a receive address register.
2332 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2335 u32 rar_entries = hw->mac.num_rar_entries;
2337 DEBUGFUNC("ixgbe_clear_rar_generic");
2339 /* Make sure we are using a valid rar index range */
2340 if (index >= rar_entries) {
2341 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2342 "RAR index %d is out of range.\n", index);
2343 return IXGBE_ERR_INVALID_ARGUMENT;
2347 * Some parts put the VMDq setting in the extra RAH bits,
2348 * so save everything except the lower 16 bits that hold part
2349 * of the address and the address valid bit.
2351 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2352 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2354 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2355 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2357 /* clear VMDq pool/queue selection for this RAR */
2358 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2360 return IXGBE_SUCCESS;
2364 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2365 * @hw: pointer to hardware structure
2367 * Places the MAC address in receive address register 0 and clears the rest
2368 * of the receive address registers. Clears the multicast table. Assumes
2369 * the receiver is in reset when the routine is called.
2371 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2374 u32 rar_entries = hw->mac.num_rar_entries;
2376 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2379 * If the current mac address is valid, assume it is a software override
2380 * to the permanent address.
2381 * Otherwise, use the permanent address from the eeprom.
2383 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2384 IXGBE_ERR_INVALID_MAC_ADDR) {
2385 /* Get the MAC address from the RAR0 for later reference */
2386 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2388 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2389 hw->mac.addr[0], hw->mac.addr[1],
2391 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2392 hw->mac.addr[4], hw->mac.addr[5]);
2394 /* Setup the receive address. */
2395 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2396 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2397 hw->mac.addr[0], hw->mac.addr[1],
2399 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2400 hw->mac.addr[4], hw->mac.addr[5]);
2402 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2404 /* clear VMDq pool/queue selection for RAR 0 */
2405 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2407 hw->addr_ctrl.overflow_promisc = 0;
2409 hw->addr_ctrl.rar_used_count = 1;
2411 /* Zero out the other receive addresses. */
2412 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2413 for (i = 1; i < rar_entries; i++) {
2414 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2415 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2419 hw->addr_ctrl.mta_in_use = 0;
2420 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2422 DEBUGOUT(" Clearing MTA\n");
2423 for (i = 0; i < hw->mac.mcft_size; i++)
2424 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2426 ixgbe_init_uta_tables(hw);
2428 return IXGBE_SUCCESS;
2432 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2433 * @hw: pointer to hardware structure
2434 * @addr: new address
2436 * Adds it to unused receive address register or goes into promiscuous mode.
2438 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2440 u32 rar_entries = hw->mac.num_rar_entries;
2443 DEBUGFUNC("ixgbe_add_uc_addr");
2445 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2446 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2449 * Place this address in the RAR if there is room,
2450 * else put the controller into promiscuous mode
2452 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2453 rar = hw->addr_ctrl.rar_used_count;
2454 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2455 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2456 hw->addr_ctrl.rar_used_count++;
2458 hw->addr_ctrl.overflow_promisc++;
2461 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2465 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2466 * @hw: pointer to hardware structure
2467 * @addr_list: the list of new addresses
2468 * @addr_count: number of addresses
2469 * @next: iterator function to walk the address list
2471 * The given list replaces any existing list. Clears the secondary addrs from
2472 * receive address registers. Uses unused receive address registers for the
2473 * first secondary addresses, and falls back to promiscuous mode as needed.
2475 * Drivers using secondary unicast addresses must set user_set_promisc when
2476 * manually putting the device into promiscuous mode.
2478 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2479 u32 addr_count, ixgbe_mc_addr_itr next)
2483 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2488 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2491 * Clear accounting of old secondary address list,
2492 * don't count RAR[0]
2494 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2495 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2496 hw->addr_ctrl.overflow_promisc = 0;
2498 /* Zero out the other receive addresses */
2499 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2500 for (i = 0; i < uc_addr_in_use; i++) {
2501 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2502 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2505 /* Add the new addresses */
2506 for (i = 0; i < addr_count; i++) {
2507 DEBUGOUT(" Adding the secondary addresses:\n");
2508 addr = next(hw, &addr_list, &vmdq);
2509 ixgbe_add_uc_addr(hw, addr, vmdq);
2512 if (hw->addr_ctrl.overflow_promisc) {
2513 /* enable promisc if not already in overflow or set by user */
2514 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2515 DEBUGOUT(" Entering address overflow promisc mode\n");
2516 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2517 fctrl |= IXGBE_FCTRL_UPE;
2518 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2521 /* only disable if set by overflow, not by user */
2522 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2523 DEBUGOUT(" Leaving address overflow promisc mode\n");
2524 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2525 fctrl &= ~IXGBE_FCTRL_UPE;
2526 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2530 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2531 return IXGBE_SUCCESS;
2535 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2536 * @hw: pointer to hardware structure
2537 * @mc_addr: the multicast address
2539 * Extracts the 12 bits, from a multicast address, to determine which
2540 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2541 * incoming rx multicast addresses, to determine the bit-vector to check in
2542 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2543 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2544 * to mc_filter_type.
2546 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2550 DEBUGFUNC("ixgbe_mta_vector");
2552 switch (hw->mac.mc_filter_type) {
2553 case 0: /* use bits [47:36] of the address */
2554 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2556 case 1: /* use bits [46:35] of the address */
2557 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2559 case 2: /* use bits [45:34] of the address */
2560 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2562 case 3: /* use bits [43:32] of the address */
2563 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2565 default: /* Invalid mc_filter_type */
2566 DEBUGOUT("MC filter type param set incorrectly\n");
2571 /* vector can only be 12-bits or boundary will be exceeded */
2577 * ixgbe_set_mta - Set bit-vector in multicast table
2578 * @hw: pointer to hardware structure
2579 * @hash_value: Multicast address hash value
2581 * Sets the bit-vector in the multicast table.
2583 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2589 DEBUGFUNC("ixgbe_set_mta");
2591 hw->addr_ctrl.mta_in_use++;
2593 vector = ixgbe_mta_vector(hw, mc_addr);
2594 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2597 * The MTA is a register array of 128 32-bit registers. It is treated
2598 * like an array of 4096 bits. We want to set bit
2599 * BitArray[vector_value]. So we figure out what register the bit is
2600 * in, read it, OR in the new bit, then write back the new value. The
2601 * register is determined by the upper 7 bits of the vector value and
2602 * the bit within that register are determined by the lower 5 bits of
2605 vector_reg = (vector >> 5) & 0x7F;
2606 vector_bit = vector & 0x1F;
2607 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2611 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2612 * @hw: pointer to hardware structure
2613 * @mc_addr_list: the list of new multicast addresses
2614 * @mc_addr_count: number of addresses
2615 * @next: iterator function to walk the multicast address list
2616 * @clear: flag, when set clears the table beforehand
2618 * When the clear flag is set, the given list replaces any existing list.
2619 * Hashes the given addresses into the multicast table.
2621 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2622 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2628 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2631 * Set the new number of MC addresses that we are being requested to
2634 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2635 hw->addr_ctrl.mta_in_use = 0;
2637 /* Clear mta_shadow */
2639 DEBUGOUT(" Clearing MTA\n");
2640 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2643 /* Update mta_shadow */
2644 for (i = 0; i < mc_addr_count; i++) {
2645 DEBUGOUT(" Adding the multicast addresses:\n");
2646 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2650 for (i = 0; i < hw->mac.mcft_size; i++)
2651 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2652 hw->mac.mta_shadow[i]);
2654 if (hw->addr_ctrl.mta_in_use > 0)
2655 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2656 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2658 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2659 return IXGBE_SUCCESS;
2663 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2664 * @hw: pointer to hardware structure
2666 * Enables multicast address in RAR and the use of the multicast hash table.
2668 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2670 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2672 DEBUGFUNC("ixgbe_enable_mc_generic");
2674 if (a->mta_in_use > 0)
2675 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2676 hw->mac.mc_filter_type);
2678 return IXGBE_SUCCESS;
2682 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2683 * @hw: pointer to hardware structure
2685 * Disables multicast address in RAR and the use of the multicast hash table.
2687 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2689 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2691 DEBUGFUNC("ixgbe_disable_mc_generic");
2693 if (a->mta_in_use > 0)
2694 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2696 return IXGBE_SUCCESS;
2700 * ixgbe_fc_enable_generic - Enable flow control
2701 * @hw: pointer to hardware structure
2703 * Enable flow control according to the current settings.
2705 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2707 s32 ret_val = IXGBE_SUCCESS;
2708 u32 mflcn_reg, fccfg_reg;
2713 DEBUGFUNC("ixgbe_fc_enable_generic");
2715 /* Validate the water mark configuration */
2716 if (!hw->fc.pause_time) {
2717 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2721 /* Low water mark of zero causes XOFF floods */
2722 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2723 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2724 hw->fc.high_water[i]) {
2725 if (!hw->fc.low_water[i] ||
2726 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2727 DEBUGOUT("Invalid water mark configuration\n");
2728 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2734 /* Negotiate the fc mode to use */
2735 ixgbe_fc_autoneg(hw);
2737 /* Disable any previous flow control settings */
2738 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2739 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2741 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2742 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2745 * The possible values of fc.current_mode are:
2746 * 0: Flow control is completely disabled
2747 * 1: Rx flow control is enabled (we can receive pause frames,
2748 * but not send pause frames).
2749 * 2: Tx flow control is enabled (we can send pause frames but
2750 * we do not support receiving pause frames).
2751 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2754 switch (hw->fc.current_mode) {
2757 * Flow control is disabled by software override or autoneg.
2758 * The code below will actually disable it in the HW.
2761 case ixgbe_fc_rx_pause:
2763 * Rx Flow control is enabled and Tx Flow control is
2764 * disabled by software override. Since there really
2765 * isn't a way to advertise that we are capable of RX
2766 * Pause ONLY, we will advertise that we support both
2767 * symmetric and asymmetric Rx PAUSE. Later, we will
2768 * disable the adapter's ability to send PAUSE frames.
2770 mflcn_reg |= IXGBE_MFLCN_RFCE;
2772 case ixgbe_fc_tx_pause:
2774 * Tx Flow control is enabled, and Rx Flow control is
2775 * disabled by software override.
2777 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2780 /* Flow control (both Rx and Tx) is enabled by SW override. */
2781 mflcn_reg |= IXGBE_MFLCN_RFCE;
2782 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2785 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2786 "Flow control param set incorrectly\n");
2787 ret_val = IXGBE_ERR_CONFIG;
2792 /* Set 802.3x based flow control settings. */
2793 mflcn_reg |= IXGBE_MFLCN_DPF;
2794 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2795 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2798 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2799 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2800 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2801 hw->fc.high_water[i]) {
2802 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2803 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2804 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2806 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2808 * In order to prevent Tx hangs when the internal Tx
2809 * switch is enabled we must set the high water mark
2810 * to the Rx packet buffer size - 24KB. This allows
2811 * the Tx switch to function even under heavy Rx
2814 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2817 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2820 /* Configure pause time (2 TCs per register) */
2821 reg = hw->fc.pause_time * 0x00010001;
2822 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2823 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2825 /* Configure flow control refresh threshold value */
2826 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2833 * ixgbe_negotiate_fc - Negotiate flow control
2834 * @hw: pointer to hardware structure
2835 * @adv_reg: flow control advertised settings
2836 * @lp_reg: link partner's flow control settings
2837 * @adv_sym: symmetric pause bit in advertisement
2838 * @adv_asm: asymmetric pause bit in advertisement
2839 * @lp_sym: symmetric pause bit in link partner advertisement
2840 * @lp_asm: asymmetric pause bit in link partner advertisement
2842 * Find the intersection between advertised settings and link partner's
2843 * advertised settings
2845 STATIC s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2846 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2848 if ((!(adv_reg)) || (!(lp_reg))) {
2849 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
2850 "Local or link partner's advertised flow control "
2851 "settings are NULL. Local: %x, link partner: %x\n",
2853 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2856 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2858 * Now we need to check if the user selected Rx ONLY
2859 * of pause frames. In this case, we had to advertise
2860 * FULL flow control because we could not advertise RX
2861 * ONLY. Hence, we must now check to see if we need to
2862 * turn OFF the TRANSMISSION of PAUSE frames.
2864 if (hw->fc.requested_mode == ixgbe_fc_full) {
2865 hw->fc.current_mode = ixgbe_fc_full;
2866 DEBUGOUT("Flow Control = FULL.\n");
2868 hw->fc.current_mode = ixgbe_fc_rx_pause;
2869 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2871 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2872 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2873 hw->fc.current_mode = ixgbe_fc_tx_pause;
2874 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2875 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2876 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2877 hw->fc.current_mode = ixgbe_fc_rx_pause;
2878 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2880 hw->fc.current_mode = ixgbe_fc_none;
2881 DEBUGOUT("Flow Control = NONE.\n");
2883 return IXGBE_SUCCESS;
2887 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2888 * @hw: pointer to hardware structure
2890 * Enable flow control according on 1 gig fiber.
2892 STATIC s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2894 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2895 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2898 * On multispeed fiber at 1g, bail out if
2899 * - link is up but AN did not complete, or if
2900 * - link is up and AN completed but timed out
2903 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2904 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2905 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
2906 DEBUGOUT("Auto-Negotiation did not complete or timed out\n");
2910 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2911 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2913 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2914 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2915 IXGBE_PCS1GANA_ASM_PAUSE,
2916 IXGBE_PCS1GANA_SYM_PAUSE,
2917 IXGBE_PCS1GANA_ASM_PAUSE);
2924 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2925 * @hw: pointer to hardware structure
2927 * Enable flow control according to IEEE clause 37.
2929 STATIC s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2931 u32 links2, anlp1_reg, autoc_reg, links;
2932 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2935 * On backplane, bail out if
2936 * - backplane autoneg was not completed, or if
2937 * - we are 82599 and link partner is not AN enabled
2939 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2940 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
2941 DEBUGOUT("Auto-Negotiation did not complete\n");
2945 if (hw->mac.type == ixgbe_mac_82599EB) {
2946 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2947 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
2948 DEBUGOUT("Link partner is not AN enabled\n");
2953 * Read the 10g AN autoc and LP ability registers and resolve
2954 * local flow control settings accordingly
2956 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2957 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2959 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2960 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2961 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2968 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2969 * @hw: pointer to hardware structure
2971 * Enable flow control according to IEEE clause 37.
2973 STATIC s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2975 u16 technology_ability_reg = 0;
2976 u16 lp_technology_ability_reg = 0;
2978 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
2979 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2980 &technology_ability_reg);
2981 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
2982 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2983 &lp_technology_ability_reg);
2985 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2986 (u32)lp_technology_ability_reg,
2987 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2988 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2992 * ixgbe_fc_autoneg - Configure flow control
2993 * @hw: pointer to hardware structure
2995 * Compares our advertised flow control capabilities to those advertised by
2996 * our link partner, and determines the proper flow control mode to use.
2998 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
3000 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3001 ixgbe_link_speed speed;
3004 DEBUGFUNC("ixgbe_fc_autoneg");
3007 * AN should have completed when the cable was plugged in.
3008 * Look for reasons to bail out. Bail out if:
3009 * - FC autoneg is disabled, or if
3012 if (hw->fc.disable_fc_autoneg) {
3013 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3014 "Flow control autoneg is disabled");
3018 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3020 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3024 switch (hw->phy.media_type) {
3025 /* Autoneg flow control on fiber adapters */
3026 case ixgbe_media_type_fiber_qsfp:
3027 case ixgbe_media_type_fiber:
3028 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
3029 ret_val = ixgbe_fc_autoneg_fiber(hw);
3032 /* Autoneg flow control on backplane adapters */
3033 case ixgbe_media_type_backplane:
3034 ret_val = ixgbe_fc_autoneg_backplane(hw);
3037 /* Autoneg flow control on copper adapters */
3038 case ixgbe_media_type_copper:
3039 if (ixgbe_device_supports_autoneg_fc(hw))
3040 ret_val = ixgbe_fc_autoneg_copper(hw);
3048 if (ret_val == IXGBE_SUCCESS) {
3049 hw->fc.fc_was_autonegged = true;
3051 hw->fc.fc_was_autonegged = false;
3052 hw->fc.current_mode = hw->fc.requested_mode;
3057 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3058 * @hw: pointer to hardware structure
3060 * System-wide timeout range is encoded in PCIe Device Control2 register.
3062 * Add 10% to specified maximum and return the number of times to poll for
3063 * completion timeout, in units of 100 microsec. Never return less than
3064 * 800 = 80 millisec.
3066 STATIC u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3071 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3072 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
3075 case IXGBE_PCIDEVCTRL2_65_130ms:
3076 pollcnt = 1300; /* 130 millisec */
3078 case IXGBE_PCIDEVCTRL2_260_520ms:
3079 pollcnt = 5200; /* 520 millisec */
3081 case IXGBE_PCIDEVCTRL2_1_2s:
3082 pollcnt = 20000; /* 2 sec */
3084 case IXGBE_PCIDEVCTRL2_4_8s:
3085 pollcnt = 80000; /* 8 sec */
3087 case IXGBE_PCIDEVCTRL2_17_34s:
3088 pollcnt = 34000; /* 34 sec */
3090 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
3091 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
3092 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
3093 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
3095 pollcnt = 800; /* 80 millisec minimum */
3099 /* add 10% to spec maximum */
3100 return (pollcnt * 11) / 10;
3104 * ixgbe_disable_pcie_master - Disable PCI-express master access
3105 * @hw: pointer to hardware structure
3107 * Disables PCI-Express master access and verifies there are no pending
3108 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
3109 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
3110 * is returned signifying master requests disabled.
3112 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
3114 s32 status = IXGBE_SUCCESS;
3118 DEBUGFUNC("ixgbe_disable_pcie_master");
3120 /* Always set this bit to ensure any future transactions are blocked */
3121 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3123 /* Exit if master requests are blocked */
3124 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3125 IXGBE_REMOVED(hw->hw_addr))
3128 /* Poll for master request bit to clear */
3129 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
3131 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3136 * Two consecutive resets are required via CTRL.RST per datasheet
3137 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
3138 * of this need. The first reset prevents new master requests from
3139 * being issued by our device. We then must wait 1usec or more for any
3140 * remaining completions from the PCIe bus to trickle in, and then reset
3141 * again to clear out any effects they may have had on our device.
3143 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
3144 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3146 if (hw->mac.type >= ixgbe_mac_X550)
3150 * Before proceeding, make sure that the PCIe block does not have
3151 * transactions pending.
3153 poll = ixgbe_pcie_timeout_poll(hw);
3154 for (i = 0; i < poll; i++) {
3156 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3157 if (IXGBE_REMOVED(hw->hw_addr))
3159 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3163 ERROR_REPORT1(IXGBE_ERROR_POLLING,
3164 "PCIe transaction pending bit also did not clear.\n");
3165 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
3172 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3173 * @hw: pointer to hardware structure
3174 * @mask: Mask to specify which semaphore to acquire
3176 * Acquires the SWFW semaphore through the GSSR register for the specified
3177 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3179 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3183 u32 fwmask = mask << 5;
3187 DEBUGFUNC("ixgbe_acquire_swfw_sync");
3189 for (i = 0; i < timeout; i++) {
3191 * SW NVM semaphore bit is used for access to all
3192 * SW_FW_SYNC bits (not just NVM)
3194 if (ixgbe_get_eeprom_semaphore(hw))
3195 return IXGBE_ERR_SWFW_SYNC;
3197 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3198 if (!(gssr & (fwmask | swmask))) {
3200 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3201 ixgbe_release_eeprom_semaphore(hw);
3202 return IXGBE_SUCCESS;
3204 /* Resource is currently in use by FW or SW */
3205 ixgbe_release_eeprom_semaphore(hw);
3210 /* If time expired clear the bits holding the lock and retry */
3211 if (gssr & (fwmask | swmask))
3212 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
3215 return IXGBE_ERR_SWFW_SYNC;
3219 * ixgbe_release_swfw_sync - Release SWFW semaphore
3220 * @hw: pointer to hardware structure
3221 * @mask: Mask to specify which semaphore to release
3223 * Releases the SWFW semaphore through the GSSR register for the specified
3224 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3226 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3231 DEBUGFUNC("ixgbe_release_swfw_sync");
3233 ixgbe_get_eeprom_semaphore(hw);
3235 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3237 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3239 ixgbe_release_eeprom_semaphore(hw);
3243 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3244 * @hw: pointer to hardware structure
3246 * Stops the receive data path and waits for the HW to internally empty
3247 * the Rx security block
3249 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3251 #define IXGBE_MAX_SECRX_POLL 40
3256 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
3259 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3260 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
3261 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3262 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
3263 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3264 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
3267 /* Use interrupt-safe sleep just in case */
3271 /* For informational purposes only */
3272 if (i >= IXGBE_MAX_SECRX_POLL)
3273 DEBUGOUT("Rx unit being enabled before security "
3274 "path fully disabled. Continuing with init.\n");
3276 return IXGBE_SUCCESS;
3280 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3281 * @hw: pointer to hardware structure
3282 * @reg_val: Value we read from AUTOC
3284 * The default case requires no protection so just to the register read.
3286 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3289 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3290 return IXGBE_SUCCESS;
3294 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
3295 * @hw: pointer to hardware structure
3296 * @reg_val: value to write to AUTOC
3297 * @locked: bool to indicate whether the SW/FW lock was already taken by
3300 * The default case requires no protection so just to the register write.
3302 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
3304 UNREFERENCED_1PARAMETER(locked);
3306 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
3307 return IXGBE_SUCCESS;
3311 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3312 * @hw: pointer to hardware structure
3314 * Enables the receive data path.
3316 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3320 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
3322 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3323 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
3324 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3325 IXGBE_WRITE_FLUSH(hw);
3327 return IXGBE_SUCCESS;
3331 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3332 * @hw: pointer to hardware structure
3333 * @regval: register value to write to RXCTRL
3335 * Enables the Rx DMA unit
3337 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3339 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
3341 if (regval & IXGBE_RXCTRL_RXEN)
3342 ixgbe_enable_rx(hw);
3344 ixgbe_disable_rx(hw);
3346 return IXGBE_SUCCESS;
3350 * ixgbe_blink_led_start_generic - Blink LED based on index.
3351 * @hw: pointer to hardware structure
3352 * @index: led number to blink
3354 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3356 ixgbe_link_speed speed = 0;
3359 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3360 s32 ret_val = IXGBE_SUCCESS;
3361 bool locked = false;
3363 DEBUGFUNC("ixgbe_blink_led_start_generic");
3366 * Link must be up to auto-blink the LEDs;
3367 * Force it if link is down.
3369 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3372 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3373 if (ret_val != IXGBE_SUCCESS)
3376 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3377 autoc_reg |= IXGBE_AUTOC_FLU;
3379 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3380 if (ret_val != IXGBE_SUCCESS)
3383 IXGBE_WRITE_FLUSH(hw);
3387 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3388 led_reg |= IXGBE_LED_BLINK(index);
3389 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3390 IXGBE_WRITE_FLUSH(hw);
3397 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3398 * @hw: pointer to hardware structure
3399 * @index: led number to stop blinking
3401 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3404 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3405 s32 ret_val = IXGBE_SUCCESS;
3406 bool locked = false;
3408 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3410 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3411 if (ret_val != IXGBE_SUCCESS)
3414 autoc_reg &= ~IXGBE_AUTOC_FLU;
3415 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3417 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3418 if (ret_val != IXGBE_SUCCESS)
3421 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3422 led_reg &= ~IXGBE_LED_BLINK(index);
3423 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3424 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3425 IXGBE_WRITE_FLUSH(hw);
3432 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3433 * @hw: pointer to hardware structure
3434 * @san_mac_offset: SAN MAC address offset
3436 * This function will read the EEPROM location for the SAN MAC address
3437 * pointer, and returns the value at that location. This is used in both
3438 * get and set mac_addr routines.
3440 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3441 u16 *san_mac_offset)
3445 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3448 * First read the EEPROM pointer to see if the MAC addresses are
3451 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3454 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3455 "eeprom at offset %d failed",
3456 IXGBE_SAN_MAC_ADDR_PTR);
3463 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3464 * @hw: pointer to hardware structure
3465 * @san_mac_addr: SAN MAC address
3467 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3468 * per-port, so set_lan_id() must be called before reading the addresses.
3469 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3470 * upon for non-SFP connections, so we must call it here.
3472 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3474 u16 san_mac_data, san_mac_offset;
3478 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3481 * First read the EEPROM pointer to see if the MAC addresses are
3482 * available. If they're not, no point in calling set_lan_id() here.
3484 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3485 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3486 goto san_mac_addr_out;
3488 /* make sure we know which port we need to program */
3489 hw->mac.ops.set_lan_id(hw);
3490 /* apply the port offset to the address offset */
3491 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3492 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3493 for (i = 0; i < 3; i++) {
3494 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3497 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3498 "eeprom read at offset %d failed",
3500 goto san_mac_addr_out;
3502 san_mac_addr[i * 2] = (u8)(san_mac_data);
3503 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3506 return IXGBE_SUCCESS;
3510 * No addresses available in this EEPROM. It's not an
3511 * error though, so just wipe the local address and return.
3513 for (i = 0; i < 6; i++)
3514 san_mac_addr[i] = 0xFF;
3515 return IXGBE_SUCCESS;
3519 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3520 * @hw: pointer to hardware structure
3521 * @san_mac_addr: SAN MAC address
3523 * Write a SAN MAC address to the EEPROM.
3525 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3528 u16 san_mac_data, san_mac_offset;
3531 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3533 /* Look for SAN mac address pointer. If not defined, return */
3534 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3535 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3536 return IXGBE_ERR_NO_SAN_ADDR_PTR;
3538 /* Make sure we know which port we need to write */
3539 hw->mac.ops.set_lan_id(hw);
3540 /* Apply the port offset to the address offset */
3541 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3542 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3544 for (i = 0; i < 3; i++) {
3545 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3546 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3547 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3551 return IXGBE_SUCCESS;
3555 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3556 * @hw: pointer to hardware structure
3558 * Read PCIe configuration space, and get the MSI-X vector count from
3559 * the capabilities table.
3561 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3567 switch (hw->mac.type) {
3568 case ixgbe_mac_82598EB:
3569 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3570 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3572 case ixgbe_mac_82599EB:
3573 case ixgbe_mac_X540:
3574 case ixgbe_mac_X550:
3575 case ixgbe_mac_X550EM_x:
3576 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3577 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3583 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3584 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3585 if (IXGBE_REMOVED(hw->hw_addr))
3587 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3589 /* MSI-X count is zero-based in HW */
3592 if (msix_count > max_msix_count)
3593 msix_count = max_msix_count;
3599 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3600 * @hw: pointer to hardware structure
3601 * @addr: Address to put into receive address register
3602 * @vmdq: VMDq pool to assign
3604 * Puts an ethernet address into a receive address register, or
3605 * finds the rar that it is aleady in; adds to the pool list
3607 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3609 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3610 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3612 u32 rar_low, rar_high;
3613 u32 addr_low, addr_high;
3615 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3617 /* swap bytes for HW little endian */
3618 addr_low = addr[0] | (addr[1] << 8)
3621 addr_high = addr[4] | (addr[5] << 8);
3624 * Either find the mac_id in rar or find the first empty space.
3625 * rar_highwater points to just after the highest currently used
3626 * rar in order to shorten the search. It grows when we add a new
3629 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3630 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3632 if (((IXGBE_RAH_AV & rar_high) == 0)
3633 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3634 first_empty_rar = rar;
3635 } else if ((rar_high & 0xFFFF) == addr_high) {
3636 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3637 if (rar_low == addr_low)
3638 break; /* found it already in the rars */
3642 if (rar < hw->mac.rar_highwater) {
3643 /* already there so just add to the pool bits */
3644 ixgbe_set_vmdq(hw, rar, vmdq);
3645 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3646 /* stick it into first empty RAR slot we found */
3647 rar = first_empty_rar;
3648 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3649 } else if (rar == hw->mac.rar_highwater) {
3650 /* add it to the top of the list and inc the highwater mark */
3651 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3652 hw->mac.rar_highwater++;
3653 } else if (rar >= hw->mac.num_rar_entries) {
3654 return IXGBE_ERR_INVALID_MAC_ADDR;
3658 * If we found rar[0], make sure the default pool bit (we use pool 0)
3659 * remains cleared to be sure default pool packets will get delivered
3662 ixgbe_clear_vmdq(hw, rar, 0);
3668 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3669 * @hw: pointer to hardware struct
3670 * @rar: receive address register index to disassociate
3671 * @vmdq: VMDq pool index to remove from the rar
3673 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3675 u32 mpsar_lo, mpsar_hi;
3676 u32 rar_entries = hw->mac.num_rar_entries;
3678 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3680 /* Make sure we are using a valid rar index range */
3681 if (rar >= rar_entries) {
3682 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3683 "RAR index %d is out of range.\n", rar);
3684 return IXGBE_ERR_INVALID_ARGUMENT;
3687 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3688 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3690 if (IXGBE_REMOVED(hw->hw_addr))
3693 if (!mpsar_lo && !mpsar_hi)
3696 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3698 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3702 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3705 } else if (vmdq < 32) {
3706 mpsar_lo &= ~(1 << vmdq);
3707 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3709 mpsar_hi &= ~(1 << (vmdq - 32));
3710 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3713 /* was that the last pool using this rar? */
3714 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
3715 hw->mac.ops.clear_rar(hw, rar);
3717 return IXGBE_SUCCESS;
3721 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3722 * @hw: pointer to hardware struct
3723 * @rar: receive address register index to associate with a VMDq index
3724 * @vmdq: VMDq pool index
3726 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3729 u32 rar_entries = hw->mac.num_rar_entries;
3731 DEBUGFUNC("ixgbe_set_vmdq_generic");
3733 /* Make sure we are using a valid rar index range */
3734 if (rar >= rar_entries) {
3735 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3736 "RAR index %d is out of range.\n", rar);
3737 return IXGBE_ERR_INVALID_ARGUMENT;
3741 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3743 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3745 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3746 mpsar |= 1 << (vmdq - 32);
3747 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3749 return IXGBE_SUCCESS;
3753 * This function should only be involved in the IOV mode.
3754 * In IOV mode, Default pool is next pool after the number of
3755 * VFs advertized and not 0.
3756 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3758 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3759 * @hw: pointer to hardware struct
3760 * @vmdq: VMDq pool index
3762 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3764 u32 rar = hw->mac.san_mac_rar_index;
3766 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3769 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3770 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3772 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3773 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3776 return IXGBE_SUCCESS;
3780 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3781 * @hw: pointer to hardware structure
3783 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3787 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3788 DEBUGOUT(" Clearing UTA\n");
3790 for (i = 0; i < 128; i++)
3791 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3793 return IXGBE_SUCCESS;
3797 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3798 * @hw: pointer to hardware structure
3799 * @vlan: VLAN id to write to VLAN filter
3801 * return the VLVF index where this VLAN id should be placed
3804 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
3807 u32 first_empty_slot = 0;
3810 /* short cut the special case */
3815 * Search for the vlan id in the VLVF entries. Save off the first empty
3816 * slot found along the way
3818 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
3819 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3820 if (!bits && !(first_empty_slot))
3821 first_empty_slot = regindex;
3822 else if ((bits & 0x0FFF) == vlan)
3827 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
3828 * in the VLVF. Else use the first empty VLVF register for this
3831 if (regindex >= IXGBE_VLVF_ENTRIES) {
3832 if (first_empty_slot)
3833 regindex = first_empty_slot;
3835 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
3836 "No space in VLVF.\n");
3837 regindex = IXGBE_ERR_NO_SPACE;
3845 * ixgbe_set_vfta_generic - Set VLAN filter table
3846 * @hw: pointer to hardware structure
3847 * @vlan: VLAN id to write to VLAN filter
3848 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3849 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3851 * Turn on/off specified VLAN in the VLAN filter table.
3853 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3860 s32 ret_val = IXGBE_SUCCESS;
3861 bool vfta_changed = false;
3863 DEBUGFUNC("ixgbe_set_vfta_generic");
3866 return IXGBE_ERR_PARAM;
3869 * this is a 2 part operation - first the VFTA, then the
3870 * VLVF and VLVFB if VT Mode is set
3871 * We don't write the VFTA until we know the VLVF part succeeded.
3875 * The VFTA is a bitstring made up of 128 32-bit registers
3876 * that enable the particular VLAN id, much like the MTA:
3877 * bits[11-5]: which register
3878 * bits[4-0]: which bit in the register
3880 regindex = (vlan >> 5) & 0x7F;
3881 bitindex = vlan & 0x1F;
3882 targetbit = (1 << bitindex);
3883 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3886 if (!(vfta & targetbit)) {
3888 vfta_changed = true;
3891 if ((vfta & targetbit)) {
3893 vfta_changed = true;
3898 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
3900 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on,
3902 if (ret_val != IXGBE_SUCCESS)
3906 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3908 return IXGBE_SUCCESS;
3912 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
3913 * @hw: pointer to hardware structure
3914 * @vlan: VLAN id to write to VLAN filter
3915 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3916 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3917 * @vfta_changed: pointer to boolean flag which indicates whether VFTA
3920 * Turn on/off specified bit in VLVF table.
3922 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3923 bool vlan_on, bool *vfta_changed)
3927 DEBUGFUNC("ixgbe_set_vlvf_generic");
3930 return IXGBE_ERR_PARAM;
3932 /* If VT Mode is set
3934 * make sure the vlan is in VLVF
3935 * set the vind bit in the matching VLVFB
3937 * clear the pool bit and possibly the vind
3939 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3940 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3944 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3949 /* set the pool bit */
3951 bits = IXGBE_READ_REG(hw,
3952 IXGBE_VLVFB(vlvf_index * 2));
3953 bits |= (1 << vind);
3955 IXGBE_VLVFB(vlvf_index * 2),
3958 bits = IXGBE_READ_REG(hw,
3959 IXGBE_VLVFB((vlvf_index * 2) + 1));
3960 bits |= (1 << (vind - 32));
3962 IXGBE_VLVFB((vlvf_index * 2) + 1),
3966 /* clear the pool bit */
3968 bits = IXGBE_READ_REG(hw,
3969 IXGBE_VLVFB(vlvf_index * 2));
3970 bits &= ~(1 << vind);
3972 IXGBE_VLVFB(vlvf_index * 2),
3974 bits |= IXGBE_READ_REG(hw,
3975 IXGBE_VLVFB((vlvf_index * 2) + 1));
3977 bits = IXGBE_READ_REG(hw,
3978 IXGBE_VLVFB((vlvf_index * 2) + 1));
3979 bits &= ~(1 << (vind - 32));
3981 IXGBE_VLVFB((vlvf_index * 2) + 1),
3983 bits |= IXGBE_READ_REG(hw,
3984 IXGBE_VLVFB(vlvf_index * 2));
3989 * If there are still bits set in the VLVFB registers
3990 * for the VLAN ID indicated we need to see if the
3991 * caller is requesting that we clear the VFTA entry bit.
3992 * If the caller has requested that we clear the VFTA
3993 * entry bit but there are still pools/VFs using this VLAN
3994 * ID entry then ignore the request. We're not worried
3995 * about the case where we're turning the VFTA VLAN ID
3996 * entry bit on, only when requested to turn it off as
3997 * there may be multiple pools and/or VFs using the
3998 * VLAN ID entry. In that case we cannot clear the
3999 * VFTA bit until all pools/VFs using that VLAN ID have also
4000 * been cleared. This will be indicated by "bits" being
4004 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
4005 (IXGBE_VLVF_VIEN | vlan));
4006 if ((!vlan_on) && (vfta_changed != NULL)) {
4007 /* someone wants to clear the vfta entry
4008 * but some pools/VFs are still using it.
4010 *vfta_changed = false;
4013 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
4016 return IXGBE_SUCCESS;
4020 * ixgbe_clear_vfta_generic - Clear VLAN filter table
4021 * @hw: pointer to hardware structure
4023 * Clears the VLAN filer table, and the VMDq index associated with the filter
4025 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
4029 DEBUGFUNC("ixgbe_clear_vfta_generic");
4031 for (offset = 0; offset < hw->mac.vft_size; offset++)
4032 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
4034 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
4035 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
4036 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
4037 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
4040 return IXGBE_SUCCESS;
4044 * ixgbe_check_mac_link_generic - Determine link and speed status
4045 * @hw: pointer to hardware structure
4046 * @speed: pointer to link speed
4047 * @link_up: true when link is up
4048 * @link_up_wait_to_complete: bool used to wait for link up or not
4050 * Reads the links register to determine if link is up and the current speed
4052 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4053 bool *link_up, bool link_up_wait_to_complete)
4055 u32 links_reg, links_orig;
4058 DEBUGFUNC("ixgbe_check_mac_link_generic");
4060 /* clear the old state */
4061 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
4063 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4065 if (links_orig != links_reg) {
4066 DEBUGOUT2("LINKS changed from %08X to %08X\n",
4067 links_orig, links_reg);
4070 if (link_up_wait_to_complete) {
4071 for (i = 0; i < hw->mac.max_link_up_time; i++) {
4072 if (links_reg & IXGBE_LINKS_UP) {
4079 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4082 if (links_reg & IXGBE_LINKS_UP)
4088 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4089 case IXGBE_LINKS_SPEED_10G_82599:
4090 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4091 if (hw->mac.type >= ixgbe_mac_X550) {
4092 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4093 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4096 case IXGBE_LINKS_SPEED_1G_82599:
4097 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4099 case IXGBE_LINKS_SPEED_100_82599:
4100 *speed = IXGBE_LINK_SPEED_100_FULL;
4101 if (hw->mac.type >= ixgbe_mac_X550) {
4102 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4103 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4107 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4110 return IXGBE_SUCCESS;
4114 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4116 * @hw: pointer to hardware structure
4117 * @wwnn_prefix: the alternative WWNN prefix
4118 * @wwpn_prefix: the alternative WWPN prefix
4120 * This function will read the EEPROM from the alternative SAN MAC address
4121 * block to check the support for the alternative WWNN/WWPN prefix support.
4123 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4127 u16 alt_san_mac_blk_offset;
4129 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
4131 /* clear output first */
4132 *wwnn_prefix = 0xFFFF;
4133 *wwpn_prefix = 0xFFFF;
4135 /* check if alternative SAN MAC is supported */
4136 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
4137 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4138 goto wwn_prefix_err;
4140 if ((alt_san_mac_blk_offset == 0) ||
4141 (alt_san_mac_blk_offset == 0xFFFF))
4142 goto wwn_prefix_out;
4144 /* check capability in alternative san mac address block */
4145 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
4146 if (hw->eeprom.ops.read(hw, offset, &caps))
4147 goto wwn_prefix_err;
4148 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
4149 goto wwn_prefix_out;
4151 /* get the corresponding prefix for WWNN/WWPN */
4152 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
4153 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4154 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4155 "eeprom read at offset %d failed", offset);
4158 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
4159 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4160 goto wwn_prefix_err;
4163 return IXGBE_SUCCESS;
4166 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4167 "eeprom read at offset %d failed", offset);
4168 return IXGBE_SUCCESS;
4172 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4173 * @hw: pointer to hardware structure
4174 * @bs: the fcoe boot status
4176 * This function will read the FCOE boot status from the iSCSI FCOE block
4178 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4180 u16 offset, caps, flags;
4183 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
4185 /* clear output first */
4186 *bs = ixgbe_fcoe_bootstatus_unavailable;
4188 /* check if FCOE IBA block is present */
4189 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
4190 status = hw->eeprom.ops.read(hw, offset, &caps);
4191 if (status != IXGBE_SUCCESS)
4194 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
4197 /* check if iSCSI FCOE block is populated */
4198 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4199 if (status != IXGBE_SUCCESS)
4202 if ((offset == 0) || (offset == 0xFFFF))
4205 /* read fcoe flags in iSCSI FCOE block */
4206 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
4207 status = hw->eeprom.ops.read(hw, offset, &flags);
4208 if (status != IXGBE_SUCCESS)
4211 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
4212 *bs = ixgbe_fcoe_bootstatus_enabled;
4214 *bs = ixgbe_fcoe_bootstatus_disabled;
4221 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4222 * @hw: pointer to hardware structure
4223 * @enable: enable or disable switch for anti-spoofing
4224 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
4227 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
4230 int pf_target_reg = pf >> 3;
4231 int pf_target_shift = pf % 8;
4234 if (hw->mac.type == ixgbe_mac_82598EB)
4238 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
4241 * PFVFSPOOF register array is size 8 with 8 bits assigned to
4242 * MAC anti-spoof enables in each register array element.
4244 for (j = 0; j < pf_target_reg; j++)
4245 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
4248 * The PF should be allowed to spoof so that it can support
4249 * emulation mode NICs. Do not set the bits assigned to the PF
4251 pfvfspoof &= (1 << pf_target_shift) - 1;
4252 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
4255 * Remaining pools belong to the PF so they do not need to have
4256 * anti-spoofing enabled.
4258 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
4259 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
4263 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4264 * @hw: pointer to hardware structure
4265 * @enable: enable or disable switch for VLAN anti-spoofing
4266 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4269 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4271 int vf_target_reg = vf >> 3;
4272 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
4275 if (hw->mac.type == ixgbe_mac_82598EB)
4278 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4280 pfvfspoof |= (1 << vf_target_shift);
4282 pfvfspoof &= ~(1 << vf_target_shift);
4283 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4287 * ixgbe_get_device_caps_generic - Get additional device capabilities
4288 * @hw: pointer to hardware structure
4289 * @device_caps: the EEPROM word with the extra device capabilities
4291 * This function will read the EEPROM location for the device capabilities,
4292 * and return the word through device_caps.
4294 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4296 DEBUGFUNC("ixgbe_get_device_caps_generic");
4298 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4300 return IXGBE_SUCCESS;
4304 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4305 * @hw: pointer to hardware structure
4308 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4313 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
4315 /* Enable relaxed ordering */
4316 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4317 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4318 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4319 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4322 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4323 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4324 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
4325 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4326 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4332 * ixgbe_calculate_checksum - Calculate checksum for buffer
4333 * @buffer: pointer to EEPROM
4334 * @length: size of EEPROM to calculate a checksum for
4335 * Calculates the checksum for some buffer on a specified length. The
4336 * checksum calculated is returned.
4338 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4343 DEBUGFUNC("ixgbe_calculate_checksum");
4348 for (i = 0; i < length; i++)
4351 return (u8) (0 - sum);
4355 * ixgbe_host_interface_command - Issue command to manageability block
4356 * @hw: pointer to the HW structure
4357 * @buffer: contains the command to write and where the return status will
4359 * @length: length of buffer, must be multiple of 4 bytes
4360 * @timeout: time in ms to wait for command completion
4361 * @return_data: read and return data from the buffer (true) or not (false)
4362 * Needed because FW structures are big endian and decoding of
4363 * these fields can be 8 bit or 16 bit based on command. Decoding
4364 * is not easily understood without making a table of commands.
4365 * So we will leave this up to the caller to read back the data
4368 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4369 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
4371 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4372 u32 length, u32 timeout, bool return_data)
4374 u32 hicr, i, bi, fwsts;
4375 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4379 DEBUGFUNC("ixgbe_host_interface_command");
4381 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4382 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4383 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4385 /* Set bit 9 of FWSTS clearing FW reset indication */
4386 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
4387 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
4389 /* Check that the host interface is enabled. */
4390 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4391 if ((hicr & IXGBE_HICR_EN) == 0) {
4392 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
4393 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4396 /* Calculate length in DWORDs. We must be DWORD aligned */
4397 if ((length % (sizeof(u32))) != 0) {
4398 DEBUGOUT("Buffer length failure, not aligned to dword");
4399 return IXGBE_ERR_INVALID_ARGUMENT;
4402 dword_len = length >> 2;
4404 /* The device driver writes the relevant command block
4405 * into the ram area.
4407 for (i = 0; i < dword_len; i++)
4408 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4409 i, IXGBE_CPU_TO_LE32(buffer[i]));
4411 /* Setting this bit tells the ARC that a new command is pending. */
4412 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4414 for (i = 0; i < timeout; i++) {
4415 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4416 if (!(hicr & IXGBE_HICR_C))
4421 /* Check command completion */
4422 if ((timeout != 0 && i == timeout) ||
4423 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
4424 ERROR_REPORT1(IXGBE_ERROR_CAUTION,
4425 "Command has failed with no status valid.\n");
4426 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4432 /* Calculate length in DWORDs */
4433 dword_len = hdr_size >> 2;
4435 /* first pull in the header so we know the buffer length */
4436 for (bi = 0; bi < dword_len; bi++) {
4437 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4438 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4441 /* If there is any thing in data position pull it in */
4442 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
4446 if (length < buf_len + hdr_size) {
4447 DEBUGOUT("Buffer not large enough for reply message.\n");
4448 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4451 /* Calculate length in DWORDs, add 3 for odd lengths */
4452 dword_len = (buf_len + 3) >> 2;
4454 /* Pull in the rest of the buffer (bi is where we left off) */
4455 for (; bi <= dword_len; bi++) {
4456 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4457 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4464 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4465 * @hw: pointer to the HW structure
4466 * @maj: driver version major number
4467 * @min: driver version minor number
4468 * @build: driver version build number
4469 * @sub: driver version sub build number
4471 * Sends driver version number to firmware through the manageability
4472 * block. On success return IXGBE_SUCCESS
4473 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4474 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4476 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4479 struct ixgbe_hic_drv_info fw_cmd;
4481 s32 ret_val = IXGBE_SUCCESS;
4483 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4485 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM)
4487 ret_val = IXGBE_ERR_SWFW_SYNC;
4491 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4492 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4493 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4494 fw_cmd.port_num = (u8)hw->bus.func;
4495 fw_cmd.ver_maj = maj;
4496 fw_cmd.ver_min = min;
4497 fw_cmd.ver_build = build;
4498 fw_cmd.ver_sub = sub;
4499 fw_cmd.hdr.checksum = 0;
4500 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4501 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4505 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4506 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4508 IXGBE_HI_COMMAND_TIMEOUT,
4510 if (ret_val != IXGBE_SUCCESS)
4513 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4514 FW_CEM_RESP_STATUS_SUCCESS)
4515 ret_val = IXGBE_SUCCESS;
4517 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4522 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4528 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4529 * @hw: pointer to hardware structure
4530 * @num_pb: number of packet buffers to allocate
4531 * @headroom: reserve n KB of headroom
4532 * @strategy: packet buffer allocation strategy
4534 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4537 u32 pbsize = hw->mac.rx_pb_size;
4539 u32 rxpktsize, txpktsize, txpbthresh;
4541 /* Reserve headroom */
4547 /* Divide remaining packet buffer space amongst the number of packet
4548 * buffers requested using supplied strategy.
4551 case PBA_STRATEGY_WEIGHTED:
4552 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4553 * buffer with 5/8 of the packet buffer space.
4555 rxpktsize = (pbsize * 5) / (num_pb * 4);
4556 pbsize -= rxpktsize * (num_pb / 2);
4557 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4558 for (; i < (num_pb / 2); i++)
4559 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4560 /* Fall through to configure remaining packet buffers */
4561 case PBA_STRATEGY_EQUAL:
4562 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4563 for (; i < num_pb; i++)
4564 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4570 /* Only support an equally distributed Tx packet buffer strategy. */
4571 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4572 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4573 for (i = 0; i < num_pb; i++) {
4574 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4575 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4578 /* Clear unused TCs, if any, to zero buffer size*/
4579 for (; i < IXGBE_MAX_PB; i++) {
4580 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4581 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4582 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4587 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4588 * @hw: pointer to the hardware structure
4590 * The 82599 and x540 MACs can experience issues if TX work is still pending
4591 * when a reset occurs. This function prevents this by flushing the PCIe
4592 * buffers on the system.
4594 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4596 u32 gcr_ext, hlreg0, i, poll;
4600 * If double reset is not requested then all transactions should
4601 * already be clear and as such there is no work to do
4603 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4607 * Set loopback enable to prevent any transmits from being sent
4608 * should the link come up. This assumes that the RXCTRL.RXEN bit
4609 * has already been cleared.
4611 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4612 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4614 /* Wait for a last completion before clearing buffers */
4615 IXGBE_WRITE_FLUSH(hw);
4619 * Before proceeding, make sure that the PCIe block does not have
4620 * transactions pending.
4622 poll = ixgbe_pcie_timeout_poll(hw);
4623 for (i = 0; i < poll; i++) {
4625 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
4626 if (IXGBE_REMOVED(hw->hw_addr))
4628 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
4633 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4634 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4635 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4636 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4638 /* Flush all writes and allow 20usec for all transactions to clear */
4639 IXGBE_WRITE_FLUSH(hw);
4642 /* restore previous register values */
4643 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4644 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4647 STATIC const u8 ixgbe_emc_temp_data[4] = {
4648 IXGBE_EMC_INTERNAL_DATA,
4649 IXGBE_EMC_DIODE1_DATA,
4650 IXGBE_EMC_DIODE2_DATA,
4651 IXGBE_EMC_DIODE3_DATA
4653 STATIC const u8 ixgbe_emc_therm_limit[4] = {
4654 IXGBE_EMC_INTERNAL_THERM_LIMIT,
4655 IXGBE_EMC_DIODE1_THERM_LIMIT,
4656 IXGBE_EMC_DIODE2_THERM_LIMIT,
4657 IXGBE_EMC_DIODE3_THERM_LIMIT
4661 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
4662 * @hw: pointer to hardware structure
4663 * @data: pointer to the thermal sensor data structure
4665 * Returns the thermal sensor data structure
4667 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
4669 s32 status = IXGBE_SUCCESS;
4677 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4679 DEBUGFUNC("ixgbe_get_thermal_sensor_data_generic");
4681 /* Only support thermal sensors attached to 82599 physical port 0 */
4682 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4683 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
4684 status = IXGBE_NOT_IMPLEMENTED;
4688 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);
4692 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) {
4693 status = IXGBE_NOT_IMPLEMENTED;
4697 status = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);
4701 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4702 != IXGBE_ETS_TYPE_EMC) {
4703 status = IXGBE_NOT_IMPLEMENTED;
4707 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4708 if (num_sensors > IXGBE_MAX_SENSORS)
4709 num_sensors = IXGBE_MAX_SENSORS;
4711 for (i = 0; i < num_sensors; i++) {
4712 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
4717 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4718 IXGBE_ETS_DATA_INDEX_SHIFT);
4719 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4720 IXGBE_ETS_DATA_LOC_SHIFT);
4722 if (sensor_location != 0) {
4723 status = hw->phy.ops.read_i2c_byte(hw,
4724 ixgbe_emc_temp_data[sensor_index],
4725 IXGBE_I2C_THERMAL_SENSOR_ADDR,
4726 &data->sensor[i].temp);
4736 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
4737 * @hw: pointer to hardware structure
4739 * Inits the thermal sensor thresholds according to the NVM map
4740 * and save off the threshold and location values into mac.thermal_sensor_data
4742 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
4744 s32 status = IXGBE_SUCCESS;
4749 u8 low_thresh_delta;
4755 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4757 DEBUGFUNC("ixgbe_init_thermal_sensor_thresh_generic");
4759 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
4761 /* Only support thermal sensors attached to 82599 physical port 0 */
4762 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4763 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
4764 return IXGBE_NOT_IMPLEMENTED;
4766 offset = IXGBE_ETS_CFG;
4767 if (hw->eeprom.ops.read(hw, offset, &ets_offset))
4769 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
4770 return IXGBE_NOT_IMPLEMENTED;
4772 offset = ets_offset;
4773 if (hw->eeprom.ops.read(hw, offset, &ets_cfg))
4775 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4776 != IXGBE_ETS_TYPE_EMC)
4777 return IXGBE_NOT_IMPLEMENTED;
4779 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
4780 IXGBE_ETS_LTHRES_DELTA_SHIFT);
4781 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4783 for (i = 0; i < num_sensors; i++) {
4784 offset = ets_offset + 1 + i;
4785 if (hw->eeprom.ops.read(hw, offset, &ets_sensor)) {
4786 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4787 "eeprom read at offset %d failed",
4791 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4792 IXGBE_ETS_DATA_INDEX_SHIFT);
4793 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4794 IXGBE_ETS_DATA_LOC_SHIFT);
4795 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
4797 hw->phy.ops.write_i2c_byte(hw,
4798 ixgbe_emc_therm_limit[sensor_index],
4799 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
4801 if ((i < IXGBE_MAX_SENSORS) && (sensor_location != 0)) {
4802 data->sensor[i].location = sensor_location;
4803 data->sensor[i].caution_thresh = therm_limit;
4804 data->sensor[i].max_op_thresh = therm_limit -
4811 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4812 "eeprom read at offset %d failed", offset);
4813 return IXGBE_NOT_IMPLEMENTED;
4818 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
4819 * @hw: pointer to hardware structure
4820 * @map: pointer to u8 arr for returning map
4822 * Read the rtrup2tc HW register and resolve its content into map
4824 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
4828 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
4829 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
4830 map[i] = IXGBE_RTRUP2TC_UP_MASK &
4831 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
4835 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
4840 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4841 if (rxctrl & IXGBE_RXCTRL_RXEN) {
4842 if (hw->mac.type != ixgbe_mac_82598EB) {
4843 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4844 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
4845 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4846 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4847 hw->mac.set_lben = true;
4849 hw->mac.set_lben = false;
4852 rxctrl &= ~IXGBE_RXCTRL_RXEN;
4853 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
4857 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
4862 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4863 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
4865 if (hw->mac.type != ixgbe_mac_82598EB) {
4866 if (hw->mac.set_lben) {
4867 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4868 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
4869 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4870 hw->mac.set_lben = false;
4876 * ixgbe_mng_present - returns true when management capability is present
4877 * @hw: pointer to hardware structure
4879 bool ixgbe_mng_present(struct ixgbe_hw *hw)
4883 if (hw->mac.type < ixgbe_mac_82599EB)
4886 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
4887 fwsm &= IXGBE_FWSM_MODE_MASK;
4888 return fwsm == IXGBE_FWSM_FW_MODE_PT;
4892 * ixgbe_mng_enabled - Is the manageability engine enabled?
4893 * @hw: pointer to hardware structure
4895 * Returns true if the manageability engine is enabled.
4897 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
4899 u32 fwsm, manc, factps;
4901 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
4902 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
4905 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
4906 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
4909 if (hw->mac.type <= ixgbe_mac_X540) {
4910 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
4911 if (factps & IXGBE_FACTPS_MNGCG)
4919 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
4920 * @hw: pointer to hardware structure
4921 * @speed: new link speed
4922 * @autoneg_wait_to_complete: true when waiting for completion is needed
4924 * Set the link speed in the MAC and/or PHY register and restarts link.
4926 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
4927 ixgbe_link_speed speed,
4928 bool autoneg_wait_to_complete)
4930 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4931 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4932 s32 status = IXGBE_SUCCESS;
4935 bool autoneg, link_up = false;
4937 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
4939 /* Mask off requested but non-supported speeds */
4940 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
4941 if (status != IXGBE_SUCCESS)
4944 speed &= link_speed;
4946 /* Try each speed one by one, highest priority first. We do this in
4947 * software because 10Gb fiber doesn't support speed autonegotiation.
4949 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
4951 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
4953 /* If we already have link at this speed, just jump out */
4954 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
4955 if (status != IXGBE_SUCCESS)
4958 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
4961 /* Set the module link speed */
4962 switch (hw->phy.media_type) {
4963 case ixgbe_media_type_fiber:
4964 ixgbe_set_rate_select_speed(hw,
4965 IXGBE_LINK_SPEED_10GB_FULL);
4967 case ixgbe_media_type_fiber_qsfp:
4968 /* QSFP module automatically detects MAC link speed */
4971 DEBUGOUT("Unexpected media type.\n");
4975 /* Allow module to change analog characteristics (1G->10G) */
4978 status = ixgbe_setup_mac_link(hw,
4979 IXGBE_LINK_SPEED_10GB_FULL,
4980 autoneg_wait_to_complete);
4981 if (status != IXGBE_SUCCESS)
4984 /* Flap the Tx laser if it has not already been done */
4985 ixgbe_flap_tx_laser(hw);
4987 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
4988 * Section 73.10.2, we may have to wait up to 500ms if KR is
4989 * attempted. 82599 uses the same timing for 10g SFI.
4991 for (i = 0; i < 5; i++) {
4992 /* Wait for the link partner to also set speed */
4995 /* If we have link, just jump out */
4996 status = ixgbe_check_link(hw, &link_speed,
4998 if (status != IXGBE_SUCCESS)
5006 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
5008 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
5009 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
5011 /* If we already have link at this speed, just jump out */
5012 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
5013 if (status != IXGBE_SUCCESS)
5016 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
5019 /* Set the module link speed */
5020 switch (hw->phy.media_type) {
5021 case ixgbe_media_type_fiber:
5022 ixgbe_set_rate_select_speed(hw,
5023 IXGBE_LINK_SPEED_1GB_FULL);
5025 case ixgbe_media_type_fiber_qsfp:
5026 /* QSFP module automatically detects link speed */
5029 DEBUGOUT("Unexpected media type.\n");
5033 /* Allow module to change analog characteristics (10G->1G) */
5036 status = ixgbe_setup_mac_link(hw,
5037 IXGBE_LINK_SPEED_1GB_FULL,
5038 autoneg_wait_to_complete);
5039 if (status != IXGBE_SUCCESS)
5042 /* Flap the Tx laser if it has not already been done */
5043 ixgbe_flap_tx_laser(hw);
5045 /* Wait for the link partner to also set speed */
5048 /* If we have link, just jump out */
5049 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
5050 if (status != IXGBE_SUCCESS)
5057 /* We didn't get link. Configure back to the highest speed we tried,
5058 * (if there was more than one). We call ourselves back with just the
5059 * single highest speed that the user requested.
5062 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
5064 autoneg_wait_to_complete);
5067 /* Set autoneg_advertised value based on input link speed */
5068 hw->phy.autoneg_advertised = 0;
5070 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
5071 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
5073 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
5074 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
5080 * ixgbe_set_soft_rate_select_speed - Set module link speed
5081 * @hw: pointer to hardware structure
5082 * @speed: link speed to set
5084 * Set module link speed via the soft rate select.
5086 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
5087 ixgbe_link_speed speed)
5093 case IXGBE_LINK_SPEED_10GB_FULL:
5094 /* one bit mask same as setting on */
5095 rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
5097 case IXGBE_LINK_SPEED_1GB_FULL:
5098 rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
5101 DEBUGOUT("Invalid fixed module speed\n");
5106 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5107 IXGBE_I2C_EEPROM_DEV_ADDR2,
5110 DEBUGOUT("Failed to read Rx Rate Select RS0\n");
5114 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5116 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5117 IXGBE_I2C_EEPROM_DEV_ADDR2,
5120 DEBUGOUT("Failed to write Rx Rate Select RS0\n");
5125 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5126 IXGBE_I2C_EEPROM_DEV_ADDR2,
5129 DEBUGOUT("Failed to read Rx Rate Select RS1\n");
5133 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5135 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5136 IXGBE_I2C_EEPROM_DEV_ADDR2,
5139 DEBUGOUT("Failed to write Rx Rate Select RS1\n");