1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
36 #include "ixgbe_dcb.h"
37 #include "ixgbe_dcb_82599.h"
38 #include "ixgbe_api.h"
40 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
41 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
42 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
43 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
44 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
45 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
47 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
48 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
49 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
50 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw);
52 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
53 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
55 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
56 u16 words, u16 *data);
57 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
58 u16 words, u16 *data);
59 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
63 * ixgbe_init_ops_generic - Inits function ptrs
64 * @hw: pointer to the hardware structure
66 * Initialize the function pointers.
68 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
70 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
71 struct ixgbe_mac_info *mac = &hw->mac;
72 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
74 DEBUGFUNC("ixgbe_init_ops_generic");
77 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic;
78 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
79 if (eec & IXGBE_EEC_PRES) {
80 eeprom->ops.read = ixgbe_read_eerd_generic;
81 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic;
83 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic;
84 eeprom->ops.read_buffer =
85 ixgbe_read_eeprom_buffer_bit_bang_generic;
87 eeprom->ops.write = ixgbe_write_eeprom_generic;
88 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic;
89 eeprom->ops.validate_checksum =
90 ixgbe_validate_eeprom_checksum_generic;
91 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic;
92 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic;
95 mac->ops.init_hw = ixgbe_init_hw_generic;
96 mac->ops.reset_hw = NULL;
97 mac->ops.start_hw = ixgbe_start_hw_generic;
98 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic;
99 mac->ops.get_media_type = NULL;
100 mac->ops.get_supported_physical_layer = NULL;
101 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic;
102 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic;
103 mac->ops.stop_adapter = ixgbe_stop_adapter_generic;
104 mac->ops.get_bus_info = ixgbe_get_bus_info_generic;
105 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie;
106 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync;
107 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync;
108 mac->ops.prot_autoc_read = prot_autoc_read_generic;
109 mac->ops.prot_autoc_write = prot_autoc_write_generic;
112 mac->ops.led_on = ixgbe_led_on_generic;
113 mac->ops.led_off = ixgbe_led_off_generic;
114 mac->ops.blink_led_start = ixgbe_blink_led_start_generic;
115 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic;
116 mac->ops.init_led_link_act = ixgbe_init_led_link_act_generic;
118 /* RAR, Multicast, VLAN */
119 mac->ops.set_rar = ixgbe_set_rar_generic;
120 mac->ops.clear_rar = ixgbe_clear_rar_generic;
121 mac->ops.insert_mac_addr = NULL;
122 mac->ops.set_vmdq = NULL;
123 mac->ops.clear_vmdq = NULL;
124 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic;
125 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic;
126 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic;
127 mac->ops.enable_mc = ixgbe_enable_mc_generic;
128 mac->ops.disable_mc = ixgbe_disable_mc_generic;
129 mac->ops.clear_vfta = NULL;
130 mac->ops.set_vfta = NULL;
131 mac->ops.set_vlvf = NULL;
132 mac->ops.init_uta_tables = NULL;
133 mac->ops.enable_rx = ixgbe_enable_rx_generic;
134 mac->ops.disable_rx = ixgbe_disable_rx_generic;
137 mac->ops.fc_enable = ixgbe_fc_enable_generic;
138 mac->ops.setup_fc = ixgbe_setup_fc_generic;
139 mac->ops.fc_autoneg = ixgbe_fc_autoneg;
142 mac->ops.get_link_capabilities = NULL;
143 mac->ops.setup_link = NULL;
144 mac->ops.check_link = NULL;
145 mac->ops.dmac_config = NULL;
146 mac->ops.dmac_update_tcs = NULL;
147 mac->ops.dmac_config_tcs = NULL;
149 return IXGBE_SUCCESS;
153 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
155 * @hw: pointer to hardware structure
157 * This function returns true if the device supports flow control
158 * autonegotiation, and false if it does not.
161 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
163 bool supported = false;
164 ixgbe_link_speed speed;
167 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
169 switch (hw->phy.media_type) {
170 case ixgbe_media_type_fiber_qsfp:
171 case ixgbe_media_type_fiber:
172 /* flow control autoneg black list */
173 switch (hw->device_id) {
174 case IXGBE_DEV_ID_X550EM_A_SFP:
175 case IXGBE_DEV_ID_X550EM_A_SFP_N:
176 case IXGBE_DEV_ID_X550EM_A_QSFP:
177 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
181 hw->mac.ops.check_link(hw, &speed, &link_up, false);
182 /* if link is down, assume supported */
184 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
191 case ixgbe_media_type_backplane:
194 case ixgbe_media_type_copper:
195 /* only some copper devices support flow control autoneg */
196 switch (hw->device_id) {
197 case IXGBE_DEV_ID_82599_T3_LOM:
198 case IXGBE_DEV_ID_X540T:
199 case IXGBE_DEV_ID_X540T1:
200 case IXGBE_DEV_ID_X550T:
201 case IXGBE_DEV_ID_X550T1:
202 case IXGBE_DEV_ID_X550EM_X_10G_T:
203 case IXGBE_DEV_ID_X550EM_A_10G_T:
204 case IXGBE_DEV_ID_X550EM_A_1G_T:
205 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
216 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
217 "Device %x does not support flow control autoneg",
223 * ixgbe_setup_fc_generic - Set up flow control
224 * @hw: pointer to hardware structure
226 * Called at init time to set up flow control.
228 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
230 s32 ret_val = IXGBE_SUCCESS;
231 u32 reg = 0, reg_bp = 0;
235 DEBUGFUNC("ixgbe_setup_fc_generic");
237 /* Validate the requested mode */
238 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
239 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
240 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
241 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
246 * 10gig parts do not have a word in the EEPROM to determine the
247 * default flow control setting, so we explicitly set it to full.
249 if (hw->fc.requested_mode == ixgbe_fc_default)
250 hw->fc.requested_mode = ixgbe_fc_full;
253 * Set up the 1G and 10G flow control advertisement registers so the
254 * HW will be able to do fc autoneg once the cable is plugged in. If
255 * we link at 10G, the 1G advertisement is harmless and vice versa.
257 switch (hw->phy.media_type) {
258 case ixgbe_media_type_backplane:
259 /* some MAC's need RMW protection on AUTOC */
260 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
261 if (ret_val != IXGBE_SUCCESS)
264 /* only backplane uses autoc so fall though */
265 case ixgbe_media_type_fiber_qsfp:
266 case ixgbe_media_type_fiber:
267 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
270 case ixgbe_media_type_copper:
271 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
272 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
279 * The possible values of fc.requested_mode are:
280 * 0: Flow control is completely disabled
281 * 1: Rx flow control is enabled (we can receive pause frames,
282 * but not send pause frames).
283 * 2: Tx flow control is enabled (we can send pause frames but
284 * we do not support receiving pause frames).
285 * 3: Both Rx and Tx flow control (symmetric) are enabled.
288 switch (hw->fc.requested_mode) {
290 /* Flow control completely disabled by software override. */
291 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
292 if (hw->phy.media_type == ixgbe_media_type_backplane)
293 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
294 IXGBE_AUTOC_ASM_PAUSE);
295 else if (hw->phy.media_type == ixgbe_media_type_copper)
296 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
298 case ixgbe_fc_tx_pause:
300 * Tx Flow control is enabled, and Rx Flow control is
301 * disabled by software override.
303 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
304 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
305 if (hw->phy.media_type == ixgbe_media_type_backplane) {
306 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
307 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
308 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
309 reg_cu |= IXGBE_TAF_ASM_PAUSE;
310 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
313 case ixgbe_fc_rx_pause:
315 * Rx Flow control is enabled and Tx Flow control is
316 * disabled by software override. Since there really
317 * isn't a way to advertise that we are capable of RX
318 * Pause ONLY, we will advertise that we support both
319 * symmetric and asymmetric Rx PAUSE, as such we fall
320 * through to the fc_full statement. Later, we will
321 * disable the adapter's ability to send PAUSE frames.
324 /* Flow control (both Rx and Tx) is enabled by SW override. */
325 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
326 if (hw->phy.media_type == ixgbe_media_type_backplane)
327 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
328 IXGBE_AUTOC_ASM_PAUSE;
329 else if (hw->phy.media_type == ixgbe_media_type_copper)
330 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
333 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
334 "Flow control param set incorrectly\n");
335 ret_val = IXGBE_ERR_CONFIG;
340 if (hw->mac.type < ixgbe_mac_X540) {
342 * Enable auto-negotiation between the MAC & PHY;
343 * the MAC will advertise clause 37 flow control.
345 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
346 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
348 /* Disable AN timeout */
349 if (hw->fc.strict_ieee)
350 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
352 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
353 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
357 * AUTOC restart handles negotiation of 1G and 10G on backplane
358 * and copper. There is no need to set the PCS1GCTL register.
361 if (hw->phy.media_type == ixgbe_media_type_backplane) {
362 reg_bp |= IXGBE_AUTOC_AN_RESTART;
363 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
366 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
367 (ixgbe_device_supports_autoneg_fc(hw))) {
368 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
369 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
372 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
378 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
379 * @hw: pointer to hardware structure
381 * Starts the hardware by filling the bus info structure and media type, clears
382 * all on chip counters, initializes receive address registers, multicast
383 * table, VLAN filter table, calls routine to set up link and flow control
384 * settings, and leaves transmit and receive units disabled and uninitialized
386 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
392 DEBUGFUNC("ixgbe_start_hw_generic");
394 /* Set the media type */
395 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
397 /* PHY ops initialization must be done in reset_hw() */
399 /* Clear the VLAN filter table */
400 hw->mac.ops.clear_vfta(hw);
402 /* Clear statistics registers */
403 hw->mac.ops.clear_hw_cntrs(hw);
405 /* Set No Snoop Disable */
406 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
407 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
408 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
409 IXGBE_WRITE_FLUSH(hw);
411 /* Setup flow control */
412 ret_val = ixgbe_setup_fc(hw);
413 if (ret_val != IXGBE_SUCCESS && ret_val != IXGBE_NOT_IMPLEMENTED)
416 /* Cache bit indicating need for crosstalk fix */
417 switch (hw->mac.type) {
418 case ixgbe_mac_82599EB:
419 case ixgbe_mac_X550EM_x:
420 case ixgbe_mac_X550EM_a:
421 hw->mac.ops.get_device_caps(hw, &device_caps);
422 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
423 hw->need_crosstalk_fix = false;
425 hw->need_crosstalk_fix = true;
428 hw->need_crosstalk_fix = false;
432 /* Clear adapter stopped flag */
433 hw->adapter_stopped = false;
435 return IXGBE_SUCCESS;
439 * ixgbe_start_hw_gen2 - Init sequence for common device family
440 * @hw: pointer to hw structure
442 * Performs the init sequence common to the second generation
444 * Devices in the second generation:
448 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
453 /* Clear the rate limiters */
454 for (i = 0; i < hw->mac.max_tx_queues; i++) {
455 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
456 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
458 IXGBE_WRITE_FLUSH(hw);
460 /* Disable relaxed ordering */
461 for (i = 0; i < hw->mac.max_tx_queues; i++) {
462 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
463 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
464 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
467 for (i = 0; i < hw->mac.max_rx_queues; i++) {
468 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
469 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
470 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
471 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
474 return IXGBE_SUCCESS;
478 * ixgbe_init_hw_generic - Generic hardware initialization
479 * @hw: pointer to hardware structure
481 * Initialize the hardware by resetting the hardware, filling the bus info
482 * structure and media type, clears all on chip counters, initializes receive
483 * address registers, multicast table, VLAN filter table, calls routine to set
484 * up link and flow control settings, and leaves transmit and receive units
485 * disabled and uninitialized
487 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
491 DEBUGFUNC("ixgbe_init_hw_generic");
493 /* Reset the hardware */
494 status = hw->mac.ops.reset_hw(hw);
496 if (status == IXGBE_SUCCESS) {
498 status = hw->mac.ops.start_hw(hw);
501 /* Initialize the LED link active for LED blink support */
502 hw->mac.ops.init_led_link_act(hw);
508 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
509 * @hw: pointer to hardware structure
511 * Clears all hardware statistics counters by reading them from the hardware
512 * Statistics counters are clear on read.
514 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
518 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
520 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
521 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
522 IXGBE_READ_REG(hw, IXGBE_ERRBC);
523 IXGBE_READ_REG(hw, IXGBE_MSPDC);
524 for (i = 0; i < 8; i++)
525 IXGBE_READ_REG(hw, IXGBE_MPC(i));
527 IXGBE_READ_REG(hw, IXGBE_MLFC);
528 IXGBE_READ_REG(hw, IXGBE_MRFC);
529 IXGBE_READ_REG(hw, IXGBE_RLEC);
530 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
531 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
532 if (hw->mac.type >= ixgbe_mac_82599EB) {
533 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
534 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
536 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
537 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
540 for (i = 0; i < 8; i++) {
541 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
542 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
543 if (hw->mac.type >= ixgbe_mac_82599EB) {
544 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
545 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
547 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
548 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
551 if (hw->mac.type >= ixgbe_mac_82599EB)
552 for (i = 0; i < 8; i++)
553 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
554 IXGBE_READ_REG(hw, IXGBE_PRC64);
555 IXGBE_READ_REG(hw, IXGBE_PRC127);
556 IXGBE_READ_REG(hw, IXGBE_PRC255);
557 IXGBE_READ_REG(hw, IXGBE_PRC511);
558 IXGBE_READ_REG(hw, IXGBE_PRC1023);
559 IXGBE_READ_REG(hw, IXGBE_PRC1522);
560 IXGBE_READ_REG(hw, IXGBE_GPRC);
561 IXGBE_READ_REG(hw, IXGBE_BPRC);
562 IXGBE_READ_REG(hw, IXGBE_MPRC);
563 IXGBE_READ_REG(hw, IXGBE_GPTC);
564 IXGBE_READ_REG(hw, IXGBE_GORCL);
565 IXGBE_READ_REG(hw, IXGBE_GORCH);
566 IXGBE_READ_REG(hw, IXGBE_GOTCL);
567 IXGBE_READ_REG(hw, IXGBE_GOTCH);
568 if (hw->mac.type == ixgbe_mac_82598EB)
569 for (i = 0; i < 8; i++)
570 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
571 IXGBE_READ_REG(hw, IXGBE_RUC);
572 IXGBE_READ_REG(hw, IXGBE_RFC);
573 IXGBE_READ_REG(hw, IXGBE_ROC);
574 IXGBE_READ_REG(hw, IXGBE_RJC);
575 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
576 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
577 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
578 IXGBE_READ_REG(hw, IXGBE_TORL);
579 IXGBE_READ_REG(hw, IXGBE_TORH);
580 IXGBE_READ_REG(hw, IXGBE_TPR);
581 IXGBE_READ_REG(hw, IXGBE_TPT);
582 IXGBE_READ_REG(hw, IXGBE_PTC64);
583 IXGBE_READ_REG(hw, IXGBE_PTC127);
584 IXGBE_READ_REG(hw, IXGBE_PTC255);
585 IXGBE_READ_REG(hw, IXGBE_PTC511);
586 IXGBE_READ_REG(hw, IXGBE_PTC1023);
587 IXGBE_READ_REG(hw, IXGBE_PTC1522);
588 IXGBE_READ_REG(hw, IXGBE_MPTC);
589 IXGBE_READ_REG(hw, IXGBE_BPTC);
590 for (i = 0; i < 16; i++) {
591 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
592 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
593 if (hw->mac.type >= ixgbe_mac_82599EB) {
594 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
595 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
596 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
597 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
598 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
600 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
601 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
605 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
607 ixgbe_identify_phy(hw);
608 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
609 IXGBE_MDIO_PCS_DEV_TYPE, &i);
610 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
611 IXGBE_MDIO_PCS_DEV_TYPE, &i);
612 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
613 IXGBE_MDIO_PCS_DEV_TYPE, &i);
614 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
615 IXGBE_MDIO_PCS_DEV_TYPE, &i);
618 return IXGBE_SUCCESS;
622 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
623 * @hw: pointer to hardware structure
624 * @pba_num: stores the part number string from the EEPROM
625 * @pba_num_size: part number string buffer length
627 * Reads the part number string from the EEPROM.
629 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
638 DEBUGFUNC("ixgbe_read_pba_string_generic");
640 if (pba_num == NULL) {
641 DEBUGOUT("PBA string buffer was null\n");
642 return IXGBE_ERR_INVALID_ARGUMENT;
645 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
647 DEBUGOUT("NVM Read Error\n");
651 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
653 DEBUGOUT("NVM Read Error\n");
658 * if data is not ptr guard the PBA must be in legacy format which
659 * means pba_ptr is actually our second data word for the PBA number
660 * and we can decode it into an ascii string
662 if (data != IXGBE_PBANUM_PTR_GUARD) {
663 DEBUGOUT("NVM PBA number is not stored as string\n");
665 /* we will need 11 characters to store the PBA */
666 if (pba_num_size < 11) {
667 DEBUGOUT("PBA string buffer too small\n");
668 return IXGBE_ERR_NO_SPACE;
671 /* extract hex string from data and pba_ptr */
672 pba_num[0] = (data >> 12) & 0xF;
673 pba_num[1] = (data >> 8) & 0xF;
674 pba_num[2] = (data >> 4) & 0xF;
675 pba_num[3] = data & 0xF;
676 pba_num[4] = (pba_ptr >> 12) & 0xF;
677 pba_num[5] = (pba_ptr >> 8) & 0xF;
680 pba_num[8] = (pba_ptr >> 4) & 0xF;
681 pba_num[9] = pba_ptr & 0xF;
683 /* put a null character on the end of our string */
686 /* switch all the data but the '-' to hex char */
687 for (offset = 0; offset < 10; offset++) {
688 if (pba_num[offset] < 0xA)
689 pba_num[offset] += '0';
690 else if (pba_num[offset] < 0x10)
691 pba_num[offset] += 'A' - 0xA;
694 return IXGBE_SUCCESS;
697 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
699 DEBUGOUT("NVM Read Error\n");
703 if (length == 0xFFFF || length == 0) {
704 DEBUGOUT("NVM PBA number section invalid length\n");
705 return IXGBE_ERR_PBA_SECTION;
708 /* check if pba_num buffer is big enough */
709 if (pba_num_size < (((u32)length * 2) - 1)) {
710 DEBUGOUT("PBA string buffer too small\n");
711 return IXGBE_ERR_NO_SPACE;
714 /* trim pba length from start of string */
718 for (offset = 0; offset < length; offset++) {
719 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
721 DEBUGOUT("NVM Read Error\n");
724 pba_num[offset * 2] = (u8)(data >> 8);
725 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
727 pba_num[offset * 2] = '\0';
729 return IXGBE_SUCCESS;
733 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
734 * @hw: pointer to hardware structure
735 * @pba_num: stores the part number from the EEPROM
737 * Reads the part number from the EEPROM.
739 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
744 DEBUGFUNC("ixgbe_read_pba_num_generic");
746 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
748 DEBUGOUT("NVM Read Error\n");
750 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
751 DEBUGOUT("NVM Not supported\n");
752 return IXGBE_NOT_IMPLEMENTED;
754 *pba_num = (u32)(data << 16);
756 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
758 DEBUGOUT("NVM Read Error\n");
763 return IXGBE_SUCCESS;
768 * @hw: pointer to the HW structure
769 * @eeprom_buf: optional pointer to EEPROM image
770 * @eeprom_buf_size: size of EEPROM image in words
771 * @max_pba_block_size: PBA block size limit
772 * @pba: pointer to output PBA structure
774 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
775 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
778 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
779 u32 eeprom_buf_size, u16 max_pba_block_size,
780 struct ixgbe_pba *pba)
786 return IXGBE_ERR_PARAM;
788 if (eeprom_buf == NULL) {
789 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
794 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
795 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
796 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
798 return IXGBE_ERR_PARAM;
802 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
803 if (pba->pba_block == NULL)
804 return IXGBE_ERR_PARAM;
806 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
812 if (pba_block_size > max_pba_block_size)
813 return IXGBE_ERR_PARAM;
815 if (eeprom_buf == NULL) {
816 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
822 if (eeprom_buf_size > (u32)(pba->word[1] +
824 memcpy(pba->pba_block,
825 &eeprom_buf[pba->word[1]],
826 pba_block_size * sizeof(u16));
828 return IXGBE_ERR_PARAM;
833 return IXGBE_SUCCESS;
837 * ixgbe_write_pba_raw
838 * @hw: pointer to the HW structure
839 * @eeprom_buf: optional pointer to EEPROM image
840 * @eeprom_buf_size: size of EEPROM image in words
841 * @pba: pointer to PBA structure
843 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
844 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
847 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
848 u32 eeprom_buf_size, struct ixgbe_pba *pba)
853 return IXGBE_ERR_PARAM;
855 if (eeprom_buf == NULL) {
856 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
861 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
862 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
863 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
865 return IXGBE_ERR_PARAM;
869 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
870 if (pba->pba_block == NULL)
871 return IXGBE_ERR_PARAM;
873 if (eeprom_buf == NULL) {
874 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
880 if (eeprom_buf_size > (u32)(pba->word[1] +
881 pba->pba_block[0])) {
882 memcpy(&eeprom_buf[pba->word[1]],
884 pba->pba_block[0] * sizeof(u16));
886 return IXGBE_ERR_PARAM;
891 return IXGBE_SUCCESS;
895 * ixgbe_get_pba_block_size
896 * @hw: pointer to the HW structure
897 * @eeprom_buf: optional pointer to EEPROM image
898 * @eeprom_buf_size: size of EEPROM image in words
899 * @pba_data_size: pointer to output variable
901 * Returns the size of the PBA block in words. Function operates on EEPROM
902 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
906 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
907 u32 eeprom_buf_size, u16 *pba_block_size)
913 DEBUGFUNC("ixgbe_get_pba_block_size");
915 if (eeprom_buf == NULL) {
916 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
921 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
922 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
923 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
925 return IXGBE_ERR_PARAM;
929 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
930 if (eeprom_buf == NULL) {
931 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
936 if (eeprom_buf_size > pba_word[1])
937 length = eeprom_buf[pba_word[1] + 0];
939 return IXGBE_ERR_PARAM;
942 if (length == 0xFFFF || length == 0)
943 return IXGBE_ERR_PBA_SECTION;
945 /* PBA number in legacy format, there is no PBA Block. */
949 if (pba_block_size != NULL)
950 *pba_block_size = length;
952 return IXGBE_SUCCESS;
956 * ixgbe_get_mac_addr_generic - Generic get MAC address
957 * @hw: pointer to hardware structure
958 * @mac_addr: Adapter MAC address
960 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
961 * A reset of the adapter must be performed prior to calling this function
962 * in order for the MAC address to have been loaded from the EEPROM into RAR0
964 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
970 DEBUGFUNC("ixgbe_get_mac_addr_generic");
972 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
973 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
975 for (i = 0; i < 4; i++)
976 mac_addr[i] = (u8)(rar_low >> (i*8));
978 for (i = 0; i < 2; i++)
979 mac_addr[i+4] = (u8)(rar_high >> (i*8));
981 return IXGBE_SUCCESS;
985 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
986 * @hw: pointer to hardware structure
987 * @link_status: the link status returned by the PCI config space
989 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
991 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
993 struct ixgbe_mac_info *mac = &hw->mac;
995 if (hw->bus.type == ixgbe_bus_type_unknown)
996 hw->bus.type = ixgbe_bus_type_pci_express;
998 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
999 case IXGBE_PCI_LINK_WIDTH_1:
1000 hw->bus.width = ixgbe_bus_width_pcie_x1;
1002 case IXGBE_PCI_LINK_WIDTH_2:
1003 hw->bus.width = ixgbe_bus_width_pcie_x2;
1005 case IXGBE_PCI_LINK_WIDTH_4:
1006 hw->bus.width = ixgbe_bus_width_pcie_x4;
1008 case IXGBE_PCI_LINK_WIDTH_8:
1009 hw->bus.width = ixgbe_bus_width_pcie_x8;
1012 hw->bus.width = ixgbe_bus_width_unknown;
1016 switch (link_status & IXGBE_PCI_LINK_SPEED) {
1017 case IXGBE_PCI_LINK_SPEED_2500:
1018 hw->bus.speed = ixgbe_bus_speed_2500;
1020 case IXGBE_PCI_LINK_SPEED_5000:
1021 hw->bus.speed = ixgbe_bus_speed_5000;
1023 case IXGBE_PCI_LINK_SPEED_8000:
1024 hw->bus.speed = ixgbe_bus_speed_8000;
1027 hw->bus.speed = ixgbe_bus_speed_unknown;
1031 mac->ops.set_lan_id(hw);
1035 * ixgbe_get_bus_info_generic - Generic set PCI bus info
1036 * @hw: pointer to hardware structure
1038 * Gets the PCI bus info (speed, width, type) then calls helper function to
1039 * store this data within the ixgbe_hw structure.
1041 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
1045 DEBUGFUNC("ixgbe_get_bus_info_generic");
1047 /* Get the negotiated link width and speed from PCI config space */
1048 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
1050 ixgbe_set_pci_config_data_generic(hw, link_status);
1052 return IXGBE_SUCCESS;
1056 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
1057 * @hw: pointer to the HW structure
1059 * Determines the LAN function id by reading memory-mapped registers and swaps
1060 * the port value if requested, and set MAC instance for devices that share
1063 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
1065 struct ixgbe_bus_info *bus = &hw->bus;
1069 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
1071 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
1072 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
1073 bus->lan_id = (u8)bus->func;
1075 /* check for a port swap */
1076 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
1077 if (reg & IXGBE_FACTPS_LFS)
1080 /* Get MAC instance from EEPROM for configuring CS4227 */
1081 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) {
1082 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4);
1083 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >>
1084 IXGBE_EE_CTRL_4_INST_ID_SHIFT;
1089 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1090 * @hw: pointer to hardware structure
1092 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
1093 * disables transmit and receive units. The adapter_stopped flag is used by
1094 * the shared code and drivers to determine if the adapter is in a stopped
1095 * state and should not touch the hardware.
1097 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1102 DEBUGFUNC("ixgbe_stop_adapter_generic");
1105 * Set the adapter_stopped flag so other driver functions stop touching
1108 hw->adapter_stopped = true;
1110 /* Disable the receive unit */
1111 ixgbe_disable_rx(hw);
1113 /* Clear interrupt mask to stop interrupts from being generated */
1114 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1116 /* Clear any pending interrupts, flush previous writes */
1117 IXGBE_READ_REG(hw, IXGBE_EICR);
1119 /* Disable the transmit unit. Each queue must be disabled. */
1120 for (i = 0; i < hw->mac.max_tx_queues; i++)
1121 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1123 /* Disable the receive unit by stopping each queue */
1124 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1125 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1126 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1127 reg_val |= IXGBE_RXDCTL_SWFLSH;
1128 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1131 /* flush all queues disables */
1132 IXGBE_WRITE_FLUSH(hw);
1136 * Prevent the PCI-E bus from hanging by disabling PCI-E master
1137 * access and verify no pending requests
1139 return ixgbe_disable_pcie_master(hw);
1143 * ixgbe_init_led_link_act_generic - Store the LED index link/activity.
1144 * @hw: pointer to hardware structure
1146 * Store the index for the link active LED. This will be used to support
1149 s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw)
1151 struct ixgbe_mac_info *mac = &hw->mac;
1152 u32 led_reg, led_mode;
1155 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1157 /* Get LED link active from the LEDCTL register */
1158 for (i = 0; i < 4; i++) {
1159 led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i);
1161 if ((led_mode & IXGBE_LED_MODE_MASK_BASE) ==
1162 IXGBE_LED_LINK_ACTIVE) {
1163 mac->led_link_act = i;
1164 return IXGBE_SUCCESS;
1169 * If LEDCTL register does not have the LED link active set, then use
1170 * known MAC defaults.
1172 switch (hw->mac.type) {
1173 case ixgbe_mac_X550EM_a:
1174 case ixgbe_mac_X550EM_x:
1175 mac->led_link_act = 1;
1178 mac->led_link_act = 2;
1180 return IXGBE_SUCCESS;
1184 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1185 * @hw: pointer to hardware structure
1186 * @index: led number to turn on
1188 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1190 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1192 DEBUGFUNC("ixgbe_led_on_generic");
1195 return IXGBE_ERR_PARAM;
1197 /* To turn on the LED, set mode to ON. */
1198 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1199 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
1200 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1201 IXGBE_WRITE_FLUSH(hw);
1203 return IXGBE_SUCCESS;
1207 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1208 * @hw: pointer to hardware structure
1209 * @index: led number to turn off
1211 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1213 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1215 DEBUGFUNC("ixgbe_led_off_generic");
1218 return IXGBE_ERR_PARAM;
1220 /* To turn off the LED, set mode to OFF. */
1221 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1222 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
1223 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1224 IXGBE_WRITE_FLUSH(hw);
1226 return IXGBE_SUCCESS;
1230 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1231 * @hw: pointer to hardware structure
1233 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1234 * ixgbe_hw struct in order to set up EEPROM access.
1236 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1238 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1242 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
1244 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1245 eeprom->type = ixgbe_eeprom_none;
1246 /* Set default semaphore delay to 10ms which is a well
1248 eeprom->semaphore_delay = 10;
1249 /* Clear EEPROM page size, it will be initialized as needed */
1250 eeprom->word_page_size = 0;
1253 * Check for EEPROM present first.
1254 * If not present leave as none
1256 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1257 if (eec & IXGBE_EEC_PRES) {
1258 eeprom->type = ixgbe_eeprom_spi;
1261 * SPI EEPROM is assumed here. This code would need to
1262 * change if a future EEPROM is not SPI.
1264 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1265 IXGBE_EEC_SIZE_SHIFT);
1266 eeprom->word_size = 1 << (eeprom_size +
1267 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1270 if (eec & IXGBE_EEC_ADDR_SIZE)
1271 eeprom->address_bits = 16;
1273 eeprom->address_bits = 8;
1274 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
1275 "%d\n", eeprom->type, eeprom->word_size,
1276 eeprom->address_bits);
1279 return IXGBE_SUCCESS;
1283 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1284 * @hw: pointer to hardware structure
1285 * @offset: offset within the EEPROM to write
1286 * @words: number of word(s)
1287 * @data: 16 bit word(s) to write to EEPROM
1289 * Reads 16 bit word(s) from EEPROM through bit-bang method
1291 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1292 u16 words, u16 *data)
1294 s32 status = IXGBE_SUCCESS;
1297 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
1299 hw->eeprom.ops.init_params(hw);
1302 status = IXGBE_ERR_INVALID_ARGUMENT;
1306 if (offset + words > hw->eeprom.word_size) {
1307 status = IXGBE_ERR_EEPROM;
1312 * The EEPROM page size cannot be queried from the chip. We do lazy
1313 * initialization. It is worth to do that when we write large buffer.
1315 if ((hw->eeprom.word_page_size == 0) &&
1316 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
1317 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1320 * We cannot hold synchronization semaphores for too long
1321 * to avoid other entity starvation. However it is more efficient
1322 * to read in bursts than synchronizing access for each word.
1324 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1325 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1326 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1327 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1330 if (status != IXGBE_SUCCESS)
1339 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1340 * @hw: pointer to hardware structure
1341 * @offset: offset within the EEPROM to be written to
1342 * @words: number of word(s)
1343 * @data: 16 bit word(s) to be written to the EEPROM
1345 * If ixgbe_eeprom_update_checksum is not called after this function, the
1346 * EEPROM will most likely contain an invalid checksum.
1348 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1349 u16 words, u16 *data)
1355 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1357 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1359 /* Prepare the EEPROM for writing */
1360 status = ixgbe_acquire_eeprom(hw);
1362 if (status == IXGBE_SUCCESS) {
1363 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1364 ixgbe_release_eeprom(hw);
1365 status = IXGBE_ERR_EEPROM;
1369 if (status == IXGBE_SUCCESS) {
1370 for (i = 0; i < words; i++) {
1371 ixgbe_standby_eeprom(hw);
1373 /* Send the WRITE ENABLE command (8 bit opcode ) */
1374 ixgbe_shift_out_eeprom_bits(hw,
1375 IXGBE_EEPROM_WREN_OPCODE_SPI,
1376 IXGBE_EEPROM_OPCODE_BITS);
1378 ixgbe_standby_eeprom(hw);
1381 * Some SPI eeproms use the 8th address bit embedded
1384 if ((hw->eeprom.address_bits == 8) &&
1385 ((offset + i) >= 128))
1386 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1388 /* Send the Write command (8-bit opcode + addr) */
1389 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1390 IXGBE_EEPROM_OPCODE_BITS);
1391 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1392 hw->eeprom.address_bits);
1394 page_size = hw->eeprom.word_page_size;
1396 /* Send the data in burst via SPI*/
1399 word = (word >> 8) | (word << 8);
1400 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1405 /* do not wrap around page */
1406 if (((offset + i) & (page_size - 1)) ==
1409 } while (++i < words);
1411 ixgbe_standby_eeprom(hw);
1414 /* Done with writing - release the EEPROM */
1415 ixgbe_release_eeprom(hw);
1422 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1423 * @hw: pointer to hardware structure
1424 * @offset: offset within the EEPROM to be written to
1425 * @data: 16 bit word to be written to the EEPROM
1427 * If ixgbe_eeprom_update_checksum is not called after this function, the
1428 * EEPROM will most likely contain an invalid checksum.
1430 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1434 DEBUGFUNC("ixgbe_write_eeprom_generic");
1436 hw->eeprom.ops.init_params(hw);
1438 if (offset >= hw->eeprom.word_size) {
1439 status = IXGBE_ERR_EEPROM;
1443 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1450 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1451 * @hw: pointer to hardware structure
1452 * @offset: offset within the EEPROM to be read
1453 * @data: read 16 bit words(s) from EEPROM
1454 * @words: number of word(s)
1456 * Reads 16 bit word(s) from EEPROM through bit-bang method
1458 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1459 u16 words, u16 *data)
1461 s32 status = IXGBE_SUCCESS;
1464 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1466 hw->eeprom.ops.init_params(hw);
1469 status = IXGBE_ERR_INVALID_ARGUMENT;
1473 if (offset + words > hw->eeprom.word_size) {
1474 status = IXGBE_ERR_EEPROM;
1479 * We cannot hold synchronization semaphores for too long
1480 * to avoid other entity starvation. However it is more efficient
1481 * to read in bursts than synchronizing access for each word.
1483 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1484 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1485 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1487 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1490 if (status != IXGBE_SUCCESS)
1499 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1500 * @hw: pointer to hardware structure
1501 * @offset: offset within the EEPROM to be read
1502 * @words: number of word(s)
1503 * @data: read 16 bit word(s) from EEPROM
1505 * Reads 16 bit word(s) from EEPROM through bit-bang method
1507 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1508 u16 words, u16 *data)
1512 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1515 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1517 /* Prepare the EEPROM for reading */
1518 status = ixgbe_acquire_eeprom(hw);
1520 if (status == IXGBE_SUCCESS) {
1521 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1522 ixgbe_release_eeprom(hw);
1523 status = IXGBE_ERR_EEPROM;
1527 if (status == IXGBE_SUCCESS) {
1528 for (i = 0; i < words; i++) {
1529 ixgbe_standby_eeprom(hw);
1531 * Some SPI eeproms use the 8th address bit embedded
1534 if ((hw->eeprom.address_bits == 8) &&
1535 ((offset + i) >= 128))
1536 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1538 /* Send the READ command (opcode + addr) */
1539 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1540 IXGBE_EEPROM_OPCODE_BITS);
1541 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1542 hw->eeprom.address_bits);
1544 /* Read the data. */
1545 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1546 data[i] = (word_in >> 8) | (word_in << 8);
1549 /* End this read operation */
1550 ixgbe_release_eeprom(hw);
1557 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1558 * @hw: pointer to hardware structure
1559 * @offset: offset within the EEPROM to be read
1560 * @data: read 16 bit value from EEPROM
1562 * Reads 16 bit value from EEPROM through bit-bang method
1564 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1569 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1571 hw->eeprom.ops.init_params(hw);
1573 if (offset >= hw->eeprom.word_size) {
1574 status = IXGBE_ERR_EEPROM;
1578 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1585 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1586 * @hw: pointer to hardware structure
1587 * @offset: offset of word in the EEPROM to read
1588 * @words: number of word(s)
1589 * @data: 16 bit word(s) from the EEPROM
1591 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1593 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1594 u16 words, u16 *data)
1597 s32 status = IXGBE_SUCCESS;
1600 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1602 hw->eeprom.ops.init_params(hw);
1605 status = IXGBE_ERR_INVALID_ARGUMENT;
1606 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1610 if (offset >= hw->eeprom.word_size) {
1611 status = IXGBE_ERR_EEPROM;
1612 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1616 for (i = 0; i < words; i++) {
1617 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1618 IXGBE_EEPROM_RW_REG_START;
1620 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1621 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1623 if (status == IXGBE_SUCCESS) {
1624 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1625 IXGBE_EEPROM_RW_REG_DATA);
1627 DEBUGOUT("Eeprom read timed out\n");
1636 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1637 * @hw: pointer to hardware structure
1638 * @offset: offset within the EEPROM to be used as a scratch pad
1640 * Discover EEPROM page size by writing marching data at given offset.
1641 * This function is called only when we are writing a new large buffer
1642 * at given offset so the data would be overwritten anyway.
1644 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1647 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1648 s32 status = IXGBE_SUCCESS;
1651 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1653 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1656 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1657 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1658 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1659 hw->eeprom.word_page_size = 0;
1660 if (status != IXGBE_SUCCESS)
1663 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1664 if (status != IXGBE_SUCCESS)
1668 * When writing in burst more than the actual page size
1669 * EEPROM address wraps around current page.
1671 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1673 DEBUGOUT1("Detected EEPROM page size = %d words.",
1674 hw->eeprom.word_page_size);
1680 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1681 * @hw: pointer to hardware structure
1682 * @offset: offset of word in the EEPROM to read
1683 * @data: word read from the EEPROM
1685 * Reads a 16 bit word from the EEPROM using the EERD register.
1687 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1689 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1693 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1694 * @hw: pointer to hardware structure
1695 * @offset: offset of word in the EEPROM to write
1696 * @words: number of word(s)
1697 * @data: word(s) write to the EEPROM
1699 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1701 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1702 u16 words, u16 *data)
1705 s32 status = IXGBE_SUCCESS;
1708 DEBUGFUNC("ixgbe_write_eewr_generic");
1710 hw->eeprom.ops.init_params(hw);
1713 status = IXGBE_ERR_INVALID_ARGUMENT;
1714 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1718 if (offset >= hw->eeprom.word_size) {
1719 status = IXGBE_ERR_EEPROM;
1720 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1724 for (i = 0; i < words; i++) {
1725 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1726 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1727 IXGBE_EEPROM_RW_REG_START;
1729 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1730 if (status != IXGBE_SUCCESS) {
1731 DEBUGOUT("Eeprom write EEWR timed out\n");
1735 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1737 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1738 if (status != IXGBE_SUCCESS) {
1739 DEBUGOUT("Eeprom write EEWR timed out\n");
1749 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1750 * @hw: pointer to hardware structure
1751 * @offset: offset of word in the EEPROM to write
1752 * @data: word write to the EEPROM
1754 * Write a 16 bit word to the EEPROM using the EEWR register.
1756 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1758 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1762 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1763 * @hw: pointer to hardware structure
1764 * @ee_reg: EEPROM flag for polling
1766 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1767 * read or write is done respectively.
1769 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1773 s32 status = IXGBE_ERR_EEPROM;
1775 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1777 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1778 if (ee_reg == IXGBE_NVM_POLL_READ)
1779 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1781 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1783 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1784 status = IXGBE_SUCCESS;
1790 if (i == IXGBE_EERD_EEWR_ATTEMPTS)
1791 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1792 "EEPROM read/write done polling timed out");
1798 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1799 * @hw: pointer to hardware structure
1801 * Prepares EEPROM for access using bit-bang method. This function should
1802 * be called before issuing a command to the EEPROM.
1804 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1806 s32 status = IXGBE_SUCCESS;
1810 DEBUGFUNC("ixgbe_acquire_eeprom");
1812 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1814 status = IXGBE_ERR_SWFW_SYNC;
1816 if (status == IXGBE_SUCCESS) {
1817 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1819 /* Request EEPROM Access */
1820 eec |= IXGBE_EEC_REQ;
1821 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1823 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1824 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1825 if (eec & IXGBE_EEC_GNT)
1830 /* Release if grant not acquired */
1831 if (!(eec & IXGBE_EEC_GNT)) {
1832 eec &= ~IXGBE_EEC_REQ;
1833 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1834 DEBUGOUT("Could not acquire EEPROM grant\n");
1836 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1837 status = IXGBE_ERR_EEPROM;
1840 /* Setup EEPROM for Read/Write */
1841 if (status == IXGBE_SUCCESS) {
1842 /* Clear CS and SK */
1843 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1844 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1845 IXGBE_WRITE_FLUSH(hw);
1853 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1854 * @hw: pointer to hardware structure
1856 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1858 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1860 s32 status = IXGBE_ERR_EEPROM;
1865 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1868 /* Get SMBI software semaphore between device drivers first */
1869 for (i = 0; i < timeout; i++) {
1871 * If the SMBI bit is 0 when we read it, then the bit will be
1872 * set and we have the semaphore
1874 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1875 if (!(swsm & IXGBE_SWSM_SMBI)) {
1876 status = IXGBE_SUCCESS;
1883 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1886 * this release is particularly important because our attempts
1887 * above to get the semaphore may have succeeded, and if there
1888 * was a timeout, we should unconditionally clear the semaphore
1889 * bits to free the driver to make progress
1891 ixgbe_release_eeprom_semaphore(hw);
1896 * If the SMBI bit is 0 when we read it, then the bit will be
1897 * set and we have the semaphore
1899 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1900 if (!(swsm & IXGBE_SWSM_SMBI))
1901 status = IXGBE_SUCCESS;
1904 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1905 if (status == IXGBE_SUCCESS) {
1906 for (i = 0; i < timeout; i++) {
1907 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1909 /* Set the SW EEPROM semaphore bit to request access */
1910 swsm |= IXGBE_SWSM_SWESMBI;
1911 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
1914 * If we set the bit successfully then we got the
1917 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1918 if (swsm & IXGBE_SWSM_SWESMBI)
1925 * Release semaphores and return error if SW EEPROM semaphore
1926 * was not granted because we don't have access to the EEPROM
1929 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1930 "SWESMBI Software EEPROM semaphore not granted.\n");
1931 ixgbe_release_eeprom_semaphore(hw);
1932 status = IXGBE_ERR_EEPROM;
1935 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1936 "Software semaphore SMBI between device drivers "
1944 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1945 * @hw: pointer to hardware structure
1947 * This function clears hardware semaphore bits.
1949 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1953 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1955 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1957 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1958 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1959 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1960 IXGBE_WRITE_FLUSH(hw);
1964 * ixgbe_ready_eeprom - Polls for EEPROM ready
1965 * @hw: pointer to hardware structure
1967 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1969 s32 status = IXGBE_SUCCESS;
1973 DEBUGFUNC("ixgbe_ready_eeprom");
1976 * Read "Status Register" repeatedly until the LSB is cleared. The
1977 * EEPROM will signal that the command has been completed by clearing
1978 * bit 0 of the internal status register. If it's not cleared within
1979 * 5 milliseconds, then error out.
1981 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1982 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1983 IXGBE_EEPROM_OPCODE_BITS);
1984 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1985 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1989 ixgbe_standby_eeprom(hw);
1993 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1994 * devices (and only 0-5mSec on 5V devices)
1996 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1997 DEBUGOUT("SPI EEPROM Status error\n");
1998 status = IXGBE_ERR_EEPROM;
2005 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
2006 * @hw: pointer to hardware structure
2008 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
2012 DEBUGFUNC("ixgbe_standby_eeprom");
2014 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2016 /* Toggle CS to flush commands */
2017 eec |= IXGBE_EEC_CS;
2018 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2019 IXGBE_WRITE_FLUSH(hw);
2021 eec &= ~IXGBE_EEC_CS;
2022 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2023 IXGBE_WRITE_FLUSH(hw);
2028 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
2029 * @hw: pointer to hardware structure
2030 * @data: data to send to the EEPROM
2031 * @count: number of bits to shift out
2033 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
2040 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
2042 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2045 * Mask is used to shift "count" bits of "data" out to the EEPROM
2046 * one bit at a time. Determine the starting bit based on count
2048 mask = 0x01 << (count - 1);
2050 for (i = 0; i < count; i++) {
2052 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
2053 * "1", and then raising and then lowering the clock (the SK
2054 * bit controls the clock input to the EEPROM). A "0" is
2055 * shifted out to the EEPROM by setting "DI" to "0" and then
2056 * raising and then lowering the clock.
2059 eec |= IXGBE_EEC_DI;
2061 eec &= ~IXGBE_EEC_DI;
2063 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2064 IXGBE_WRITE_FLUSH(hw);
2068 ixgbe_raise_eeprom_clk(hw, &eec);
2069 ixgbe_lower_eeprom_clk(hw, &eec);
2072 * Shift mask to signify next bit of data to shift in to the
2078 /* We leave the "DI" bit set to "0" when we leave this routine. */
2079 eec &= ~IXGBE_EEC_DI;
2080 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2081 IXGBE_WRITE_FLUSH(hw);
2085 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
2086 * @hw: pointer to hardware structure
2088 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
2094 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
2097 * In order to read a register from the EEPROM, we need to shift
2098 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
2099 * the clock input to the EEPROM (setting the SK bit), and then reading
2100 * the value of the "DO" bit. During this "shifting in" process the
2101 * "DI" bit should always be clear.
2103 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2105 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
2107 for (i = 0; i < count; i++) {
2109 ixgbe_raise_eeprom_clk(hw, &eec);
2111 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2113 eec &= ~(IXGBE_EEC_DI);
2114 if (eec & IXGBE_EEC_DO)
2117 ixgbe_lower_eeprom_clk(hw, &eec);
2124 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
2125 * @hw: pointer to hardware structure
2126 * @eec: EEC register's current value
2128 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2130 DEBUGFUNC("ixgbe_raise_eeprom_clk");
2133 * Raise the clock input to the EEPROM
2134 * (setting the SK bit), then delay
2136 *eec = *eec | IXGBE_EEC_SK;
2137 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2138 IXGBE_WRITE_FLUSH(hw);
2143 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2144 * @hw: pointer to hardware structure
2145 * @eecd: EECD's current value
2147 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2149 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2152 * Lower the clock input to the EEPROM (clearing the SK bit), then
2155 *eec = *eec & ~IXGBE_EEC_SK;
2156 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2157 IXGBE_WRITE_FLUSH(hw);
2162 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2163 * @hw: pointer to hardware structure
2165 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2169 DEBUGFUNC("ixgbe_release_eeprom");
2171 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2173 eec |= IXGBE_EEC_CS; /* Pull CS high */
2174 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
2176 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2177 IXGBE_WRITE_FLUSH(hw);
2181 /* Stop requesting EEPROM access */
2182 eec &= ~IXGBE_EEC_REQ;
2183 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2185 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2187 /* Delay before attempt to obtain semaphore again to allow FW access */
2188 msec_delay(hw->eeprom.semaphore_delay);
2192 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2193 * @hw: pointer to hardware structure
2195 * Returns a negative error code on error, or the 16-bit checksum
2197 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2206 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
2208 /* Include 0x0-0x3F in the checksum */
2209 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
2210 if (hw->eeprom.ops.read(hw, i, &word)) {
2211 DEBUGOUT("EEPROM read failed\n");
2212 return IXGBE_ERR_EEPROM;
2217 /* Include all data from pointers except for the fw pointer */
2218 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
2219 if (hw->eeprom.ops.read(hw, i, &pointer)) {
2220 DEBUGOUT("EEPROM read failed\n");
2221 return IXGBE_ERR_EEPROM;
2224 /* If the pointer seems invalid */
2225 if (pointer == 0xFFFF || pointer == 0)
2228 if (hw->eeprom.ops.read(hw, pointer, &length)) {
2229 DEBUGOUT("EEPROM read failed\n");
2230 return IXGBE_ERR_EEPROM;
2233 if (length == 0xFFFF || length == 0)
2236 for (j = pointer + 1; j <= pointer + length; j++) {
2237 if (hw->eeprom.ops.read(hw, j, &word)) {
2238 DEBUGOUT("EEPROM read failed\n");
2239 return IXGBE_ERR_EEPROM;
2245 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2247 return (s32)checksum;
2251 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2252 * @hw: pointer to hardware structure
2253 * @checksum_val: calculated checksum
2255 * Performs checksum calculation and validates the EEPROM checksum. If the
2256 * caller does not need checksum_val, the value can be NULL.
2258 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2263 u16 read_checksum = 0;
2265 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
2267 /* Read the first word from the EEPROM. If this times out or fails, do
2268 * not continue or we could be in for a very long wait while every
2271 status = hw->eeprom.ops.read(hw, 0, &checksum);
2273 DEBUGOUT("EEPROM read failed\n");
2277 status = hw->eeprom.ops.calc_checksum(hw);
2281 checksum = (u16)(status & 0xffff);
2283 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2285 DEBUGOUT("EEPROM read failed\n");
2289 /* Verify read checksum from EEPROM is the same as
2290 * calculated checksum
2292 if (read_checksum != checksum)
2293 status = IXGBE_ERR_EEPROM_CHECKSUM;
2295 /* If the user cares, return the calculated checksum */
2297 *checksum_val = checksum;
2303 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2304 * @hw: pointer to hardware structure
2306 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2311 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
2313 /* Read the first word from the EEPROM. If this times out or fails, do
2314 * not continue or we could be in for a very long wait while every
2317 status = hw->eeprom.ops.read(hw, 0, &checksum);
2319 DEBUGOUT("EEPROM read failed\n");
2323 status = hw->eeprom.ops.calc_checksum(hw);
2327 checksum = (u16)(status & 0xffff);
2329 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
2335 * ixgbe_validate_mac_addr - Validate MAC address
2336 * @mac_addr: pointer to MAC address.
2338 * Tests a MAC address to ensure it is a valid Individual Address.
2340 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
2342 s32 status = IXGBE_SUCCESS;
2344 DEBUGFUNC("ixgbe_validate_mac_addr");
2346 /* Make sure it is not a multicast address */
2347 if (IXGBE_IS_MULTICAST(mac_addr)) {
2348 status = IXGBE_ERR_INVALID_MAC_ADDR;
2349 /* Not a broadcast address */
2350 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
2351 status = IXGBE_ERR_INVALID_MAC_ADDR;
2352 /* Reject the zero address */
2353 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
2354 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
2355 status = IXGBE_ERR_INVALID_MAC_ADDR;
2361 * ixgbe_set_rar_generic - Set Rx address register
2362 * @hw: pointer to hardware structure
2363 * @index: Receive address register to write
2364 * @addr: Address to put into receive address register
2365 * @vmdq: VMDq "set" or "pool" index
2366 * @enable_addr: set flag that address is active
2368 * Puts an ethernet address into a receive address register.
2370 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2373 u32 rar_low, rar_high;
2374 u32 rar_entries = hw->mac.num_rar_entries;
2376 DEBUGFUNC("ixgbe_set_rar_generic");
2378 /* Make sure we are using a valid rar index range */
2379 if (index >= rar_entries) {
2380 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2381 "RAR index %d is out of range.\n", index);
2382 return IXGBE_ERR_INVALID_ARGUMENT;
2385 /* setup VMDq pool selection before this RAR gets enabled */
2386 hw->mac.ops.set_vmdq(hw, index, vmdq);
2389 * HW expects these in little endian so we reverse the byte
2390 * order from network order (big endian) to little endian
2392 rar_low = ((u32)addr[0] |
2393 ((u32)addr[1] << 8) |
2394 ((u32)addr[2] << 16) |
2395 ((u32)addr[3] << 24));
2397 * Some parts put the VMDq setting in the extra RAH bits,
2398 * so save everything except the lower 16 bits that hold part
2399 * of the address and the address valid bit.
2401 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2402 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2403 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2405 if (enable_addr != 0)
2406 rar_high |= IXGBE_RAH_AV;
2408 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2409 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2411 return IXGBE_SUCCESS;
2415 * ixgbe_clear_rar_generic - Remove Rx address register
2416 * @hw: pointer to hardware structure
2417 * @index: Receive address register to write
2419 * Clears an ethernet address from a receive address register.
2421 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2424 u32 rar_entries = hw->mac.num_rar_entries;
2426 DEBUGFUNC("ixgbe_clear_rar_generic");
2428 /* Make sure we are using a valid rar index range */
2429 if (index >= rar_entries) {
2430 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2431 "RAR index %d is out of range.\n", index);
2432 return IXGBE_ERR_INVALID_ARGUMENT;
2436 * Some parts put the VMDq setting in the extra RAH bits,
2437 * so save everything except the lower 16 bits that hold part
2438 * of the address and the address valid bit.
2440 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2441 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2443 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2444 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2446 /* clear VMDq pool/queue selection for this RAR */
2447 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2449 return IXGBE_SUCCESS;
2453 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2454 * @hw: pointer to hardware structure
2456 * Places the MAC address in receive address register 0 and clears the rest
2457 * of the receive address registers. Clears the multicast table. Assumes
2458 * the receiver is in reset when the routine is called.
2460 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2463 u32 rar_entries = hw->mac.num_rar_entries;
2465 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2468 * If the current mac address is valid, assume it is a software override
2469 * to the permanent address.
2470 * Otherwise, use the permanent address from the eeprom.
2472 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2473 IXGBE_ERR_INVALID_MAC_ADDR) {
2474 /* Get the MAC address from the RAR0 for later reference */
2475 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2477 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2478 hw->mac.addr[0], hw->mac.addr[1],
2480 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2481 hw->mac.addr[4], hw->mac.addr[5]);
2483 /* Setup the receive address. */
2484 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2485 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2486 hw->mac.addr[0], hw->mac.addr[1],
2488 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2489 hw->mac.addr[4], hw->mac.addr[5]);
2491 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2494 /* clear VMDq pool/queue selection for RAR 0 */
2495 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2497 hw->addr_ctrl.overflow_promisc = 0;
2499 hw->addr_ctrl.rar_used_count = 1;
2501 /* Zero out the other receive addresses. */
2502 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2503 for (i = 1; i < rar_entries; i++) {
2504 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2505 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2509 hw->addr_ctrl.mta_in_use = 0;
2510 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2512 DEBUGOUT(" Clearing MTA\n");
2513 for (i = 0; i < hw->mac.mcft_size; i++)
2514 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2516 ixgbe_init_uta_tables(hw);
2518 return IXGBE_SUCCESS;
2522 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2523 * @hw: pointer to hardware structure
2524 * @addr: new address
2526 * Adds it to unused receive address register or goes into promiscuous mode.
2528 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2530 u32 rar_entries = hw->mac.num_rar_entries;
2533 DEBUGFUNC("ixgbe_add_uc_addr");
2535 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2536 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2539 * Place this address in the RAR if there is room,
2540 * else put the controller into promiscuous mode
2542 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2543 rar = hw->addr_ctrl.rar_used_count;
2544 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2545 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2546 hw->addr_ctrl.rar_used_count++;
2548 hw->addr_ctrl.overflow_promisc++;
2551 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2555 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2556 * @hw: pointer to hardware structure
2557 * @addr_list: the list of new addresses
2558 * @addr_count: number of addresses
2559 * @next: iterator function to walk the address list
2561 * The given list replaces any existing list. Clears the secondary addrs from
2562 * receive address registers. Uses unused receive address registers for the
2563 * first secondary addresses, and falls back to promiscuous mode as needed.
2565 * Drivers using secondary unicast addresses must set user_set_promisc when
2566 * manually putting the device into promiscuous mode.
2568 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2569 u32 addr_count, ixgbe_mc_addr_itr next)
2573 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2578 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2581 * Clear accounting of old secondary address list,
2582 * don't count RAR[0]
2584 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2585 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2586 hw->addr_ctrl.overflow_promisc = 0;
2588 /* Zero out the other receive addresses */
2589 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2590 for (i = 0; i < uc_addr_in_use; i++) {
2591 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2592 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2595 /* Add the new addresses */
2596 for (i = 0; i < addr_count; i++) {
2597 DEBUGOUT(" Adding the secondary addresses:\n");
2598 addr = next(hw, &addr_list, &vmdq);
2599 ixgbe_add_uc_addr(hw, addr, vmdq);
2602 if (hw->addr_ctrl.overflow_promisc) {
2603 /* enable promisc if not already in overflow or set by user */
2604 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2605 DEBUGOUT(" Entering address overflow promisc mode\n");
2606 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2607 fctrl |= IXGBE_FCTRL_UPE;
2608 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2611 /* only disable if set by overflow, not by user */
2612 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2613 DEBUGOUT(" Leaving address overflow promisc mode\n");
2614 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2615 fctrl &= ~IXGBE_FCTRL_UPE;
2616 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2620 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2621 return IXGBE_SUCCESS;
2625 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2626 * @hw: pointer to hardware structure
2627 * @mc_addr: the multicast address
2629 * Extracts the 12 bits, from a multicast address, to determine which
2630 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2631 * incoming rx multicast addresses, to determine the bit-vector to check in
2632 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2633 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2634 * to mc_filter_type.
2636 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2640 DEBUGFUNC("ixgbe_mta_vector");
2642 switch (hw->mac.mc_filter_type) {
2643 case 0: /* use bits [47:36] of the address */
2644 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2646 case 1: /* use bits [46:35] of the address */
2647 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2649 case 2: /* use bits [45:34] of the address */
2650 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2652 case 3: /* use bits [43:32] of the address */
2653 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2655 default: /* Invalid mc_filter_type */
2656 DEBUGOUT("MC filter type param set incorrectly\n");
2661 /* vector can only be 12-bits or boundary will be exceeded */
2667 * ixgbe_set_mta - Set bit-vector in multicast table
2668 * @hw: pointer to hardware structure
2669 * @hash_value: Multicast address hash value
2671 * Sets the bit-vector in the multicast table.
2673 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2679 DEBUGFUNC("ixgbe_set_mta");
2681 hw->addr_ctrl.mta_in_use++;
2683 vector = ixgbe_mta_vector(hw, mc_addr);
2684 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2687 * The MTA is a register array of 128 32-bit registers. It is treated
2688 * like an array of 4096 bits. We want to set bit
2689 * BitArray[vector_value]. So we figure out what register the bit is
2690 * in, read it, OR in the new bit, then write back the new value. The
2691 * register is determined by the upper 7 bits of the vector value and
2692 * the bit within that register are determined by the lower 5 bits of
2695 vector_reg = (vector >> 5) & 0x7F;
2696 vector_bit = vector & 0x1F;
2697 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2701 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2702 * @hw: pointer to hardware structure
2703 * @mc_addr_list: the list of new multicast addresses
2704 * @mc_addr_count: number of addresses
2705 * @next: iterator function to walk the multicast address list
2706 * @clear: flag, when set clears the table beforehand
2708 * When the clear flag is set, the given list replaces any existing list.
2709 * Hashes the given addresses into the multicast table.
2711 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2712 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2718 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2721 * Set the new number of MC addresses that we are being requested to
2724 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2725 hw->addr_ctrl.mta_in_use = 0;
2727 /* Clear mta_shadow */
2729 DEBUGOUT(" Clearing MTA\n");
2730 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2733 /* Update mta_shadow */
2734 for (i = 0; i < mc_addr_count; i++) {
2735 DEBUGOUT(" Adding the multicast addresses:\n");
2736 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2740 for (i = 0; i < hw->mac.mcft_size; i++)
2741 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2742 hw->mac.mta_shadow[i]);
2744 if (hw->addr_ctrl.mta_in_use > 0)
2745 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2746 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2748 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2749 return IXGBE_SUCCESS;
2753 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2754 * @hw: pointer to hardware structure
2756 * Enables multicast address in RAR and the use of the multicast hash table.
2758 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2760 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2762 DEBUGFUNC("ixgbe_enable_mc_generic");
2764 if (a->mta_in_use > 0)
2765 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2766 hw->mac.mc_filter_type);
2768 return IXGBE_SUCCESS;
2772 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2773 * @hw: pointer to hardware structure
2775 * Disables multicast address in RAR and the use of the multicast hash table.
2777 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2779 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2781 DEBUGFUNC("ixgbe_disable_mc_generic");
2783 if (a->mta_in_use > 0)
2784 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2786 return IXGBE_SUCCESS;
2790 * ixgbe_fc_enable_generic - Enable flow control
2791 * @hw: pointer to hardware structure
2793 * Enable flow control according to the current settings.
2795 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2797 s32 ret_val = IXGBE_SUCCESS;
2798 u32 mflcn_reg, fccfg_reg;
2803 DEBUGFUNC("ixgbe_fc_enable_generic");
2805 /* Validate the water mark configuration */
2806 if (!hw->fc.pause_time) {
2807 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2811 /* Low water mark of zero causes XOFF floods */
2812 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2813 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2814 hw->fc.high_water[i]) {
2815 if (!hw->fc.low_water[i] ||
2816 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2817 DEBUGOUT("Invalid water mark configuration\n");
2818 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2824 /* Negotiate the fc mode to use */
2825 hw->mac.ops.fc_autoneg(hw);
2827 /* Disable any previous flow control settings */
2828 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2829 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2831 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2832 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2835 * The possible values of fc.current_mode are:
2836 * 0: Flow control is completely disabled
2837 * 1: Rx flow control is enabled (we can receive pause frames,
2838 * but not send pause frames).
2839 * 2: Tx flow control is enabled (we can send pause frames but
2840 * we do not support receiving pause frames).
2841 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2844 switch (hw->fc.current_mode) {
2847 * Flow control is disabled by software override or autoneg.
2848 * The code below will actually disable it in the HW.
2851 case ixgbe_fc_rx_pause:
2853 * Rx Flow control is enabled and Tx Flow control is
2854 * disabled by software override. Since there really
2855 * isn't a way to advertise that we are capable of RX
2856 * Pause ONLY, we will advertise that we support both
2857 * symmetric and asymmetric Rx PAUSE. Later, we will
2858 * disable the adapter's ability to send PAUSE frames.
2860 mflcn_reg |= IXGBE_MFLCN_RFCE;
2862 case ixgbe_fc_tx_pause:
2864 * Tx Flow control is enabled, and Rx Flow control is
2865 * disabled by software override.
2867 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2870 /* Flow control (both Rx and Tx) is enabled by SW override. */
2871 mflcn_reg |= IXGBE_MFLCN_RFCE;
2872 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2875 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2876 "Flow control param set incorrectly\n");
2877 ret_val = IXGBE_ERR_CONFIG;
2882 /* Set 802.3x based flow control settings. */
2883 mflcn_reg |= IXGBE_MFLCN_DPF;
2884 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2885 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2888 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2889 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2890 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2891 hw->fc.high_water[i]) {
2892 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2893 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2894 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2896 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2898 * In order to prevent Tx hangs when the internal Tx
2899 * switch is enabled we must set the high water mark
2900 * to the Rx packet buffer size - 24KB. This allows
2901 * the Tx switch to function even under heavy Rx
2904 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2907 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2910 /* Configure pause time (2 TCs per register) */
2911 reg = hw->fc.pause_time * 0x00010001;
2912 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2913 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2915 /* Configure flow control refresh threshold value */
2916 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2923 * ixgbe_negotiate_fc - Negotiate flow control
2924 * @hw: pointer to hardware structure
2925 * @adv_reg: flow control advertised settings
2926 * @lp_reg: link partner's flow control settings
2927 * @adv_sym: symmetric pause bit in advertisement
2928 * @adv_asm: asymmetric pause bit in advertisement
2929 * @lp_sym: symmetric pause bit in link partner advertisement
2930 * @lp_asm: asymmetric pause bit in link partner advertisement
2932 * Find the intersection between advertised settings and link partner's
2933 * advertised settings
2935 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2936 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2938 if ((!(adv_reg)) || (!(lp_reg))) {
2939 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
2940 "Local or link partner's advertised flow control "
2941 "settings are NULL. Local: %x, link partner: %x\n",
2943 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2946 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2948 * Now we need to check if the user selected Rx ONLY
2949 * of pause frames. In this case, we had to advertise
2950 * FULL flow control because we could not advertise RX
2951 * ONLY. Hence, we must now check to see if we need to
2952 * turn OFF the TRANSMISSION of PAUSE frames.
2954 if (hw->fc.requested_mode == ixgbe_fc_full) {
2955 hw->fc.current_mode = ixgbe_fc_full;
2956 DEBUGOUT("Flow Control = FULL.\n");
2958 hw->fc.current_mode = ixgbe_fc_rx_pause;
2959 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2961 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2962 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2963 hw->fc.current_mode = ixgbe_fc_tx_pause;
2964 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2965 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2966 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2967 hw->fc.current_mode = ixgbe_fc_rx_pause;
2968 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2970 hw->fc.current_mode = ixgbe_fc_none;
2971 DEBUGOUT("Flow Control = NONE.\n");
2973 return IXGBE_SUCCESS;
2977 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2978 * @hw: pointer to hardware structure
2980 * Enable flow control according on 1 gig fiber.
2982 STATIC s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2984 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2985 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2988 * On multispeed fiber at 1g, bail out if
2989 * - link is up but AN did not complete, or if
2990 * - link is up and AN completed but timed out
2993 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2994 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2995 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
2996 DEBUGOUT("Auto-Negotiation did not complete or timed out\n");
3000 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
3001 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
3003 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
3004 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
3005 IXGBE_PCS1GANA_ASM_PAUSE,
3006 IXGBE_PCS1GANA_SYM_PAUSE,
3007 IXGBE_PCS1GANA_ASM_PAUSE);
3014 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
3015 * @hw: pointer to hardware structure
3017 * Enable flow control according to IEEE clause 37.
3019 STATIC s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
3021 u32 links2, anlp1_reg, autoc_reg, links;
3022 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3025 * On backplane, bail out if
3026 * - backplane autoneg was not completed, or if
3027 * - we are 82599 and link partner is not AN enabled
3029 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
3030 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
3031 DEBUGOUT("Auto-Negotiation did not complete\n");
3035 if (hw->mac.type == ixgbe_mac_82599EB) {
3036 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
3037 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
3038 DEBUGOUT("Link partner is not AN enabled\n");
3043 * Read the 10g AN autoc and LP ability registers and resolve
3044 * local flow control settings accordingly
3046 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3047 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
3049 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
3050 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
3051 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
3058 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
3059 * @hw: pointer to hardware structure
3061 * Enable flow control according to IEEE clause 37.
3063 STATIC s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
3065 u16 technology_ability_reg = 0;
3066 u16 lp_technology_ability_reg = 0;
3068 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
3069 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3070 &technology_ability_reg);
3071 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
3072 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3073 &lp_technology_ability_reg);
3075 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
3076 (u32)lp_technology_ability_reg,
3077 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
3078 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
3082 * ixgbe_fc_autoneg - Configure flow control
3083 * @hw: pointer to hardware structure
3085 * Compares our advertised flow control capabilities to those advertised by
3086 * our link partner, and determines the proper flow control mode to use.
3088 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
3090 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3091 ixgbe_link_speed speed;
3094 DEBUGFUNC("ixgbe_fc_autoneg");
3097 * AN should have completed when the cable was plugged in.
3098 * Look for reasons to bail out. Bail out if:
3099 * - FC autoneg is disabled, or if
3102 if (hw->fc.disable_fc_autoneg) {
3103 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3104 "Flow control autoneg is disabled");
3108 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3110 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3114 switch (hw->phy.media_type) {
3115 /* Autoneg flow control on fiber adapters */
3116 case ixgbe_media_type_fiber_qsfp:
3117 case ixgbe_media_type_fiber:
3118 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
3119 ret_val = ixgbe_fc_autoneg_fiber(hw);
3122 /* Autoneg flow control on backplane adapters */
3123 case ixgbe_media_type_backplane:
3124 ret_val = ixgbe_fc_autoneg_backplane(hw);
3127 /* Autoneg flow control on copper adapters */
3128 case ixgbe_media_type_copper:
3129 if (ixgbe_device_supports_autoneg_fc(hw))
3130 ret_val = ixgbe_fc_autoneg_copper(hw);
3138 if (ret_val == IXGBE_SUCCESS) {
3139 hw->fc.fc_was_autonegged = true;
3141 hw->fc.fc_was_autonegged = false;
3142 hw->fc.current_mode = hw->fc.requested_mode;
3147 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3148 * @hw: pointer to hardware structure
3150 * System-wide timeout range is encoded in PCIe Device Control2 register.
3152 * Add 10% to specified maximum and return the number of times to poll for
3153 * completion timeout, in units of 100 microsec. Never return less than
3154 * 800 = 80 millisec.
3156 STATIC u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3161 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3162 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
3165 case IXGBE_PCIDEVCTRL2_65_130ms:
3166 pollcnt = 1300; /* 130 millisec */
3168 case IXGBE_PCIDEVCTRL2_260_520ms:
3169 pollcnt = 5200; /* 520 millisec */
3171 case IXGBE_PCIDEVCTRL2_1_2s:
3172 pollcnt = 20000; /* 2 sec */
3174 case IXGBE_PCIDEVCTRL2_4_8s:
3175 pollcnt = 80000; /* 8 sec */
3177 case IXGBE_PCIDEVCTRL2_17_34s:
3178 pollcnt = 34000; /* 34 sec */
3180 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
3181 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
3182 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
3183 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
3185 pollcnt = 800; /* 80 millisec minimum */
3189 /* add 10% to spec maximum */
3190 return (pollcnt * 11) / 10;
3194 * ixgbe_disable_pcie_master - Disable PCI-express master access
3195 * @hw: pointer to hardware structure
3197 * Disables PCI-Express master access and verifies there are no pending
3198 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
3199 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
3200 * is returned signifying master requests disabled.
3202 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
3204 s32 status = IXGBE_SUCCESS;
3208 DEBUGFUNC("ixgbe_disable_pcie_master");
3210 /* Always set this bit to ensure any future transactions are blocked */
3211 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3213 /* Exit if master requests are blocked */
3214 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3215 IXGBE_REMOVED(hw->hw_addr))
3218 /* Poll for master request bit to clear */
3219 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
3221 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3226 * Two consecutive resets are required via CTRL.RST per datasheet
3227 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
3228 * of this need. The first reset prevents new master requests from
3229 * being issued by our device. We then must wait 1usec or more for any
3230 * remaining completions from the PCIe bus to trickle in, and then reset
3231 * again to clear out any effects they may have had on our device.
3233 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
3234 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3236 if (hw->mac.type >= ixgbe_mac_X550)
3240 * Before proceeding, make sure that the PCIe block does not have
3241 * transactions pending.
3243 poll = ixgbe_pcie_timeout_poll(hw);
3244 for (i = 0; i < poll; i++) {
3246 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3247 if (IXGBE_REMOVED(hw->hw_addr))
3249 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3253 ERROR_REPORT1(IXGBE_ERROR_POLLING,
3254 "PCIe transaction pending bit also did not clear.\n");
3255 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
3262 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3263 * @hw: pointer to hardware structure
3264 * @mask: Mask to specify which semaphore to acquire
3266 * Acquires the SWFW semaphore through the GSSR register for the specified
3267 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3269 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3273 u32 fwmask = mask << 5;
3277 DEBUGFUNC("ixgbe_acquire_swfw_sync");
3279 for (i = 0; i < timeout; i++) {
3281 * SW NVM semaphore bit is used for access to all
3282 * SW_FW_SYNC bits (not just NVM)
3284 if (ixgbe_get_eeprom_semaphore(hw))
3285 return IXGBE_ERR_SWFW_SYNC;
3287 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3288 if (!(gssr & (fwmask | swmask))) {
3290 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3291 ixgbe_release_eeprom_semaphore(hw);
3292 return IXGBE_SUCCESS;
3294 /* Resource is currently in use by FW or SW */
3295 ixgbe_release_eeprom_semaphore(hw);
3300 /* If time expired clear the bits holding the lock and retry */
3301 if (gssr & (fwmask | swmask))
3302 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
3305 return IXGBE_ERR_SWFW_SYNC;
3309 * ixgbe_release_swfw_sync - Release SWFW semaphore
3310 * @hw: pointer to hardware structure
3311 * @mask: Mask to specify which semaphore to release
3313 * Releases the SWFW semaphore through the GSSR register for the specified
3314 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3316 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3321 DEBUGFUNC("ixgbe_release_swfw_sync");
3323 ixgbe_get_eeprom_semaphore(hw);
3325 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3327 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3329 ixgbe_release_eeprom_semaphore(hw);
3333 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3334 * @hw: pointer to hardware structure
3336 * Stops the receive data path and waits for the HW to internally empty
3337 * the Rx security block
3339 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3341 #define IXGBE_MAX_SECRX_POLL 40
3346 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
3349 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3350 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
3351 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3352 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
3353 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3354 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
3357 /* Use interrupt-safe sleep just in case */
3361 /* For informational purposes only */
3362 if (i >= IXGBE_MAX_SECRX_POLL)
3363 DEBUGOUT("Rx unit being enabled before security "
3364 "path fully disabled. Continuing with init.\n");
3366 return IXGBE_SUCCESS;
3370 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3371 * @hw: pointer to hardware structure
3372 * @reg_val: Value we read from AUTOC
3374 * The default case requires no protection so just to the register read.
3376 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3379 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3380 return IXGBE_SUCCESS;
3384 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
3385 * @hw: pointer to hardware structure
3386 * @reg_val: value to write to AUTOC
3387 * @locked: bool to indicate whether the SW/FW lock was already taken by
3390 * The default case requires no protection so just to the register write.
3392 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
3394 UNREFERENCED_1PARAMETER(locked);
3396 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
3397 return IXGBE_SUCCESS;
3401 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3402 * @hw: pointer to hardware structure
3404 * Enables the receive data path.
3406 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3410 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
3412 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3413 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
3414 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3415 IXGBE_WRITE_FLUSH(hw);
3417 return IXGBE_SUCCESS;
3421 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3422 * @hw: pointer to hardware structure
3423 * @regval: register value to write to RXCTRL
3425 * Enables the Rx DMA unit
3427 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3429 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
3431 if (regval & IXGBE_RXCTRL_RXEN)
3432 ixgbe_enable_rx(hw);
3434 ixgbe_disable_rx(hw);
3436 return IXGBE_SUCCESS;
3440 * ixgbe_blink_led_start_generic - Blink LED based on index.
3441 * @hw: pointer to hardware structure
3442 * @index: led number to blink
3444 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3446 ixgbe_link_speed speed = 0;
3449 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3450 s32 ret_val = IXGBE_SUCCESS;
3451 bool locked = false;
3453 DEBUGFUNC("ixgbe_blink_led_start_generic");
3456 return IXGBE_ERR_PARAM;
3459 * Link must be up to auto-blink the LEDs;
3460 * Force it if link is down.
3462 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3465 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3466 if (ret_val != IXGBE_SUCCESS)
3469 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3470 autoc_reg |= IXGBE_AUTOC_FLU;
3472 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3473 if (ret_val != IXGBE_SUCCESS)
3476 IXGBE_WRITE_FLUSH(hw);
3480 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3481 led_reg |= IXGBE_LED_BLINK(index);
3482 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3483 IXGBE_WRITE_FLUSH(hw);
3490 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3491 * @hw: pointer to hardware structure
3492 * @index: led number to stop blinking
3494 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3497 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3498 s32 ret_val = IXGBE_SUCCESS;
3499 bool locked = false;
3501 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3504 return IXGBE_ERR_PARAM;
3507 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3508 if (ret_val != IXGBE_SUCCESS)
3511 autoc_reg &= ~IXGBE_AUTOC_FLU;
3512 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3514 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3515 if (ret_val != IXGBE_SUCCESS)
3518 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3519 led_reg &= ~IXGBE_LED_BLINK(index);
3520 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3521 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3522 IXGBE_WRITE_FLUSH(hw);
3529 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3530 * @hw: pointer to hardware structure
3531 * @san_mac_offset: SAN MAC address offset
3533 * This function will read the EEPROM location for the SAN MAC address
3534 * pointer, and returns the value at that location. This is used in both
3535 * get and set mac_addr routines.
3537 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3538 u16 *san_mac_offset)
3542 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3545 * First read the EEPROM pointer to see if the MAC addresses are
3548 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3551 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3552 "eeprom at offset %d failed",
3553 IXGBE_SAN_MAC_ADDR_PTR);
3560 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3561 * @hw: pointer to hardware structure
3562 * @san_mac_addr: SAN MAC address
3564 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3565 * per-port, so set_lan_id() must be called before reading the addresses.
3566 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3567 * upon for non-SFP connections, so we must call it here.
3569 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3571 u16 san_mac_data, san_mac_offset;
3575 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3578 * First read the EEPROM pointer to see if the MAC addresses are
3579 * available. If they're not, no point in calling set_lan_id() here.
3581 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3582 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3583 goto san_mac_addr_out;
3585 /* make sure we know which port we need to program */
3586 hw->mac.ops.set_lan_id(hw);
3587 /* apply the port offset to the address offset */
3588 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3589 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3590 for (i = 0; i < 3; i++) {
3591 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3594 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3595 "eeprom read at offset %d failed",
3597 goto san_mac_addr_out;
3599 san_mac_addr[i * 2] = (u8)(san_mac_data);
3600 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3603 return IXGBE_SUCCESS;
3607 * No addresses available in this EEPROM. It's not an
3608 * error though, so just wipe the local address and return.
3610 for (i = 0; i < 6; i++)
3611 san_mac_addr[i] = 0xFF;
3612 return IXGBE_SUCCESS;
3616 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3617 * @hw: pointer to hardware structure
3618 * @san_mac_addr: SAN MAC address
3620 * Write a SAN MAC address to the EEPROM.
3622 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3625 u16 san_mac_data, san_mac_offset;
3628 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3630 /* Look for SAN mac address pointer. If not defined, return */
3631 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3632 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3633 return IXGBE_ERR_NO_SAN_ADDR_PTR;
3635 /* Make sure we know which port we need to write */
3636 hw->mac.ops.set_lan_id(hw);
3637 /* Apply the port offset to the address offset */
3638 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3639 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3641 for (i = 0; i < 3; i++) {
3642 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3643 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3644 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3648 return IXGBE_SUCCESS;
3652 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3653 * @hw: pointer to hardware structure
3655 * Read PCIe configuration space, and get the MSI-X vector count from
3656 * the capabilities table.
3658 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3664 switch (hw->mac.type) {
3665 case ixgbe_mac_82598EB:
3666 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3667 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3669 case ixgbe_mac_82599EB:
3670 case ixgbe_mac_X540:
3671 case ixgbe_mac_X550:
3672 case ixgbe_mac_X550EM_x:
3673 case ixgbe_mac_X550EM_a:
3674 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3675 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3681 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3682 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3683 if (IXGBE_REMOVED(hw->hw_addr))
3685 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3687 /* MSI-X count is zero-based in HW */
3690 if (msix_count > max_msix_count)
3691 msix_count = max_msix_count;
3697 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3698 * @hw: pointer to hardware structure
3699 * @addr: Address to put into receive address register
3700 * @vmdq: VMDq pool to assign
3702 * Puts an ethernet address into a receive address register, or
3703 * finds the rar that it is aleady in; adds to the pool list
3705 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3707 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3708 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3710 u32 rar_low, rar_high;
3711 u32 addr_low, addr_high;
3713 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3715 /* swap bytes for HW little endian */
3716 addr_low = addr[0] | (addr[1] << 8)
3719 addr_high = addr[4] | (addr[5] << 8);
3722 * Either find the mac_id in rar or find the first empty space.
3723 * rar_highwater points to just after the highest currently used
3724 * rar in order to shorten the search. It grows when we add a new
3727 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3728 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3730 if (((IXGBE_RAH_AV & rar_high) == 0)
3731 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3732 first_empty_rar = rar;
3733 } else if ((rar_high & 0xFFFF) == addr_high) {
3734 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3735 if (rar_low == addr_low)
3736 break; /* found it already in the rars */
3740 if (rar < hw->mac.rar_highwater) {
3741 /* already there so just add to the pool bits */
3742 ixgbe_set_vmdq(hw, rar, vmdq);
3743 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3744 /* stick it into first empty RAR slot we found */
3745 rar = first_empty_rar;
3746 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3747 } else if (rar == hw->mac.rar_highwater) {
3748 /* add it to the top of the list and inc the highwater mark */
3749 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3750 hw->mac.rar_highwater++;
3751 } else if (rar >= hw->mac.num_rar_entries) {
3752 return IXGBE_ERR_INVALID_MAC_ADDR;
3756 * If we found rar[0], make sure the default pool bit (we use pool 0)
3757 * remains cleared to be sure default pool packets will get delivered
3760 ixgbe_clear_vmdq(hw, rar, 0);
3766 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3767 * @hw: pointer to hardware struct
3768 * @rar: receive address register index to disassociate
3769 * @vmdq: VMDq pool index to remove from the rar
3771 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3773 u32 mpsar_lo, mpsar_hi;
3774 u32 rar_entries = hw->mac.num_rar_entries;
3776 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3778 /* Make sure we are using a valid rar index range */
3779 if (rar >= rar_entries) {
3780 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3781 "RAR index %d is out of range.\n", rar);
3782 return IXGBE_ERR_INVALID_ARGUMENT;
3785 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3786 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3788 if (IXGBE_REMOVED(hw->hw_addr))
3791 if (!mpsar_lo && !mpsar_hi)
3794 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3796 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3800 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3803 } else if (vmdq < 32) {
3804 mpsar_lo &= ~(1 << vmdq);
3805 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3807 mpsar_hi &= ~(1 << (vmdq - 32));
3808 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3811 /* was that the last pool using this rar? */
3812 if (mpsar_lo == 0 && mpsar_hi == 0 &&
3813 rar != 0 && rar != hw->mac.san_mac_rar_index)
3814 hw->mac.ops.clear_rar(hw, rar);
3816 return IXGBE_SUCCESS;
3820 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3821 * @hw: pointer to hardware struct
3822 * @rar: receive address register index to associate with a VMDq index
3823 * @vmdq: VMDq pool index
3825 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3828 u32 rar_entries = hw->mac.num_rar_entries;
3830 DEBUGFUNC("ixgbe_set_vmdq_generic");
3832 /* Make sure we are using a valid rar index range */
3833 if (rar >= rar_entries) {
3834 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3835 "RAR index %d is out of range.\n", rar);
3836 return IXGBE_ERR_INVALID_ARGUMENT;
3840 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3842 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3844 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3845 mpsar |= 1 << (vmdq - 32);
3846 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3848 return IXGBE_SUCCESS;
3852 * This function should only be involved in the IOV mode.
3853 * In IOV mode, Default pool is next pool after the number of
3854 * VFs advertized and not 0.
3855 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3857 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3858 * @hw: pointer to hardware struct
3859 * @vmdq: VMDq pool index
3861 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3863 u32 rar = hw->mac.san_mac_rar_index;
3865 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3868 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3869 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3871 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3872 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3875 return IXGBE_SUCCESS;
3879 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3880 * @hw: pointer to hardware structure
3882 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3886 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3887 DEBUGOUT(" Clearing UTA\n");
3889 for (i = 0; i < 128; i++)
3890 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3892 return IXGBE_SUCCESS;
3896 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3897 * @hw: pointer to hardware structure
3898 * @vlan: VLAN id to write to VLAN filter
3900 * return the VLVF index where this VLAN id should be placed
3903 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)
3905 s32 regindex, first_empty_slot;
3908 /* short cut the special case */
3912 /* if vlvf_bypass is set we don't want to use an empty slot, we
3913 * will simply bypass the VLVF if there are no entries present in the
3914 * VLVF that contain our VLAN
3916 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0;
3918 /* add VLAN enable bit for comparison */
3919 vlan |= IXGBE_VLVF_VIEN;
3921 /* Search for the vlan id in the VLVF entries. Save off the first empty
3922 * slot found along the way.
3924 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1
3926 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) {
3927 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3930 if (!first_empty_slot && !bits)
3931 first_empty_slot = regindex;
3934 /* If we are here then we didn't find the VLAN. Return first empty
3935 * slot we found during our search, else error.
3937 if (!first_empty_slot)
3938 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "No space in VLVF.\n");
3940 return first_empty_slot ? first_empty_slot : IXGBE_ERR_NO_SPACE;
3944 * ixgbe_set_vfta_generic - Set VLAN filter table
3945 * @hw: pointer to hardware structure
3946 * @vlan: VLAN id to write to VLAN filter
3947 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
3948 * @vlan_on: boolean flag to turn on/off VLAN
3949 * @vlvf_bypass: boolean flag indicating updating default pool is okay
3951 * Turn on/off specified VLAN in the VLAN filter table.
3953 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3954 bool vlan_on, bool vlvf_bypass)
3956 u32 regidx, vfta_delta, vfta;
3959 DEBUGFUNC("ixgbe_set_vfta_generic");
3961 if (vlan > 4095 || vind > 63)
3962 return IXGBE_ERR_PARAM;
3965 * this is a 2 part operation - first the VFTA, then the
3966 * VLVF and VLVFB if VT Mode is set
3967 * We don't write the VFTA until we know the VLVF part succeeded.
3971 * The VFTA is a bitstring made up of 128 32-bit registers
3972 * that enable the particular VLAN id, much like the MTA:
3973 * bits[11-5]: which register
3974 * bits[4-0]: which bit in the register
3977 vfta_delta = 1 << (vlan % 32);
3978 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx));
3981 * vfta_delta represents the difference between the current value
3982 * of vfta and the value we want in the register. Since the diff
3983 * is an XOR mask we can just update the vfta using an XOR
3985 vfta_delta &= vlan_on ? ~vfta : vfta;
3989 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
3991 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta,
3993 if (ret_val != IXGBE_SUCCESS) {
4000 /* Update VFTA now that we are ready for traffic */
4002 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta);
4004 return IXGBE_SUCCESS;
4008 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
4009 * @hw: pointer to hardware structure
4010 * @vlan: VLAN id to write to VLAN filter
4011 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
4012 * @vlan_on: boolean flag to turn on/off VLAN in VLVF
4013 * @vfta_delta: pointer to the difference between the current value of VFTA
4014 * and the desired value
4015 * @vfta: the desired value of the VFTA
4016 * @vlvf_bypass: boolean flag indicating updating default pool is okay
4018 * Turn on/off specified bit in VLVF table.
4020 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
4021 bool vlan_on, u32 *vfta_delta, u32 vfta,
4027 DEBUGFUNC("ixgbe_set_vlvf_generic");
4029 if (vlan > 4095 || vind > 63)
4030 return IXGBE_ERR_PARAM;
4032 /* If VT Mode is set
4034 * make sure the vlan is in VLVF
4035 * set the vind bit in the matching VLVFB
4037 * clear the pool bit and possibly the vind
4039 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE))
4040 return IXGBE_SUCCESS;
4042 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
4046 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32));
4048 /* set the pool bit */
4049 bits |= 1 << (vind % 32);
4053 /* clear the pool bit */
4054 bits ^= 1 << (vind % 32);
4057 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) {
4058 /* Clear VFTA first, then disable VLVF. Otherwise
4059 * we run the risk of stray packets leaking into
4060 * the PF via the default pool
4063 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta);
4065 /* disable VLVF and clear remaining bit from pool */
4066 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
4067 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0);
4069 return IXGBE_SUCCESS;
4072 /* If there are still bits set in the VLVFB registers
4073 * for the VLAN ID indicated we need to see if the
4074 * caller is requesting that we clear the VFTA entry bit.
4075 * If the caller has requested that we clear the VFTA
4076 * entry bit but there are still pools/VFs using this VLAN
4077 * ID entry then ignore the request. We're not worried
4078 * about the case where we're turning the VFTA VLAN ID
4079 * entry bit on, only when requested to turn it off as
4080 * there may be multiple pools and/or VFs using the
4081 * VLAN ID entry. In that case we cannot clear the
4082 * VFTA bit until all pools/VFs using that VLAN ID have also
4083 * been cleared. This will be indicated by "bits" being
4089 /* record pool change and enable VLAN ID if not already enabled */
4090 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits);
4091 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan);
4093 return IXGBE_SUCCESS;
4097 * ixgbe_clear_vfta_generic - Clear VLAN filter table
4098 * @hw: pointer to hardware structure
4100 * Clears the VLAN filer table, and the VMDq index associated with the filter
4102 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
4106 DEBUGFUNC("ixgbe_clear_vfta_generic");
4108 for (offset = 0; offset < hw->mac.vft_size; offset++)
4109 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
4111 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
4112 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
4113 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
4114 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0);
4117 return IXGBE_SUCCESS;
4121 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
4122 * @hw: pointer to hardware structure
4124 * Contains the logic to identify if we need to verify link for the
4127 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw)
4130 /* Does FW say we need the fix */
4131 if (!hw->need_crosstalk_fix)
4134 /* Only consider SFP+ PHYs i.e. media type fiber */
4135 switch (hw->mac.ops.get_media_type(hw)) {
4136 case ixgbe_media_type_fiber:
4137 case ixgbe_media_type_fiber_qsfp:
4147 * ixgbe_check_mac_link_generic - Determine link and speed status
4148 * @hw: pointer to hardware structure
4149 * @speed: pointer to link speed
4150 * @link_up: true when link is up
4151 * @link_up_wait_to_complete: bool used to wait for link up or not
4153 * Reads the links register to determine if link is up and the current speed
4155 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4156 bool *link_up, bool link_up_wait_to_complete)
4158 u32 links_reg, links_orig;
4161 DEBUGFUNC("ixgbe_check_mac_link_generic");
4163 /* If Crosstalk fix enabled do the sanity check of making sure
4164 * the SFP+ cage is full.
4166 if (ixgbe_need_crosstalk_fix(hw)) {
4169 switch (hw->mac.type) {
4170 case ixgbe_mac_82599EB:
4171 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4174 case ixgbe_mac_X550EM_x:
4175 case ixgbe_mac_X550EM_a:
4176 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4180 /* sanity check - No SFP+ devices here */
4181 sfp_cage_full = false;
4185 if (!sfp_cage_full) {
4187 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4188 return IXGBE_SUCCESS;
4192 /* clear the old state */
4193 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
4195 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4197 if (links_orig != links_reg) {
4198 DEBUGOUT2("LINKS changed from %08X to %08X\n",
4199 links_orig, links_reg);
4202 if (link_up_wait_to_complete) {
4203 for (i = 0; i < hw->mac.max_link_up_time; i++) {
4204 if (links_reg & IXGBE_LINKS_UP) {
4211 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4214 if (links_reg & IXGBE_LINKS_UP)
4220 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4221 case IXGBE_LINKS_SPEED_10G_82599:
4222 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4223 if (hw->mac.type >= ixgbe_mac_X550) {
4224 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4225 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4228 case IXGBE_LINKS_SPEED_1G_82599:
4229 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4231 case IXGBE_LINKS_SPEED_100_82599:
4232 *speed = IXGBE_LINK_SPEED_100_FULL;
4233 if (hw->mac.type >= ixgbe_mac_X550) {
4234 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4235 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4238 case IXGBE_LINKS_SPEED_10_X550EM_A:
4239 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4240 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4241 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
4242 *speed = IXGBE_LINK_SPEED_10_FULL;
4246 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4249 return IXGBE_SUCCESS;
4253 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4255 * @hw: pointer to hardware structure
4256 * @wwnn_prefix: the alternative WWNN prefix
4257 * @wwpn_prefix: the alternative WWPN prefix
4259 * This function will read the EEPROM from the alternative SAN MAC address
4260 * block to check the support for the alternative WWNN/WWPN prefix support.
4262 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4266 u16 alt_san_mac_blk_offset;
4268 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
4270 /* clear output first */
4271 *wwnn_prefix = 0xFFFF;
4272 *wwpn_prefix = 0xFFFF;
4274 /* check if alternative SAN MAC is supported */
4275 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
4276 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4277 goto wwn_prefix_err;
4279 if ((alt_san_mac_blk_offset == 0) ||
4280 (alt_san_mac_blk_offset == 0xFFFF))
4281 goto wwn_prefix_out;
4283 /* check capability in alternative san mac address block */
4284 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
4285 if (hw->eeprom.ops.read(hw, offset, &caps))
4286 goto wwn_prefix_err;
4287 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
4288 goto wwn_prefix_out;
4290 /* get the corresponding prefix for WWNN/WWPN */
4291 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
4292 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4293 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4294 "eeprom read at offset %d failed", offset);
4297 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
4298 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4299 goto wwn_prefix_err;
4302 return IXGBE_SUCCESS;
4305 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4306 "eeprom read at offset %d failed", offset);
4307 return IXGBE_SUCCESS;
4311 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4312 * @hw: pointer to hardware structure
4313 * @bs: the fcoe boot status
4315 * This function will read the FCOE boot status from the iSCSI FCOE block
4317 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4319 u16 offset, caps, flags;
4322 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
4324 /* clear output first */
4325 *bs = ixgbe_fcoe_bootstatus_unavailable;
4327 /* check if FCOE IBA block is present */
4328 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
4329 status = hw->eeprom.ops.read(hw, offset, &caps);
4330 if (status != IXGBE_SUCCESS)
4333 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
4336 /* check if iSCSI FCOE block is populated */
4337 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4338 if (status != IXGBE_SUCCESS)
4341 if ((offset == 0) || (offset == 0xFFFF))
4344 /* read fcoe flags in iSCSI FCOE block */
4345 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
4346 status = hw->eeprom.ops.read(hw, offset, &flags);
4347 if (status != IXGBE_SUCCESS)
4350 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
4351 *bs = ixgbe_fcoe_bootstatus_enabled;
4353 *bs = ixgbe_fcoe_bootstatus_disabled;
4360 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4361 * @hw: pointer to hardware structure
4362 * @enable: enable or disable switch for MAC anti-spoofing
4363 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
4366 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4368 int vf_target_reg = vf >> 3;
4369 int vf_target_shift = vf % 8;
4372 if (hw->mac.type == ixgbe_mac_82598EB)
4375 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4377 pfvfspoof |= (1 << vf_target_shift);
4379 pfvfspoof &= ~(1 << vf_target_shift);
4380 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4384 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4385 * @hw: pointer to hardware structure
4386 * @enable: enable or disable switch for VLAN anti-spoofing
4387 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4390 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4392 int vf_target_reg = vf >> 3;
4393 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
4396 if (hw->mac.type == ixgbe_mac_82598EB)
4399 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4401 pfvfspoof |= (1 << vf_target_shift);
4403 pfvfspoof &= ~(1 << vf_target_shift);
4404 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4408 * ixgbe_get_device_caps_generic - Get additional device capabilities
4409 * @hw: pointer to hardware structure
4410 * @device_caps: the EEPROM word with the extra device capabilities
4412 * This function will read the EEPROM location for the device capabilities,
4413 * and return the word through device_caps.
4415 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4417 DEBUGFUNC("ixgbe_get_device_caps_generic");
4419 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4421 return IXGBE_SUCCESS;
4425 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4426 * @hw: pointer to hardware structure
4429 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4434 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
4436 /* Enable relaxed ordering */
4437 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4438 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4439 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4440 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4443 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4444 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4445 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
4446 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4447 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4453 * ixgbe_calculate_checksum - Calculate checksum for buffer
4454 * @buffer: pointer to EEPROM
4455 * @length: size of EEPROM to calculate a checksum for
4456 * Calculates the checksum for some buffer on a specified length. The
4457 * checksum calculated is returned.
4459 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4464 DEBUGFUNC("ixgbe_calculate_checksum");
4469 for (i = 0; i < length; i++)
4472 return (u8) (0 - sum);
4476 * ixgbe_hic_unlocked - Issue command to manageability block unlocked
4477 * @hw: pointer to the HW structure
4478 * @buffer: command to write and where the return status will be placed
4479 * @length: length of buffer, must be multiple of 4 bytes
4480 * @timeout: time in ms to wait for command completion
4482 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4483 * else returns semaphore error when encountering an error acquiring
4484 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4486 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held
4489 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length,
4495 DEBUGFUNC("ixgbe_hic_unlocked");
4497 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4498 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4499 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4502 /* Set bit 9 of FWSTS clearing FW reset indication */
4503 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
4504 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
4506 /* Check that the host interface is enabled. */
4507 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4508 if (!(hicr & IXGBE_HICR_EN)) {
4509 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
4510 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4513 /* Calculate length in DWORDs. We must be DWORD aligned */
4514 if (length % sizeof(u32)) {
4515 DEBUGOUT("Buffer length failure, not aligned to dword");
4516 return IXGBE_ERR_INVALID_ARGUMENT;
4519 dword_len = length >> 2;
4521 /* The device driver writes the relevant command block
4522 * into the ram area.
4524 for (i = 0; i < dword_len; i++)
4525 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4526 i, IXGBE_CPU_TO_LE32(buffer[i]));
4528 /* Setting this bit tells the ARC that a new command is pending. */
4529 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4531 for (i = 0; i < timeout; i++) {
4532 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4533 if (!(hicr & IXGBE_HICR_C))
4538 /* Check command completion */
4539 if ((timeout && i == timeout) ||
4540 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
4541 ERROR_REPORT1(IXGBE_ERROR_CAUTION,
4542 "Command has failed with no status valid.\n");
4543 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4546 return IXGBE_SUCCESS;
4550 * ixgbe_host_interface_command - Issue command to manageability block
4551 * @hw: pointer to the HW structure
4552 * @buffer: contains the command to write and where the return status will
4554 * @length: length of buffer, must be multiple of 4 bytes
4555 * @timeout: time in ms to wait for command completion
4556 * @return_data: read and return data from the buffer (true) or not (false)
4557 * Needed because FW structures are big endian and decoding of
4558 * these fields can be 8 bit or 16 bit based on command. Decoding
4559 * is not easily understood without making a table of commands.
4560 * So we will leave this up to the caller to read back the data
4563 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4564 * else returns semaphore error when encountering an error acquiring
4565 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4567 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4568 u32 length, u32 timeout, bool return_data)
4570 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4576 DEBUGFUNC("ixgbe_host_interface_command");
4578 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4579 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4580 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4583 /* Take management host interface semaphore */
4584 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4588 status = ixgbe_hic_unlocked(hw, buffer, length, timeout);
4595 /* Calculate length in DWORDs */
4596 dword_len = hdr_size >> 2;
4598 /* first pull in the header so we know the buffer length */
4599 for (bi = 0; bi < dword_len; bi++) {
4600 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4601 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4604 /* If there is any thing in data position pull it in */
4605 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
4609 if (length < buf_len + hdr_size) {
4610 DEBUGOUT("Buffer not large enough for reply message.\n");
4611 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4615 /* Calculate length in DWORDs, add 3 for odd lengths */
4616 dword_len = (buf_len + 3) >> 2;
4618 /* Pull in the rest of the buffer (bi is where we left off) */
4619 for (; bi <= dword_len; bi++) {
4620 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4621 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4625 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4631 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4632 * @hw: pointer to the HW structure
4633 * @maj: driver version major number
4634 * @min: driver version minor number
4635 * @build: driver version build number
4636 * @sub: driver version sub build number
4638 * Sends driver version number to firmware through the manageability
4639 * block. On success return IXGBE_SUCCESS
4640 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4641 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4643 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4644 u8 build, u8 sub, u16 len,
4645 const char *driver_ver)
4647 struct ixgbe_hic_drv_info fw_cmd;
4649 s32 ret_val = IXGBE_SUCCESS;
4651 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4652 UNREFERENCED_2PARAMETER(len, driver_ver);
4654 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4655 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4656 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4657 fw_cmd.port_num = (u8)hw->bus.func;
4658 fw_cmd.ver_maj = maj;
4659 fw_cmd.ver_min = min;
4660 fw_cmd.ver_build = build;
4661 fw_cmd.ver_sub = sub;
4662 fw_cmd.hdr.checksum = 0;
4663 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4664 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4668 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4669 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4671 IXGBE_HI_COMMAND_TIMEOUT,
4673 if (ret_val != IXGBE_SUCCESS)
4676 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4677 FW_CEM_RESP_STATUS_SUCCESS)
4678 ret_val = IXGBE_SUCCESS;
4680 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4689 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4690 * @hw: pointer to hardware structure
4691 * @num_pb: number of packet buffers to allocate
4692 * @headroom: reserve n KB of headroom
4693 * @strategy: packet buffer allocation strategy
4695 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4698 u32 pbsize = hw->mac.rx_pb_size;
4700 u32 rxpktsize, txpktsize, txpbthresh;
4702 /* Reserve headroom */
4708 /* Divide remaining packet buffer space amongst the number of packet
4709 * buffers requested using supplied strategy.
4712 case PBA_STRATEGY_WEIGHTED:
4713 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4714 * buffer with 5/8 of the packet buffer space.
4716 rxpktsize = (pbsize * 5) / (num_pb * 4);
4717 pbsize -= rxpktsize * (num_pb / 2);
4718 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4719 for (; i < (num_pb / 2); i++)
4720 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4721 /* Fall through to configure remaining packet buffers */
4722 case PBA_STRATEGY_EQUAL:
4723 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4724 for (; i < num_pb; i++)
4725 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4731 /* Only support an equally distributed Tx packet buffer strategy. */
4732 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4733 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4734 for (i = 0; i < num_pb; i++) {
4735 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4736 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4739 /* Clear unused TCs, if any, to zero buffer size*/
4740 for (; i < IXGBE_MAX_PB; i++) {
4741 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4742 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4743 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4748 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4749 * @hw: pointer to the hardware structure
4751 * The 82599 and x540 MACs can experience issues if TX work is still pending
4752 * when a reset occurs. This function prevents this by flushing the PCIe
4753 * buffers on the system.
4755 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4757 u32 gcr_ext, hlreg0, i, poll;
4761 * If double reset is not requested then all transactions should
4762 * already be clear and as such there is no work to do
4764 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4768 * Set loopback enable to prevent any transmits from being sent
4769 * should the link come up. This assumes that the RXCTRL.RXEN bit
4770 * has already been cleared.
4772 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4773 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4775 /* Wait for a last completion before clearing buffers */
4776 IXGBE_WRITE_FLUSH(hw);
4780 * Before proceeding, make sure that the PCIe block does not have
4781 * transactions pending.
4783 poll = ixgbe_pcie_timeout_poll(hw);
4784 for (i = 0; i < poll; i++) {
4786 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
4787 if (IXGBE_REMOVED(hw->hw_addr))
4789 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
4794 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4795 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4796 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4797 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4799 /* Flush all writes and allow 20usec for all transactions to clear */
4800 IXGBE_WRITE_FLUSH(hw);
4803 /* restore previous register values */
4804 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4805 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4808 STATIC const u8 ixgbe_emc_temp_data[4] = {
4809 IXGBE_EMC_INTERNAL_DATA,
4810 IXGBE_EMC_DIODE1_DATA,
4811 IXGBE_EMC_DIODE2_DATA,
4812 IXGBE_EMC_DIODE3_DATA
4814 STATIC const u8 ixgbe_emc_therm_limit[4] = {
4815 IXGBE_EMC_INTERNAL_THERM_LIMIT,
4816 IXGBE_EMC_DIODE1_THERM_LIMIT,
4817 IXGBE_EMC_DIODE2_THERM_LIMIT,
4818 IXGBE_EMC_DIODE3_THERM_LIMIT
4822 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
4823 * @hw: pointer to hardware structure
4824 * @data: pointer to the thermal sensor data structure
4826 * Returns the thermal sensor data structure
4828 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
4830 s32 status = IXGBE_SUCCESS;
4838 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4840 DEBUGFUNC("ixgbe_get_thermal_sensor_data_generic");
4842 /* Only support thermal sensors attached to 82599 physical port 0 */
4843 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4844 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
4845 status = IXGBE_NOT_IMPLEMENTED;
4849 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);
4853 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) {
4854 status = IXGBE_NOT_IMPLEMENTED;
4858 status = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);
4862 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4863 != IXGBE_ETS_TYPE_EMC) {
4864 status = IXGBE_NOT_IMPLEMENTED;
4868 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4869 if (num_sensors > IXGBE_MAX_SENSORS)
4870 num_sensors = IXGBE_MAX_SENSORS;
4872 for (i = 0; i < num_sensors; i++) {
4873 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
4878 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4879 IXGBE_ETS_DATA_INDEX_SHIFT);
4880 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4881 IXGBE_ETS_DATA_LOC_SHIFT);
4883 if (sensor_location != 0) {
4884 status = hw->phy.ops.read_i2c_byte(hw,
4885 ixgbe_emc_temp_data[sensor_index],
4886 IXGBE_I2C_THERMAL_SENSOR_ADDR,
4887 &data->sensor[i].temp);
4897 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
4898 * @hw: pointer to hardware structure
4900 * Inits the thermal sensor thresholds according to the NVM map
4901 * and save off the threshold and location values into mac.thermal_sensor_data
4903 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
4905 s32 status = IXGBE_SUCCESS;
4910 u8 low_thresh_delta;
4916 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4918 DEBUGFUNC("ixgbe_init_thermal_sensor_thresh_generic");
4920 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
4922 /* Only support thermal sensors attached to 82599 physical port 0 */
4923 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4924 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
4925 return IXGBE_NOT_IMPLEMENTED;
4927 offset = IXGBE_ETS_CFG;
4928 if (hw->eeprom.ops.read(hw, offset, &ets_offset))
4930 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
4931 return IXGBE_NOT_IMPLEMENTED;
4933 offset = ets_offset;
4934 if (hw->eeprom.ops.read(hw, offset, &ets_cfg))
4936 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4937 != IXGBE_ETS_TYPE_EMC)
4938 return IXGBE_NOT_IMPLEMENTED;
4940 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
4941 IXGBE_ETS_LTHRES_DELTA_SHIFT);
4942 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4944 for (i = 0; i < num_sensors; i++) {
4945 offset = ets_offset + 1 + i;
4946 if (hw->eeprom.ops.read(hw, offset, &ets_sensor)) {
4947 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4948 "eeprom read at offset %d failed",
4952 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4953 IXGBE_ETS_DATA_INDEX_SHIFT);
4954 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4955 IXGBE_ETS_DATA_LOC_SHIFT);
4956 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
4958 hw->phy.ops.write_i2c_byte(hw,
4959 ixgbe_emc_therm_limit[sensor_index],
4960 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
4962 if ((i < IXGBE_MAX_SENSORS) && (sensor_location != 0)) {
4963 data->sensor[i].location = sensor_location;
4964 data->sensor[i].caution_thresh = therm_limit;
4965 data->sensor[i].max_op_thresh = therm_limit -
4972 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4973 "eeprom read at offset %d failed", offset);
4974 return IXGBE_NOT_IMPLEMENTED;
4979 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
4980 * @hw: pointer to hardware structure
4981 * @map: pointer to u8 arr for returning map
4983 * Read the rtrup2tc HW register and resolve its content into map
4985 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
4989 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
4990 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
4991 map[i] = IXGBE_RTRUP2TC_UP_MASK &
4992 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
4996 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
5001 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5002 if (rxctrl & IXGBE_RXCTRL_RXEN) {
5003 if (hw->mac.type != ixgbe_mac_82598EB) {
5004 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5005 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
5006 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
5007 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
5008 hw->mac.set_lben = true;
5010 hw->mac.set_lben = false;
5013 rxctrl &= ~IXGBE_RXCTRL_RXEN;
5014 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
5018 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
5023 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5024 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
5026 if (hw->mac.type != ixgbe_mac_82598EB) {
5027 if (hw->mac.set_lben) {
5028 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5029 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
5030 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
5031 hw->mac.set_lben = false;
5037 * ixgbe_mng_present - returns true when management capability is present
5038 * @hw: pointer to hardware structure
5040 bool ixgbe_mng_present(struct ixgbe_hw *hw)
5044 if (hw->mac.type < ixgbe_mac_82599EB)
5047 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5048 fwsm &= IXGBE_FWSM_MODE_MASK;
5049 return fwsm == IXGBE_FWSM_FW_MODE_PT;
5053 * ixgbe_mng_enabled - Is the manageability engine enabled?
5054 * @hw: pointer to hardware structure
5056 * Returns true if the manageability engine is enabled.
5058 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
5060 u32 fwsm, manc, factps;
5062 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5063 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
5066 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
5067 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
5070 if (hw->mac.type <= ixgbe_mac_X540) {
5071 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
5072 if (factps & IXGBE_FACTPS_MNGCG)
5080 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
5081 * @hw: pointer to hardware structure
5082 * @speed: new link speed
5083 * @autoneg_wait_to_complete: true when waiting for completion is needed
5085 * Set the link speed in the MAC and/or PHY register and restarts link.
5087 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
5088 ixgbe_link_speed speed,
5089 bool autoneg_wait_to_complete)
5091 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
5092 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
5093 s32 status = IXGBE_SUCCESS;
5096 bool autoneg, link_up = false;
5098 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
5100 /* Mask off requested but non-supported speeds */
5101 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
5102 if (status != IXGBE_SUCCESS)
5105 speed &= link_speed;
5107 /* Try each speed one by one, highest priority first. We do this in
5108 * software because 10Gb fiber doesn't support speed autonegotiation.
5110 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
5112 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5114 /* Set the module link speed */
5115 switch (hw->phy.media_type) {
5116 case ixgbe_media_type_fiber:
5117 ixgbe_set_rate_select_speed(hw,
5118 IXGBE_LINK_SPEED_10GB_FULL);
5120 case ixgbe_media_type_fiber_qsfp:
5121 /* QSFP module automatically detects MAC link speed */
5124 DEBUGOUT("Unexpected media type.\n");
5128 /* Allow module to change analog characteristics (1G->10G) */
5131 status = ixgbe_setup_mac_link(hw,
5132 IXGBE_LINK_SPEED_10GB_FULL,
5133 autoneg_wait_to_complete);
5134 if (status != IXGBE_SUCCESS)
5137 /* Flap the Tx laser if it has not already been done */
5138 ixgbe_flap_tx_laser(hw);
5140 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
5141 * Section 73.10.2, we may have to wait up to 500ms if KR is
5142 * attempted. 82599 uses the same timing for 10g SFI.
5144 for (i = 0; i < 5; i++) {
5145 /* Wait for the link partner to also set speed */
5148 /* If we have link, just jump out */
5149 status = ixgbe_check_link(hw, &link_speed,
5151 if (status != IXGBE_SUCCESS)
5159 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
5161 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
5162 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
5164 /* Set the module link speed */
5165 switch (hw->phy.media_type) {
5166 case ixgbe_media_type_fiber:
5167 ixgbe_set_rate_select_speed(hw,
5168 IXGBE_LINK_SPEED_1GB_FULL);
5170 case ixgbe_media_type_fiber_qsfp:
5171 /* QSFP module automatically detects link speed */
5174 DEBUGOUT("Unexpected media type.\n");
5178 /* Allow module to change analog characteristics (10G->1G) */
5181 status = ixgbe_setup_mac_link(hw,
5182 IXGBE_LINK_SPEED_1GB_FULL,
5183 autoneg_wait_to_complete);
5184 if (status != IXGBE_SUCCESS)
5187 /* Flap the Tx laser if it has not already been done */
5188 ixgbe_flap_tx_laser(hw);
5190 /* Wait for the link partner to also set speed */
5193 /* If we have link, just jump out */
5194 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
5195 if (status != IXGBE_SUCCESS)
5202 /* We didn't get link. Configure back to the highest speed we tried,
5203 * (if there was more than one). We call ourselves back with just the
5204 * single highest speed that the user requested.
5207 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
5209 autoneg_wait_to_complete);
5212 /* Set autoneg_advertised value based on input link speed */
5213 hw->phy.autoneg_advertised = 0;
5215 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
5216 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
5218 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
5219 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
5225 * ixgbe_set_soft_rate_select_speed - Set module link speed
5226 * @hw: pointer to hardware structure
5227 * @speed: link speed to set
5229 * Set module link speed via the soft rate select.
5231 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
5232 ixgbe_link_speed speed)
5238 case IXGBE_LINK_SPEED_10GB_FULL:
5239 /* one bit mask same as setting on */
5240 rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
5242 case IXGBE_LINK_SPEED_1GB_FULL:
5243 rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
5246 DEBUGOUT("Invalid fixed module speed\n");
5251 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5252 IXGBE_I2C_EEPROM_DEV_ADDR2,
5255 DEBUGOUT("Failed to read Rx Rate Select RS0\n");
5259 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5261 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5262 IXGBE_I2C_EEPROM_DEV_ADDR2,
5265 DEBUGOUT("Failed to write Rx Rate Select RS0\n");
5270 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5271 IXGBE_I2C_EEPROM_DEV_ADDR2,
5274 DEBUGOUT("Failed to read Rx Rate Select RS1\n");
5278 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5280 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5281 IXGBE_I2C_EEPROM_DEV_ADDR2,
5284 DEBUGOUT("Failed to write Rx Rate Select RS1\n");