1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
36 #include "ixgbe_dcb.h"
37 #include "ixgbe_dcb_82599.h"
38 #include "ixgbe_api.h"
40 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
41 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
42 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
43 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
44 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
45 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
47 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
48 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
49 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
50 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw);
52 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
53 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
55 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
56 u16 words, u16 *data);
57 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
58 u16 words, u16 *data);
59 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
63 * ixgbe_init_ops_generic - Inits function ptrs
64 * @hw: pointer to the hardware structure
66 * Initialize the function pointers.
68 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
70 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
71 struct ixgbe_mac_info *mac = &hw->mac;
72 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
74 DEBUGFUNC("ixgbe_init_ops_generic");
77 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic;
78 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
79 if (eec & IXGBE_EEC_PRES) {
80 eeprom->ops.read = ixgbe_read_eerd_generic;
81 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic;
83 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic;
84 eeprom->ops.read_buffer =
85 ixgbe_read_eeprom_buffer_bit_bang_generic;
87 eeprom->ops.write = ixgbe_write_eeprom_generic;
88 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic;
89 eeprom->ops.validate_checksum =
90 ixgbe_validate_eeprom_checksum_generic;
91 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic;
92 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic;
95 mac->ops.init_hw = ixgbe_init_hw_generic;
96 mac->ops.reset_hw = NULL;
97 mac->ops.start_hw = ixgbe_start_hw_generic;
98 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic;
99 mac->ops.get_media_type = NULL;
100 mac->ops.get_supported_physical_layer = NULL;
101 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic;
102 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic;
103 mac->ops.stop_adapter = ixgbe_stop_adapter_generic;
104 mac->ops.get_bus_info = ixgbe_get_bus_info_generic;
105 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie;
106 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync;
107 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync;
108 mac->ops.prot_autoc_read = prot_autoc_read_generic;
109 mac->ops.prot_autoc_write = prot_autoc_write_generic;
112 mac->ops.led_on = ixgbe_led_on_generic;
113 mac->ops.led_off = ixgbe_led_off_generic;
114 mac->ops.blink_led_start = ixgbe_blink_led_start_generic;
115 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic;
117 /* RAR, Multicast, VLAN */
118 mac->ops.set_rar = ixgbe_set_rar_generic;
119 mac->ops.clear_rar = ixgbe_clear_rar_generic;
120 mac->ops.insert_mac_addr = NULL;
121 mac->ops.set_vmdq = NULL;
122 mac->ops.clear_vmdq = NULL;
123 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic;
124 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic;
125 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic;
126 mac->ops.enable_mc = ixgbe_enable_mc_generic;
127 mac->ops.disable_mc = ixgbe_disable_mc_generic;
128 mac->ops.clear_vfta = NULL;
129 mac->ops.set_vfta = NULL;
130 mac->ops.set_vlvf = NULL;
131 mac->ops.init_uta_tables = NULL;
132 mac->ops.enable_rx = ixgbe_enable_rx_generic;
133 mac->ops.disable_rx = ixgbe_disable_rx_generic;
136 mac->ops.fc_enable = ixgbe_fc_enable_generic;
137 mac->ops.setup_fc = ixgbe_setup_fc_generic;
138 mac->ops.fc_autoneg = ixgbe_fc_autoneg;
141 mac->ops.get_link_capabilities = NULL;
142 mac->ops.setup_link = NULL;
143 mac->ops.check_link = NULL;
144 mac->ops.dmac_config = NULL;
145 mac->ops.dmac_update_tcs = NULL;
146 mac->ops.dmac_config_tcs = NULL;
148 return IXGBE_SUCCESS;
152 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
154 * @hw: pointer to hardware structure
156 * This function returns true if the device supports flow control
157 * autonegotiation, and false if it does not.
160 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
162 bool supported = false;
163 ixgbe_link_speed speed;
166 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
168 switch (hw->phy.media_type) {
169 case ixgbe_media_type_fiber_qsfp:
170 case ixgbe_media_type_fiber:
171 hw->mac.ops.check_link(hw, &speed, &link_up, false);
172 /* if link is down, assume supported */
174 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
179 case ixgbe_media_type_backplane:
182 case ixgbe_media_type_copper:
183 /* only some copper devices support flow control autoneg */
184 switch (hw->device_id) {
185 case IXGBE_DEV_ID_82599_T3_LOM:
186 case IXGBE_DEV_ID_X540T:
187 case IXGBE_DEV_ID_X540T1:
188 case IXGBE_DEV_ID_X550T:
189 case IXGBE_DEV_ID_X550T1:
190 case IXGBE_DEV_ID_X550EM_X_10G_T:
191 case IXGBE_DEV_ID_X550EM_A_10G_T:
201 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
202 "Device %x does not support flow control autoneg",
208 * ixgbe_setup_fc_generic - Set up flow control
209 * @hw: pointer to hardware structure
211 * Called at init time to set up flow control.
213 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
215 s32 ret_val = IXGBE_SUCCESS;
216 u32 reg = 0, reg_bp = 0;
220 DEBUGFUNC("ixgbe_setup_fc_generic");
222 /* Validate the requested mode */
223 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
224 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
225 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
226 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
231 * 10gig parts do not have a word in the EEPROM to determine the
232 * default flow control setting, so we explicitly set it to full.
234 if (hw->fc.requested_mode == ixgbe_fc_default)
235 hw->fc.requested_mode = ixgbe_fc_full;
238 * Set up the 1G and 10G flow control advertisement registers so the
239 * HW will be able to do fc autoneg once the cable is plugged in. If
240 * we link at 10G, the 1G advertisement is harmless and vice versa.
242 switch (hw->phy.media_type) {
243 case ixgbe_media_type_backplane:
244 /* some MAC's need RMW protection on AUTOC */
245 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
246 if (ret_val != IXGBE_SUCCESS)
249 /* only backplane uses autoc so fall though */
250 case ixgbe_media_type_fiber_qsfp:
251 case ixgbe_media_type_fiber:
252 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
255 case ixgbe_media_type_copper:
256 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
257 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
264 * The possible values of fc.requested_mode are:
265 * 0: Flow control is completely disabled
266 * 1: Rx flow control is enabled (we can receive pause frames,
267 * but not send pause frames).
268 * 2: Tx flow control is enabled (we can send pause frames but
269 * we do not support receiving pause frames).
270 * 3: Both Rx and Tx flow control (symmetric) are enabled.
273 switch (hw->fc.requested_mode) {
275 /* Flow control completely disabled by software override. */
276 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
277 if (hw->phy.media_type == ixgbe_media_type_backplane)
278 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
279 IXGBE_AUTOC_ASM_PAUSE);
280 else if (hw->phy.media_type == ixgbe_media_type_copper)
281 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
283 case ixgbe_fc_tx_pause:
285 * Tx Flow control is enabled, and Rx Flow control is
286 * disabled by software override.
288 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
289 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
290 if (hw->phy.media_type == ixgbe_media_type_backplane) {
291 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
292 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
293 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
294 reg_cu |= IXGBE_TAF_ASM_PAUSE;
295 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
298 case ixgbe_fc_rx_pause:
300 * Rx Flow control is enabled and Tx Flow control is
301 * disabled by software override. Since there really
302 * isn't a way to advertise that we are capable of RX
303 * Pause ONLY, we will advertise that we support both
304 * symmetric and asymmetric Rx PAUSE, as such we fall
305 * through to the fc_full statement. Later, we will
306 * disable the adapter's ability to send PAUSE frames.
309 /* Flow control (both Rx and Tx) is enabled by SW override. */
310 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
311 if (hw->phy.media_type == ixgbe_media_type_backplane)
312 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
313 IXGBE_AUTOC_ASM_PAUSE;
314 else if (hw->phy.media_type == ixgbe_media_type_copper)
315 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
318 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
319 "Flow control param set incorrectly\n");
320 ret_val = IXGBE_ERR_CONFIG;
325 if (hw->mac.type < ixgbe_mac_X540) {
327 * Enable auto-negotiation between the MAC & PHY;
328 * the MAC will advertise clause 37 flow control.
330 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
331 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
333 /* Disable AN timeout */
334 if (hw->fc.strict_ieee)
335 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
337 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
338 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
342 * AUTOC restart handles negotiation of 1G and 10G on backplane
343 * and copper. There is no need to set the PCS1GCTL register.
346 if (hw->phy.media_type == ixgbe_media_type_backplane) {
347 reg_bp |= IXGBE_AUTOC_AN_RESTART;
348 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
351 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
352 (ixgbe_device_supports_autoneg_fc(hw))) {
353 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
354 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
357 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
363 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
364 * @hw: pointer to hardware structure
366 * Starts the hardware by filling the bus info structure and media type, clears
367 * all on chip counters, initializes receive address registers, multicast
368 * table, VLAN filter table, calls routine to set up link and flow control
369 * settings, and leaves transmit and receive units disabled and uninitialized
371 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
377 DEBUGFUNC("ixgbe_start_hw_generic");
379 /* Set the media type */
380 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
382 /* PHY ops initialization must be done in reset_hw() */
384 /* Clear the VLAN filter table */
385 hw->mac.ops.clear_vfta(hw);
387 /* Clear statistics registers */
388 hw->mac.ops.clear_hw_cntrs(hw);
390 /* Set No Snoop Disable */
391 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
392 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
393 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
394 IXGBE_WRITE_FLUSH(hw);
396 /* Setup flow control */
397 ret_val = ixgbe_setup_fc(hw);
398 if (ret_val != IXGBE_SUCCESS)
401 /* Cache bit indicating need for crosstalk fix */
402 switch (hw->mac.type) {
403 case ixgbe_mac_82599EB:
404 case ixgbe_mac_X550EM_x:
405 case ixgbe_mac_X550EM_a:
406 hw->mac.ops.get_device_caps(hw, &device_caps);
407 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
408 hw->need_crosstalk_fix = false;
410 hw->need_crosstalk_fix = true;
413 hw->need_crosstalk_fix = false;
417 /* Clear adapter stopped flag */
418 hw->adapter_stopped = false;
425 * ixgbe_start_hw_gen2 - Init sequence for common device family
426 * @hw: pointer to hw structure
428 * Performs the init sequence common to the second generation
430 * Devices in the second generation:
434 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
439 /* Clear the rate limiters */
440 for (i = 0; i < hw->mac.max_tx_queues; i++) {
441 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
442 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
444 IXGBE_WRITE_FLUSH(hw);
446 /* Disable relaxed ordering */
447 for (i = 0; i < hw->mac.max_tx_queues; i++) {
448 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
449 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
450 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
453 for (i = 0; i < hw->mac.max_rx_queues; i++) {
454 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
455 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
456 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
457 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
460 return IXGBE_SUCCESS;
464 * ixgbe_init_hw_generic - Generic hardware initialization
465 * @hw: pointer to hardware structure
467 * Initialize the hardware by resetting the hardware, filling the bus info
468 * structure and media type, clears all on chip counters, initializes receive
469 * address registers, multicast table, VLAN filter table, calls routine to set
470 * up link and flow control settings, and leaves transmit and receive units
471 * disabled and uninitialized
473 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
477 DEBUGFUNC("ixgbe_init_hw_generic");
479 /* Reset the hardware */
480 status = hw->mac.ops.reset_hw(hw);
482 if (status == IXGBE_SUCCESS) {
484 status = hw->mac.ops.start_hw(hw);
491 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
492 * @hw: pointer to hardware structure
494 * Clears all hardware statistics counters by reading them from the hardware
495 * Statistics counters are clear on read.
497 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
501 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
503 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
504 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
505 IXGBE_READ_REG(hw, IXGBE_ERRBC);
506 IXGBE_READ_REG(hw, IXGBE_MSPDC);
507 for (i = 0; i < 8; i++)
508 IXGBE_READ_REG(hw, IXGBE_MPC(i));
510 IXGBE_READ_REG(hw, IXGBE_MLFC);
511 IXGBE_READ_REG(hw, IXGBE_MRFC);
512 IXGBE_READ_REG(hw, IXGBE_RLEC);
513 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
514 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
515 if (hw->mac.type >= ixgbe_mac_82599EB) {
516 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
517 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
519 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
520 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
523 for (i = 0; i < 8; i++) {
524 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
525 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
526 if (hw->mac.type >= ixgbe_mac_82599EB) {
527 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
528 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
530 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
531 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
534 if (hw->mac.type >= ixgbe_mac_82599EB)
535 for (i = 0; i < 8; i++)
536 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
537 IXGBE_READ_REG(hw, IXGBE_PRC64);
538 IXGBE_READ_REG(hw, IXGBE_PRC127);
539 IXGBE_READ_REG(hw, IXGBE_PRC255);
540 IXGBE_READ_REG(hw, IXGBE_PRC511);
541 IXGBE_READ_REG(hw, IXGBE_PRC1023);
542 IXGBE_READ_REG(hw, IXGBE_PRC1522);
543 IXGBE_READ_REG(hw, IXGBE_GPRC);
544 IXGBE_READ_REG(hw, IXGBE_BPRC);
545 IXGBE_READ_REG(hw, IXGBE_MPRC);
546 IXGBE_READ_REG(hw, IXGBE_GPTC);
547 IXGBE_READ_REG(hw, IXGBE_GORCL);
548 IXGBE_READ_REG(hw, IXGBE_GORCH);
549 IXGBE_READ_REG(hw, IXGBE_GOTCL);
550 IXGBE_READ_REG(hw, IXGBE_GOTCH);
551 if (hw->mac.type == ixgbe_mac_82598EB)
552 for (i = 0; i < 8; i++)
553 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
554 IXGBE_READ_REG(hw, IXGBE_RUC);
555 IXGBE_READ_REG(hw, IXGBE_RFC);
556 IXGBE_READ_REG(hw, IXGBE_ROC);
557 IXGBE_READ_REG(hw, IXGBE_RJC);
558 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
559 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
560 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
561 IXGBE_READ_REG(hw, IXGBE_TORL);
562 IXGBE_READ_REG(hw, IXGBE_TORH);
563 IXGBE_READ_REG(hw, IXGBE_TPR);
564 IXGBE_READ_REG(hw, IXGBE_TPT);
565 IXGBE_READ_REG(hw, IXGBE_PTC64);
566 IXGBE_READ_REG(hw, IXGBE_PTC127);
567 IXGBE_READ_REG(hw, IXGBE_PTC255);
568 IXGBE_READ_REG(hw, IXGBE_PTC511);
569 IXGBE_READ_REG(hw, IXGBE_PTC1023);
570 IXGBE_READ_REG(hw, IXGBE_PTC1522);
571 IXGBE_READ_REG(hw, IXGBE_MPTC);
572 IXGBE_READ_REG(hw, IXGBE_BPTC);
573 for (i = 0; i < 16; i++) {
574 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
575 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
576 if (hw->mac.type >= ixgbe_mac_82599EB) {
577 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
578 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
579 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
580 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
581 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
583 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
584 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
588 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
590 ixgbe_identify_phy(hw);
591 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
592 IXGBE_MDIO_PCS_DEV_TYPE, &i);
593 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
594 IXGBE_MDIO_PCS_DEV_TYPE, &i);
595 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
596 IXGBE_MDIO_PCS_DEV_TYPE, &i);
597 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
598 IXGBE_MDIO_PCS_DEV_TYPE, &i);
601 return IXGBE_SUCCESS;
605 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
606 * @hw: pointer to hardware structure
607 * @pba_num: stores the part number string from the EEPROM
608 * @pba_num_size: part number string buffer length
610 * Reads the part number string from the EEPROM.
612 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
621 DEBUGFUNC("ixgbe_read_pba_string_generic");
623 if (pba_num == NULL) {
624 DEBUGOUT("PBA string buffer was null\n");
625 return IXGBE_ERR_INVALID_ARGUMENT;
628 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
630 DEBUGOUT("NVM Read Error\n");
634 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
636 DEBUGOUT("NVM Read Error\n");
641 * if data is not ptr guard the PBA must be in legacy format which
642 * means pba_ptr is actually our second data word for the PBA number
643 * and we can decode it into an ascii string
645 if (data != IXGBE_PBANUM_PTR_GUARD) {
646 DEBUGOUT("NVM PBA number is not stored as string\n");
648 /* we will need 11 characters to store the PBA */
649 if (pba_num_size < 11) {
650 DEBUGOUT("PBA string buffer too small\n");
651 return IXGBE_ERR_NO_SPACE;
654 /* extract hex string from data and pba_ptr */
655 pba_num[0] = (data >> 12) & 0xF;
656 pba_num[1] = (data >> 8) & 0xF;
657 pba_num[2] = (data >> 4) & 0xF;
658 pba_num[3] = data & 0xF;
659 pba_num[4] = (pba_ptr >> 12) & 0xF;
660 pba_num[5] = (pba_ptr >> 8) & 0xF;
663 pba_num[8] = (pba_ptr >> 4) & 0xF;
664 pba_num[9] = pba_ptr & 0xF;
666 /* put a null character on the end of our string */
669 /* switch all the data but the '-' to hex char */
670 for (offset = 0; offset < 10; offset++) {
671 if (pba_num[offset] < 0xA)
672 pba_num[offset] += '0';
673 else if (pba_num[offset] < 0x10)
674 pba_num[offset] += 'A' - 0xA;
677 return IXGBE_SUCCESS;
680 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
682 DEBUGOUT("NVM Read Error\n");
686 if (length == 0xFFFF || length == 0) {
687 DEBUGOUT("NVM PBA number section invalid length\n");
688 return IXGBE_ERR_PBA_SECTION;
691 /* check if pba_num buffer is big enough */
692 if (pba_num_size < (((u32)length * 2) - 1)) {
693 DEBUGOUT("PBA string buffer too small\n");
694 return IXGBE_ERR_NO_SPACE;
697 /* trim pba length from start of string */
701 for (offset = 0; offset < length; offset++) {
702 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
704 DEBUGOUT("NVM Read Error\n");
707 pba_num[offset * 2] = (u8)(data >> 8);
708 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
710 pba_num[offset * 2] = '\0';
712 return IXGBE_SUCCESS;
716 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
717 * @hw: pointer to hardware structure
718 * @pba_num: stores the part number from the EEPROM
720 * Reads the part number from the EEPROM.
722 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
727 DEBUGFUNC("ixgbe_read_pba_num_generic");
729 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
731 DEBUGOUT("NVM Read Error\n");
733 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
734 DEBUGOUT("NVM Not supported\n");
735 return IXGBE_NOT_IMPLEMENTED;
737 *pba_num = (u32)(data << 16);
739 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
741 DEBUGOUT("NVM Read Error\n");
746 return IXGBE_SUCCESS;
751 * @hw: pointer to the HW structure
752 * @eeprom_buf: optional pointer to EEPROM image
753 * @eeprom_buf_size: size of EEPROM image in words
754 * @max_pba_block_size: PBA block size limit
755 * @pba: pointer to output PBA structure
757 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
758 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
761 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
762 u32 eeprom_buf_size, u16 max_pba_block_size,
763 struct ixgbe_pba *pba)
769 return IXGBE_ERR_PARAM;
771 if (eeprom_buf == NULL) {
772 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
777 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
778 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
779 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
781 return IXGBE_ERR_PARAM;
785 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
786 if (pba->pba_block == NULL)
787 return IXGBE_ERR_PARAM;
789 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
795 if (pba_block_size > max_pba_block_size)
796 return IXGBE_ERR_PARAM;
798 if (eeprom_buf == NULL) {
799 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
805 if (eeprom_buf_size > (u32)(pba->word[1] +
807 memcpy(pba->pba_block,
808 &eeprom_buf[pba->word[1]],
809 pba_block_size * sizeof(u16));
811 return IXGBE_ERR_PARAM;
816 return IXGBE_SUCCESS;
820 * ixgbe_write_pba_raw
821 * @hw: pointer to the HW structure
822 * @eeprom_buf: optional pointer to EEPROM image
823 * @eeprom_buf_size: size of EEPROM image in words
824 * @pba: pointer to PBA structure
826 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
827 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
830 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
831 u32 eeprom_buf_size, struct ixgbe_pba *pba)
836 return IXGBE_ERR_PARAM;
838 if (eeprom_buf == NULL) {
839 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
844 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
845 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
846 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
848 return IXGBE_ERR_PARAM;
852 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
853 if (pba->pba_block == NULL)
854 return IXGBE_ERR_PARAM;
856 if (eeprom_buf == NULL) {
857 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
863 if (eeprom_buf_size > (u32)(pba->word[1] +
864 pba->pba_block[0])) {
865 memcpy(&eeprom_buf[pba->word[1]],
867 pba->pba_block[0] * sizeof(u16));
869 return IXGBE_ERR_PARAM;
874 return IXGBE_SUCCESS;
878 * ixgbe_get_pba_block_size
879 * @hw: pointer to the HW structure
880 * @eeprom_buf: optional pointer to EEPROM image
881 * @eeprom_buf_size: size of EEPROM image in words
882 * @pba_data_size: pointer to output variable
884 * Returns the size of the PBA block in words. Function operates on EEPROM
885 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
889 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
890 u32 eeprom_buf_size, u16 *pba_block_size)
896 DEBUGFUNC("ixgbe_get_pba_block_size");
898 if (eeprom_buf == NULL) {
899 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
904 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
905 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
906 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
908 return IXGBE_ERR_PARAM;
912 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
913 if (eeprom_buf == NULL) {
914 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
919 if (eeprom_buf_size > pba_word[1])
920 length = eeprom_buf[pba_word[1] + 0];
922 return IXGBE_ERR_PARAM;
925 if (length == 0xFFFF || length == 0)
926 return IXGBE_ERR_PBA_SECTION;
928 /* PBA number in legacy format, there is no PBA Block. */
932 if (pba_block_size != NULL)
933 *pba_block_size = length;
935 return IXGBE_SUCCESS;
939 * ixgbe_get_mac_addr_generic - Generic get MAC address
940 * @hw: pointer to hardware structure
941 * @mac_addr: Adapter MAC address
943 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
944 * A reset of the adapter must be performed prior to calling this function
945 * in order for the MAC address to have been loaded from the EEPROM into RAR0
947 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
953 DEBUGFUNC("ixgbe_get_mac_addr_generic");
955 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
956 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
958 for (i = 0; i < 4; i++)
959 mac_addr[i] = (u8)(rar_low >> (i*8));
961 for (i = 0; i < 2; i++)
962 mac_addr[i+4] = (u8)(rar_high >> (i*8));
964 return IXGBE_SUCCESS;
968 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
969 * @hw: pointer to hardware structure
970 * @link_status: the link status returned by the PCI config space
972 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
974 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
976 struct ixgbe_mac_info *mac = &hw->mac;
978 if (hw->bus.type == ixgbe_bus_type_unknown)
979 hw->bus.type = ixgbe_bus_type_pci_express;
981 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
982 case IXGBE_PCI_LINK_WIDTH_1:
983 hw->bus.width = ixgbe_bus_width_pcie_x1;
985 case IXGBE_PCI_LINK_WIDTH_2:
986 hw->bus.width = ixgbe_bus_width_pcie_x2;
988 case IXGBE_PCI_LINK_WIDTH_4:
989 hw->bus.width = ixgbe_bus_width_pcie_x4;
991 case IXGBE_PCI_LINK_WIDTH_8:
992 hw->bus.width = ixgbe_bus_width_pcie_x8;
995 hw->bus.width = ixgbe_bus_width_unknown;
999 switch (link_status & IXGBE_PCI_LINK_SPEED) {
1000 case IXGBE_PCI_LINK_SPEED_2500:
1001 hw->bus.speed = ixgbe_bus_speed_2500;
1003 case IXGBE_PCI_LINK_SPEED_5000:
1004 hw->bus.speed = ixgbe_bus_speed_5000;
1006 case IXGBE_PCI_LINK_SPEED_8000:
1007 hw->bus.speed = ixgbe_bus_speed_8000;
1010 hw->bus.speed = ixgbe_bus_speed_unknown;
1014 mac->ops.set_lan_id(hw);
1018 * ixgbe_get_bus_info_generic - Generic set PCI bus info
1019 * @hw: pointer to hardware structure
1021 * Gets the PCI bus info (speed, width, type) then calls helper function to
1022 * store this data within the ixgbe_hw structure.
1024 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
1028 DEBUGFUNC("ixgbe_get_bus_info_generic");
1030 /* Get the negotiated link width and speed from PCI config space */
1031 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
1033 ixgbe_set_pci_config_data_generic(hw, link_status);
1035 return IXGBE_SUCCESS;
1039 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
1040 * @hw: pointer to the HW structure
1042 * Determines the LAN function id by reading memory-mapped registers and swaps
1043 * the port value if requested, and set MAC instance for devices that share
1046 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
1048 struct ixgbe_bus_info *bus = &hw->bus;
1052 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
1054 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
1055 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
1056 bus->lan_id = (u8)bus->func;
1058 /* check for a port swap */
1059 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
1060 if (reg & IXGBE_FACTPS_LFS)
1063 /* Get MAC instance from EEPROM for configuring CS4227 */
1064 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) {
1065 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4);
1066 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >>
1067 IXGBE_EE_CTRL_4_INST_ID_SHIFT;
1072 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1073 * @hw: pointer to hardware structure
1075 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
1076 * disables transmit and receive units. The adapter_stopped flag is used by
1077 * the shared code and drivers to determine if the adapter is in a stopped
1078 * state and should not touch the hardware.
1080 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1085 DEBUGFUNC("ixgbe_stop_adapter_generic");
1088 * Set the adapter_stopped flag so other driver functions stop touching
1091 hw->adapter_stopped = true;
1093 /* Disable the receive unit */
1094 ixgbe_disable_rx(hw);
1096 /* Clear interrupt mask to stop interrupts from being generated */
1097 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1099 /* Clear any pending interrupts, flush previous writes */
1100 IXGBE_READ_REG(hw, IXGBE_EICR);
1102 /* Disable the transmit unit. Each queue must be disabled. */
1103 for (i = 0; i < hw->mac.max_tx_queues; i++)
1104 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1106 /* Disable the receive unit by stopping each queue */
1107 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1108 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1109 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1110 reg_val |= IXGBE_RXDCTL_SWFLSH;
1111 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1114 /* flush all queues disables */
1115 IXGBE_WRITE_FLUSH(hw);
1119 * Prevent the PCI-E bus from hanging by disabling PCI-E master
1120 * access and verify no pending requests
1122 return ixgbe_disable_pcie_master(hw);
1126 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1127 * @hw: pointer to hardware structure
1128 * @index: led number to turn on
1130 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1132 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1134 DEBUGFUNC("ixgbe_led_on_generic");
1136 /* To turn on the LED, set mode to ON. */
1137 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1138 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
1139 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1140 IXGBE_WRITE_FLUSH(hw);
1142 return IXGBE_SUCCESS;
1146 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1147 * @hw: pointer to hardware structure
1148 * @index: led number to turn off
1150 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1152 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1154 DEBUGFUNC("ixgbe_led_off_generic");
1156 /* To turn off the LED, set mode to OFF. */
1157 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1158 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
1159 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1160 IXGBE_WRITE_FLUSH(hw);
1162 return IXGBE_SUCCESS;
1166 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1167 * @hw: pointer to hardware structure
1169 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1170 * ixgbe_hw struct in order to set up EEPROM access.
1172 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1174 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1178 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
1180 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1181 eeprom->type = ixgbe_eeprom_none;
1182 /* Set default semaphore delay to 10ms which is a well
1184 eeprom->semaphore_delay = 10;
1185 /* Clear EEPROM page size, it will be initialized as needed */
1186 eeprom->word_page_size = 0;
1189 * Check for EEPROM present first.
1190 * If not present leave as none
1192 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1193 if (eec & IXGBE_EEC_PRES) {
1194 eeprom->type = ixgbe_eeprom_spi;
1197 * SPI EEPROM is assumed here. This code would need to
1198 * change if a future EEPROM is not SPI.
1200 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1201 IXGBE_EEC_SIZE_SHIFT);
1202 eeprom->word_size = 1 << (eeprom_size +
1203 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1206 if (eec & IXGBE_EEC_ADDR_SIZE)
1207 eeprom->address_bits = 16;
1209 eeprom->address_bits = 8;
1210 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
1211 "%d\n", eeprom->type, eeprom->word_size,
1212 eeprom->address_bits);
1215 return IXGBE_SUCCESS;
1219 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1220 * @hw: pointer to hardware structure
1221 * @offset: offset within the EEPROM to write
1222 * @words: number of word(s)
1223 * @data: 16 bit word(s) to write to EEPROM
1225 * Reads 16 bit word(s) from EEPROM through bit-bang method
1227 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1228 u16 words, u16 *data)
1230 s32 status = IXGBE_SUCCESS;
1233 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
1235 hw->eeprom.ops.init_params(hw);
1238 status = IXGBE_ERR_INVALID_ARGUMENT;
1242 if (offset + words > hw->eeprom.word_size) {
1243 status = IXGBE_ERR_EEPROM;
1248 * The EEPROM page size cannot be queried from the chip. We do lazy
1249 * initialization. It is worth to do that when we write large buffer.
1251 if ((hw->eeprom.word_page_size == 0) &&
1252 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
1253 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1256 * We cannot hold synchronization semaphores for too long
1257 * to avoid other entity starvation. However it is more efficient
1258 * to read in bursts than synchronizing access for each word.
1260 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1261 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1262 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1263 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1266 if (status != IXGBE_SUCCESS)
1275 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1276 * @hw: pointer to hardware structure
1277 * @offset: offset within the EEPROM to be written to
1278 * @words: number of word(s)
1279 * @data: 16 bit word(s) to be written to the EEPROM
1281 * If ixgbe_eeprom_update_checksum is not called after this function, the
1282 * EEPROM will most likely contain an invalid checksum.
1284 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1285 u16 words, u16 *data)
1291 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1293 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1295 /* Prepare the EEPROM for writing */
1296 status = ixgbe_acquire_eeprom(hw);
1298 if (status == IXGBE_SUCCESS) {
1299 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1300 ixgbe_release_eeprom(hw);
1301 status = IXGBE_ERR_EEPROM;
1305 if (status == IXGBE_SUCCESS) {
1306 for (i = 0; i < words; i++) {
1307 ixgbe_standby_eeprom(hw);
1309 /* Send the WRITE ENABLE command (8 bit opcode ) */
1310 ixgbe_shift_out_eeprom_bits(hw,
1311 IXGBE_EEPROM_WREN_OPCODE_SPI,
1312 IXGBE_EEPROM_OPCODE_BITS);
1314 ixgbe_standby_eeprom(hw);
1317 * Some SPI eeproms use the 8th address bit embedded
1320 if ((hw->eeprom.address_bits == 8) &&
1321 ((offset + i) >= 128))
1322 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1324 /* Send the Write command (8-bit opcode + addr) */
1325 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1326 IXGBE_EEPROM_OPCODE_BITS);
1327 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1328 hw->eeprom.address_bits);
1330 page_size = hw->eeprom.word_page_size;
1332 /* Send the data in burst via SPI*/
1335 word = (word >> 8) | (word << 8);
1336 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1341 /* do not wrap around page */
1342 if (((offset + i) & (page_size - 1)) ==
1345 } while (++i < words);
1347 ixgbe_standby_eeprom(hw);
1350 /* Done with writing - release the EEPROM */
1351 ixgbe_release_eeprom(hw);
1358 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1359 * @hw: pointer to hardware structure
1360 * @offset: offset within the EEPROM to be written to
1361 * @data: 16 bit word to be written to the EEPROM
1363 * If ixgbe_eeprom_update_checksum is not called after this function, the
1364 * EEPROM will most likely contain an invalid checksum.
1366 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1370 DEBUGFUNC("ixgbe_write_eeprom_generic");
1372 hw->eeprom.ops.init_params(hw);
1374 if (offset >= hw->eeprom.word_size) {
1375 status = IXGBE_ERR_EEPROM;
1379 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1386 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1387 * @hw: pointer to hardware structure
1388 * @offset: offset within the EEPROM to be read
1389 * @data: read 16 bit words(s) from EEPROM
1390 * @words: number of word(s)
1392 * Reads 16 bit word(s) from EEPROM through bit-bang method
1394 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1395 u16 words, u16 *data)
1397 s32 status = IXGBE_SUCCESS;
1400 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1402 hw->eeprom.ops.init_params(hw);
1405 status = IXGBE_ERR_INVALID_ARGUMENT;
1409 if (offset + words > hw->eeprom.word_size) {
1410 status = IXGBE_ERR_EEPROM;
1415 * We cannot hold synchronization semaphores for too long
1416 * to avoid other entity starvation. However it is more efficient
1417 * to read in bursts than synchronizing access for each word.
1419 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1420 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1421 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1423 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1426 if (status != IXGBE_SUCCESS)
1435 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1436 * @hw: pointer to hardware structure
1437 * @offset: offset within the EEPROM to be read
1438 * @words: number of word(s)
1439 * @data: read 16 bit word(s) from EEPROM
1441 * Reads 16 bit word(s) from EEPROM through bit-bang method
1443 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1444 u16 words, u16 *data)
1448 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1451 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1453 /* Prepare the EEPROM for reading */
1454 status = ixgbe_acquire_eeprom(hw);
1456 if (status == IXGBE_SUCCESS) {
1457 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1458 ixgbe_release_eeprom(hw);
1459 status = IXGBE_ERR_EEPROM;
1463 if (status == IXGBE_SUCCESS) {
1464 for (i = 0; i < words; i++) {
1465 ixgbe_standby_eeprom(hw);
1467 * Some SPI eeproms use the 8th address bit embedded
1470 if ((hw->eeprom.address_bits == 8) &&
1471 ((offset + i) >= 128))
1472 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1474 /* Send the READ command (opcode + addr) */
1475 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1476 IXGBE_EEPROM_OPCODE_BITS);
1477 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1478 hw->eeprom.address_bits);
1480 /* Read the data. */
1481 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1482 data[i] = (word_in >> 8) | (word_in << 8);
1485 /* End this read operation */
1486 ixgbe_release_eeprom(hw);
1493 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1494 * @hw: pointer to hardware structure
1495 * @offset: offset within the EEPROM to be read
1496 * @data: read 16 bit value from EEPROM
1498 * Reads 16 bit value from EEPROM through bit-bang method
1500 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1505 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1507 hw->eeprom.ops.init_params(hw);
1509 if (offset >= hw->eeprom.word_size) {
1510 status = IXGBE_ERR_EEPROM;
1514 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1521 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1522 * @hw: pointer to hardware structure
1523 * @offset: offset of word in the EEPROM to read
1524 * @words: number of word(s)
1525 * @data: 16 bit word(s) from the EEPROM
1527 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1529 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1530 u16 words, u16 *data)
1533 s32 status = IXGBE_SUCCESS;
1536 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1538 hw->eeprom.ops.init_params(hw);
1541 status = IXGBE_ERR_INVALID_ARGUMENT;
1542 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1546 if (offset >= hw->eeprom.word_size) {
1547 status = IXGBE_ERR_EEPROM;
1548 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1552 for (i = 0; i < words; i++) {
1553 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1554 IXGBE_EEPROM_RW_REG_START;
1556 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1557 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1559 if (status == IXGBE_SUCCESS) {
1560 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1561 IXGBE_EEPROM_RW_REG_DATA);
1563 DEBUGOUT("Eeprom read timed out\n");
1572 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1573 * @hw: pointer to hardware structure
1574 * @offset: offset within the EEPROM to be used as a scratch pad
1576 * Discover EEPROM page size by writing marching data at given offset.
1577 * This function is called only when we are writing a new large buffer
1578 * at given offset so the data would be overwritten anyway.
1580 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1583 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1584 s32 status = IXGBE_SUCCESS;
1587 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1589 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1592 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1593 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1594 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1595 hw->eeprom.word_page_size = 0;
1596 if (status != IXGBE_SUCCESS)
1599 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1600 if (status != IXGBE_SUCCESS)
1604 * When writing in burst more than the actual page size
1605 * EEPROM address wraps around current page.
1607 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1609 DEBUGOUT1("Detected EEPROM page size = %d words.",
1610 hw->eeprom.word_page_size);
1616 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1617 * @hw: pointer to hardware structure
1618 * @offset: offset of word in the EEPROM to read
1619 * @data: word read from the EEPROM
1621 * Reads a 16 bit word from the EEPROM using the EERD register.
1623 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1625 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1629 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1630 * @hw: pointer to hardware structure
1631 * @offset: offset of word in the EEPROM to write
1632 * @words: number of word(s)
1633 * @data: word(s) write to the EEPROM
1635 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1637 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1638 u16 words, u16 *data)
1641 s32 status = IXGBE_SUCCESS;
1644 DEBUGFUNC("ixgbe_write_eewr_generic");
1646 hw->eeprom.ops.init_params(hw);
1649 status = IXGBE_ERR_INVALID_ARGUMENT;
1650 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1654 if (offset >= hw->eeprom.word_size) {
1655 status = IXGBE_ERR_EEPROM;
1656 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1660 for (i = 0; i < words; i++) {
1661 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1662 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1663 IXGBE_EEPROM_RW_REG_START;
1665 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1666 if (status != IXGBE_SUCCESS) {
1667 DEBUGOUT("Eeprom write EEWR timed out\n");
1671 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1673 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1674 if (status != IXGBE_SUCCESS) {
1675 DEBUGOUT("Eeprom write EEWR timed out\n");
1685 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1686 * @hw: pointer to hardware structure
1687 * @offset: offset of word in the EEPROM to write
1688 * @data: word write to the EEPROM
1690 * Write a 16 bit word to the EEPROM using the EEWR register.
1692 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1694 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1698 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1699 * @hw: pointer to hardware structure
1700 * @ee_reg: EEPROM flag for polling
1702 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1703 * read or write is done respectively.
1705 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1709 s32 status = IXGBE_ERR_EEPROM;
1711 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1713 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1714 if (ee_reg == IXGBE_NVM_POLL_READ)
1715 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1717 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1719 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1720 status = IXGBE_SUCCESS;
1726 if (i == IXGBE_EERD_EEWR_ATTEMPTS)
1727 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1728 "EEPROM read/write done polling timed out");
1734 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1735 * @hw: pointer to hardware structure
1737 * Prepares EEPROM for access using bit-bang method. This function should
1738 * be called before issuing a command to the EEPROM.
1740 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1742 s32 status = IXGBE_SUCCESS;
1746 DEBUGFUNC("ixgbe_acquire_eeprom");
1748 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1750 status = IXGBE_ERR_SWFW_SYNC;
1752 if (status == IXGBE_SUCCESS) {
1753 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1755 /* Request EEPROM Access */
1756 eec |= IXGBE_EEC_REQ;
1757 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1759 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1760 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1761 if (eec & IXGBE_EEC_GNT)
1766 /* Release if grant not acquired */
1767 if (!(eec & IXGBE_EEC_GNT)) {
1768 eec &= ~IXGBE_EEC_REQ;
1769 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1770 DEBUGOUT("Could not acquire EEPROM grant\n");
1772 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1773 status = IXGBE_ERR_EEPROM;
1776 /* Setup EEPROM for Read/Write */
1777 if (status == IXGBE_SUCCESS) {
1778 /* Clear CS and SK */
1779 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1780 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1781 IXGBE_WRITE_FLUSH(hw);
1789 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1790 * @hw: pointer to hardware structure
1792 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1794 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1796 s32 status = IXGBE_ERR_EEPROM;
1801 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1804 /* Get SMBI software semaphore between device drivers first */
1805 for (i = 0; i < timeout; i++) {
1807 * If the SMBI bit is 0 when we read it, then the bit will be
1808 * set and we have the semaphore
1810 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1811 if (!(swsm & IXGBE_SWSM_SMBI)) {
1812 status = IXGBE_SUCCESS;
1819 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1822 * this release is particularly important because our attempts
1823 * above to get the semaphore may have succeeded, and if there
1824 * was a timeout, we should unconditionally clear the semaphore
1825 * bits to free the driver to make progress
1827 ixgbe_release_eeprom_semaphore(hw);
1832 * If the SMBI bit is 0 when we read it, then the bit will be
1833 * set and we have the semaphore
1835 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1836 if (!(swsm & IXGBE_SWSM_SMBI))
1837 status = IXGBE_SUCCESS;
1840 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1841 if (status == IXGBE_SUCCESS) {
1842 for (i = 0; i < timeout; i++) {
1843 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1845 /* Set the SW EEPROM semaphore bit to request access */
1846 swsm |= IXGBE_SWSM_SWESMBI;
1847 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
1850 * If we set the bit successfully then we got the
1853 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1854 if (swsm & IXGBE_SWSM_SWESMBI)
1861 * Release semaphores and return error if SW EEPROM semaphore
1862 * was not granted because we don't have access to the EEPROM
1865 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1866 "SWESMBI Software EEPROM semaphore not granted.\n");
1867 ixgbe_release_eeprom_semaphore(hw);
1868 status = IXGBE_ERR_EEPROM;
1871 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1872 "Software semaphore SMBI between device drivers "
1880 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1881 * @hw: pointer to hardware structure
1883 * This function clears hardware semaphore bits.
1885 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1889 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1891 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1893 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1894 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1895 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1896 IXGBE_WRITE_FLUSH(hw);
1900 * ixgbe_ready_eeprom - Polls for EEPROM ready
1901 * @hw: pointer to hardware structure
1903 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1905 s32 status = IXGBE_SUCCESS;
1909 DEBUGFUNC("ixgbe_ready_eeprom");
1912 * Read "Status Register" repeatedly until the LSB is cleared. The
1913 * EEPROM will signal that the command has been completed by clearing
1914 * bit 0 of the internal status register. If it's not cleared within
1915 * 5 milliseconds, then error out.
1917 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1918 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1919 IXGBE_EEPROM_OPCODE_BITS);
1920 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1921 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1925 ixgbe_standby_eeprom(hw);
1929 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1930 * devices (and only 0-5mSec on 5V devices)
1932 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1933 DEBUGOUT("SPI EEPROM Status error\n");
1934 status = IXGBE_ERR_EEPROM;
1941 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1942 * @hw: pointer to hardware structure
1944 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1948 DEBUGFUNC("ixgbe_standby_eeprom");
1950 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1952 /* Toggle CS to flush commands */
1953 eec |= IXGBE_EEC_CS;
1954 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1955 IXGBE_WRITE_FLUSH(hw);
1957 eec &= ~IXGBE_EEC_CS;
1958 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1959 IXGBE_WRITE_FLUSH(hw);
1964 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1965 * @hw: pointer to hardware structure
1966 * @data: data to send to the EEPROM
1967 * @count: number of bits to shift out
1969 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1976 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
1978 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1981 * Mask is used to shift "count" bits of "data" out to the EEPROM
1982 * one bit at a time. Determine the starting bit based on count
1984 mask = 0x01 << (count - 1);
1986 for (i = 0; i < count; i++) {
1988 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1989 * "1", and then raising and then lowering the clock (the SK
1990 * bit controls the clock input to the EEPROM). A "0" is
1991 * shifted out to the EEPROM by setting "DI" to "0" and then
1992 * raising and then lowering the clock.
1995 eec |= IXGBE_EEC_DI;
1997 eec &= ~IXGBE_EEC_DI;
1999 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2000 IXGBE_WRITE_FLUSH(hw);
2004 ixgbe_raise_eeprom_clk(hw, &eec);
2005 ixgbe_lower_eeprom_clk(hw, &eec);
2008 * Shift mask to signify next bit of data to shift in to the
2014 /* We leave the "DI" bit set to "0" when we leave this routine. */
2015 eec &= ~IXGBE_EEC_DI;
2016 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2017 IXGBE_WRITE_FLUSH(hw);
2021 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
2022 * @hw: pointer to hardware structure
2024 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
2030 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
2033 * In order to read a register from the EEPROM, we need to shift
2034 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
2035 * the clock input to the EEPROM (setting the SK bit), and then reading
2036 * the value of the "DO" bit. During this "shifting in" process the
2037 * "DI" bit should always be clear.
2039 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2041 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
2043 for (i = 0; i < count; i++) {
2045 ixgbe_raise_eeprom_clk(hw, &eec);
2047 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2049 eec &= ~(IXGBE_EEC_DI);
2050 if (eec & IXGBE_EEC_DO)
2053 ixgbe_lower_eeprom_clk(hw, &eec);
2060 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
2061 * @hw: pointer to hardware structure
2062 * @eec: EEC register's current value
2064 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2066 DEBUGFUNC("ixgbe_raise_eeprom_clk");
2069 * Raise the clock input to the EEPROM
2070 * (setting the SK bit), then delay
2072 *eec = *eec | IXGBE_EEC_SK;
2073 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2074 IXGBE_WRITE_FLUSH(hw);
2079 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2080 * @hw: pointer to hardware structure
2081 * @eecd: EECD's current value
2083 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2085 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2088 * Lower the clock input to the EEPROM (clearing the SK bit), then
2091 *eec = *eec & ~IXGBE_EEC_SK;
2092 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2093 IXGBE_WRITE_FLUSH(hw);
2098 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2099 * @hw: pointer to hardware structure
2101 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2105 DEBUGFUNC("ixgbe_release_eeprom");
2107 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2109 eec |= IXGBE_EEC_CS; /* Pull CS high */
2110 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
2112 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2113 IXGBE_WRITE_FLUSH(hw);
2117 /* Stop requesting EEPROM access */
2118 eec &= ~IXGBE_EEC_REQ;
2119 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2121 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2123 /* Delay before attempt to obtain semaphore again to allow FW access */
2124 msec_delay(hw->eeprom.semaphore_delay);
2128 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2129 * @hw: pointer to hardware structure
2131 * Returns a negative error code on error, or the 16-bit checksum
2133 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2142 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
2144 /* Include 0x0-0x3F in the checksum */
2145 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
2146 if (hw->eeprom.ops.read(hw, i, &word)) {
2147 DEBUGOUT("EEPROM read failed\n");
2148 return IXGBE_ERR_EEPROM;
2153 /* Include all data from pointers except for the fw pointer */
2154 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
2155 if (hw->eeprom.ops.read(hw, i, &pointer)) {
2156 DEBUGOUT("EEPROM read failed\n");
2157 return IXGBE_ERR_EEPROM;
2160 /* If the pointer seems invalid */
2161 if (pointer == 0xFFFF || pointer == 0)
2164 if (hw->eeprom.ops.read(hw, pointer, &length)) {
2165 DEBUGOUT("EEPROM read failed\n");
2166 return IXGBE_ERR_EEPROM;
2169 if (length == 0xFFFF || length == 0)
2172 for (j = pointer + 1; j <= pointer + length; j++) {
2173 if (hw->eeprom.ops.read(hw, j, &word)) {
2174 DEBUGOUT("EEPROM read failed\n");
2175 return IXGBE_ERR_EEPROM;
2181 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2183 return (s32)checksum;
2187 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2188 * @hw: pointer to hardware structure
2189 * @checksum_val: calculated checksum
2191 * Performs checksum calculation and validates the EEPROM checksum. If the
2192 * caller does not need checksum_val, the value can be NULL.
2194 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2199 u16 read_checksum = 0;
2201 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
2203 /* Read the first word from the EEPROM. If this times out or fails, do
2204 * not continue or we could be in for a very long wait while every
2207 status = hw->eeprom.ops.read(hw, 0, &checksum);
2209 DEBUGOUT("EEPROM read failed\n");
2213 status = hw->eeprom.ops.calc_checksum(hw);
2217 checksum = (u16)(status & 0xffff);
2219 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2221 DEBUGOUT("EEPROM read failed\n");
2225 /* Verify read checksum from EEPROM is the same as
2226 * calculated checksum
2228 if (read_checksum != checksum)
2229 status = IXGBE_ERR_EEPROM_CHECKSUM;
2231 /* If the user cares, return the calculated checksum */
2233 *checksum_val = checksum;
2239 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2240 * @hw: pointer to hardware structure
2242 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2247 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
2249 /* Read the first word from the EEPROM. If this times out or fails, do
2250 * not continue or we could be in for a very long wait while every
2253 status = hw->eeprom.ops.read(hw, 0, &checksum);
2255 DEBUGOUT("EEPROM read failed\n");
2259 status = hw->eeprom.ops.calc_checksum(hw);
2263 checksum = (u16)(status & 0xffff);
2265 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
2271 * ixgbe_validate_mac_addr - Validate MAC address
2272 * @mac_addr: pointer to MAC address.
2274 * Tests a MAC address to ensure it is a valid Individual Address.
2276 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
2278 s32 status = IXGBE_SUCCESS;
2280 DEBUGFUNC("ixgbe_validate_mac_addr");
2282 /* Make sure it is not a multicast address */
2283 if (IXGBE_IS_MULTICAST(mac_addr)) {
2284 status = IXGBE_ERR_INVALID_MAC_ADDR;
2285 /* Not a broadcast address */
2286 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
2287 status = IXGBE_ERR_INVALID_MAC_ADDR;
2288 /* Reject the zero address */
2289 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
2290 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
2291 status = IXGBE_ERR_INVALID_MAC_ADDR;
2297 * ixgbe_set_rar_generic - Set Rx address register
2298 * @hw: pointer to hardware structure
2299 * @index: Receive address register to write
2300 * @addr: Address to put into receive address register
2301 * @vmdq: VMDq "set" or "pool" index
2302 * @enable_addr: set flag that address is active
2304 * Puts an ethernet address into a receive address register.
2306 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2309 u32 rar_low, rar_high;
2310 u32 rar_entries = hw->mac.num_rar_entries;
2312 DEBUGFUNC("ixgbe_set_rar_generic");
2314 /* Make sure we are using a valid rar index range */
2315 if (index >= rar_entries) {
2316 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2317 "RAR index %d is out of range.\n", index);
2318 return IXGBE_ERR_INVALID_ARGUMENT;
2321 /* setup VMDq pool selection before this RAR gets enabled */
2322 hw->mac.ops.set_vmdq(hw, index, vmdq);
2325 * HW expects these in little endian so we reverse the byte
2326 * order from network order (big endian) to little endian
2328 rar_low = ((u32)addr[0] |
2329 ((u32)addr[1] << 8) |
2330 ((u32)addr[2] << 16) |
2331 ((u32)addr[3] << 24));
2333 * Some parts put the VMDq setting in the extra RAH bits,
2334 * so save everything except the lower 16 bits that hold part
2335 * of the address and the address valid bit.
2337 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2338 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2339 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2341 if (enable_addr != 0)
2342 rar_high |= IXGBE_RAH_AV;
2344 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2345 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2347 return IXGBE_SUCCESS;
2351 * ixgbe_clear_rar_generic - Remove Rx address register
2352 * @hw: pointer to hardware structure
2353 * @index: Receive address register to write
2355 * Clears an ethernet address from a receive address register.
2357 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2360 u32 rar_entries = hw->mac.num_rar_entries;
2362 DEBUGFUNC("ixgbe_clear_rar_generic");
2364 /* Make sure we are using a valid rar index range */
2365 if (index >= rar_entries) {
2366 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2367 "RAR index %d is out of range.\n", index);
2368 return IXGBE_ERR_INVALID_ARGUMENT;
2372 * Some parts put the VMDq setting in the extra RAH bits,
2373 * so save everything except the lower 16 bits that hold part
2374 * of the address and the address valid bit.
2376 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2377 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2379 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2380 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2382 /* clear VMDq pool/queue selection for this RAR */
2383 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2385 return IXGBE_SUCCESS;
2389 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2390 * @hw: pointer to hardware structure
2392 * Places the MAC address in receive address register 0 and clears the rest
2393 * of the receive address registers. Clears the multicast table. Assumes
2394 * the receiver is in reset when the routine is called.
2396 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2399 u32 rar_entries = hw->mac.num_rar_entries;
2401 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2404 * If the current mac address is valid, assume it is a software override
2405 * to the permanent address.
2406 * Otherwise, use the permanent address from the eeprom.
2408 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2409 IXGBE_ERR_INVALID_MAC_ADDR) {
2410 /* Get the MAC address from the RAR0 for later reference */
2411 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2413 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2414 hw->mac.addr[0], hw->mac.addr[1],
2416 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2417 hw->mac.addr[4], hw->mac.addr[5]);
2419 /* Setup the receive address. */
2420 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2421 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2422 hw->mac.addr[0], hw->mac.addr[1],
2424 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2425 hw->mac.addr[4], hw->mac.addr[5]);
2427 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2430 /* clear VMDq pool/queue selection for RAR 0 */
2431 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2433 hw->addr_ctrl.overflow_promisc = 0;
2435 hw->addr_ctrl.rar_used_count = 1;
2437 /* Zero out the other receive addresses. */
2438 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2439 for (i = 1; i < rar_entries; i++) {
2440 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2441 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2445 hw->addr_ctrl.mta_in_use = 0;
2446 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2448 DEBUGOUT(" Clearing MTA\n");
2449 for (i = 0; i < hw->mac.mcft_size; i++)
2450 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2452 ixgbe_init_uta_tables(hw);
2454 return IXGBE_SUCCESS;
2458 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2459 * @hw: pointer to hardware structure
2460 * @addr: new address
2462 * Adds it to unused receive address register or goes into promiscuous mode.
2464 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2466 u32 rar_entries = hw->mac.num_rar_entries;
2469 DEBUGFUNC("ixgbe_add_uc_addr");
2471 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2472 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2475 * Place this address in the RAR if there is room,
2476 * else put the controller into promiscuous mode
2478 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2479 rar = hw->addr_ctrl.rar_used_count;
2480 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2481 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2482 hw->addr_ctrl.rar_used_count++;
2484 hw->addr_ctrl.overflow_promisc++;
2487 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2491 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2492 * @hw: pointer to hardware structure
2493 * @addr_list: the list of new addresses
2494 * @addr_count: number of addresses
2495 * @next: iterator function to walk the address list
2497 * The given list replaces any existing list. Clears the secondary addrs from
2498 * receive address registers. Uses unused receive address registers for the
2499 * first secondary addresses, and falls back to promiscuous mode as needed.
2501 * Drivers using secondary unicast addresses must set user_set_promisc when
2502 * manually putting the device into promiscuous mode.
2504 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2505 u32 addr_count, ixgbe_mc_addr_itr next)
2509 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2514 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2517 * Clear accounting of old secondary address list,
2518 * don't count RAR[0]
2520 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2521 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2522 hw->addr_ctrl.overflow_promisc = 0;
2524 /* Zero out the other receive addresses */
2525 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2526 for (i = 0; i < uc_addr_in_use; i++) {
2527 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2528 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2531 /* Add the new addresses */
2532 for (i = 0; i < addr_count; i++) {
2533 DEBUGOUT(" Adding the secondary addresses:\n");
2534 addr = next(hw, &addr_list, &vmdq);
2535 ixgbe_add_uc_addr(hw, addr, vmdq);
2538 if (hw->addr_ctrl.overflow_promisc) {
2539 /* enable promisc if not already in overflow or set by user */
2540 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2541 DEBUGOUT(" Entering address overflow promisc mode\n");
2542 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2543 fctrl |= IXGBE_FCTRL_UPE;
2544 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2547 /* only disable if set by overflow, not by user */
2548 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2549 DEBUGOUT(" Leaving address overflow promisc mode\n");
2550 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2551 fctrl &= ~IXGBE_FCTRL_UPE;
2552 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2556 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2557 return IXGBE_SUCCESS;
2561 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2562 * @hw: pointer to hardware structure
2563 * @mc_addr: the multicast address
2565 * Extracts the 12 bits, from a multicast address, to determine which
2566 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2567 * incoming rx multicast addresses, to determine the bit-vector to check in
2568 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2569 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2570 * to mc_filter_type.
2572 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2576 DEBUGFUNC("ixgbe_mta_vector");
2578 switch (hw->mac.mc_filter_type) {
2579 case 0: /* use bits [47:36] of the address */
2580 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2582 case 1: /* use bits [46:35] of the address */
2583 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2585 case 2: /* use bits [45:34] of the address */
2586 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2588 case 3: /* use bits [43:32] of the address */
2589 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2591 default: /* Invalid mc_filter_type */
2592 DEBUGOUT("MC filter type param set incorrectly\n");
2597 /* vector can only be 12-bits or boundary will be exceeded */
2603 * ixgbe_set_mta - Set bit-vector in multicast table
2604 * @hw: pointer to hardware structure
2605 * @hash_value: Multicast address hash value
2607 * Sets the bit-vector in the multicast table.
2609 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2615 DEBUGFUNC("ixgbe_set_mta");
2617 hw->addr_ctrl.mta_in_use++;
2619 vector = ixgbe_mta_vector(hw, mc_addr);
2620 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2623 * The MTA is a register array of 128 32-bit registers. It is treated
2624 * like an array of 4096 bits. We want to set bit
2625 * BitArray[vector_value]. So we figure out what register the bit is
2626 * in, read it, OR in the new bit, then write back the new value. The
2627 * register is determined by the upper 7 bits of the vector value and
2628 * the bit within that register are determined by the lower 5 bits of
2631 vector_reg = (vector >> 5) & 0x7F;
2632 vector_bit = vector & 0x1F;
2633 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2637 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2638 * @hw: pointer to hardware structure
2639 * @mc_addr_list: the list of new multicast addresses
2640 * @mc_addr_count: number of addresses
2641 * @next: iterator function to walk the multicast address list
2642 * @clear: flag, when set clears the table beforehand
2644 * When the clear flag is set, the given list replaces any existing list.
2645 * Hashes the given addresses into the multicast table.
2647 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2648 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2654 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2657 * Set the new number of MC addresses that we are being requested to
2660 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2661 hw->addr_ctrl.mta_in_use = 0;
2663 /* Clear mta_shadow */
2665 DEBUGOUT(" Clearing MTA\n");
2666 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2669 /* Update mta_shadow */
2670 for (i = 0; i < mc_addr_count; i++) {
2671 DEBUGOUT(" Adding the multicast addresses:\n");
2672 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2676 for (i = 0; i < hw->mac.mcft_size; i++)
2677 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2678 hw->mac.mta_shadow[i]);
2680 if (hw->addr_ctrl.mta_in_use > 0)
2681 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2682 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2684 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2685 return IXGBE_SUCCESS;
2689 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2690 * @hw: pointer to hardware structure
2692 * Enables multicast address in RAR and the use of the multicast hash table.
2694 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2696 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2698 DEBUGFUNC("ixgbe_enable_mc_generic");
2700 if (a->mta_in_use > 0)
2701 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2702 hw->mac.mc_filter_type);
2704 return IXGBE_SUCCESS;
2708 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2709 * @hw: pointer to hardware structure
2711 * Disables multicast address in RAR and the use of the multicast hash table.
2713 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2715 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2717 DEBUGFUNC("ixgbe_disable_mc_generic");
2719 if (a->mta_in_use > 0)
2720 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2722 return IXGBE_SUCCESS;
2726 * ixgbe_fc_enable_generic - Enable flow control
2727 * @hw: pointer to hardware structure
2729 * Enable flow control according to the current settings.
2731 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2733 s32 ret_val = IXGBE_SUCCESS;
2734 u32 mflcn_reg, fccfg_reg;
2739 DEBUGFUNC("ixgbe_fc_enable_generic");
2741 /* Validate the water mark configuration */
2742 if (!hw->fc.pause_time) {
2743 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2747 /* Low water mark of zero causes XOFF floods */
2748 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2749 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2750 hw->fc.high_water[i]) {
2751 if (!hw->fc.low_water[i] ||
2752 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2753 DEBUGOUT("Invalid water mark configuration\n");
2754 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2760 /* Negotiate the fc mode to use */
2761 hw->mac.ops.fc_autoneg(hw);
2763 /* Disable any previous flow control settings */
2764 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2765 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2767 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2768 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2771 * The possible values of fc.current_mode are:
2772 * 0: Flow control is completely disabled
2773 * 1: Rx flow control is enabled (we can receive pause frames,
2774 * but not send pause frames).
2775 * 2: Tx flow control is enabled (we can send pause frames but
2776 * we do not support receiving pause frames).
2777 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2780 switch (hw->fc.current_mode) {
2783 * Flow control is disabled by software override or autoneg.
2784 * The code below will actually disable it in the HW.
2787 case ixgbe_fc_rx_pause:
2789 * Rx Flow control is enabled and Tx Flow control is
2790 * disabled by software override. Since there really
2791 * isn't a way to advertise that we are capable of RX
2792 * Pause ONLY, we will advertise that we support both
2793 * symmetric and asymmetric Rx PAUSE. Later, we will
2794 * disable the adapter's ability to send PAUSE frames.
2796 mflcn_reg |= IXGBE_MFLCN_RFCE;
2798 case ixgbe_fc_tx_pause:
2800 * Tx Flow control is enabled, and Rx Flow control is
2801 * disabled by software override.
2803 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2806 /* Flow control (both Rx and Tx) is enabled by SW override. */
2807 mflcn_reg |= IXGBE_MFLCN_RFCE;
2808 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2811 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2812 "Flow control param set incorrectly\n");
2813 ret_val = IXGBE_ERR_CONFIG;
2818 /* Set 802.3x based flow control settings. */
2819 mflcn_reg |= IXGBE_MFLCN_DPF;
2820 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2821 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2824 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2825 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2826 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2827 hw->fc.high_water[i]) {
2828 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2829 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2830 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2832 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2834 * In order to prevent Tx hangs when the internal Tx
2835 * switch is enabled we must set the high water mark
2836 * to the Rx packet buffer size - 24KB. This allows
2837 * the Tx switch to function even under heavy Rx
2840 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2843 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2846 /* Configure pause time (2 TCs per register) */
2847 reg = hw->fc.pause_time * 0x00010001;
2848 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2849 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2851 /* Configure flow control refresh threshold value */
2852 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2859 * ixgbe_negotiate_fc - Negotiate flow control
2860 * @hw: pointer to hardware structure
2861 * @adv_reg: flow control advertised settings
2862 * @lp_reg: link partner's flow control settings
2863 * @adv_sym: symmetric pause bit in advertisement
2864 * @adv_asm: asymmetric pause bit in advertisement
2865 * @lp_sym: symmetric pause bit in link partner advertisement
2866 * @lp_asm: asymmetric pause bit in link partner advertisement
2868 * Find the intersection between advertised settings and link partner's
2869 * advertised settings
2871 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2872 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2874 if ((!(adv_reg)) || (!(lp_reg))) {
2875 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
2876 "Local or link partner's advertised flow control "
2877 "settings are NULL. Local: %x, link partner: %x\n",
2879 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2882 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2884 * Now we need to check if the user selected Rx ONLY
2885 * of pause frames. In this case, we had to advertise
2886 * FULL flow control because we could not advertise RX
2887 * ONLY. Hence, we must now check to see if we need to
2888 * turn OFF the TRANSMISSION of PAUSE frames.
2890 if (hw->fc.requested_mode == ixgbe_fc_full) {
2891 hw->fc.current_mode = ixgbe_fc_full;
2892 DEBUGOUT("Flow Control = FULL.\n");
2894 hw->fc.current_mode = ixgbe_fc_rx_pause;
2895 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2897 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2898 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2899 hw->fc.current_mode = ixgbe_fc_tx_pause;
2900 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2901 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2902 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2903 hw->fc.current_mode = ixgbe_fc_rx_pause;
2904 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2906 hw->fc.current_mode = ixgbe_fc_none;
2907 DEBUGOUT("Flow Control = NONE.\n");
2909 return IXGBE_SUCCESS;
2913 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2914 * @hw: pointer to hardware structure
2916 * Enable flow control according on 1 gig fiber.
2918 STATIC s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2920 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2921 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2924 * On multispeed fiber at 1g, bail out if
2925 * - link is up but AN did not complete, or if
2926 * - link is up and AN completed but timed out
2929 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2930 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2931 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
2932 DEBUGOUT("Auto-Negotiation did not complete or timed out\n");
2936 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2937 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2939 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2940 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2941 IXGBE_PCS1GANA_ASM_PAUSE,
2942 IXGBE_PCS1GANA_SYM_PAUSE,
2943 IXGBE_PCS1GANA_ASM_PAUSE);
2950 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2951 * @hw: pointer to hardware structure
2953 * Enable flow control according to IEEE clause 37.
2955 STATIC s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2957 u32 links2, anlp1_reg, autoc_reg, links;
2958 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2961 * On backplane, bail out if
2962 * - backplane autoneg was not completed, or if
2963 * - we are 82599 and link partner is not AN enabled
2965 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2966 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
2967 DEBUGOUT("Auto-Negotiation did not complete\n");
2971 if (hw->mac.type == ixgbe_mac_82599EB) {
2972 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2973 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
2974 DEBUGOUT("Link partner is not AN enabled\n");
2979 * Read the 10g AN autoc and LP ability registers and resolve
2980 * local flow control settings accordingly
2982 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2983 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2985 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2986 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2987 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2994 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2995 * @hw: pointer to hardware structure
2997 * Enable flow control according to IEEE clause 37.
2999 STATIC s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
3001 u16 technology_ability_reg = 0;
3002 u16 lp_technology_ability_reg = 0;
3004 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
3005 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3006 &technology_ability_reg);
3007 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
3008 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3009 &lp_technology_ability_reg);
3011 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
3012 (u32)lp_technology_ability_reg,
3013 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
3014 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
3018 * ixgbe_fc_autoneg - Configure flow control
3019 * @hw: pointer to hardware structure
3021 * Compares our advertised flow control capabilities to those advertised by
3022 * our link partner, and determines the proper flow control mode to use.
3024 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
3026 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3027 ixgbe_link_speed speed;
3030 DEBUGFUNC("ixgbe_fc_autoneg");
3033 * AN should have completed when the cable was plugged in.
3034 * Look for reasons to bail out. Bail out if:
3035 * - FC autoneg is disabled, or if
3038 if (hw->fc.disable_fc_autoneg) {
3039 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3040 "Flow control autoneg is disabled");
3044 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3046 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3050 switch (hw->phy.media_type) {
3051 /* Autoneg flow control on fiber adapters */
3052 case ixgbe_media_type_fiber_qsfp:
3053 case ixgbe_media_type_fiber:
3054 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
3055 ret_val = ixgbe_fc_autoneg_fiber(hw);
3058 /* Autoneg flow control on backplane adapters */
3059 case ixgbe_media_type_backplane:
3060 ret_val = ixgbe_fc_autoneg_backplane(hw);
3063 /* Autoneg flow control on copper adapters */
3064 case ixgbe_media_type_copper:
3065 if (ixgbe_device_supports_autoneg_fc(hw))
3066 ret_val = ixgbe_fc_autoneg_copper(hw);
3074 if (ret_val == IXGBE_SUCCESS) {
3075 hw->fc.fc_was_autonegged = true;
3077 hw->fc.fc_was_autonegged = false;
3078 hw->fc.current_mode = hw->fc.requested_mode;
3083 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3084 * @hw: pointer to hardware structure
3086 * System-wide timeout range is encoded in PCIe Device Control2 register.
3088 * Add 10% to specified maximum and return the number of times to poll for
3089 * completion timeout, in units of 100 microsec. Never return less than
3090 * 800 = 80 millisec.
3092 STATIC u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3097 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3098 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
3101 case IXGBE_PCIDEVCTRL2_65_130ms:
3102 pollcnt = 1300; /* 130 millisec */
3104 case IXGBE_PCIDEVCTRL2_260_520ms:
3105 pollcnt = 5200; /* 520 millisec */
3107 case IXGBE_PCIDEVCTRL2_1_2s:
3108 pollcnt = 20000; /* 2 sec */
3110 case IXGBE_PCIDEVCTRL2_4_8s:
3111 pollcnt = 80000; /* 8 sec */
3113 case IXGBE_PCIDEVCTRL2_17_34s:
3114 pollcnt = 34000; /* 34 sec */
3116 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
3117 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
3118 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
3119 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
3121 pollcnt = 800; /* 80 millisec minimum */
3125 /* add 10% to spec maximum */
3126 return (pollcnt * 11) / 10;
3130 * ixgbe_disable_pcie_master - Disable PCI-express master access
3131 * @hw: pointer to hardware structure
3133 * Disables PCI-Express master access and verifies there are no pending
3134 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
3135 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
3136 * is returned signifying master requests disabled.
3138 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
3140 s32 status = IXGBE_SUCCESS;
3144 DEBUGFUNC("ixgbe_disable_pcie_master");
3146 /* Always set this bit to ensure any future transactions are blocked */
3147 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3149 /* Exit if master requests are blocked */
3150 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3151 IXGBE_REMOVED(hw->hw_addr))
3154 /* Poll for master request bit to clear */
3155 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
3157 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3162 * Two consecutive resets are required via CTRL.RST per datasheet
3163 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
3164 * of this need. The first reset prevents new master requests from
3165 * being issued by our device. We then must wait 1usec or more for any
3166 * remaining completions from the PCIe bus to trickle in, and then reset
3167 * again to clear out any effects they may have had on our device.
3169 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
3170 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3172 if (hw->mac.type >= ixgbe_mac_X550)
3176 * Before proceeding, make sure that the PCIe block does not have
3177 * transactions pending.
3179 poll = ixgbe_pcie_timeout_poll(hw);
3180 for (i = 0; i < poll; i++) {
3182 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3183 if (IXGBE_REMOVED(hw->hw_addr))
3185 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3189 ERROR_REPORT1(IXGBE_ERROR_POLLING,
3190 "PCIe transaction pending bit also did not clear.\n");
3191 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
3198 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3199 * @hw: pointer to hardware structure
3200 * @mask: Mask to specify which semaphore to acquire
3202 * Acquires the SWFW semaphore through the GSSR register for the specified
3203 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3205 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3209 u32 fwmask = mask << 5;
3213 DEBUGFUNC("ixgbe_acquire_swfw_sync");
3215 for (i = 0; i < timeout; i++) {
3217 * SW NVM semaphore bit is used for access to all
3218 * SW_FW_SYNC bits (not just NVM)
3220 if (ixgbe_get_eeprom_semaphore(hw))
3221 return IXGBE_ERR_SWFW_SYNC;
3223 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3224 if (!(gssr & (fwmask | swmask))) {
3226 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3227 ixgbe_release_eeprom_semaphore(hw);
3228 return IXGBE_SUCCESS;
3230 /* Resource is currently in use by FW or SW */
3231 ixgbe_release_eeprom_semaphore(hw);
3236 /* If time expired clear the bits holding the lock and retry */
3237 if (gssr & (fwmask | swmask))
3238 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
3241 return IXGBE_ERR_SWFW_SYNC;
3245 * ixgbe_release_swfw_sync - Release SWFW semaphore
3246 * @hw: pointer to hardware structure
3247 * @mask: Mask to specify which semaphore to release
3249 * Releases the SWFW semaphore through the GSSR register for the specified
3250 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3252 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3257 DEBUGFUNC("ixgbe_release_swfw_sync");
3259 ixgbe_get_eeprom_semaphore(hw);
3261 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3263 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3265 ixgbe_release_eeprom_semaphore(hw);
3269 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3270 * @hw: pointer to hardware structure
3272 * Stops the receive data path and waits for the HW to internally empty
3273 * the Rx security block
3275 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3277 #define IXGBE_MAX_SECRX_POLL 40
3282 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
3285 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3286 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
3287 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3288 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
3289 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3290 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
3293 /* Use interrupt-safe sleep just in case */
3297 /* For informational purposes only */
3298 if (i >= IXGBE_MAX_SECRX_POLL)
3299 DEBUGOUT("Rx unit being enabled before security "
3300 "path fully disabled. Continuing with init.\n");
3302 return IXGBE_SUCCESS;
3306 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3307 * @hw: pointer to hardware structure
3308 * @reg_val: Value we read from AUTOC
3310 * The default case requires no protection so just to the register read.
3312 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3315 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3316 return IXGBE_SUCCESS;
3320 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
3321 * @hw: pointer to hardware structure
3322 * @reg_val: value to write to AUTOC
3323 * @locked: bool to indicate whether the SW/FW lock was already taken by
3326 * The default case requires no protection so just to the register write.
3328 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
3330 UNREFERENCED_1PARAMETER(locked);
3332 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
3333 return IXGBE_SUCCESS;
3337 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3338 * @hw: pointer to hardware structure
3340 * Enables the receive data path.
3342 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3346 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
3348 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3349 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
3350 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3351 IXGBE_WRITE_FLUSH(hw);
3353 return IXGBE_SUCCESS;
3357 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3358 * @hw: pointer to hardware structure
3359 * @regval: register value to write to RXCTRL
3361 * Enables the Rx DMA unit
3363 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3365 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
3367 if (regval & IXGBE_RXCTRL_RXEN)
3368 ixgbe_enable_rx(hw);
3370 ixgbe_disable_rx(hw);
3372 return IXGBE_SUCCESS;
3376 * ixgbe_blink_led_start_generic - Blink LED based on index.
3377 * @hw: pointer to hardware structure
3378 * @index: led number to blink
3380 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3382 ixgbe_link_speed speed = 0;
3385 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3386 s32 ret_val = IXGBE_SUCCESS;
3387 bool locked = false;
3389 DEBUGFUNC("ixgbe_blink_led_start_generic");
3392 * Link must be up to auto-blink the LEDs;
3393 * Force it if link is down.
3395 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3398 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3399 if (ret_val != IXGBE_SUCCESS)
3402 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3403 autoc_reg |= IXGBE_AUTOC_FLU;
3405 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3406 if (ret_val != IXGBE_SUCCESS)
3409 IXGBE_WRITE_FLUSH(hw);
3413 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3414 led_reg |= IXGBE_LED_BLINK(index);
3415 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3416 IXGBE_WRITE_FLUSH(hw);
3423 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3424 * @hw: pointer to hardware structure
3425 * @index: led number to stop blinking
3427 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3430 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3431 s32 ret_val = IXGBE_SUCCESS;
3432 bool locked = false;
3434 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3436 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3437 if (ret_val != IXGBE_SUCCESS)
3440 autoc_reg &= ~IXGBE_AUTOC_FLU;
3441 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3443 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3444 if (ret_val != IXGBE_SUCCESS)
3447 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3448 led_reg &= ~IXGBE_LED_BLINK(index);
3449 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3450 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3451 IXGBE_WRITE_FLUSH(hw);
3458 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3459 * @hw: pointer to hardware structure
3460 * @san_mac_offset: SAN MAC address offset
3462 * This function will read the EEPROM location for the SAN MAC address
3463 * pointer, and returns the value at that location. This is used in both
3464 * get and set mac_addr routines.
3466 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3467 u16 *san_mac_offset)
3471 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3474 * First read the EEPROM pointer to see if the MAC addresses are
3477 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3480 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3481 "eeprom at offset %d failed",
3482 IXGBE_SAN_MAC_ADDR_PTR);
3489 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3490 * @hw: pointer to hardware structure
3491 * @san_mac_addr: SAN MAC address
3493 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3494 * per-port, so set_lan_id() must be called before reading the addresses.
3495 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3496 * upon for non-SFP connections, so we must call it here.
3498 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3500 u16 san_mac_data, san_mac_offset;
3504 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3507 * First read the EEPROM pointer to see if the MAC addresses are
3508 * available. If they're not, no point in calling set_lan_id() here.
3510 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3511 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3512 goto san_mac_addr_out;
3514 /* make sure we know which port we need to program */
3515 hw->mac.ops.set_lan_id(hw);
3516 /* apply the port offset to the address offset */
3517 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3518 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3519 for (i = 0; i < 3; i++) {
3520 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3523 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3524 "eeprom read at offset %d failed",
3526 goto san_mac_addr_out;
3528 san_mac_addr[i * 2] = (u8)(san_mac_data);
3529 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3532 return IXGBE_SUCCESS;
3536 * No addresses available in this EEPROM. It's not an
3537 * error though, so just wipe the local address and return.
3539 for (i = 0; i < 6; i++)
3540 san_mac_addr[i] = 0xFF;
3541 return IXGBE_SUCCESS;
3545 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3546 * @hw: pointer to hardware structure
3547 * @san_mac_addr: SAN MAC address
3549 * Write a SAN MAC address to the EEPROM.
3551 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3554 u16 san_mac_data, san_mac_offset;
3557 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3559 /* Look for SAN mac address pointer. If not defined, return */
3560 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3561 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3562 return IXGBE_ERR_NO_SAN_ADDR_PTR;
3564 /* Make sure we know which port we need to write */
3565 hw->mac.ops.set_lan_id(hw);
3566 /* Apply the port offset to the address offset */
3567 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3568 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3570 for (i = 0; i < 3; i++) {
3571 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3572 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3573 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3577 return IXGBE_SUCCESS;
3581 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3582 * @hw: pointer to hardware structure
3584 * Read PCIe configuration space, and get the MSI-X vector count from
3585 * the capabilities table.
3587 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3593 switch (hw->mac.type) {
3594 case ixgbe_mac_82598EB:
3595 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3596 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3598 case ixgbe_mac_82599EB:
3599 case ixgbe_mac_X540:
3600 case ixgbe_mac_X550:
3601 case ixgbe_mac_X550EM_x:
3602 case ixgbe_mac_X550EM_a:
3603 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3604 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3610 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3611 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3612 if (IXGBE_REMOVED(hw->hw_addr))
3614 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3616 /* MSI-X count is zero-based in HW */
3619 if (msix_count > max_msix_count)
3620 msix_count = max_msix_count;
3626 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3627 * @hw: pointer to hardware structure
3628 * @addr: Address to put into receive address register
3629 * @vmdq: VMDq pool to assign
3631 * Puts an ethernet address into a receive address register, or
3632 * finds the rar that it is aleady in; adds to the pool list
3634 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3636 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3637 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3639 u32 rar_low, rar_high;
3640 u32 addr_low, addr_high;
3642 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3644 /* swap bytes for HW little endian */
3645 addr_low = addr[0] | (addr[1] << 8)
3648 addr_high = addr[4] | (addr[5] << 8);
3651 * Either find the mac_id in rar or find the first empty space.
3652 * rar_highwater points to just after the highest currently used
3653 * rar in order to shorten the search. It grows when we add a new
3656 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3657 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3659 if (((IXGBE_RAH_AV & rar_high) == 0)
3660 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3661 first_empty_rar = rar;
3662 } else if ((rar_high & 0xFFFF) == addr_high) {
3663 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3664 if (rar_low == addr_low)
3665 break; /* found it already in the rars */
3669 if (rar < hw->mac.rar_highwater) {
3670 /* already there so just add to the pool bits */
3671 ixgbe_set_vmdq(hw, rar, vmdq);
3672 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3673 /* stick it into first empty RAR slot we found */
3674 rar = first_empty_rar;
3675 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3676 } else if (rar == hw->mac.rar_highwater) {
3677 /* add it to the top of the list and inc the highwater mark */
3678 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3679 hw->mac.rar_highwater++;
3680 } else if (rar >= hw->mac.num_rar_entries) {
3681 return IXGBE_ERR_INVALID_MAC_ADDR;
3685 * If we found rar[0], make sure the default pool bit (we use pool 0)
3686 * remains cleared to be sure default pool packets will get delivered
3689 ixgbe_clear_vmdq(hw, rar, 0);
3695 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3696 * @hw: pointer to hardware struct
3697 * @rar: receive address register index to disassociate
3698 * @vmdq: VMDq pool index to remove from the rar
3700 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3702 u32 mpsar_lo, mpsar_hi;
3703 u32 rar_entries = hw->mac.num_rar_entries;
3705 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3707 /* Make sure we are using a valid rar index range */
3708 if (rar >= rar_entries) {
3709 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3710 "RAR index %d is out of range.\n", rar);
3711 return IXGBE_ERR_INVALID_ARGUMENT;
3714 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3715 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3717 if (IXGBE_REMOVED(hw->hw_addr))
3720 if (!mpsar_lo && !mpsar_hi)
3723 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3725 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3729 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3732 } else if (vmdq < 32) {
3733 mpsar_lo &= ~(1 << vmdq);
3734 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3736 mpsar_hi &= ~(1 << (vmdq - 32));
3737 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3740 /* was that the last pool using this rar? */
3741 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
3742 hw->mac.ops.clear_rar(hw, rar);
3744 return IXGBE_SUCCESS;
3748 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3749 * @hw: pointer to hardware struct
3750 * @rar: receive address register index to associate with a VMDq index
3751 * @vmdq: VMDq pool index
3753 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3756 u32 rar_entries = hw->mac.num_rar_entries;
3758 DEBUGFUNC("ixgbe_set_vmdq_generic");
3760 /* Make sure we are using a valid rar index range */
3761 if (rar >= rar_entries) {
3762 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3763 "RAR index %d is out of range.\n", rar);
3764 return IXGBE_ERR_INVALID_ARGUMENT;
3768 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3770 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3772 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3773 mpsar |= 1 << (vmdq - 32);
3774 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3776 return IXGBE_SUCCESS;
3780 * This function should only be involved in the IOV mode.
3781 * In IOV mode, Default pool is next pool after the number of
3782 * VFs advertized and not 0.
3783 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3785 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3786 * @hw: pointer to hardware struct
3787 * @vmdq: VMDq pool index
3789 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3791 u32 rar = hw->mac.san_mac_rar_index;
3793 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3796 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3797 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3799 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3800 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3803 return IXGBE_SUCCESS;
3807 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3808 * @hw: pointer to hardware structure
3810 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3814 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3815 DEBUGOUT(" Clearing UTA\n");
3817 for (i = 0; i < 128; i++)
3818 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3820 return IXGBE_SUCCESS;
3824 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3825 * @hw: pointer to hardware structure
3826 * @vlan: VLAN id to write to VLAN filter
3828 * return the VLVF index where this VLAN id should be placed
3831 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)
3833 s32 regindex, first_empty_slot;
3836 /* short cut the special case */
3840 /* if vlvf_bypass is set we don't want to use an empty slot, we
3841 * will simply bypass the VLVF if there are no entries present in the
3842 * VLVF that contain our VLAN
3844 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0;
3846 /* add VLAN enable bit for comparison */
3847 vlan |= IXGBE_VLVF_VIEN;
3849 /* Search for the vlan id in the VLVF entries. Save off the first empty
3850 * slot found along the way.
3852 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1
3854 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) {
3855 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3858 if (!first_empty_slot && !bits)
3859 first_empty_slot = regindex;
3862 /* If we are here then we didn't find the VLAN. Return first empty
3863 * slot we found during our search, else error.
3865 if (!first_empty_slot)
3866 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "No space in VLVF.\n");
3868 return first_empty_slot ? first_empty_slot : IXGBE_ERR_NO_SPACE;
3872 * ixgbe_set_vfta_generic - Set VLAN filter table
3873 * @hw: pointer to hardware structure
3874 * @vlan: VLAN id to write to VLAN filter
3875 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
3876 * @vlan_on: boolean flag to turn on/off VLAN
3877 * @vlvf_bypass: boolean flag indicating updating default pool is okay
3879 * Turn on/off specified VLAN in the VLAN filter table.
3881 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3882 bool vlan_on, bool vlvf_bypass)
3884 u32 regidx, vfta_delta, vfta;
3887 DEBUGFUNC("ixgbe_set_vfta_generic");
3889 if (vlan > 4095 || vind > 63)
3890 return IXGBE_ERR_PARAM;
3893 * this is a 2 part operation - first the VFTA, then the
3894 * VLVF and VLVFB if VT Mode is set
3895 * We don't write the VFTA until we know the VLVF part succeeded.
3899 * The VFTA is a bitstring made up of 128 32-bit registers
3900 * that enable the particular VLAN id, much like the MTA:
3901 * bits[11-5]: which register
3902 * bits[4-0]: which bit in the register
3905 vfta_delta = 1 << (vlan % 32);
3906 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx));
3908 /* vfta_delta represents the difference between the current value
3909 * of vfta and the value we want in the register. Since the diff
3910 * is an XOR mask we can just update the vfta using an XOR
3912 vfta_delta &= vlan_on ? ~vfta : vfta;
3916 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
3918 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta,
3920 if (ret_val != IXGBE_SUCCESS) {
3927 /* Update VFTA now that we are ready for traffic */
3929 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta);
3931 return IXGBE_SUCCESS;
3935 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
3936 * @hw: pointer to hardware structure
3937 * @vlan: VLAN id to write to VLAN filter
3938 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
3939 * @vlan_on: boolean flag to turn on/off VLAN in VLVF
3940 * @vfta_delta: pointer to the difference between the current value of VFTA
3941 * and the desired value
3942 * @vfta: the desired value of the VFTA
3943 * @vlvf_bypass: boolean flag indicating updating default pool is okay
3945 * Turn on/off specified bit in VLVF table.
3947 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3948 bool vlan_on, u32 *vfta_delta, u32 vfta,
3954 DEBUGFUNC("ixgbe_set_vlvf_generic");
3956 if (vlan > 4095 || vind > 63)
3957 return IXGBE_ERR_PARAM;
3959 /* If VT Mode is set
3961 * make sure the vlan is in VLVF
3962 * set the vind bit in the matching VLVFB
3964 * clear the pool bit and possibly the vind
3966 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE))
3967 return IXGBE_SUCCESS;
3968 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
3972 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32));
3974 /* set the pool bit */
3975 bits |= 1 << (vind % 32);
3979 /* clear the pool bit */
3980 bits ^= 1 << (vind % 32);
3983 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) {
3984 /* Clear VFTA first, then disable VLVF. Otherwise
3985 * we run the risk of stray packets leaking into
3986 * the PF via the default pool
3989 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta);
3991 /* disable VLVF and clear remaining bit from pool */
3992 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3993 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0);
3995 return IXGBE_SUCCESS;
3997 /* If there are still bits set in the VLVFB registers
3998 * for the VLAN ID indicated we need to see if the
3999 * caller is requesting that we clear the VFTA entry bit.
4000 * If the caller has requested that we clear the VFTA
4001 * entry bit but there are still pools/VFs using this VLAN
4002 * ID entry then ignore the request. We're not worried
4003 * about the case where we're turning the VFTA VLAN ID
4004 * entry bit on, only when requested to turn it off as
4005 * there may be multiple pools and/or VFs using the
4006 * VLAN ID entry. In that case we cannot clear the
4007 * VFTA bit until all pools/VFs using that VLAN ID have also
4008 * been cleared. This will be indicated by "bits" being
4014 /* record pool change and enable VLAN ID if not already enabled */
4015 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits);
4016 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan);
4018 return IXGBE_SUCCESS;
4022 * ixgbe_clear_vfta_generic - Clear VLAN filter table
4023 * @hw: pointer to hardware structure
4025 * Clears the VLAN filer table, and the VMDq index associated with the filter
4027 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
4031 DEBUGFUNC("ixgbe_clear_vfta_generic");
4033 for (offset = 0; offset < hw->mac.vft_size; offset++)
4034 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
4036 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
4037 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
4038 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
4039 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0);
4042 return IXGBE_SUCCESS;
4046 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
4047 * @hw: pointer to hardware structure
4049 * Contains the logic to identify if we need to verify link for the
4052 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw)
4055 /* Does FW say we need the fix */
4056 if (!hw->need_crosstalk_fix)
4059 /* Only consider SFP+ PHYs i.e. media type fiber */
4060 switch (hw->mac.ops.get_media_type(hw)) {
4061 case ixgbe_media_type_fiber:
4062 case ixgbe_media_type_fiber_qsfp:
4072 * ixgbe_check_mac_link_generic - Determine link and speed status
4073 * @hw: pointer to hardware structure
4074 * @speed: pointer to link speed
4075 * @link_up: true when link is up
4076 * @link_up_wait_to_complete: bool used to wait for link up or not
4078 * Reads the links register to determine if link is up and the current speed
4080 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4081 bool *link_up, bool link_up_wait_to_complete)
4083 u32 links_reg, links_orig;
4086 DEBUGFUNC("ixgbe_check_mac_link_generic");
4088 /* If Crosstalk fix enabled do the sanity check of making sure
4089 * the SFP+ cage is full.
4091 if (ixgbe_need_crosstalk_fix(hw)) {
4094 switch (hw->mac.type) {
4095 case ixgbe_mac_82599EB:
4096 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4099 case ixgbe_mac_X550EM_x:
4100 case ixgbe_mac_X550EM_a:
4101 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4105 /* sanity check - No SFP+ devices here */
4106 sfp_cage_full = false;
4110 if (!sfp_cage_full) {
4112 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4113 return IXGBE_SUCCESS;
4117 /* clear the old state */
4118 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
4120 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4122 if (links_orig != links_reg) {
4123 DEBUGOUT2("LINKS changed from %08X to %08X\n",
4124 links_orig, links_reg);
4127 if (link_up_wait_to_complete) {
4128 for (i = 0; i < hw->mac.max_link_up_time; i++) {
4129 if (links_reg & IXGBE_LINKS_UP) {
4136 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4139 if (links_reg & IXGBE_LINKS_UP)
4145 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4146 case IXGBE_LINKS_SPEED_10G_82599:
4147 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4148 if (hw->mac.type >= ixgbe_mac_X550) {
4149 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4150 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4153 case IXGBE_LINKS_SPEED_1G_82599:
4154 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4156 case IXGBE_LINKS_SPEED_100_82599:
4157 *speed = IXGBE_LINK_SPEED_100_FULL;
4158 if (hw->mac.type >= ixgbe_mac_X550) {
4159 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4160 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4164 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4167 return IXGBE_SUCCESS;
4171 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4173 * @hw: pointer to hardware structure
4174 * @wwnn_prefix: the alternative WWNN prefix
4175 * @wwpn_prefix: the alternative WWPN prefix
4177 * This function will read the EEPROM from the alternative SAN MAC address
4178 * block to check the support for the alternative WWNN/WWPN prefix support.
4180 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4184 u16 alt_san_mac_blk_offset;
4186 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
4188 /* clear output first */
4189 *wwnn_prefix = 0xFFFF;
4190 *wwpn_prefix = 0xFFFF;
4192 /* check if alternative SAN MAC is supported */
4193 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
4194 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4195 goto wwn_prefix_err;
4197 if ((alt_san_mac_blk_offset == 0) ||
4198 (alt_san_mac_blk_offset == 0xFFFF))
4199 goto wwn_prefix_out;
4201 /* check capability in alternative san mac address block */
4202 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
4203 if (hw->eeprom.ops.read(hw, offset, &caps))
4204 goto wwn_prefix_err;
4205 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
4206 goto wwn_prefix_out;
4208 /* get the corresponding prefix for WWNN/WWPN */
4209 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
4210 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4211 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4212 "eeprom read at offset %d failed", offset);
4215 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
4216 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4217 goto wwn_prefix_err;
4220 return IXGBE_SUCCESS;
4223 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4224 "eeprom read at offset %d failed", offset);
4225 return IXGBE_SUCCESS;
4229 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4230 * @hw: pointer to hardware structure
4231 * @bs: the fcoe boot status
4233 * This function will read the FCOE boot status from the iSCSI FCOE block
4235 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4237 u16 offset, caps, flags;
4240 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
4242 /* clear output first */
4243 *bs = ixgbe_fcoe_bootstatus_unavailable;
4245 /* check if FCOE IBA block is present */
4246 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
4247 status = hw->eeprom.ops.read(hw, offset, &caps);
4248 if (status != IXGBE_SUCCESS)
4251 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
4254 /* check if iSCSI FCOE block is populated */
4255 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4256 if (status != IXGBE_SUCCESS)
4259 if ((offset == 0) || (offset == 0xFFFF))
4262 /* read fcoe flags in iSCSI FCOE block */
4263 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
4264 status = hw->eeprom.ops.read(hw, offset, &flags);
4265 if (status != IXGBE_SUCCESS)
4268 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
4269 *bs = ixgbe_fcoe_bootstatus_enabled;
4271 *bs = ixgbe_fcoe_bootstatus_disabled;
4278 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4279 * @hw: pointer to hardware structure
4280 * @enable: enable or disable switch for MAC anti-spoofing
4281 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
4284 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4286 int vf_target_reg = vf >> 3;
4287 int vf_target_shift = vf % 8;
4290 if (hw->mac.type == ixgbe_mac_82598EB)
4293 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4295 pfvfspoof |= (1 << vf_target_shift);
4297 pfvfspoof &= ~(1 << vf_target_shift);
4298 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4302 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4303 * @hw: pointer to hardware structure
4304 * @enable: enable or disable switch for VLAN anti-spoofing
4305 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4308 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4310 int vf_target_reg = vf >> 3;
4311 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
4314 if (hw->mac.type == ixgbe_mac_82598EB)
4317 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4319 pfvfspoof |= (1 << vf_target_shift);
4321 pfvfspoof &= ~(1 << vf_target_shift);
4322 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4326 * ixgbe_get_device_caps_generic - Get additional device capabilities
4327 * @hw: pointer to hardware structure
4328 * @device_caps: the EEPROM word with the extra device capabilities
4330 * This function will read the EEPROM location for the device capabilities,
4331 * and return the word through device_caps.
4333 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4335 DEBUGFUNC("ixgbe_get_device_caps_generic");
4337 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4339 return IXGBE_SUCCESS;
4343 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4344 * @hw: pointer to hardware structure
4347 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4352 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
4354 /* Enable relaxed ordering */
4355 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4356 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4357 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4358 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4361 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4362 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4363 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
4364 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4365 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4371 * ixgbe_calculate_checksum - Calculate checksum for buffer
4372 * @buffer: pointer to EEPROM
4373 * @length: size of EEPROM to calculate a checksum for
4374 * Calculates the checksum for some buffer on a specified length. The
4375 * checksum calculated is returned.
4377 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4382 DEBUGFUNC("ixgbe_calculate_checksum");
4387 for (i = 0; i < length; i++)
4390 return (u8) (0 - sum);
4394 * ixgbe_host_interface_command - Issue command to manageability block
4395 * @hw: pointer to the HW structure
4396 * @buffer: contains the command to write and where the return status will
4398 * @length: length of buffer, must be multiple of 4 bytes
4399 * @timeout: time in ms to wait for command completion
4400 * @return_data: read and return data from the buffer (true) or not (false)
4401 * Needed because FW structures are big endian and decoding of
4402 * these fields can be 8 bit or 16 bit based on command. Decoding
4403 * is not easily understood without making a table of commands.
4404 * So we will leave this up to the caller to read back the data
4407 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4408 * else returns semaphore error when encountering an error acquiring
4409 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4411 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4412 u32 length, u32 timeout, bool return_data)
4414 u32 hicr, i, bi, fwsts;
4415 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4420 DEBUGFUNC("ixgbe_host_interface_command");
4422 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4423 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4424 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4426 /* Take management host interface semaphore */
4427 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4432 /* Set bit 9 of FWSTS clearing FW reset indication */
4433 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
4434 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
4436 /* Check that the host interface is enabled. */
4437 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4438 if ((hicr & IXGBE_HICR_EN) == 0) {
4439 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
4440 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4444 /* Calculate length in DWORDs. We must be DWORD aligned */
4445 if ((length % (sizeof(u32))) != 0) {
4446 DEBUGOUT("Buffer length failure, not aligned to dword");
4447 status = IXGBE_ERR_INVALID_ARGUMENT;
4451 dword_len = length >> 2;
4453 /* The device driver writes the relevant command block
4454 * into the ram area.
4456 for (i = 0; i < dword_len; i++)
4457 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4458 i, IXGBE_CPU_TO_LE32(buffer[i]));
4460 /* Setting this bit tells the ARC that a new command is pending. */
4461 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4463 for (i = 0; i < timeout; i++) {
4464 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4465 if (!(hicr & IXGBE_HICR_C))
4470 /* Check command completion */
4471 if ((timeout != 0 && i == timeout) ||
4472 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
4473 ERROR_REPORT1(IXGBE_ERROR_CAUTION,
4474 "Command has failed with no status valid.\n");
4475 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4482 /* Calculate length in DWORDs */
4483 dword_len = hdr_size >> 2;
4485 /* first pull in the header so we know the buffer length */
4486 for (bi = 0; bi < dword_len; bi++) {
4487 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4488 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4491 /* If there is any thing in data position pull it in */
4492 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
4496 if (length < buf_len + hdr_size) {
4497 DEBUGOUT("Buffer not large enough for reply message.\n");
4498 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4502 /* Calculate length in DWORDs, add 3 for odd lengths */
4503 dword_len = (buf_len + 3) >> 2;
4505 /* Pull in the rest of the buffer (bi is where we left off) */
4506 for (; bi <= dword_len; bi++) {
4507 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4508 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4512 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4518 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4519 * @hw: pointer to the HW structure
4520 * @maj: driver version major number
4521 * @min: driver version minor number
4522 * @build: driver version build number
4523 * @sub: driver version sub build number
4525 * Sends driver version number to firmware through the manageability
4526 * block. On success return IXGBE_SUCCESS
4527 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4528 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4530 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4533 struct ixgbe_hic_drv_info fw_cmd;
4535 s32 ret_val = IXGBE_SUCCESS;
4537 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4539 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4540 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4541 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4542 fw_cmd.port_num = (u8)hw->bus.func;
4543 fw_cmd.ver_maj = maj;
4544 fw_cmd.ver_min = min;
4545 fw_cmd.ver_build = build;
4546 fw_cmd.ver_sub = sub;
4547 fw_cmd.hdr.checksum = 0;
4548 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4549 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4553 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4554 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4556 IXGBE_HI_COMMAND_TIMEOUT,
4558 if (ret_val != IXGBE_SUCCESS)
4561 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4562 FW_CEM_RESP_STATUS_SUCCESS)
4563 ret_val = IXGBE_SUCCESS;
4565 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4574 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4575 * @hw: pointer to hardware structure
4576 * @num_pb: number of packet buffers to allocate
4577 * @headroom: reserve n KB of headroom
4578 * @strategy: packet buffer allocation strategy
4580 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4583 u32 pbsize = hw->mac.rx_pb_size;
4585 u32 rxpktsize, txpktsize, txpbthresh;
4587 /* Reserve headroom */
4593 /* Divide remaining packet buffer space amongst the number of packet
4594 * buffers requested using supplied strategy.
4597 case PBA_STRATEGY_WEIGHTED:
4598 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4599 * buffer with 5/8 of the packet buffer space.
4601 rxpktsize = (pbsize * 5) / (num_pb * 4);
4602 pbsize -= rxpktsize * (num_pb / 2);
4603 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4604 for (; i < (num_pb / 2); i++)
4605 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4606 /* Fall through to configure remaining packet buffers */
4607 case PBA_STRATEGY_EQUAL:
4608 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4609 for (; i < num_pb; i++)
4610 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4616 /* Only support an equally distributed Tx packet buffer strategy. */
4617 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4618 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4619 for (i = 0; i < num_pb; i++) {
4620 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4621 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4624 /* Clear unused TCs, if any, to zero buffer size*/
4625 for (; i < IXGBE_MAX_PB; i++) {
4626 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4627 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4628 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4633 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4634 * @hw: pointer to the hardware structure
4636 * The 82599 and x540 MACs can experience issues if TX work is still pending
4637 * when a reset occurs. This function prevents this by flushing the PCIe
4638 * buffers on the system.
4640 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4642 u32 gcr_ext, hlreg0, i, poll;
4646 * If double reset is not requested then all transactions should
4647 * already be clear and as such there is no work to do
4649 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4653 * Set loopback enable to prevent any transmits from being sent
4654 * should the link come up. This assumes that the RXCTRL.RXEN bit
4655 * has already been cleared.
4657 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4658 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4660 /* Wait for a last completion before clearing buffers */
4661 IXGBE_WRITE_FLUSH(hw);
4665 * Before proceeding, make sure that the PCIe block does not have
4666 * transactions pending.
4668 poll = ixgbe_pcie_timeout_poll(hw);
4669 for (i = 0; i < poll; i++) {
4671 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
4672 if (IXGBE_REMOVED(hw->hw_addr))
4674 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
4679 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4680 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4681 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4682 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4684 /* Flush all writes and allow 20usec for all transactions to clear */
4685 IXGBE_WRITE_FLUSH(hw);
4688 /* restore previous register values */
4689 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4690 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4693 STATIC const u8 ixgbe_emc_temp_data[4] = {
4694 IXGBE_EMC_INTERNAL_DATA,
4695 IXGBE_EMC_DIODE1_DATA,
4696 IXGBE_EMC_DIODE2_DATA,
4697 IXGBE_EMC_DIODE3_DATA
4699 STATIC const u8 ixgbe_emc_therm_limit[4] = {
4700 IXGBE_EMC_INTERNAL_THERM_LIMIT,
4701 IXGBE_EMC_DIODE1_THERM_LIMIT,
4702 IXGBE_EMC_DIODE2_THERM_LIMIT,
4703 IXGBE_EMC_DIODE3_THERM_LIMIT
4707 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
4708 * @hw: pointer to hardware structure
4709 * @data: pointer to the thermal sensor data structure
4711 * Returns the thermal sensor data structure
4713 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
4715 s32 status = IXGBE_SUCCESS;
4723 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4725 DEBUGFUNC("ixgbe_get_thermal_sensor_data_generic");
4727 /* Only support thermal sensors attached to 82599 physical port 0 */
4728 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4729 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
4730 status = IXGBE_NOT_IMPLEMENTED;
4734 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);
4738 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) {
4739 status = IXGBE_NOT_IMPLEMENTED;
4743 status = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);
4747 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4748 != IXGBE_ETS_TYPE_EMC) {
4749 status = IXGBE_NOT_IMPLEMENTED;
4753 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4754 if (num_sensors > IXGBE_MAX_SENSORS)
4755 num_sensors = IXGBE_MAX_SENSORS;
4757 for (i = 0; i < num_sensors; i++) {
4758 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
4763 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4764 IXGBE_ETS_DATA_INDEX_SHIFT);
4765 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4766 IXGBE_ETS_DATA_LOC_SHIFT);
4768 if (sensor_location != 0) {
4769 status = hw->phy.ops.read_i2c_byte(hw,
4770 ixgbe_emc_temp_data[sensor_index],
4771 IXGBE_I2C_THERMAL_SENSOR_ADDR,
4772 &data->sensor[i].temp);
4782 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
4783 * @hw: pointer to hardware structure
4785 * Inits the thermal sensor thresholds according to the NVM map
4786 * and save off the threshold and location values into mac.thermal_sensor_data
4788 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
4790 s32 status = IXGBE_SUCCESS;
4795 u8 low_thresh_delta;
4801 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4803 DEBUGFUNC("ixgbe_init_thermal_sensor_thresh_generic");
4805 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
4807 /* Only support thermal sensors attached to 82599 physical port 0 */
4808 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4809 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
4810 return IXGBE_NOT_IMPLEMENTED;
4812 offset = IXGBE_ETS_CFG;
4813 if (hw->eeprom.ops.read(hw, offset, &ets_offset))
4815 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
4816 return IXGBE_NOT_IMPLEMENTED;
4818 offset = ets_offset;
4819 if (hw->eeprom.ops.read(hw, offset, &ets_cfg))
4821 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4822 != IXGBE_ETS_TYPE_EMC)
4823 return IXGBE_NOT_IMPLEMENTED;
4825 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
4826 IXGBE_ETS_LTHRES_DELTA_SHIFT);
4827 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4829 for (i = 0; i < num_sensors; i++) {
4830 offset = ets_offset + 1 + i;
4831 if (hw->eeprom.ops.read(hw, offset, &ets_sensor)) {
4832 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4833 "eeprom read at offset %d failed",
4837 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4838 IXGBE_ETS_DATA_INDEX_SHIFT);
4839 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4840 IXGBE_ETS_DATA_LOC_SHIFT);
4841 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
4843 hw->phy.ops.write_i2c_byte(hw,
4844 ixgbe_emc_therm_limit[sensor_index],
4845 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
4847 if ((i < IXGBE_MAX_SENSORS) && (sensor_location != 0)) {
4848 data->sensor[i].location = sensor_location;
4849 data->sensor[i].caution_thresh = therm_limit;
4850 data->sensor[i].max_op_thresh = therm_limit -
4857 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4858 "eeprom read at offset %d failed", offset);
4859 return IXGBE_NOT_IMPLEMENTED;
4864 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
4865 * @hw: pointer to hardware structure
4866 * @map: pointer to u8 arr for returning map
4868 * Read the rtrup2tc HW register and resolve its content into map
4870 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
4874 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
4875 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
4876 map[i] = IXGBE_RTRUP2TC_UP_MASK &
4877 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
4881 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
4886 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4887 if (rxctrl & IXGBE_RXCTRL_RXEN) {
4888 if (hw->mac.type != ixgbe_mac_82598EB) {
4889 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4890 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
4891 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4892 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4893 hw->mac.set_lben = true;
4895 hw->mac.set_lben = false;
4898 rxctrl &= ~IXGBE_RXCTRL_RXEN;
4899 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
4903 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
4908 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4909 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
4911 if (hw->mac.type != ixgbe_mac_82598EB) {
4912 if (hw->mac.set_lben) {
4913 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4914 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
4915 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4916 hw->mac.set_lben = false;
4922 * ixgbe_mng_present - returns true when management capability is present
4923 * @hw: pointer to hardware structure
4925 bool ixgbe_mng_present(struct ixgbe_hw *hw)
4929 if (hw->mac.type < ixgbe_mac_82599EB)
4932 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
4933 fwsm &= IXGBE_FWSM_MODE_MASK;
4934 return fwsm == IXGBE_FWSM_FW_MODE_PT;
4938 * ixgbe_mng_enabled - Is the manageability engine enabled?
4939 * @hw: pointer to hardware structure
4941 * Returns true if the manageability engine is enabled.
4943 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
4945 u32 fwsm, manc, factps;
4947 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
4948 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
4951 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
4952 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
4955 if (hw->mac.type <= ixgbe_mac_X540) {
4956 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
4957 if (factps & IXGBE_FACTPS_MNGCG)
4965 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
4966 * @hw: pointer to hardware structure
4967 * @speed: new link speed
4968 * @autoneg_wait_to_complete: true when waiting for completion is needed
4970 * Set the link speed in the MAC and/or PHY register and restarts link.
4972 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
4973 ixgbe_link_speed speed,
4974 bool autoneg_wait_to_complete)
4976 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4977 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4978 s32 status = IXGBE_SUCCESS;
4981 bool autoneg, link_up = false;
4983 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
4985 /* Mask off requested but non-supported speeds */
4986 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
4987 if (status != IXGBE_SUCCESS)
4990 speed &= link_speed;
4992 /* Try each speed one by one, highest priority first. We do this in
4993 * software because 10Gb fiber doesn't support speed autonegotiation.
4995 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
4997 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
4999 /* If we already have link at this speed, just jump out */
5000 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
5001 if (status != IXGBE_SUCCESS)
5004 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
5007 /* Set the module link speed */
5008 switch (hw->phy.media_type) {
5009 case ixgbe_media_type_fiber:
5010 ixgbe_set_rate_select_speed(hw,
5011 IXGBE_LINK_SPEED_10GB_FULL);
5013 case ixgbe_media_type_fiber_qsfp:
5014 /* QSFP module automatically detects MAC link speed */
5017 DEBUGOUT("Unexpected media type.\n");
5021 /* Allow module to change analog characteristics (1G->10G) */
5024 status = ixgbe_setup_mac_link(hw,
5025 IXGBE_LINK_SPEED_10GB_FULL,
5026 autoneg_wait_to_complete);
5027 if (status != IXGBE_SUCCESS)
5030 /* Flap the Tx laser if it has not already been done */
5031 ixgbe_flap_tx_laser(hw);
5033 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
5034 * Section 73.10.2, we may have to wait up to 500ms if KR is
5035 * attempted. 82599 uses the same timing for 10g SFI.
5037 for (i = 0; i < 5; i++) {
5038 /* Wait for the link partner to also set speed */
5041 /* If we have link, just jump out */
5042 status = ixgbe_check_link(hw, &link_speed,
5044 if (status != IXGBE_SUCCESS)
5052 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
5054 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
5055 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
5057 /* If we already have link at this speed, just jump out */
5058 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
5059 if (status != IXGBE_SUCCESS)
5062 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
5065 /* Set the module link speed */
5066 switch (hw->phy.media_type) {
5067 case ixgbe_media_type_fiber:
5068 ixgbe_set_rate_select_speed(hw,
5069 IXGBE_LINK_SPEED_1GB_FULL);
5071 case ixgbe_media_type_fiber_qsfp:
5072 /* QSFP module automatically detects link speed */
5075 DEBUGOUT("Unexpected media type.\n");
5079 /* Allow module to change analog characteristics (10G->1G) */
5082 status = ixgbe_setup_mac_link(hw,
5083 IXGBE_LINK_SPEED_1GB_FULL,
5084 autoneg_wait_to_complete);
5085 if (status != IXGBE_SUCCESS)
5088 /* Flap the Tx laser if it has not already been done */
5089 ixgbe_flap_tx_laser(hw);
5091 /* Wait for the link partner to also set speed */
5094 /* If we have link, just jump out */
5095 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
5096 if (status != IXGBE_SUCCESS)
5103 /* We didn't get link. Configure back to the highest speed we tried,
5104 * (if there was more than one). We call ourselves back with just the
5105 * single highest speed that the user requested.
5108 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
5110 autoneg_wait_to_complete);
5113 /* Set autoneg_advertised value based on input link speed */
5114 hw->phy.autoneg_advertised = 0;
5116 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
5117 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
5119 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
5120 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
5126 * ixgbe_set_soft_rate_select_speed - Set module link speed
5127 * @hw: pointer to hardware structure
5128 * @speed: link speed to set
5130 * Set module link speed via the soft rate select.
5132 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
5133 ixgbe_link_speed speed)
5139 case IXGBE_LINK_SPEED_10GB_FULL:
5140 /* one bit mask same as setting on */
5141 rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
5143 case IXGBE_LINK_SPEED_1GB_FULL:
5144 rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
5147 DEBUGOUT("Invalid fixed module speed\n");
5152 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5153 IXGBE_I2C_EEPROM_DEV_ADDR2,
5156 DEBUGOUT("Failed to read Rx Rate Select RS0\n");
5160 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5162 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5163 IXGBE_I2C_EEPROM_DEV_ADDR2,
5166 DEBUGOUT("Failed to write Rx Rate Select RS0\n");
5171 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5172 IXGBE_I2C_EEPROM_DEV_ADDR2,
5175 DEBUGOUT("Failed to read Rx Rate Select RS1\n");
5179 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5181 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5182 IXGBE_I2C_EEPROM_DEV_ADDR2,
5185 DEBUGOUT("Failed to write Rx Rate Select RS1\n");