1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
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32 ***************************************************************************/
35 #include "ixgbe_type.h"
36 #include "ixgbe_dcb.h"
37 #include "ixgbe_dcb_82598.h"
38 #include "ixgbe_dcb_82599.h"
41 * ixgbe_dcb_calculate_tc_credits - This calculates the ieee traffic class
42 * credits from the configured bandwidth percentages. Credits
43 * are the smallest unit programmable into the underlying
44 * hardware. The IEEE 802.1Qaz specification do not use bandwidth
45 * groups so this is much simplified from the CEE case.
46 * @bw: bandwidth index by traffic class
47 * @refill: refill credits index by traffic class
48 * @max: max credits by traffic class
49 * @max_frame_size: maximum frame size
51 s32 ixgbe_dcb_calculate_tc_credits(u8 *bw, u16 *refill, u16 *max,
54 int min_percent = 100;
55 int min_credit, multiplier;
58 min_credit = ((max_frame_size / 2) + IXGBE_DCB_CREDIT_QUANTUM - 1) /
59 IXGBE_DCB_CREDIT_QUANTUM;
61 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
62 if (bw[i] < min_percent && bw[i])
66 multiplier = (min_credit / min_percent) + 1;
68 /* Find out the hw credits for each TC */
69 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
70 int val = min(bw[i] * multiplier, IXGBE_DCB_MAX_CREDIT_REFILL);
76 max[i] = bw[i] ? (bw[i]*IXGBE_DCB_MAX_CREDIT)/100 : min_credit;
83 * ixgbe_dcb_calculate_tc_credits_cee - Calculates traffic class credits
84 * @hw: pointer to hardware structure
85 * @dcb_config: Struct containing DCB settings
86 * @max_frame_size: Maximum frame size
87 * @direction: Configuring either Tx or Rx
89 * This function calculates the credits allocated to each traffic class.
90 * It should be called only after the rules are checked by
91 * ixgbe_dcb_check_config_cee().
93 s32 ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw *hw,
94 struct ixgbe_dcb_config *dcb_config,
95 u32 max_frame_size, u8 direction)
97 struct ixgbe_dcb_tc_path *p;
98 u32 min_multiplier = 0;
99 u16 min_percent = 100;
100 s32 ret_val = IXGBE_SUCCESS;
101 /* Initialization values default for Tx settings */
103 u32 credit_refill = 0;
105 u16 link_percentage = 0;
109 if (dcb_config == NULL) {
110 ret_val = IXGBE_ERR_CONFIG;
114 min_credit = ((max_frame_size / 2) + IXGBE_DCB_CREDIT_QUANTUM - 1) /
115 IXGBE_DCB_CREDIT_QUANTUM;
117 /* Find smallest link percentage */
118 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
119 p = &dcb_config->tc_config[i].path[direction];
120 bw_percent = dcb_config->bw_percentage[direction][p->bwg_id];
121 link_percentage = p->bwg_percent;
123 link_percentage = (link_percentage * bw_percent) / 100;
125 if (link_percentage && link_percentage < min_percent)
126 min_percent = link_percentage;
130 * The ratio between traffic classes will control the bandwidth
131 * percentages seen on the wire. To calculate this ratio we use
132 * a multiplier. It is required that the refill credits must be
133 * larger than the max frame size so here we find the smallest
134 * multiplier that will allow all bandwidth percentages to be
135 * greater than the max frame size.
137 min_multiplier = (min_credit / min_percent) + 1;
139 /* Find out the link percentage for each TC first */
140 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
141 p = &dcb_config->tc_config[i].path[direction];
142 bw_percent = dcb_config->bw_percentage[direction][p->bwg_id];
144 link_percentage = p->bwg_percent;
145 /* Must be careful of integer division for very small nums */
146 link_percentage = (link_percentage * bw_percent) / 100;
147 if (p->bwg_percent > 0 && link_percentage == 0)
150 /* Save link_percentage for reference */
151 p->link_percent = (u8)link_percentage;
153 /* Calculate credit refill ratio using multiplier */
154 credit_refill = min(link_percentage * min_multiplier,
155 (u32)IXGBE_DCB_MAX_CREDIT_REFILL);
157 /* Refill at least minimum credit */
158 if (credit_refill < min_credit)
159 credit_refill = min_credit;
161 p->data_credits_refill = (u16)credit_refill;
163 /* Calculate maximum credit for the TC */
164 credit_max = (link_percentage * IXGBE_DCB_MAX_CREDIT) / 100;
167 * Adjustment based on rule checking, if the percentage
168 * of a TC is too small, the maximum credit may not be
169 * enough to send out a jumbo frame in data plane arbitration.
171 if (credit_max < min_credit)
172 credit_max = min_credit;
174 if (direction == IXGBE_DCB_TX_CONFIG) {
176 * Adjustment based on rule checking, if the
177 * percentage of a TC is too small, the maximum
178 * credit may not be enough to send out a TSO
179 * packet in descriptor plane arbitration.
181 if (credit_max && (credit_max <
182 IXGBE_DCB_MIN_TSO_CREDIT)
183 && (hw->mac.type == ixgbe_mac_82598EB))
184 credit_max = IXGBE_DCB_MIN_TSO_CREDIT;
186 dcb_config->tc_config[i].desc_credits_max =
190 p->data_credits_max = (u16)credit_max;
198 * ixgbe_dcb_unpack_pfc_cee - Unpack dcb_config PFC info
199 * @cfg: dcb configuration to unpack into hardware consumable fields
200 * @map: user priority to traffic class map
201 * @pfc_up: u8 to store user priority PFC bitmask
203 * This unpacks the dcb configuration PFC info which is stored per
204 * traffic class into a 8bit user priority bitmask that can be
205 * consumed by hardware routines. The priority to tc map must be
206 * updated before calling this routine to use current up-to maps.
208 void ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *cfg, u8 *map, u8 *pfc_up)
210 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
214 * If the TC for this user priority has PFC enabled then set the
215 * matching bit in 'pfc_up' to reflect that PFC is enabled.
217 for (*pfc_up = 0, up = 0; up < IXGBE_DCB_MAX_USER_PRIORITY; up++) {
218 if (tc_config[map[up]].pfc != ixgbe_dcb_pfc_disabled)
223 void ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config *cfg, int direction,
226 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
229 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
230 refill[tc] = tc_config[tc].path[direction].data_credits_refill;
233 void ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config *cfg, u16 *max)
235 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
238 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
239 max[tc] = tc_config[tc].desc_credits_max;
242 void ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config *cfg, int direction,
245 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
248 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
249 bwgid[tc] = tc_config[tc].path[direction].bwg_id;
252 void ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config *cfg, int direction,
255 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
258 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
259 tsa[tc] = tc_config[tc].path[direction].tsa;
262 u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *cfg, int direction, u8 up)
264 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
265 u8 prio_mask = 1 << up;
266 u8 tc = cfg->num_tcs.pg_tcs;
268 /* If tc is 0 then DCB is likely not enabled or supported */
273 * Test from maximum TC to 1 and report the first match we find. If
274 * we find no match we can assume that the TC is 0 since the TC must
275 * be set for all user priorities
277 for (tc--; tc; tc--) {
278 if (prio_mask & tc_config[tc].path[direction].up_to_tc_bitmap)
285 void ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *cfg, int direction,
290 for (up = 0; up < IXGBE_DCB_MAX_USER_PRIORITY; up++)
291 map[up] = ixgbe_dcb_get_tc_from_up(cfg, direction, up);
295 * ixgbe_dcb_config - Struct containing DCB settings.
296 * @dcb_config: Pointer to DCB config structure
298 * This function checks DCB rules for DCB settings.
299 * The following rules are checked:
300 * 1. The sum of bandwidth percentages of all Bandwidth Groups must total 100%.
301 * 2. The sum of bandwidth percentages of all Traffic Classes within a Bandwidth
302 * Group must total 100.
303 * 3. A Traffic Class should not be set to both Link Strict Priority
304 * and Group Strict Priority.
305 * 4. Link strict Bandwidth Groups can only have link strict traffic classes
306 * with zero bandwidth.
308 s32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *dcb_config)
310 struct ixgbe_dcb_tc_path *p;
311 s32 ret_val = IXGBE_SUCCESS;
312 u8 i, j, bw = 0, bw_id;
313 u8 bw_sum[2][IXGBE_DCB_MAX_BW_GROUP];
314 bool link_strict[2][IXGBE_DCB_MAX_BW_GROUP];
316 memset(bw_sum, 0, sizeof(bw_sum));
317 memset(link_strict, 0, sizeof(link_strict));
319 /* First Tx, then Rx */
320 for (i = 0; i < 2; i++) {
321 /* Check each traffic class for rule violation */
322 for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
323 p = &dcb_config->tc_config[j].path[i];
328 if (bw_id >= IXGBE_DCB_MAX_BW_GROUP) {
329 ret_val = IXGBE_ERR_CONFIG;
332 if (p->tsa == ixgbe_dcb_tsa_strict) {
333 link_strict[i][bw_id] = true;
334 /* Link strict should have zero bandwidth */
336 ret_val = IXGBE_ERR_CONFIG;
341 * Traffic classes without link strict
342 * should have non-zero bandwidth.
344 ret_val = IXGBE_ERR_CONFIG;
347 bw_sum[i][bw_id] += bw;
352 /* Check each bandwidth group for rule violation */
353 for (j = 0; j < IXGBE_DCB_MAX_BW_GROUP; j++) {
354 bw += dcb_config->bw_percentage[i][j];
356 * Sum of bandwidth percentages of all traffic classes
357 * within a Bandwidth Group must total 100 except for
358 * link strict group (zero bandwidth).
360 if (link_strict[i][j]) {
363 * Link strict group should have zero
366 ret_val = IXGBE_ERR_CONFIG;
369 } else if (bw_sum[i][j] != IXGBE_DCB_BW_PERCENT &&
371 ret_val = IXGBE_ERR_CONFIG;
376 if (bw != IXGBE_DCB_BW_PERCENT) {
377 ret_val = IXGBE_ERR_CONFIG;
388 * ixgbe_dcb_get_tc_stats - Returns status of each traffic class
389 * @hw: pointer to hardware structure
390 * @stats: pointer to statistics structure
391 * @tc_count: Number of elements in bwg_array.
393 * This function returns the status data for each of the Traffic Classes in use.
395 s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats,
398 s32 ret = IXGBE_NOT_IMPLEMENTED;
399 switch (hw->mac.type) {
400 case ixgbe_mac_82598EB:
401 ret = ixgbe_dcb_get_tc_stats_82598(hw, stats, tc_count);
403 case ixgbe_mac_82599EB:
406 case ixgbe_mac_X550EM_x:
407 case ixgbe_mac_X550EM_a:
408 ret = ixgbe_dcb_get_tc_stats_82599(hw, stats, tc_count);
417 * ixgbe_dcb_get_pfc_stats - Returns CBFC status of each traffic class
418 * @hw: pointer to hardware structure
419 * @stats: pointer to statistics structure
420 * @tc_count: Number of elements in bwg_array.
422 * This function returns the CBFC status data for each of the Traffic Classes.
424 s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats,
427 s32 ret = IXGBE_NOT_IMPLEMENTED;
428 switch (hw->mac.type) {
429 case ixgbe_mac_82598EB:
430 ret = ixgbe_dcb_get_pfc_stats_82598(hw, stats, tc_count);
432 case ixgbe_mac_82599EB:
435 case ixgbe_mac_X550EM_x:
436 case ixgbe_mac_X550EM_a:
437 ret = ixgbe_dcb_get_pfc_stats_82599(hw, stats, tc_count);
446 * ixgbe_dcb_config_rx_arbiter_cee - Config Rx arbiter
447 * @hw: pointer to hardware structure
448 * @dcb_config: pointer to ixgbe_dcb_config structure
450 * Configure Rx Data Arbiter and credits for each traffic class.
452 s32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *hw,
453 struct ixgbe_dcb_config *dcb_config)
455 s32 ret = IXGBE_NOT_IMPLEMENTED;
456 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };
457 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };
458 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
459 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };
460 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };
462 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
463 ixgbe_dcb_unpack_max_cee(dcb_config, max);
464 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
465 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
466 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
468 switch (hw->mac.type) {
469 case ixgbe_mac_82598EB:
470 ret = ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
472 case ixgbe_mac_82599EB:
475 case ixgbe_mac_X550EM_x:
476 case ixgbe_mac_X550EM_a:
477 ret = ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwgid,
487 * ixgbe_dcb_config_tx_desc_arbiter_cee - Config Tx Desc arbiter
488 * @hw: pointer to hardware structure
489 * @dcb_config: pointer to ixgbe_dcb_config structure
491 * Configure Tx Descriptor Arbiter and credits for each traffic class.
493 s32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *hw,
494 struct ixgbe_dcb_config *dcb_config)
496 s32 ret = IXGBE_NOT_IMPLEMENTED;
497 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS];
498 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS];
499 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS];
500 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS];
502 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
503 ixgbe_dcb_unpack_max_cee(dcb_config, max);
504 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
505 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
507 switch (hw->mac.type) {
508 case ixgbe_mac_82598EB:
509 ret = ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max,
512 case ixgbe_mac_82599EB:
515 case ixgbe_mac_X550EM_x:
516 case ixgbe_mac_X550EM_a:
517 ret = ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
527 * ixgbe_dcb_config_tx_data_arbiter_cee - Config Tx data arbiter
528 * @hw: pointer to hardware structure
529 * @dcb_config: pointer to ixgbe_dcb_config structure
531 * Configure Tx Data Arbiter and credits for each traffic class.
533 s32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *hw,
534 struct ixgbe_dcb_config *dcb_config)
536 s32 ret = IXGBE_NOT_IMPLEMENTED;
537 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS];
538 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS];
539 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
540 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS];
541 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS];
543 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
544 ixgbe_dcb_unpack_max_cee(dcb_config, max);
545 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
546 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
547 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
549 switch (hw->mac.type) {
550 case ixgbe_mac_82598EB:
551 ret = ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max,
554 case ixgbe_mac_82599EB:
557 case ixgbe_mac_X550EM_x:
558 case ixgbe_mac_X550EM_a:
559 ret = ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max,
570 * ixgbe_dcb_config_pfc_cee - Config priority flow control
571 * @hw: pointer to hardware structure
572 * @dcb_config: pointer to ixgbe_dcb_config structure
574 * Configure Priority Flow Control for each traffic class.
576 s32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw *hw,
577 struct ixgbe_dcb_config *dcb_config)
579 s32 ret = IXGBE_NOT_IMPLEMENTED;
581 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
583 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
584 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
586 switch (hw->mac.type) {
587 case ixgbe_mac_82598EB:
588 ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en);
590 case ixgbe_mac_82599EB:
593 case ixgbe_mac_X550EM_x:
594 case ixgbe_mac_X550EM_a:
595 ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map);
604 * ixgbe_dcb_config_tc_stats - Config traffic class statistics
605 * @hw: pointer to hardware structure
607 * Configure queue statistics registers, all queues belonging to same traffic
608 * class uses a single set of queue statistics counters.
610 s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *hw)
612 s32 ret = IXGBE_NOT_IMPLEMENTED;
613 switch (hw->mac.type) {
614 case ixgbe_mac_82598EB:
615 ret = ixgbe_dcb_config_tc_stats_82598(hw);
617 case ixgbe_mac_82599EB:
620 case ixgbe_mac_X550EM_x:
621 case ixgbe_mac_X550EM_a:
622 ret = ixgbe_dcb_config_tc_stats_82599(hw, NULL);
631 * ixgbe_dcb_hw_config_cee - Config and enable DCB
632 * @hw: pointer to hardware structure
633 * @dcb_config: pointer to ixgbe_dcb_config structure
635 * Configure dcb settings and enable dcb mode.
637 s32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw *hw,
638 struct ixgbe_dcb_config *dcb_config)
640 s32 ret = IXGBE_NOT_IMPLEMENTED;
642 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS];
643 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS];
644 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
645 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS];
646 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS];
648 /* Unpack CEE standard containers */
649 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
650 ixgbe_dcb_unpack_max_cee(dcb_config, max);
651 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
652 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
653 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
655 switch (hw->mac.type) {
656 case ixgbe_mac_82598EB:
657 ret = ixgbe_dcb_hw_config_82598(hw, dcb_config->link_speed,
658 refill, max, bwgid, tsa);
660 case ixgbe_mac_82599EB:
663 case ixgbe_mac_X550EM_x:
664 case ixgbe_mac_X550EM_a:
665 ixgbe_dcb_config_82599(hw, dcb_config);
666 ret = ixgbe_dcb_hw_config_82599(hw, dcb_config->link_speed,
670 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
676 if (!ret && dcb_config->pfc_mode_enable) {
677 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
678 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
684 /* Helper routines to abstract HW specifics from DCB netlink ops */
685 s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *hw, u8 pfc_en, u8 *map)
687 int ret = IXGBE_ERR_PARAM;
689 switch (hw->mac.type) {
690 case ixgbe_mac_82598EB:
691 ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en);
693 case ixgbe_mac_82599EB:
696 case ixgbe_mac_X550EM_x:
697 case ixgbe_mac_X550EM_a:
698 ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map);
706 s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw, u16 *refill, u16 *max,
707 u8 *bwg_id, u8 *tsa, u8 *map)
709 switch (hw->mac.type) {
710 case ixgbe_mac_82598EB:
711 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
712 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,
714 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,
717 case ixgbe_mac_82599EB:
720 case ixgbe_mac_X550EM_x:
721 case ixgbe_mac_X550EM_a:
722 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
724 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,
726 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,