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32 ***************************************************************************/
35 #include "ixgbe_type.h"
36 #include "ixgbe_dcb.h"
37 #include "ixgbe_dcb_82599.h"
40 * ixgbe_dcb_get_tc_stats_82599 - Returns status for each traffic class
41 * @hw: pointer to hardware structure
42 * @stats: pointer to statistics structure
43 * @tc_count: Number of elements in bwg_array.
45 * This function returns the status data for each of the Traffic Classes in use.
47 s32 ixgbe_dcb_get_tc_stats_82599(struct ixgbe_hw *hw,
48 struct ixgbe_hw_stats *stats,
53 DEBUGFUNC("dcb_get_tc_stats");
55 if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)
56 return IXGBE_ERR_PARAM;
58 /* Statistics pertaining to each traffic class */
59 for (tc = 0; tc < tc_count; tc++) {
60 /* Transmitted Packets */
61 stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc));
62 /* Transmitted Bytes (read low first to prevent missed carry) */
63 stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(tc));
65 (((u64)(IXGBE_READ_REG(hw, IXGBE_QBTC_H(tc)))) << 32);
66 /* Received Packets */
67 stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc));
68 /* Received Bytes (read low first to prevent missed carry) */
69 stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(tc));
71 (((u64)(IXGBE_READ_REG(hw, IXGBE_QBRC_H(tc)))) << 32);
73 /* Received Dropped Packet */
74 stats->qprdc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRDC(tc));
81 * ixgbe_dcb_get_pfc_stats_82599 - Return CBFC status data
82 * @hw: pointer to hardware structure
83 * @stats: pointer to statistics structure
84 * @tc_count: Number of elements in bwg_array.
86 * This function returns the CBFC status data for each of the Traffic Classes.
88 s32 ixgbe_dcb_get_pfc_stats_82599(struct ixgbe_hw *hw,
89 struct ixgbe_hw_stats *stats,
94 DEBUGFUNC("dcb_get_pfc_stats");
96 if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)
97 return IXGBE_ERR_PARAM;
99 for (tc = 0; tc < tc_count; tc++) {
100 /* Priority XOFF Transmitted */
101 stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc));
102 /* Priority XOFF Received */
103 stats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(tc));
106 return IXGBE_SUCCESS;
110 * ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter
111 * @hw: pointer to hardware structure
112 * @refill: refill credits index by traffic class
113 * @max: max credits index by traffic class
114 * @bwg_id: bandwidth grouping indexed by traffic class
115 * @tsa: transmission selection algorithm indexed by traffic class
116 * @map: priority to tc assignments indexed by priority
118 * Configure Rx Packet Arbiter and credits for each traffic class.
120 s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
121 u16 *max, u8 *bwg_id, u8 *tsa,
125 u32 credit_refill = 0;
130 * Disable the arbiter before changing parameters
131 * (always enable recycle mode; WSP)
133 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
134 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
137 * map all UPs to TCs. up_to_tc_bitmap for each TC has corresponding
138 * bits sets for the UPs that needs to be mappped to that TC.
139 * e.g if priorities 6 and 7 are to be mapped to a TC then the
140 * up_to_tc_bitmap value for that TC will be 11000000 in binary.
143 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
144 reg |= (map[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT));
146 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
148 /* Configure traffic class credits and priority */
149 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
150 credit_refill = refill[i];
152 reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT);
154 reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT;
156 if (tsa[i] == ixgbe_dcb_tsa_strict)
157 reg |= IXGBE_RTRPT4C_LSP;
159 IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg);
163 * Configure Rx packet plane (recycle mode; WSP) and
166 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
167 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
169 return IXGBE_SUCCESS;
173 * ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter
174 * @hw: pointer to hardware structure
175 * @refill: refill credits index by traffic class
176 * @max: max credits index by traffic class
177 * @bwg_id: bandwidth grouping indexed by traffic class
178 * @tsa: transmission selection algorithm indexed by traffic class
180 * Configure Tx Descriptor Arbiter and credits for each traffic class.
182 s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
183 u16 *max, u8 *bwg_id, u8 *tsa)
185 u32 reg, max_credits;
188 /* Clear the per-Tx queue credits; we use per-TC instead */
189 for (i = 0; i < 128; i++) {
190 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
191 IXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0);
194 /* Configure traffic class credits and priority */
195 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
196 max_credits = max[i];
197 reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT;
199 reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT;
201 if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
202 reg |= IXGBE_RTTDT2C_GSP;
204 if (tsa[i] == ixgbe_dcb_tsa_strict)
205 reg |= IXGBE_RTTDT2C_LSP;
207 IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg);
211 * Configure Tx descriptor plane (recycle mode; WSP) and
214 reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM;
215 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
217 return IXGBE_SUCCESS;
221 * ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter
222 * @hw: pointer to hardware structure
223 * @refill: refill credits index by traffic class
224 * @max: max credits index by traffic class
225 * @bwg_id: bandwidth grouping indexed by traffic class
226 * @tsa: transmission selection algorithm indexed by traffic class
227 * @map: priority to tc assignments indexed by priority
229 * Configure Tx Packet Arbiter and credits for each traffic class.
231 s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
232 u16 *max, u8 *bwg_id, u8 *tsa,
239 * Disable the arbiter before changing parameters
240 * (always enable recycle mode; SP; arb delay)
242 reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
243 (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT) |
245 IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
248 * map all UPs to TCs. up_to_tc_bitmap for each TC has corresponding
249 * bits sets for the UPs that needs to be mappped to that TC.
250 * e.g if priorities 6 and 7 are to be mapped to a TC then the
251 * up_to_tc_bitmap value for that TC will be 11000000 in binary.
254 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
255 reg |= (map[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT));
257 IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg);
259 /* Configure traffic class credits and priority */
260 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
262 reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT;
263 reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT;
265 if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
266 reg |= IXGBE_RTTPT2C_GSP;
268 if (tsa[i] == ixgbe_dcb_tsa_strict)
269 reg |= IXGBE_RTTPT2C_LSP;
271 IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg);
275 * Configure Tx packet plane (recycle mode; SP; arb delay) and
278 reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
279 (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT);
280 IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
282 return IXGBE_SUCCESS;
286 * ixgbe_dcb_config_pfc_82599 - Configure priority flow control
287 * @hw: pointer to hardware structure
288 * @pfc_en: enabled pfc bitmask
289 * @map: priority to tc assignments indexed by priority
291 * Configure Priority Flow Control (PFC) for each traffic class.
293 s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *map)
295 u32 i, j, fcrtl, reg;
298 /* Enable Transmit Priority Flow Control */
299 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, IXGBE_FCCFG_TFCE_PRIORITY);
301 /* Enable Receive Priority Flow Control */
302 reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
303 reg |= IXGBE_MFLCN_DPF;
306 * X540 supports per TC Rx priority flow control. So
307 * clear all TCs and only enable those that should be
310 reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
312 if (hw->mac.type >= ixgbe_mac_X540)
313 reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;
316 reg |= IXGBE_MFLCN_RPFCE;
318 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
320 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++) {
326 /* Configure PFC Tx thresholds per TC */
327 for (i = 0; i <= max_tc; i++) {
330 for (j = 0; j < IXGBE_DCB_MAX_USER_PRIORITY; j++) {
331 if ((map[j] == i) && (pfc_en & (1 << j))) {
338 reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
339 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
340 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
343 * In order to prevent Tx hangs when the internal Tx
344 * switch is enabled we must set the high water mark
345 * to the Rx packet buffer size - 24KB. This allows
346 * the Tx switch to function even under heavy Rx
349 reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
350 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
353 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
356 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
357 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
358 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), 0);
361 /* Configure pause time (2 TCs per register) */
362 reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
363 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
364 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
366 /* Configure flow control refresh threshold value */
367 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
369 return IXGBE_SUCCESS;
373 * ixgbe_dcb_config_tc_stats_82599 - Config traffic class statistics
374 * @hw: pointer to hardware structure
375 * @dcb_config: pointer to ixgbe_dcb_config structure
377 * Configure queue statistics registers, all queues belonging to same traffic
378 * class uses a single set of queue statistics counters.
380 s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw,
381 struct ixgbe_dcb_config *dcb_config)
386 bool vt_mode = false;
388 if (dcb_config != NULL) {
389 tc_count = dcb_config->num_tcs.pg_tcs;
390 vt_mode = dcb_config->vt_mode;
393 if (!((tc_count == 8 && vt_mode == false) || tc_count == 4))
394 return IXGBE_ERR_PARAM;
396 if (tc_count == 8 && vt_mode == false) {
398 * Receive Queues stats setting
399 * 32 RQSMR registers, each configuring 4 queues.
401 * Set all 16 queues of each TC to the same stat
402 * with TC 'n' going to stat 'n'.
404 for (i = 0; i < 32; i++) {
405 reg = 0x01010101 * (i / 4);
406 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
409 * Transmit Queues stats setting
410 * 32 TQSM registers, each controlling 4 queues.
412 * Set all queues of each TC to the same stat
413 * with TC 'n' going to stat 'n'.
414 * Tx queues are allocated non-uniformly to TCs:
415 * 32, 32, 16, 16, 8, 8, 8, 8.
417 for (i = 0; i < 32; i++) {
434 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
436 } else if (tc_count == 4 && vt_mode == false) {
438 * Receive Queues stats setting
439 * 32 RQSMR registers, each configuring 4 queues.
441 * Set all 16 queues of each TC to the same stat
442 * with TC 'n' going to stat 'n'.
444 for (i = 0; i < 32; i++) {
446 /* In 4 TC mode, odd 16-queue ranges are
450 reg = 0x01010101 * (i / 8);
451 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
454 * Transmit Queues stats setting
455 * 32 TQSM registers, each controlling 4 queues.
457 * Set all queues of each TC to the same stat
458 * with TC 'n' going to stat 'n'.
459 * Tx queues are allocated non-uniformly to TCs:
462 for (i = 0; i < 32; i++) {
471 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
473 } else if (tc_count == 4 && vt_mode == true) {
475 * Receive Queues stats setting
476 * 32 RQSMR registers, each configuring 4 queues.
478 * Queue Indexing in 32 VF with DCB mode maps 4 TC's to each
479 * pool. Set all 32 queues of each TC across pools to the same
480 * stat with TC 'n' going to stat 'n'.
482 for (i = 0; i < 32; i++)
483 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0x03020100);
485 * Transmit Queues stats setting
486 * 32 TQSM registers, each controlling 4 queues.
488 * Queue Indexing in 32 VF with DCB mode maps 4 TC's to each
489 * pool. Set all 32 queues of each TC across pools to the same
490 * stat with TC 'n' going to stat 'n'.
492 for (i = 0; i < 32; i++)
493 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0x03020100);
496 return IXGBE_SUCCESS;
500 * ixgbe_dcb_config_82599 - Configure general DCB parameters
501 * @hw: pointer to hardware structure
502 * @dcb_config: pointer to ixgbe_dcb_config structure
504 * Configure general DCB parameters.
506 s32 ixgbe_dcb_config_82599(struct ixgbe_hw *hw,
507 struct ixgbe_dcb_config *dcb_config)
512 /* Disable the Tx desc arbiter so that MTQC can be changed */
513 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
514 reg |= IXGBE_RTTDCS_ARBDIS;
515 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
517 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
518 if (dcb_config->num_tcs.pg_tcs == 8) {
519 /* Enable DCB for Rx with 8 TCs */
520 switch (reg & IXGBE_MRQC_MRQE_MASK) {
522 case IXGBE_MRQC_RT4TCEN:
523 /* RSS disabled cases */
524 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
527 case IXGBE_MRQC_RSSEN:
528 case IXGBE_MRQC_RTRSS4TCEN:
529 /* RSS enabled cases */
530 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
531 IXGBE_MRQC_RTRSS8TCEN;
535 * Unsupported value, assume stale data,
539 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
543 if (dcb_config->num_tcs.pg_tcs == 4) {
544 /* We support both VT-on and VT-off with 4 TCs. */
545 if (dcb_config->vt_mode)
546 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
547 IXGBE_MRQC_VMDQRT4TCEN;
549 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
550 IXGBE_MRQC_RTRSS4TCEN;
552 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
554 /* Enable DCB for Tx with 8 TCs */
555 if (dcb_config->num_tcs.pg_tcs == 8)
556 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
558 /* We support both VT-on and VT-off with 4 TCs. */
559 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
560 if (dcb_config->vt_mode)
561 reg |= IXGBE_MTQC_VT_ENA;
563 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
565 /* Disable drop for all queues */
566 for (q = 0; q < 128; q++)
567 IXGBE_WRITE_REG(hw, IXGBE_QDE,
568 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
570 /* Enable the Tx desc arbiter */
571 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
572 reg &= ~IXGBE_RTTDCS_ARBDIS;
573 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
575 /* Enable Security TX Buffer IFG for DCB */
576 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
577 reg |= IXGBE_SECTX_DCB;
578 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
580 return IXGBE_SUCCESS;
584 * ixgbe_dcb_hw_config_82599 - Configure and enable DCB
585 * @hw: pointer to hardware structure
586 * @link_speed: unused
587 * @refill: refill credits index by traffic class
588 * @max: max credits index by traffic class
589 * @bwg_id: bandwidth grouping indexed by traffic class
590 * @tsa: transmission selection algorithm indexed by traffic class
591 * @map: priority to tc assignments indexed by priority
593 * Configure dcb settings and enable dcb mode.
595 s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, int link_speed,
596 u16 *refill, u16 *max, u8 *bwg_id, u8 *tsa,
599 UNREFERENCED_1PARAMETER(link_speed);
601 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, tsa,
603 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,
605 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,
608 return IXGBE_SUCCESS;