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32 ***************************************************************************/
35 #include "ixgbe_type.h"
36 #include "ixgbe_dcb.h"
37 #include "ixgbe_dcb_82599.h"
40 * ixgbe_dcb_get_tc_stats_82599 - Returns status for each traffic class
41 * @hw: pointer to hardware structure
42 * @stats: pointer to statistics structure
43 * @tc_count: Number of elements in bwg_array.
45 * This function returns the status data for each of the Traffic Classes in use.
47 s32 ixgbe_dcb_get_tc_stats_82599(struct ixgbe_hw *hw,
48 struct ixgbe_hw_stats *stats,
53 DEBUGFUNC("dcb_get_tc_stats");
55 if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)
56 return IXGBE_ERR_PARAM;
58 /* Statistics pertaining to each traffic class */
59 for (tc = 0; tc < tc_count; tc++) {
60 /* Transmitted Packets */
61 stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc));
62 /* Transmitted Bytes (read low first to prevent missed carry) */
63 stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(tc));
65 (((u64)(IXGBE_READ_REG(hw, IXGBE_QBTC_H(tc)))) << 32);
66 /* Received Packets */
67 stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc));
68 /* Received Bytes (read low first to prevent missed carry) */
69 stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(tc));
71 (((u64)(IXGBE_READ_REG(hw, IXGBE_QBRC_H(tc)))) << 32);
73 /* Received Dropped Packet */
74 stats->qprdc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRDC(tc));
81 * ixgbe_dcb_get_pfc_stats_82599 - Return CBFC status data
82 * @hw: pointer to hardware structure
83 * @stats: pointer to statistics structure
84 * @tc_count: Number of elements in bwg_array.
86 * This function returns the CBFC status data for each of the Traffic Classes.
88 s32 ixgbe_dcb_get_pfc_stats_82599(struct ixgbe_hw *hw,
89 struct ixgbe_hw_stats *stats,
94 DEBUGFUNC("dcb_get_pfc_stats");
96 if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)
97 return IXGBE_ERR_PARAM;
99 for (tc = 0; tc < tc_count; tc++) {
100 /* Priority XOFF Transmitted */
101 stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc));
102 /* Priority XOFF Received */
103 stats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(tc));
106 return IXGBE_SUCCESS;
110 * ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter
111 * @hw: pointer to hardware structure
112 * @dcb_config: pointer to ixgbe_dcb_config structure
114 * Configure Rx Packet Arbiter and credits for each traffic class.
116 s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
117 u16 *max, u8 *bwg_id, u8 *tsa,
121 u32 credit_refill = 0;
126 * Disable the arbiter before changing parameters
127 * (always enable recycle mode; WSP)
129 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
130 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
133 * map all UPs to TCs. up_to_tc_bitmap for each TC has corresponding
134 * bits sets for the UPs that needs to be mappped to that TC.
135 * e.g if priorities 6 and 7 are to be mapped to a TC then the
136 * up_to_tc_bitmap value for that TC will be 11000000 in binary.
139 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
140 reg |= (map[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT));
142 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
144 /* Configure traffic class credits and priority */
145 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
146 credit_refill = refill[i];
148 reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT);
150 reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT;
152 if (tsa[i] == ixgbe_dcb_tsa_strict)
153 reg |= IXGBE_RTRPT4C_LSP;
155 IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg);
159 * Configure Rx packet plane (recycle mode; WSP) and
162 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
163 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
165 return IXGBE_SUCCESS;
169 * ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter
170 * @hw: pointer to hardware structure
171 * @dcb_config: pointer to ixgbe_dcb_config structure
173 * Configure Tx Descriptor Arbiter and credits for each traffic class.
175 s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
176 u16 *max, u8 *bwg_id, u8 *tsa)
178 u32 reg, max_credits;
181 /* Clear the per-Tx queue credits; we use per-TC instead */
182 for (i = 0; i < 128; i++) {
183 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
184 IXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0);
187 /* Configure traffic class credits and priority */
188 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
189 max_credits = max[i];
190 reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT;
192 reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT;
194 if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
195 reg |= IXGBE_RTTDT2C_GSP;
197 if (tsa[i] == ixgbe_dcb_tsa_strict)
198 reg |= IXGBE_RTTDT2C_LSP;
200 IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg);
204 * Configure Tx descriptor plane (recycle mode; WSP) and
207 reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM;
208 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
210 return IXGBE_SUCCESS;
214 * ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter
215 * @hw: pointer to hardware structure
216 * @dcb_config: pointer to ixgbe_dcb_config structure
218 * Configure Tx Packet Arbiter and credits for each traffic class.
220 s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
221 u16 *max, u8 *bwg_id, u8 *tsa,
228 * Disable the arbiter before changing parameters
229 * (always enable recycle mode; SP; arb delay)
231 reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
232 (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT) |
234 IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
237 * map all UPs to TCs. up_to_tc_bitmap for each TC has corresponding
238 * bits sets for the UPs that needs to be mappped to that TC.
239 * e.g if priorities 6 and 7 are to be mapped to a TC then the
240 * up_to_tc_bitmap value for that TC will be 11000000 in binary.
243 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
244 reg |= (map[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT));
246 IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg);
248 /* Configure traffic class credits and priority */
249 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
251 reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT;
252 reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT;
254 if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
255 reg |= IXGBE_RTTPT2C_GSP;
257 if (tsa[i] == ixgbe_dcb_tsa_strict)
258 reg |= IXGBE_RTTPT2C_LSP;
260 IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg);
264 * Configure Tx packet plane (recycle mode; SP; arb delay) and
267 reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
268 (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT);
269 IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
271 return IXGBE_SUCCESS;
275 * ixgbe_dcb_config_pfc_82599 - Configure priority flow control
276 * @hw: pointer to hardware structure
277 * @pfc_en: enabled pfc bitmask
278 * @map: priority to tc assignments indexed by priority
280 * Configure Priority Flow Control (PFC) for each traffic class.
282 s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *map)
284 u32 i, j, fcrtl, reg;
287 /* Enable Transmit Priority Flow Control */
288 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, IXGBE_FCCFG_TFCE_PRIORITY);
290 /* Enable Receive Priority Flow Control */
291 reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
292 reg |= IXGBE_MFLCN_DPF;
295 * X540 supports per TC Rx priority flow control. So
296 * clear all TCs and only enable those that should be
299 reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
301 if (hw->mac.type >= ixgbe_mac_X540)
302 reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;
305 reg |= IXGBE_MFLCN_RPFCE;
307 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
309 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++) {
315 /* Configure PFC Tx thresholds per TC */
316 for (i = 0; i <= max_tc; i++) {
319 for (j = 0; j < IXGBE_DCB_MAX_USER_PRIORITY; j++) {
320 if ((map[j] == i) && (pfc_en & (1 << j))) {
327 reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
328 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
329 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
332 * In order to prevent Tx hangs when the internal Tx
333 * switch is enabled we must set the high water mark
334 * to the Rx packet buffer size - 24KB. This allows
335 * the Tx switch to function even under heavy Rx
338 reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
339 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
342 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
345 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
346 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
347 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), 0);
350 /* Configure pause time (2 TCs per register) */
351 reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
352 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
353 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
355 /* Configure flow control refresh threshold value */
356 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
358 return IXGBE_SUCCESS;
362 * ixgbe_dcb_config_tc_stats_82599 - Config traffic class statistics
363 * @hw: pointer to hardware structure
365 * Configure queue statistics registers, all queues belonging to same traffic
366 * class uses a single set of queue statistics counters.
368 s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw,
369 struct ixgbe_dcb_config *dcb_config)
374 bool vt_mode = false;
376 if (dcb_config != NULL) {
377 tc_count = dcb_config->num_tcs.pg_tcs;
378 vt_mode = dcb_config->vt_mode;
381 if (!((tc_count == 8 && vt_mode == false) || tc_count == 4))
382 return IXGBE_ERR_PARAM;
384 if (tc_count == 8 && vt_mode == false) {
386 * Receive Queues stats setting
387 * 32 RQSMR registers, each configuring 4 queues.
389 * Set all 16 queues of each TC to the same stat
390 * with TC 'n' going to stat 'n'.
392 for (i = 0; i < 32; i++) {
393 reg = 0x01010101 * (i / 4);
394 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
397 * Transmit Queues stats setting
398 * 32 TQSM registers, each controlling 4 queues.
400 * Set all queues of each TC to the same stat
401 * with TC 'n' going to stat 'n'.
402 * Tx queues are allocated non-uniformly to TCs:
403 * 32, 32, 16, 16, 8, 8, 8, 8.
405 for (i = 0; i < 32; i++) {
422 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
424 } else if (tc_count == 4 && vt_mode == false) {
426 * Receive Queues stats setting
427 * 32 RQSMR registers, each configuring 4 queues.
429 * Set all 16 queues of each TC to the same stat
430 * with TC 'n' going to stat 'n'.
432 for (i = 0; i < 32; i++) {
434 /* In 4 TC mode, odd 16-queue ranges are
438 reg = 0x01010101 * (i / 8);
439 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
442 * Transmit Queues stats setting
443 * 32 TQSM registers, each controlling 4 queues.
445 * Set all queues of each TC to the same stat
446 * with TC 'n' going to stat 'n'.
447 * Tx queues are allocated non-uniformly to TCs:
450 for (i = 0; i < 32; i++) {
459 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
461 } else if (tc_count == 4 && vt_mode == true) {
463 * Receive Queues stats setting
464 * 32 RQSMR registers, each configuring 4 queues.
466 * Queue Indexing in 32 VF with DCB mode maps 4 TC's to each
467 * pool. Set all 32 queues of each TC across pools to the same
468 * stat with TC 'n' going to stat 'n'.
470 for (i = 0; i < 32; i++)
471 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0x03020100);
473 * Transmit Queues stats setting
474 * 32 TQSM registers, each controlling 4 queues.
476 * Queue Indexing in 32 VF with DCB mode maps 4 TC's to each
477 * pool. Set all 32 queues of each TC across pools to the same
478 * stat with TC 'n' going to stat 'n'.
480 for (i = 0; i < 32; i++)
481 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0x03020100);
484 return IXGBE_SUCCESS;
488 * ixgbe_dcb_config_82599 - Configure general DCB parameters
489 * @hw: pointer to hardware structure
490 * @dcb_config: pointer to ixgbe_dcb_config structure
492 * Configure general DCB parameters.
494 s32 ixgbe_dcb_config_82599(struct ixgbe_hw *hw,
495 struct ixgbe_dcb_config *dcb_config)
500 /* Disable the Tx desc arbiter so that MTQC can be changed */
501 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
502 reg |= IXGBE_RTTDCS_ARBDIS;
503 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
505 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
506 if (dcb_config->num_tcs.pg_tcs == 8) {
507 /* Enable DCB for Rx with 8 TCs */
508 switch (reg & IXGBE_MRQC_MRQE_MASK) {
510 case IXGBE_MRQC_RT4TCEN:
511 /* RSS disabled cases */
512 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
515 case IXGBE_MRQC_RSSEN:
516 case IXGBE_MRQC_RTRSS4TCEN:
517 /* RSS enabled cases */
518 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
519 IXGBE_MRQC_RTRSS8TCEN;
523 * Unsupported value, assume stale data,
527 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
531 if (dcb_config->num_tcs.pg_tcs == 4) {
532 /* We support both VT-on and VT-off with 4 TCs. */
533 if (dcb_config->vt_mode)
534 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
535 IXGBE_MRQC_VMDQRT4TCEN;
537 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
538 IXGBE_MRQC_RTRSS4TCEN;
540 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
542 /* Enable DCB for Tx with 8 TCs */
543 if (dcb_config->num_tcs.pg_tcs == 8)
544 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
546 /* We support both VT-on and VT-off with 4 TCs. */
547 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
548 if (dcb_config->vt_mode)
549 reg |= IXGBE_MTQC_VT_ENA;
551 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
553 /* Disable drop for all queues */
554 for (q = 0; q < 128; q++)
555 IXGBE_WRITE_REG(hw, IXGBE_QDE,
556 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
558 /* Enable the Tx desc arbiter */
559 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
560 reg &= ~IXGBE_RTTDCS_ARBDIS;
561 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
563 /* Enable Security TX Buffer IFG for DCB */
564 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
565 reg |= IXGBE_SECTX_DCB;
566 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
568 return IXGBE_SUCCESS;
572 * ixgbe_dcb_hw_config_82599 - Configure and enable DCB
573 * @hw: pointer to hardware structure
574 * @dcb_config: pointer to ixgbe_dcb_config structure
576 * Configure dcb settings and enable dcb mode.
578 s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, int link_speed,
579 u16 *refill, u16 *max, u8 *bwg_id, u8 *tsa,
582 UNREFERENCED_1PARAMETER(link_speed);
584 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, tsa,
586 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,
588 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,
591 return IXGBE_SUCCESS;