1 /******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
42 #include <rte_common.h>
43 #include <rte_debug.h>
44 #include <rte_cycles.h>
46 #include <rte_byteorder.h>
49 #include "../ixgbe_logs.h"
50 #include "../ixgbe_bypass_defines.h"
52 #define ASSERT(x) if(!(x)) rte_panic("IXGBE: x")
54 #define DELAY(x) rte_delay_us(x)
55 #define usec_delay(x) DELAY(x)
56 #define msec_delay(x) DELAY(1000*(x))
58 #define DEBUGFUNC(F) DEBUGOUT(F "\n");
59 #define DEBUGOUT(S, args...) PMD_DRV_LOG_RAW(DEBUG, S, ##args)
60 #define DEBUGOUT1(S, args...) DEBUGOUT(S, ##args)
61 #define DEBUGOUT2(S, args...) DEBUGOUT(S, ##args)
62 #define DEBUGOUT3(S, args...) DEBUGOUT(S, ##args)
63 #define DEBUGOUT6(S, args...) DEBUGOUT(S, ##args)
64 #define DEBUGOUT7(S, args...) DEBUGOUT(S, ##args)
66 #define ERROR_REPORT1(e, S, args...) DEBUGOUT(S, ##args)
67 #define ERROR_REPORT2(e, S, args...) DEBUGOUT(S, ##args)
68 #define ERROR_REPORT3(e, S, args...) DEBUGOUT(S, ##args)
75 #define min(a,b) RTE_MIN(a,b)
77 #define EWARN(hw, S, args...) DEBUGOUT1(S, ##args)
79 /* Bunch of defines for shared code bogosity */
80 #define UNREFERENCED_PARAMETER(_p)
81 #define UNREFERENCED_1PARAMETER(_p)
82 #define UNREFERENCED_2PARAMETER(_p, _q)
83 #define UNREFERENCED_3PARAMETER(_p, _q, _r)
84 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s)
85 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t)
87 /* Shared code error reporting */
91 IXGBE_ERROR_INVALID_STATE,
92 IXGBE_ERROR_UNSUPPORTED,
98 #define IXGBE_NTOHL(_i) rte_be_to_cpu_32(_i)
99 #define IXGBE_NTOHS(_i) rte_be_to_cpu_16(_i)
100 #define IXGBE_CPU_TO_LE16(_i) rte_cpu_to_le_16(_i)
101 #define IXGBE_CPU_TO_LE32(_i) rte_cpu_to_le_32(_i)
102 #define IXGBE_LE32_TO_CPU(_i) rte_le_to_cpu_32(_i)
103 #define IXGBE_LE32_TO_CPUS(_i) rte_le_to_cpu_32(_i)
104 #define IXGBE_CPU_TO_BE16(_i) rte_cpu_to_be_16(_i)
105 #define IXGBE_CPU_TO_BE32(_i) rte_cpu_to_be_32(_i)
106 #define IXGBE_BE32_TO_CPU(_i) rte_be_to_cpu_32(_i)
110 typedef uint16_t u16;
112 typedef uint32_t u32;
114 typedef uint64_t u64;
119 #define mb() rte_mb()
120 #define wmb() rte_wmb()
121 #define rmb() rte_rmb()
125 #define prefetch(x) rte_prefetch0(x)
127 #define IXGBE_PCI_REG(reg) rte_read32(reg)
129 static inline uint32_t ixgbe_read_addr(volatile void* addr)
131 return rte_le_to_cpu_32(IXGBE_PCI_REG(addr));
134 #define IXGBE_PCI_REG_WRITE(reg, value) \
135 rte_write32((rte_cpu_to_le_32(value)), reg)
137 #define IXGBE_PCI_REG_WRITE_RELAXED(reg, value) \
138 rte_write32_relaxed((rte_cpu_to_le_32(value)), reg)
140 #define IXGBE_PCI_REG_ADDR(hw, reg) \
141 ((volatile uint32_t *)((char *)(hw)->hw_addr + (reg)))
143 #define IXGBE_PCI_REG_ARRAY_ADDR(hw, reg, index) \
144 IXGBE_PCI_REG_ADDR((hw), (reg) + ((index) << 2))
146 /* Not implemented !! */
147 #define IXGBE_READ_PCIE_WORD(hw, reg) 0
148 #define IXGBE_WRITE_PCIE_WORD(hw, reg, value) do { } while(0)
150 #define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)
152 #define IXGBE_READ_REG(hw, reg) \
153 ixgbe_read_addr(IXGBE_PCI_REG_ADDR((hw), (reg)))
155 #define IXGBE_WRITE_REG(hw, reg, value) \
156 IXGBE_PCI_REG_WRITE(IXGBE_PCI_REG_ADDR((hw), (reg)), (value))
158 #define IXGBE_READ_REG_ARRAY(hw, reg, index) \
159 IXGBE_PCI_REG(IXGBE_PCI_REG_ARRAY_ADDR((hw), (reg), (index)))
161 #define IXGBE_WRITE_REG_ARRAY(hw, reg, index, value) \
162 IXGBE_PCI_REG_WRITE(IXGBE_PCI_REG_ARRAY_ADDR((hw), (reg), (index)), (value))
164 #define IXGBE_WRITE_REG_THEN_POLL_MASK(hw, reg, val, mask, poll_ms) \
166 uint32_t cnt = poll_ms; \
167 IXGBE_WRITE_REG(hw, (reg), (val)); \
168 while (((IXGBE_READ_REG(hw, (reg))) & (mask)) && (cnt--)) \
172 #endif /* _IXGBE_OS_H_ */