1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
13 #include <rte_common.h>
14 #include <rte_debug.h>
15 #include <rte_cycles.h>
17 #include <rte_byteorder.h>
20 #include "../ixgbe_logs.h"
21 #include "../ixgbe_bypass_defines.h"
23 #define ASSERT(x) if(!(x)) rte_panic("IXGBE: x")
25 #define DELAY(x) rte_delay_us_sleep(x)
26 #define usec_delay(x) DELAY(x)
27 #define msec_delay(x) DELAY(1000*(x))
29 #define DEBUGFUNC(F) DEBUGOUT(F "\n");
30 #define DEBUGOUT(S, args...) PMD_DRV_LOG_RAW(DEBUG, S, ##args)
31 #define DEBUGOUT1(S, args...) DEBUGOUT(S, ##args)
32 #define DEBUGOUT2(S, args...) DEBUGOUT(S, ##args)
33 #define DEBUGOUT3(S, args...) DEBUGOUT(S, ##args)
34 #define DEBUGOUT6(S, args...) DEBUGOUT(S, ##args)
35 #define DEBUGOUT7(S, args...) DEBUGOUT(S, ##args)
37 #define ERROR_REPORT1(e, S, args...) DEBUGOUT(S, ##args)
38 #define ERROR_REPORT2(e, S, args...) DEBUGOUT(S, ##args)
39 #define ERROR_REPORT3(e, S, args...) DEBUGOUT(S, ##args)
46 #define min(a,b) RTE_MIN(a,b)
48 #define EWARN(hw, S, args...) DEBUGOUT1(S, ##args)
50 /* Bunch of defines for shared code bogosity */
51 #define UNREFERENCED_PARAMETER(_p)
52 #define UNREFERENCED_1PARAMETER(_p)
53 #define UNREFERENCED_2PARAMETER(_p, _q)
54 #define UNREFERENCED_3PARAMETER(_p, _q, _r)
55 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s)
56 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t)
58 /* Shared code error reporting */
62 IXGBE_ERROR_INVALID_STATE,
63 IXGBE_ERROR_UNSUPPORTED,
69 #define IXGBE_NTOHL(_i) rte_be_to_cpu_32(_i)
70 #define IXGBE_NTOHS(_i) rte_be_to_cpu_16(_i)
71 #define IXGBE_CPU_TO_LE16(_i) rte_cpu_to_le_16(_i)
72 #define IXGBE_CPU_TO_LE32(_i) rte_cpu_to_le_32(_i)
73 #define IXGBE_LE32_TO_CPU(_i) rte_le_to_cpu_32(_i)
74 #define IXGBE_LE32_TO_CPUS(_i) rte_le_to_cpu_32(_i)
75 #define IXGBE_CPU_TO_BE16(_i) rte_cpu_to_be_16(_i)
76 #define IXGBE_CPU_TO_BE32(_i) rte_cpu_to_be_32(_i)
77 #define IXGBE_BE32_TO_CPU(_i) rte_be_to_cpu_32(_i)
88 #define wmb() rte_wmb()
89 #define rmb() rte_rmb()
93 #define prefetch(x) rte_prefetch0(x)
95 #define IXGBE_PCI_REG(reg) rte_read32(reg)
97 static inline uint32_t ixgbe_read_addr(volatile void* addr)
99 return rte_le_to_cpu_32(IXGBE_PCI_REG(addr));
102 #define IXGBE_PCI_REG_WRITE(reg, value) \
103 rte_write32((rte_cpu_to_le_32(value)), reg)
105 #define IXGBE_PCI_REG_WRITE_RELAXED(reg, value) \
106 rte_write32_relaxed((rte_cpu_to_le_32(value)), reg)
108 #define IXGBE_PCI_REG_WC_WRITE(reg, value) \
109 rte_write32_wc((rte_cpu_to_le_32(value)), reg)
111 #define IXGBE_PCI_REG_WC_WRITE_RELAXED(reg, value) \
112 rte_write32_wc_relaxed((rte_cpu_to_le_32(value)), reg)
114 #define IXGBE_PCI_REG_ADDR(hw, reg) \
115 ((volatile uint32_t *)((char *)(hw)->hw_addr + (reg)))
117 #define IXGBE_PCI_REG_ARRAY_ADDR(hw, reg, index) \
118 IXGBE_PCI_REG_ADDR((hw), (reg) + ((index) << 2))
120 /* Not implemented !! */
121 #define IXGBE_READ_PCIE_WORD(hw, reg) 0
122 #define IXGBE_WRITE_PCIE_WORD(hw, reg, value) do { } while(0)
124 #define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)
126 #define IXGBE_READ_REG(hw, reg) \
127 ixgbe_read_addr(IXGBE_PCI_REG_ADDR((hw), (reg)))
129 #define IXGBE_WRITE_REG(hw, reg, value) \
130 IXGBE_PCI_REG_WRITE(IXGBE_PCI_REG_ADDR((hw), (reg)), (value))
132 #define IXGBE_READ_REG_ARRAY(hw, reg, index) \
133 IXGBE_PCI_REG(IXGBE_PCI_REG_ARRAY_ADDR((hw), (reg), (index)))
135 #define IXGBE_WRITE_REG_ARRAY(hw, reg, index, value) \
136 IXGBE_PCI_REG_WRITE(IXGBE_PCI_REG_ARRAY_ADDR((hw), (reg), (index)), (value))
138 #define IXGBE_WRITE_REG_THEN_POLL_MASK(hw, reg, val, mask, poll_ms) \
140 uint32_t cnt = poll_ms; \
141 IXGBE_WRITE_REG(hw, (reg), (val)); \
142 while (((IXGBE_READ_REG(hw, (reg))) & (mask)) && (cnt--)) \
146 #endif /* _IXGBE_OS_H_ */