drivers/net/ixgbe/base/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_api.h"
  35 #include "ixgbe_common.h"
  36 #include "ixgbe_phy.h"
  37
  38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
  39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  50                                           u8 *sff8472_data);
  51
  52 /**
  53  * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
  54  * @hw: pointer to the hardware structure
  55  * @byte: byte to send
  56  *
  57  * Returns an error code on error.
  58  */
  59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
  60 {
  61         s32 status;
  62
  63         status = ixgbe_clock_out_i2c_byte(hw, byte);
  64         if (status)
  65                 return status;
  66         return ixgbe_get_i2c_ack(hw);
  67 }
  68
  69 /**
  70  * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
  71  * @hw: pointer to the hardware structure
  72  * @byte: pointer to a u8 to receive the byte
  73  *
  74  * Returns an error code on error.
  75  */
  76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
  77 {
  78         s32 status;
  79
  80         status = ixgbe_clock_in_i2c_byte(hw, byte);
  81         if (status)
  82                 return status;
  83         /* ACK */
  84         return ixgbe_clock_out_i2c_bit(hw, false);
  85 }
  86
  87 /**
  88  * ixgbe_ones_comp_byte_add - Perform one's complement addition
  89  * @add1 - addend 1
  90  * @add2 - addend 2
  91  *
  92  * Returns one's complement 8-bit sum.
  93  */
  94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
  95 {
  96         u16 sum = add1 + add2;
  97
  98         sum = (sum & 0xFF) + (sum >> 8);
  99         return sum & 0xFF;
 100 }
 101
 102 /**
 103  * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
 104  * @hw: pointer to the hardware structure
 105  * @addr: I2C bus address to read from
 106  * @reg: I2C device register to read from
 107  * @val: pointer to location to receive read value
 108  * @lock: true if to take and release semaphore
 109  *
 110  * Returns an error code on error.
 111  */
 112 STATIC s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
 113                                                u16 reg, u16 *val, bool lock)
 114 {
 115         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 116         int max_retry = 10;
 117         int retry = 0;
 118         u8 csum_byte;
 119         u8 high_bits;
 120         u8 low_bits;
 121         u8 reg_high;
 122         u8 csum;
 123
 124         if (hw->mac.type >= ixgbe_mac_X550)
 125                 max_retry = 3;
 126         reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
 127         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 128         csum = ~csum;
 129         do {
 130                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 131                         return IXGBE_ERR_SWFW_SYNC;
 132                 ixgbe_i2c_start(hw);
 133                 /* Device Address and write indication */
 134                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 135                         goto fail;
 136                 /* Write bits 14:8 */
 137                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 138                         goto fail;
 139                 /* Write bits 7:0 */
 140                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 141                         goto fail;
 142                 /* Write csum */
 143                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 144                         goto fail;
 145                 /* Re-start condition */
 146                 ixgbe_i2c_start(hw);
 147                 /* Device Address and read indication */
 148                 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
 149                         goto fail;
 150                 /* Get upper bits */
 151                 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
 152                         goto fail;
 153                 /* Get low bits */
 154                 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
 155                         goto fail;
 156                 /* Get csum */
 157                 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
 158                         goto fail;
 159                 /* NACK */
 160                 if (ixgbe_clock_out_i2c_bit(hw, false))
 161                         goto fail;
 162                 ixgbe_i2c_stop(hw);
 163                 if (lock)
 164                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 165                 *val = (high_bits << 8) | low_bits;
 166                 return 0;
 167
 168 fail:
 169                 ixgbe_i2c_bus_clear(hw);
 170                 if (lock)
 171                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 172                 retry++;
 173                 if (retry < max_retry)
 174                         DEBUGOUT("I2C byte read combined error - Retrying.\n");
 175                 else
 176                         DEBUGOUT("I2C byte read combined error.\n");
 177         } while (retry < max_retry);
 178
 179         return IXGBE_ERR_I2C;
 180 }
 181
 182 /**
 183  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 184  * @hw: pointer to the hardware structure
 185  * @addr: I2C bus address to read from
 186  * @reg: I2C device register to read from
 187  * @val: pointer to location to receive read value
 188  *
 189  * Returns an error code on error.
 190  **/
 191 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 192                                            u16 reg, u16 *val)
 193 {
 194         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 195 }
 196
 197 /**
 198  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 199  * @hw: pointer to the hardware structure
 200  * @addr: I2C bus address to read from
 201  * @reg: I2C device register to read from
 202  * @val: pointer to location to receive read value
 203  *
 204  * Returns an error code on error.
 205  **/
 206 STATIC s32
 207 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 208                                          u16 reg, u16 *val)
 209 {
 210         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 211 }
 212
 213 /**
 214  * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
 215  * @hw: pointer to the hardware structure
 216  * @addr: I2C bus address to write to
 217  * @reg: I2C device register to write to
 218  * @val: value to write
 219  * @lock: true if to take and release semaphore
 220  *
 221  * Returns an error code on error.
 222  */
 223 STATIC s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
 224                                                 u16 reg, u16 val, bool lock)
 225 {
 226         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 227         int max_retry = 1;
 228         int retry = 0;
 229         u8 reg_high;
 230         u8 csum;
 231
 232         reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
 233         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 234         csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
 235         csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
 236         csum = ~csum;
 237         do {
 238                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 239                         return IXGBE_ERR_SWFW_SYNC;
 240                 ixgbe_i2c_start(hw);
 241                 /* Device Address and write indication */
 242                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 243                         goto fail;
 244                 /* Write bits 14:8 */
 245                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 246                         goto fail;
 247                 /* Write bits 7:0 */
 248                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 249                         goto fail;
 250                 /* Write data 15:8 */
 251                 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
 252                         goto fail;
 253                 /* Write data 7:0 */
 254                 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
 255                         goto fail;
 256                 /* Write csum */
 257                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 258                         goto fail;
 259                 ixgbe_i2c_stop(hw);
 260                 if (lock)
 261                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 262                 return 0;
 263
 264 fail:
 265                 ixgbe_i2c_bus_clear(hw);
 266                 if (lock)
 267                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 268                 retry++;
 269                 if (retry < max_retry)
 270                         DEBUGOUT("I2C byte write combined error - Retrying.\n");
 271                 else
 272                         DEBUGOUT("I2C byte write combined error.\n");
 273         } while (retry < max_retry);
 274
 275         return IXGBE_ERR_I2C;
 276 }
 277
 278 /**
 279  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 280  * @hw: pointer to the hardware structure
 281  * @addr: I2C bus address to write to
 282  * @reg: I2C device register to write to
 283  * @val: value to write
 284  *
 285  * Returns an error code on error.
 286  **/
 287 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 288                                             u8 addr, u16 reg, u16 val)
 289 {
 290         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 291 }
 292
 293 /**
 294  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 295  * @hw: pointer to the hardware structure
 296  * @addr: I2C bus address to write to
 297  * @reg: I2C device register to write to
 298  * @val: value to write
 299  *
 300  * Returns an error code on error.
 301  **/
 302 STATIC s32
 303 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 304                                           u8 addr, u16 reg, u16 val)
 305 {
 306         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 307 }
 308
 309 /**
 310  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
 311  *  @hw: pointer to the hardware structure
 312  *
 313  *  Initialize the function pointers.
 314  **/
 315 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
 316 {
 317         struct ixgbe_phy_info *phy = &hw->phy;
 318
 319         DEBUGFUNC("ixgbe_init_phy_ops_generic");
 320
 321         /* PHY */
 322         phy->ops.identify = ixgbe_identify_phy_generic;
 323         phy->ops.reset = ixgbe_reset_phy_generic;
 324         phy->ops.read_reg = ixgbe_read_phy_reg_generic;
 325         phy->ops.write_reg = ixgbe_write_phy_reg_generic;
 326         phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
 327         phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
 328         phy->ops.setup_link = ixgbe_setup_phy_link_generic;
 329         phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
 330         phy->ops.check_link = NULL;
 331         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
 332         phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
 333         phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
 334         phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
 335         phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
 336         phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
 337         phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
 338         phy->ops.identify_sfp = ixgbe_identify_module_generic;
 339         phy->sfp_type = ixgbe_sfp_type_unknown;
 340         phy->ops.read_i2c_combined = ixgbe_read_i2c_combined_generic;
 341         phy->ops.write_i2c_combined = ixgbe_write_i2c_combined_generic;
 342         phy->ops.read_i2c_combined_unlocked =
 343                                 ixgbe_read_i2c_combined_generic_unlocked;
 344         phy->ops.write_i2c_combined_unlocked =
 345                                 ixgbe_write_i2c_combined_generic_unlocked;
 346         phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
 347         phy->ops.write_i2c_byte_unlocked =
 348                                 ixgbe_write_i2c_byte_generic_unlocked;
 349         phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
 350         return IXGBE_SUCCESS;
 351 }
 352
 353 /**
 354  *  ixgbe_identify_phy_generic - Get physical layer module
 355  *  @hw: pointer to hardware structure
 356  *
 357  *  Determines the physical layer module found on the current adapter.
 358  **/
 359 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 360 {
 361         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 362         u32 phy_addr;
 363         u16 ext_ability = 0;
 364
 365         DEBUGFUNC("ixgbe_identify_phy_generic");
 366
 367         if (!hw->phy.phy_semaphore_mask) {
 368                 if (hw->bus.lan_id)
 369                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 370                 else
 371                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 372         }
 373
 374         if (hw->phy.type == ixgbe_phy_unknown) {
 375                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 376                         if (ixgbe_validate_phy_addr(hw, phy_addr)) {
 377                                 hw->phy.addr = phy_addr;
 378                                 ixgbe_get_phy_id(hw);
 379                                 hw->phy.type =
 380                                         ixgbe_get_phy_type_from_id(hw->phy.id);
 381
 382                                 if (hw->phy.type == ixgbe_phy_unknown) {
 383                                         hw->phy.ops.read_reg(hw,
 384                                                   IXGBE_MDIO_PHY_EXT_ABILITY,
 385                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 386                                                   &ext_ability);
 387                                         if (ext_ability &
 388                                             (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 389                                              IXGBE_MDIO_PHY_1000BASET_ABILITY))
 390                                                 hw->phy.type =
 391                                                          ixgbe_phy_cu_unknown;
 392                                         else
 393                                                 hw->phy.type =
 394                                                          ixgbe_phy_generic;
 395                                 }
 396
 397                                 status = IXGBE_SUCCESS;
 398                                 break;
 399                         }
 400                 }
 401
 402                 /* Certain media types do not have a phy so an address will not
 403                  * be found and the code will take this path.  Caller has to
 404                  * decide if it is an error or not.
 405                  */
 406                 if (status != IXGBE_SUCCESS) {
 407                         hw->phy.addr = 0;
 408                 }
 409         } else {
 410                 status = IXGBE_SUCCESS;
 411         }
 412
 413         return status;
 414 }
 415
 416 /**
 417  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 418  * @hw: pointer to the hardware structure
 419  *
 420  * This function checks the MMNGC.MNG_VETO bit to see if there are
 421  * any constraints on link from manageability.  For MAC's that don't
 422  * have this bit just return faluse since the link can not be blocked
 423  * via this method.
 424  **/
 425 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 426 {
 427         u32 mmngc;
 428
 429         DEBUGFUNC("ixgbe_check_reset_blocked");
 430
 431         /* If we don't have this bit, it can't be blocking */
 432         if (hw->mac.type == ixgbe_mac_82598EB)
 433                 return false;
 434
 435         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 436         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 437                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 438                               "MNG_VETO bit detected.\n");
 439                 return true;
 440         }
 441
 442         return false;
 443 }
 444
 445 /**
 446  *  ixgbe_validate_phy_addr - Determines phy address is valid
 447  *  @hw: pointer to hardware structure
 448  *
 449  **/
 450 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 451 {
 452         u16 phy_id = 0;
 453         bool valid = false;
 454
 455         DEBUGFUNC("ixgbe_validate_phy_addr");
 456
 457         hw->phy.addr = phy_addr;
 458         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 459                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 460
 461         if (phy_id != 0xFFFF && phy_id != 0x0)
 462                 valid = true;
 463
 464         return valid;
 465 }
 466
 467 /**
 468  *  ixgbe_get_phy_id - Get the phy type
 469  *  @hw: pointer to hardware structure
 470  *
 471  **/
 472 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 473 {
 474         u32 status;
 475         u16 phy_id_high = 0;
 476         u16 phy_id_low = 0;
 477
 478         DEBUGFUNC("ixgbe_get_phy_id");
 479
 480         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 481                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 482                                       &phy_id_high);
 483
 484         if (status == IXGBE_SUCCESS) {
 485                 hw->phy.id = (u32)(phy_id_high << 16);
 486                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 487                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 488                                               &phy_id_low);
 489                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 490                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 491         }
 492         return status;
 493 }
 494
 495 /**
 496  *  ixgbe_get_phy_type_from_id - Get the phy type
 497  *  @hw: pointer to hardware structure
 498  *
 499  **/
 500 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 501 {
 502         enum ixgbe_phy_type phy_type;
 503
 504         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 505
 506         switch (phy_id) {
 507         case TN1010_PHY_ID:
 508                 phy_type = ixgbe_phy_tn;
 509                 break;
 510         case X550_PHY_ID1:
 511         case X550_PHY_ID2:
 512         case X550_PHY_ID3:
 513         case X540_PHY_ID:
 514                 phy_type = ixgbe_phy_aq;
 515                 break;
 516         case QT2022_PHY_ID:
 517                 phy_type = ixgbe_phy_qt;
 518                 break;
 519         case ATH_PHY_ID:
 520                 phy_type = ixgbe_phy_nl;
 521                 break;
 522         case X557_PHY_ID:
 523                 phy_type = ixgbe_phy_x550em_ext_t;
 524                 break;
 525         default:
 526                 phy_type = ixgbe_phy_unknown;
 527                 break;
 528         }
 529
 530         DEBUGOUT1("phy type found is %d\n", phy_type);
 531         return phy_type;
 532 }
 533
 534 /**
 535  *  ixgbe_reset_phy_generic - Performs a PHY reset
 536  *  @hw: pointer to hardware structure
 537  **/
 538 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 539 {
 540         u32 i;
 541         u16 ctrl = 0;
 542         s32 status = IXGBE_SUCCESS;
 543
 544         DEBUGFUNC("ixgbe_reset_phy_generic");
 545
 546         if (hw->phy.type == ixgbe_phy_unknown)
 547                 status = ixgbe_identify_phy_generic(hw);
 548
 549         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 550                 goto out;
 551
 552         /* Don't reset PHY if it's shut down due to overtemp. */
 553         if (!hw->phy.reset_if_overtemp &&
 554             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 555                 goto out;
 556
 557         /* Blocked by MNG FW so bail */
 558         if (ixgbe_check_reset_blocked(hw))
 559                 goto out;
 560
 561         /*
 562          * Perform soft PHY reset to the PHY_XS.
 563          * This will cause a soft reset to the PHY
 564          */
 565         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 566                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 567                               IXGBE_MDIO_PHY_XS_RESET);
 568
 569         /*
 570          * Poll for reset bit to self-clear indicating reset is complete.
 571          * Some PHYs could take up to 3 seconds to complete and need about
 572          * 1.7 usec delay after the reset is complete.
 573          */
 574         for (i = 0; i < 30; i++) {
 575                 msec_delay(100);
 576                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 577                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
 578                 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 579                         usec_delay(2);
 580                         break;
 581                 }
 582         }
 583
 584         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 585                 status = IXGBE_ERR_RESET_FAILED;
 586                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 587                              "PHY reset polling failed to complete.\n");
 588         }
 589
 590 out:
 591         return status;
 592 }
 593
 594 /**
 595  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 596  *  the SWFW lock
 597  *  @hw: pointer to hardware structure
 598  *  @reg_addr: 32 bit address of PHY register to read
 599  *  @phy_data: Pointer to read data from PHY register
 600  **/
 601 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 602                        u16 *phy_data)
 603 {
 604         u32 i, data, command;
 605
 606         /* Setup and write the address cycle command */
 607         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 608                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 609                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 610                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 611
 612         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 613
 614         /*
 615          * Check every 10 usec to see if the address cycle completed.
 616          * The MDI Command bit will clear when the operation is
 617          * complete
 618          */
 619         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 620                 usec_delay(10);
 621
 622                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 623                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 624                                 break;
 625         }
 626
 627
 628         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 629                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 630                 return IXGBE_ERR_PHY;
 631         }
 632
 633         /*
 634          * Address cycle complete, setup and write the read
 635          * command
 636          */
 637         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 638                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 639                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 640                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 641
 642         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 643
 644         /*
 645          * Check every 10 usec to see if the address cycle
 646          * completed. The MDI Command bit will clear when the
 647          * operation is complete
 648          */
 649         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 650                 usec_delay(10);
 651
 652                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 653                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 654                         break;
 655         }
 656
 657         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 658                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 659                 return IXGBE_ERR_PHY;
 660         }
 661
 662         /*
 663          * Read operation is complete.  Get the data
 664          * from MSRWD
 665          */
 666         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 667         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 668         *phy_data = (u16)(data);
 669
 670         return IXGBE_SUCCESS;
 671 }
 672
 673 /**
 674  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 675  *  using the SWFW lock - this function is needed in most cases
 676  *  @hw: pointer to hardware structure
 677  *  @reg_addr: 32 bit address of PHY register to read
 678  *  @phy_data: Pointer to read data from PHY register
 679  **/
 680 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 681                                u32 device_type, u16 *phy_data)
 682 {
 683         s32 status;
 684         u32 gssr = hw->phy.phy_semaphore_mask;
 685
 686         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 687
 688         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 689                 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
 690                                                 phy_data);
 691                 hw->mac.ops.release_swfw_sync(hw, gssr);
 692         } else {
 693                 status = IXGBE_ERR_SWFW_SYNC;
 694         }
 695
 696         return status;
 697 }
 698
 699 /**
 700  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 701  *  without SWFW lock
 702  *  @hw: pointer to hardware structure
 703  *  @reg_addr: 32 bit PHY register to write
 704  *  @device_type: 5 bit device type
 705  *  @phy_data: Data to write to the PHY register
 706  **/
 707 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 708                                 u32 device_type, u16 phy_data)
 709 {
 710         u32 i, command;
 711
 712         /* Put the data in the MDI single read and write data register*/
 713         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 714
 715         /* Setup and write the address cycle command */
 716         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 717                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 718                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 719                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 720
 721         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 722
 723         /*
 724          * Check every 10 usec to see if the address cycle completed.
 725          * The MDI Command bit will clear when the operation is
 726          * complete
 727          */
 728         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 729                 usec_delay(10);
 730
 731                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 732                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 733                         break;
 734         }
 735
 736         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 737                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 738                 return IXGBE_ERR_PHY;
 739         }
 740
 741         /*
 742          * Address cycle complete, setup and write the write
 743          * command
 744          */
 745         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 746                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 747                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 748                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 749
 750         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 751
 752         /*
 753          * Check every 10 usec to see if the address cycle
 754          * completed. The MDI Command bit will clear when the
 755          * operation is complete
 756          */
 757         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 758                 usec_delay(10);
 759
 760                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 761                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 762                         break;
 763         }
 764
 765         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 766                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 767                 return IXGBE_ERR_PHY;
 768         }
 769
 770         return IXGBE_SUCCESS;
 771 }
 772
 773 /**
 774  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 775  *  using SWFW lock- this function is needed in most cases
 776  *  @hw: pointer to hardware structure
 777  *  @reg_addr: 32 bit PHY register to write
 778  *  @device_type: 5 bit device type
 779  *  @phy_data: Data to write to the PHY register
 780  **/
 781 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 782                                 u32 device_type, u16 phy_data)
 783 {
 784         s32 status;
 785         u32 gssr = hw->phy.phy_semaphore_mask;
 786
 787         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 788
 789         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 790                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
 791                                                  phy_data);
 792                 hw->mac.ops.release_swfw_sync(hw, gssr);
 793         } else {
 794                 status = IXGBE_ERR_SWFW_SYNC;
 795         }
 796
 797         return status;
 798 }
 799
 800 /**
 801  *  ixgbe_setup_phy_link_generic - Set and restart auto-neg
 802  *  @hw: pointer to hardware structure
 803  *
 804  *  Restart auto-negotiation and PHY and waits for completion.
 805  **/
 806 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 807 {
 808         s32 status = IXGBE_SUCCESS;
 809         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 810         bool autoneg = false;
 811         ixgbe_link_speed speed;
 812
 813         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 814
 815         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 816
 817         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 818                 /* Set or unset auto-negotiation 10G advertisement */
 819                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 820                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 821                                      &autoneg_reg);
 822
 823                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 824                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 825                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 826
 827                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 828                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 829                                       autoneg_reg);
 830         }
 831
 832         if (hw->mac.type == ixgbe_mac_X550) {
 833                 if (speed & IXGBE_LINK_SPEED_5GB_FULL) {
 834                         /* Set or unset auto-negotiation 5G advertisement */
 835                         hw->phy.ops.read_reg(hw,
 836                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 837                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 838                                 &autoneg_reg);
 839
 840                         autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
 841                         if (hw->phy.autoneg_advertised &
 842                              IXGBE_LINK_SPEED_5GB_FULL)
 843                                 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
 844
 845                         hw->phy.ops.write_reg(hw,
 846                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 847                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 848                                 autoneg_reg);
 849                 }
 850
 851                 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) {
 852                         /* Set or unset auto-negotiation 2.5G advertisement */
 853                         hw->phy.ops.read_reg(hw,
 854                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 855                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 856                                 &autoneg_reg);
 857
 858                         autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
 859                         if (hw->phy.autoneg_advertised &
 860                             IXGBE_LINK_SPEED_2_5GB_FULL)
 861                                 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
 862
 863                         hw->phy.ops.write_reg(hw,
 864                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 865                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 866                                 autoneg_reg);
 867                 }
 868         }
 869
 870         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 871                 /* Set or unset auto-negotiation 1G advertisement */
 872                 hw->phy.ops.read_reg(hw,
 873                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 874                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 875                                      &autoneg_reg);
 876
 877                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 878                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 879                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 880
 881                 hw->phy.ops.write_reg(hw,
 882                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 883                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 884                                       autoneg_reg);
 885         }
 886
 887         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 888                 /* Set or unset auto-negotiation 100M advertisement */
 889                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 890                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 891                                      &autoneg_reg);
 892
 893                 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 894                                  IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 895                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 896                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 897
 898                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 899                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 900                                       autoneg_reg);
 901         }
 902
 903         /* Blocked by MNG FW so don't reset PHY */
 904         if (ixgbe_check_reset_blocked(hw))
 905                 return status;
 906
 907         /* Restart PHY auto-negotiation. */
 908         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 909                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 910
 911         autoneg_reg |= IXGBE_MII_RESTART;
 912
 913         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 914                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 915
 916         return status;
 917 }
 918
 919 /**
 920  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 921  *  @hw: pointer to hardware structure
 922  *  @speed: new link speed
 923  **/
 924 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 925                                        ixgbe_link_speed speed,
 926                                        bool autoneg_wait_to_complete)
 927 {
 928         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 929
 930         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 931
 932         /*
 933          * Clear autoneg_advertised and set new values based on input link
 934          * speed.
 935          */
 936         hw->phy.autoneg_advertised = 0;
 937
 938         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 939                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 940
 941         if (speed & IXGBE_LINK_SPEED_5GB_FULL)
 942                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
 943
 944         if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
 945                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
 946
 947         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 948                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 949
 950         if (speed & IXGBE_LINK_SPEED_100_FULL)
 951                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 952
 953         /* Setup link based on the new speed settings */
 954         hw->phy.ops.setup_link(hw);
 955
 956         return IXGBE_SUCCESS;
 957 }
 958
 959 /**
 960  * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
 961  * @hw: pointer to hardware structure
 962  *
 963  * Determines the supported link capabilities by reading the PHY auto
 964  * negotiation register.
 965  **/
 966 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
 967 {
 968         s32 status;
 969         u16 speed_ability;
 970
 971         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 972                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 973                                       &speed_ability);
 974         if (status)
 975                 return status;
 976
 977         if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 978                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
 979         if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 980                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
 981         if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 982                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
 983
 984         switch (hw->mac.type) {
 985         case ixgbe_mac_X550:
 986                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
 987                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
 988                 break;
 989         case ixgbe_mac_X550EM_x:
 990                 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
 991                 break;
 992         default:
 993                 break;
 994         }
 995
 996         return status;
 997 }
 998
 999 /**
1000  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
1001  *  @hw: pointer to hardware structure
1002  *  @speed: pointer to link speed
1003  *  @autoneg: boolean auto-negotiation value
1004  **/
1005 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
1006                                                ixgbe_link_speed *speed,
1007                                                bool *autoneg)
1008 {
1009         s32 status = IXGBE_SUCCESS;
1010
1011         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
1012
1013         *autoneg = true;
1014         if (!hw->phy.speeds_supported)
1015                 status = ixgbe_get_copper_speeds_supported(hw);
1016
1017         *speed = hw->phy.speeds_supported;
1018         return status;
1019 }
1020
1021 /**
1022  *  ixgbe_check_phy_link_tnx - Determine link and speed status
1023  *  @hw: pointer to hardware structure
1024  *
1025  *  Reads the VS1 register to determine if link is up and the current speed for
1026  *  the PHY.
1027  **/
1028 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1029                              bool *link_up)
1030 {
1031         s32 status = IXGBE_SUCCESS;
1032         u32 time_out;
1033         u32 max_time_out = 10;
1034         u16 phy_link = 0;
1035         u16 phy_speed = 0;
1036         u16 phy_data = 0;
1037
1038         DEBUGFUNC("ixgbe_check_phy_link_tnx");
1039
1040         /* Initialize speed and link to default case */
1041         *link_up = false;
1042         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1043
1044         /*
1045          * Check current speed and link status of the PHY register.
1046          * This is a vendor specific register and may have to
1047          * be changed for other copper PHYs.
1048          */
1049         for (time_out = 0; time_out < max_time_out; time_out++) {
1050                 usec_delay(10);
1051                 status = hw->phy.ops.read_reg(hw,
1052                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1053                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1054                                         &phy_data);
1055                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1056                 phy_speed = phy_data &
1057                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1058                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1059                         *link_up = true;
1060                         if (phy_speed ==
1061                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1062                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1063                         break;
1064                 }
1065         }
1066
1067         return status;
1068 }
1069
1070 /**
1071  *      ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1072  *      @hw: pointer to hardware structure
1073  *
1074  *      Restart auto-negotiation and PHY and waits for completion.
1075  **/
1076 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1077 {
1078         s32 status = IXGBE_SUCCESS;
1079         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1080         bool autoneg = false;
1081         ixgbe_link_speed speed;
1082
1083         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1084
1085         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1086
1087         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1088                 /* Set or unset auto-negotiation 10G advertisement */
1089                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1090                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1091                                      &autoneg_reg);
1092
1093                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1094                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1095                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1096
1097                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1098                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1099                                       autoneg_reg);
1100         }
1101
1102         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1103                 /* Set or unset auto-negotiation 1G advertisement */
1104                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1105                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1106                                      &autoneg_reg);
1107
1108                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1109                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1110                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1111
1112                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1113                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1114                                       autoneg_reg);
1115         }
1116
1117         if (speed & IXGBE_LINK_SPEED_100_FULL) {
1118                 /* Set or unset auto-negotiation 100M advertisement */
1119                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1120                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1121                                      &autoneg_reg);
1122
1123                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1124                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1125                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1126
1127                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1128                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1129                                       autoneg_reg);
1130         }
1131
1132         /* Blocked by MNG FW so don't reset PHY */
1133         if (ixgbe_check_reset_blocked(hw))
1134                 return status;
1135
1136         /* Restart PHY auto-negotiation. */
1137         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1138                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1139
1140         autoneg_reg |= IXGBE_MII_RESTART;
1141
1142         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1143                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1144
1145         return status;
1146 }
1147
1148 /**
1149  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1150  *  @hw: pointer to hardware structure
1151  *  @firmware_version: pointer to the PHY Firmware Version
1152  **/
1153 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1154                                        u16 *firmware_version)
1155 {
1156         s32 status;
1157
1158         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1159
1160         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1161                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1162                                       firmware_version);
1163
1164         return status;
1165 }
1166
1167 /**
1168  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1169  *  @hw: pointer to hardware structure
1170  *  @firmware_version: pointer to the PHY Firmware Version
1171  **/
1172 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1173                                            u16 *firmware_version)
1174 {
1175         s32 status;
1176
1177         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1178
1179         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1180                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1181                                       firmware_version);
1182
1183         return status;
1184 }
1185
1186 /**
1187  *  ixgbe_reset_phy_nl - Performs a PHY reset
1188  *  @hw: pointer to hardware structure
1189  **/
1190 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1191 {
1192         u16 phy_offset, control, eword, edata, block_crc;
1193         bool end_data = false;
1194         u16 list_offset, data_offset;
1195         u16 phy_data = 0;
1196         s32 ret_val = IXGBE_SUCCESS;
1197         u32 i;
1198
1199         DEBUGFUNC("ixgbe_reset_phy_nl");
1200
1201         /* Blocked by MNG FW so bail */
1202         if (ixgbe_check_reset_blocked(hw))
1203                 goto out;
1204
1205         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1206                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1207
1208         /* reset the PHY and poll for completion */
1209         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1210                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
1211                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1212
1213         for (i = 0; i < 100; i++) {
1214                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1215                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1216                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1217                         break;
1218                 msec_delay(10);
1219         }
1220
1221         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1222                 DEBUGOUT("PHY reset did not complete.\n");
1223                 ret_val = IXGBE_ERR_PHY;
1224                 goto out;
1225         }
1226
1227         /* Get init offsets */
1228         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1229                                                       &data_offset);
1230         if (ret_val != IXGBE_SUCCESS)
1231                 goto out;
1232
1233         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1234         data_offset++;
1235         while (!end_data) {
1236                 /*
1237                  * Read control word from PHY init contents offset
1238                  */
1239                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1240                 if (ret_val)
1241                         goto err_eeprom;
1242                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1243                            IXGBE_CONTROL_SHIFT_NL;
1244                 edata = eword & IXGBE_DATA_MASK_NL;
1245                 switch (control) {
1246                 case IXGBE_DELAY_NL:
1247                         data_offset++;
1248                         DEBUGOUT1("DELAY: %d MS\n", edata);
1249                         msec_delay(edata);
1250                         break;
1251                 case IXGBE_DATA_NL:
1252                         DEBUGOUT("DATA:\n");
1253                         data_offset++;
1254                         ret_val = hw->eeprom.ops.read(hw, data_offset,
1255                                                       &phy_offset);
1256                         if (ret_val)
1257                                 goto err_eeprom;
1258                         data_offset++;
1259                         for (i = 0; i < edata; i++) {
1260                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
1261                                                               &eword);
1262                                 if (ret_val)
1263                                         goto err_eeprom;
1264                                 hw->phy.ops.write_reg(hw, phy_offset,
1265                                                       IXGBE_TWINAX_DEV, eword);
1266                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1267                                           phy_offset);
1268                                 data_offset++;
1269                                 phy_offset++;
1270                         }
1271                         break;
1272                 case IXGBE_CONTROL_NL:
1273                         data_offset++;
1274                         DEBUGOUT("CONTROL:\n");
1275                         if (edata == IXGBE_CONTROL_EOL_NL) {
1276                                 DEBUGOUT("EOL\n");
1277                                 end_data = true;
1278                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
1279                                 DEBUGOUT("SOL\n");
1280                         } else {
1281                                 DEBUGOUT("Bad control value\n");
1282                                 ret_val = IXGBE_ERR_PHY;
1283                                 goto out;
1284                         }
1285                         break;
1286                 default:
1287                         DEBUGOUT("Bad control type\n");
1288                         ret_val = IXGBE_ERR_PHY;
1289                         goto out;
1290                 }
1291         }
1292
1293 out:
1294         return ret_val;
1295
1296 err_eeprom:
1297         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1298                       "eeprom read at offset %d failed", data_offset);
1299         return IXGBE_ERR_PHY;
1300 }
1301
1302 /**
1303  *  ixgbe_identify_module_generic - Identifies module type
1304  *  @hw: pointer to hardware structure
1305  *
1306  *  Determines HW type and calls appropriate function.
1307  **/
1308 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1309 {
1310         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1311
1312         DEBUGFUNC("ixgbe_identify_module_generic");
1313
1314         switch (hw->mac.ops.get_media_type(hw)) {
1315         case ixgbe_media_type_fiber:
1316                 status = ixgbe_identify_sfp_module_generic(hw);
1317                 break;
1318
1319         case ixgbe_media_type_fiber_qsfp:
1320                 status = ixgbe_identify_qsfp_module_generic(hw);
1321                 break;
1322
1323         default:
1324                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1325                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1326                 break;
1327         }
1328
1329         return status;
1330 }
1331
1332 /**
1333  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1334  *  @hw: pointer to hardware structure
1335  *
1336  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1337  **/
1338 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1339 {
1340         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1341         u32 vendor_oui = 0;
1342         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1343         u8 identifier = 0;
1344         u8 comp_codes_1g = 0;
1345         u8 comp_codes_10g = 0;
1346         u8 oui_bytes[3] = {0, 0, 0};
1347         u8 cable_tech = 0;
1348         u8 cable_spec = 0;
1349         u16 enforce_sfp = 0;
1350
1351         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1352
1353         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1354                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1355                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1356                 goto out;
1357         }
1358
1359         /* LAN ID is needed for I2C access */
1360         hw->mac.ops.set_lan_id(hw);
1361
1362         status = hw->phy.ops.read_i2c_eeprom(hw,
1363                                              IXGBE_SFF_IDENTIFIER,
1364                                              &identifier);
1365
1366         if (status != IXGBE_SUCCESS)
1367                 goto err_read_i2c_eeprom;
1368
1369         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1370                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1371                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1372         } else {
1373                 status = hw->phy.ops.read_i2c_eeprom(hw,
1374                                                      IXGBE_SFF_1GBE_COMP_CODES,
1375                                                      &comp_codes_1g);
1376
1377                 if (status != IXGBE_SUCCESS)
1378                         goto err_read_i2c_eeprom;
1379
1380                 status = hw->phy.ops.read_i2c_eeprom(hw,
1381                                                      IXGBE_SFF_10GBE_COMP_CODES,
1382                                                      &comp_codes_10g);
1383
1384                 if (status != IXGBE_SUCCESS)
1385                         goto err_read_i2c_eeprom;
1386                 status = hw->phy.ops.read_i2c_eeprom(hw,
1387                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1388                                                      &cable_tech);
1389
1390                 if (status != IXGBE_SUCCESS)
1391                         goto err_read_i2c_eeprom;
1392
1393                  /* ID Module
1394                   * =========
1395                   * 0   SFP_DA_CU
1396                   * 1   SFP_SR
1397                   * 2   SFP_LR
1398                   * 3   SFP_DA_CORE0 - 82599-specific
1399                   * 4   SFP_DA_CORE1 - 82599-specific
1400                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1401                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1402                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1403                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1404                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1405                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1406                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1407                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1408                   */
1409                 if (hw->mac.type == ixgbe_mac_82598EB) {
1410                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1411                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1412                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1413                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1414                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1415                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1416                         else
1417                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1418                 } else {
1419                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1420                                 if (hw->bus.lan_id == 0)
1421                                         hw->phy.sfp_type =
1422                                                      ixgbe_sfp_type_da_cu_core0;
1423                                 else
1424                                         hw->phy.sfp_type =
1425                                                      ixgbe_sfp_type_da_cu_core1;
1426                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1427                                 hw->phy.ops.read_i2c_eeprom(
1428                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1429                                                 &cable_spec);
1430                                 if (cable_spec &
1431                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1432                                         if (hw->bus.lan_id == 0)
1433                                                 hw->phy.sfp_type =
1434                                                 ixgbe_sfp_type_da_act_lmt_core0;
1435                                         else
1436                                                 hw->phy.sfp_type =
1437                                                 ixgbe_sfp_type_da_act_lmt_core1;
1438                                 } else {
1439                                         hw->phy.sfp_type =
1440                                                         ixgbe_sfp_type_unknown;
1441                                 }
1442                         } else if (comp_codes_10g &
1443                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1444                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1445                                 if (hw->bus.lan_id == 0)
1446                                         hw->phy.sfp_type =
1447                                                       ixgbe_sfp_type_srlr_core0;
1448                                 else
1449                                         hw->phy.sfp_type =
1450                                                       ixgbe_sfp_type_srlr_core1;
1451                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1452                                 if (hw->bus.lan_id == 0)
1453                                         hw->phy.sfp_type =
1454                                                 ixgbe_sfp_type_1g_cu_core0;
1455                                 else
1456                                         hw->phy.sfp_type =
1457                                                 ixgbe_sfp_type_1g_cu_core1;
1458                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1459                                 if (hw->bus.lan_id == 0)
1460                                         hw->phy.sfp_type =
1461                                                 ixgbe_sfp_type_1g_sx_core0;
1462                                 else
1463                                         hw->phy.sfp_type =
1464                                                 ixgbe_sfp_type_1g_sx_core1;
1465                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1466                                 if (hw->bus.lan_id == 0)
1467                                         hw->phy.sfp_type =
1468                                                 ixgbe_sfp_type_1g_lx_core0;
1469                                 else
1470                                         hw->phy.sfp_type =
1471                                                 ixgbe_sfp_type_1g_lx_core1;
1472                         } else {
1473                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1474                         }
1475                 }
1476
1477                 if (hw->phy.sfp_type != stored_sfp_type)
1478                         hw->phy.sfp_setup_needed = true;
1479
1480                 /* Determine if the SFP+ PHY is dual speed or not. */
1481                 hw->phy.multispeed_fiber = false;
1482                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1483                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1484                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1485                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1486                         hw->phy.multispeed_fiber = true;
1487
1488                 /* Determine PHY vendor */
1489                 if (hw->phy.type != ixgbe_phy_nl) {
1490                         hw->phy.id = identifier;
1491                         status = hw->phy.ops.read_i2c_eeprom(hw,
1492                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1493                                                     &oui_bytes[0]);
1494
1495                         if (status != IXGBE_SUCCESS)
1496                                 goto err_read_i2c_eeprom;
1497
1498                         status = hw->phy.ops.read_i2c_eeprom(hw,
1499                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1500                                                     &oui_bytes[1]);
1501
1502                         if (status != IXGBE_SUCCESS)
1503                                 goto err_read_i2c_eeprom;
1504
1505                         status = hw->phy.ops.read_i2c_eeprom(hw,
1506                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1507                                                     &oui_bytes[2]);
1508
1509                         if (status != IXGBE_SUCCESS)
1510                                 goto err_read_i2c_eeprom;
1511
1512                         vendor_oui =
1513                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1514                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1515                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1516
1517                         switch (vendor_oui) {
1518                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1519                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1520                                         hw->phy.type =
1521                                                     ixgbe_phy_sfp_passive_tyco;
1522                                 break;
1523                         case IXGBE_SFF_VENDOR_OUI_FTL:
1524                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1525                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1526                                 else
1527                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1528                                 break;
1529                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1530                                 hw->phy.type = ixgbe_phy_sfp_avago;
1531                                 break;
1532                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1533                                 hw->phy.type = ixgbe_phy_sfp_intel;
1534                                 break;
1535                         default:
1536                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1537                                         hw->phy.type =
1538                                                  ixgbe_phy_sfp_passive_unknown;
1539                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1540                                         hw->phy.type =
1541                                                 ixgbe_phy_sfp_active_unknown;
1542                                 else
1543                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1544                                 break;
1545                         }
1546                 }
1547
1548                 /* Allow any DA cable vendor */
1549                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1550                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1551                         status = IXGBE_SUCCESS;
1552                         goto out;
1553                 }
1554
1555                 /* Verify supported 1G SFP modules */
1556                 if (comp_codes_10g == 0 &&
1557                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1558                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1559                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1560                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1561                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1562                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1563                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1564                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1565                         goto out;
1566                 }
1567
1568                 /* Anything else 82598-based is supported */
1569                 if (hw->mac.type == ixgbe_mac_82598EB) {
1570                         status = IXGBE_SUCCESS;
1571                         goto out;
1572                 }
1573
1574                 ixgbe_get_device_caps(hw, &enforce_sfp);
1575                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1576                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1577                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1578                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1579                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1580                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1581                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1582                         /* Make sure we're a supported PHY type */
1583                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1584                                 status = IXGBE_SUCCESS;
1585                         } else {
1586                                 if (hw->allow_unsupported_sfp == true) {
1587                                         EWARN(hw, "WARNING: Intel (R) Network "
1588                                               "Connections are quality tested "
1589                                               "using Intel (R) Ethernet Optics."
1590                                               " Using untested modules is not "
1591                                               "supported and may cause unstable"
1592                                               " operation or damage to the "
1593                                               "module or the adapter. Intel "
1594                                               "Corporation is not responsible "
1595                                               "for any harm caused by using "
1596                                               "untested modules.\n", status);
1597                                         status = IXGBE_SUCCESS;
1598                                 } else {
1599                                         DEBUGOUT("SFP+ module not supported\n");
1600                                         hw->phy.type =
1601                                                 ixgbe_phy_sfp_unsupported;
1602                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1603                                 }
1604                         }
1605                 } else {
1606                         status = IXGBE_SUCCESS;
1607                 }
1608         }
1609
1610 out:
1611         return status;
1612
1613 err_read_i2c_eeprom:
1614         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1615         if (hw->phy.type != ixgbe_phy_nl) {
1616                 hw->phy.id = 0;
1617                 hw->phy.type = ixgbe_phy_unknown;
1618         }
1619         return IXGBE_ERR_SFP_NOT_PRESENT;
1620 }
1621
1622 /**
1623  *  ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1624  *  @hw: pointer to hardware structure
1625  *
1626  *  Determines physical layer capabilities of the current SFP.
1627  */
1628 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1629 {
1630         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1631         u8 comp_codes_10g = 0;
1632         u8 comp_codes_1g = 0;
1633
1634         DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1635
1636         hw->phy.ops.identify_sfp(hw);
1637         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1638                 return physical_layer;
1639
1640         switch (hw->phy.type) {
1641         case ixgbe_phy_sfp_passive_tyco:
1642         case ixgbe_phy_sfp_passive_unknown:
1643         case ixgbe_phy_qsfp_passive_unknown:
1644                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1645                 break;
1646         case ixgbe_phy_sfp_ftl_active:
1647         case ixgbe_phy_sfp_active_unknown:
1648         case ixgbe_phy_qsfp_active_unknown:
1649                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1650                 break;
1651         case ixgbe_phy_sfp_avago:
1652         case ixgbe_phy_sfp_ftl:
1653         case ixgbe_phy_sfp_intel:
1654         case ixgbe_phy_sfp_unknown:
1655                 hw->phy.ops.read_i2c_eeprom(hw,
1656                       IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1657                 hw->phy.ops.read_i2c_eeprom(hw,
1658                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1659                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1660                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1661                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1662                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1663                 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1664                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1665                 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1666                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1667                 break;
1668         case ixgbe_phy_qsfp_intel:
1669         case ixgbe_phy_qsfp_unknown:
1670                 hw->phy.ops.read_i2c_eeprom(hw,
1671                       IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1672                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1673                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1674                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1675                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1676                 break;
1677         default:
1678                 break;
1679         }
1680
1681         return physical_layer;
1682 }
1683
1684 /**
1685  *  ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1686  *  @hw: pointer to hardware structure
1687  *
1688  *  Searches for and identifies the QSFP module and assigns appropriate PHY type
1689  **/
1690 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1691 {
1692         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1693         u32 vendor_oui = 0;
1694         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1695         u8 identifier = 0;
1696         u8 comp_codes_1g = 0;
1697         u8 comp_codes_10g = 0;
1698         u8 oui_bytes[3] = {0, 0, 0};
1699         u16 enforce_sfp = 0;
1700         u8 connector = 0;
1701         u8 cable_length = 0;
1702         u8 device_tech = 0;
1703         bool active_cable = false;
1704
1705         DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1706
1707         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1708                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1709                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1710                 goto out;
1711         }
1712
1713         /* LAN ID is needed for I2C access */
1714         hw->mac.ops.set_lan_id(hw);
1715
1716         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1717                                              &identifier);
1718
1719         if (status != IXGBE_SUCCESS)
1720                 goto err_read_i2c_eeprom;
1721
1722         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1723                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1724                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1725                 goto out;
1726         }
1727
1728         hw->phy.id = identifier;
1729
1730         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1731                                              &comp_codes_10g);
1732
1733         if (status != IXGBE_SUCCESS)
1734                 goto err_read_i2c_eeprom;
1735
1736         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1737                                              &comp_codes_1g);
1738
1739         if (status != IXGBE_SUCCESS)
1740                 goto err_read_i2c_eeprom;
1741
1742         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1743                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1744                 if (hw->bus.lan_id == 0)
1745                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1746                 else
1747                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1748         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1749                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1750                 if (hw->bus.lan_id == 0)
1751                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1752                 else
1753                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1754         } else {
1755                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1756                         active_cable = true;
1757
1758                 if (!active_cable) {
1759                         /* check for active DA cables that pre-date
1760                          * SFF-8436 v3.6 */
1761                         hw->phy.ops.read_i2c_eeprom(hw,
1762                                         IXGBE_SFF_QSFP_CONNECTOR,
1763                                         &connector);
1764
1765                         hw->phy.ops.read_i2c_eeprom(hw,
1766                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1767                                         &cable_length);
1768
1769                         hw->phy.ops.read_i2c_eeprom(hw,
1770                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1771                                         &device_tech);
1772
1773                         if ((connector ==
1774                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1775                             (cable_length > 0) &&
1776                             ((device_tech >> 4) ==
1777                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1778                                 active_cable = true;
1779                 }
1780
1781                 if (active_cable) {
1782                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1783                         if (hw->bus.lan_id == 0)
1784                                 hw->phy.sfp_type =
1785                                                 ixgbe_sfp_type_da_act_lmt_core0;
1786                         else
1787                                 hw->phy.sfp_type =
1788                                                 ixgbe_sfp_type_da_act_lmt_core1;
1789                 } else {
1790                         /* unsupported module type */
1791                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1792                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1793                         goto out;
1794                 }
1795         }
1796
1797         if (hw->phy.sfp_type != stored_sfp_type)
1798                 hw->phy.sfp_setup_needed = true;
1799
1800         /* Determine if the QSFP+ PHY is dual speed or not. */
1801         hw->phy.multispeed_fiber = false;
1802         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1803            (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1804            ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1805            (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1806                 hw->phy.multispeed_fiber = true;
1807
1808         /* Determine PHY vendor for optical modules */
1809         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1810                               IXGBE_SFF_10GBASELR_CAPABLE))  {
1811                 status = hw->phy.ops.read_i2c_eeprom(hw,
1812                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1813                                             &oui_bytes[0]);
1814
1815                 if (status != IXGBE_SUCCESS)
1816                         goto err_read_i2c_eeprom;
1817
1818                 status = hw->phy.ops.read_i2c_eeprom(hw,
1819                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1820                                             &oui_bytes[1]);
1821
1822                 if (status != IXGBE_SUCCESS)
1823                         goto err_read_i2c_eeprom;
1824
1825                 status = hw->phy.ops.read_i2c_eeprom(hw,
1826                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1827                                             &oui_bytes[2]);
1828
1829                 if (status != IXGBE_SUCCESS)
1830                         goto err_read_i2c_eeprom;
1831
1832                 vendor_oui =
1833                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1834                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1835                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1836
1837                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1838                         hw->phy.type = ixgbe_phy_qsfp_intel;
1839                 else
1840                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1841
1842                 ixgbe_get_device_caps(hw, &enforce_sfp);
1843                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1844                         /* Make sure we're a supported PHY type */
1845                         if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1846                                 status = IXGBE_SUCCESS;
1847                         } else {
1848                                 if (hw->allow_unsupported_sfp == true) {
1849                                         EWARN(hw, "WARNING: Intel (R) Network "
1850                                               "Connections are quality tested "
1851                                               "using Intel (R) Ethernet Optics."
1852                                               " Using untested modules is not "
1853                                               "supported and may cause unstable"
1854                                               " operation or damage to the "
1855                                               "module or the adapter. Intel "
1856                                               "Corporation is not responsible "
1857                                               "for any harm caused by using "
1858                                               "untested modules.\n", status);
1859                                         status = IXGBE_SUCCESS;
1860                                 } else {
1861                                         DEBUGOUT("QSFP module not supported\n");
1862                                         hw->phy.type =
1863                                                 ixgbe_phy_sfp_unsupported;
1864                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1865                                 }
1866                         }
1867                 } else {
1868                         status = IXGBE_SUCCESS;
1869                 }
1870         }
1871
1872 out:
1873         return status;
1874
1875 err_read_i2c_eeprom:
1876         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1877         hw->phy.id = 0;
1878         hw->phy.type = ixgbe_phy_unknown;
1879
1880         return IXGBE_ERR_SFP_NOT_PRESENT;
1881 }
1882
1883
1884 /**
1885  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1886  *  @hw: pointer to hardware structure
1887  *  @list_offset: offset to the SFP ID list
1888  *  @data_offset: offset to the SFP data block
1889  *
1890  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1891  *  so it returns the offsets to the phy init sequence block.
1892  **/
1893 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1894                                         u16 *list_offset,
1895                                         u16 *data_offset)
1896 {
1897         u16 sfp_id;
1898         u16 sfp_type = hw->phy.sfp_type;
1899
1900         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1901
1902         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1903                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1904
1905         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1906                 return IXGBE_ERR_SFP_NOT_PRESENT;
1907
1908         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1909             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1910                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1911
1912         /*
1913          * Limiting active cables and 1G Phys must be initialized as
1914          * SR modules
1915          */
1916         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1917             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1918             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1919             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1920                 sfp_type = ixgbe_sfp_type_srlr_core0;
1921         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1922                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1923                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1924                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1925                 sfp_type = ixgbe_sfp_type_srlr_core1;
1926
1927         /* Read offset to PHY init contents */
1928         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1929                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1930                               "eeprom read at offset %d failed",
1931                               IXGBE_PHY_INIT_OFFSET_NL);
1932                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1933         }
1934
1935         if ((!*list_offset) || (*list_offset == 0xFFFF))
1936                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1937
1938         /* Shift offset to first ID word */
1939         (*list_offset)++;
1940
1941         /*
1942          * Find the matching SFP ID in the EEPROM
1943          * and program the init sequence
1944          */
1945         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1946                 goto err_phy;
1947
1948         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1949                 if (sfp_id == sfp_type) {
1950                         (*list_offset)++;
1951                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1952                                 goto err_phy;
1953                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1954                                 DEBUGOUT("SFP+ module not supported\n");
1955                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1956                         } else {
1957                                 break;
1958                         }
1959                 } else {
1960                         (*list_offset) += 2;
1961                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1962                                 goto err_phy;
1963                 }
1964         }
1965
1966         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1967                 DEBUGOUT("No matching SFP+ module found\n");
1968                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1969         }
1970
1971         return IXGBE_SUCCESS;
1972
1973 err_phy:
1974         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1975                       "eeprom read at offset %d failed", *list_offset);
1976         return IXGBE_ERR_PHY;
1977 }
1978
1979 /**
1980  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1981  *  @hw: pointer to hardware structure
1982  *  @byte_offset: EEPROM byte offset to read
1983  *  @eeprom_data: value read
1984  *
1985  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1986  **/
1987 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1988                                   u8 *eeprom_data)
1989 {
1990         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1991
1992         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1993                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1994                                          eeprom_data);
1995 }
1996
1997 /**
1998  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1999  *  @hw: pointer to hardware structure
2000  *  @byte_offset: byte offset at address 0xA2
2001  *  @eeprom_data: value read
2002  *
2003  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
2004  **/
2005 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
2006                                           u8 *sff8472_data)
2007 {
2008         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
2009                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
2010                                          sff8472_data);
2011 }
2012
2013 /**
2014  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
2015  *  @hw: pointer to hardware structure
2016  *  @byte_offset: EEPROM byte offset to write
2017  *  @eeprom_data: value to write
2018  *
2019  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
2020  **/
2021 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
2022                                    u8 eeprom_data)
2023 {
2024         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
2025
2026         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
2027                                           IXGBE_I2C_EEPROM_DEV_ADDR,
2028                                           eeprom_data);
2029 }
2030
2031 /**
2032  * ixgbe_is_sfp_probe - Returns true if SFP is being detected
2033  * @hw: pointer to hardware structure
2034  * @offset: eeprom offset to be read
2035  * @addr: I2C address to be read
2036  */
2037 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
2038 {
2039         if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
2040             offset == IXGBE_SFF_IDENTIFIER &&
2041             hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2042                 return true;
2043         return false;
2044 }
2045
2046 /**
2047  *  ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
2048  *  @hw: pointer to hardware structure
2049  *  @byte_offset: byte offset to read
2050  *  @data: value read
2051  *  @lock: true if to take and release semaphore
2052  *
2053  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2054  *  a specified device address.
2055  **/
2056 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2057                                            u8 dev_addr, u8 *data, bool lock)
2058 {
2059         s32 status;
2060         u32 max_retry = 10;
2061         u32 retry = 0;
2062         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2063         bool nack = 1;
2064         *data = 0;
2065
2066         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2067
2068         if (hw->mac.type >= ixgbe_mac_X550)
2069                 max_retry = 3;
2070         if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2071                 max_retry = IXGBE_SFP_DETECT_RETRIES;
2072
2073         do {
2074                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2075                         return IXGBE_ERR_SWFW_SYNC;
2076
2077                 ixgbe_i2c_start(hw);
2078
2079                 /* Device Address and write indication */
2080                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2081                 if (status != IXGBE_SUCCESS)
2082                         goto fail;
2083
2084                 status = ixgbe_get_i2c_ack(hw);
2085                 if (status != IXGBE_SUCCESS)
2086                         goto fail;
2087
2088                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2089                 if (status != IXGBE_SUCCESS)
2090                         goto fail;
2091
2092                 status = ixgbe_get_i2c_ack(hw);
2093                 if (status != IXGBE_SUCCESS)
2094                         goto fail;
2095
2096                 ixgbe_i2c_start(hw);
2097
2098                 /* Device Address and read indication */
2099                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2100                 if (status != IXGBE_SUCCESS)
2101                         goto fail;
2102
2103                 status = ixgbe_get_i2c_ack(hw);
2104                 if (status != IXGBE_SUCCESS)
2105                         goto fail;
2106
2107                 status = ixgbe_clock_in_i2c_byte(hw, data);
2108                 if (status != IXGBE_SUCCESS)
2109                         goto fail;
2110
2111                 status = ixgbe_clock_out_i2c_bit(hw, nack);
2112                 if (status != IXGBE_SUCCESS)
2113                         goto fail;
2114
2115                 ixgbe_i2c_stop(hw);
2116                 if (lock)
2117                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2118                 return IXGBE_SUCCESS;
2119
2120 fail:
2121                 ixgbe_i2c_bus_clear(hw);
2122                 if (lock) {
2123                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2124                         msec_delay(100);
2125                 }
2126                 retry++;
2127                 if (retry < max_retry)
2128                         DEBUGOUT("I2C byte read error - Retrying.\n");
2129                 else
2130                         DEBUGOUT("I2C byte read error.\n");
2131
2132         } while (retry < max_retry);
2133
2134         return status;
2135 }
2136
2137 /**
2138  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2139  *  @hw: pointer to hardware structure
2140  *  @byte_offset: byte offset to read
2141  *  @data: value read
2142  *
2143  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2144  *  a specified device address.
2145  **/
2146 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2147                                 u8 dev_addr, u8 *data)
2148 {
2149         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2150                                                data, true);
2151 }
2152
2153 /**
2154  *  ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2155  *  @hw: pointer to hardware structure
2156  *  @byte_offset: byte offset to read
2157  *  @data: value read
2158  *
2159  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2160  *  a specified device address.
2161  **/
2162 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2163                                          u8 dev_addr, u8 *data)
2164 {
2165         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2166                                                data, false);
2167 }
2168
2169 /**
2170  *  ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2171  *  @hw: pointer to hardware structure
2172  *  @byte_offset: byte offset to write
2173  *  @data: value to write
2174  *  @lock: true if to take and release semaphore
2175  *
2176  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2177  *  a specified device address.
2178  **/
2179 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2180                                             u8 dev_addr, u8 data, bool lock)
2181 {
2182         s32 status;
2183         u32 max_retry = 1;
2184         u32 retry = 0;
2185         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2186
2187         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2188
2189         if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2190             IXGBE_SUCCESS)
2191                 return IXGBE_ERR_SWFW_SYNC;
2192
2193         do {
2194                 ixgbe_i2c_start(hw);
2195
2196                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2197                 if (status != IXGBE_SUCCESS)
2198                         goto fail;
2199
2200                 status = ixgbe_get_i2c_ack(hw);
2201                 if (status != IXGBE_SUCCESS)
2202                         goto fail;
2203
2204                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2205                 if (status != IXGBE_SUCCESS)
2206                         goto fail;
2207
2208                 status = ixgbe_get_i2c_ack(hw);
2209                 if (status != IXGBE_SUCCESS)
2210                         goto fail;
2211
2212                 status = ixgbe_clock_out_i2c_byte(hw, data);
2213                 if (status != IXGBE_SUCCESS)
2214                         goto fail;
2215
2216                 status = ixgbe_get_i2c_ack(hw);
2217                 if (status != IXGBE_SUCCESS)
2218                         goto fail;
2219
2220                 ixgbe_i2c_stop(hw);
2221                 if (lock)
2222                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2223                 return IXGBE_SUCCESS;
2224
2225 fail:
2226                 ixgbe_i2c_bus_clear(hw);
2227                 retry++;
2228                 if (retry < max_retry)
2229                         DEBUGOUT("I2C byte write error - Retrying.\n");
2230                 else
2231                         DEBUGOUT("I2C byte write error.\n");
2232         } while (retry < max_retry);
2233
2234         if (lock)
2235                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2236
2237         return status;
2238 }
2239
2240 /**
2241  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2242  *  @hw: pointer to hardware structure
2243  *  @byte_offset: byte offset to write
2244  *  @data: value to write
2245  *
2246  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2247  *  a specified device address.
2248  **/
2249 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2250                                  u8 dev_addr, u8 data)
2251 {
2252         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2253                                                 data, true);
2254 }
2255
2256 /**
2257  *  ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2258  *  @hw: pointer to hardware structure
2259  *  @byte_offset: byte offset to write
2260  *  @data: value to write
2261  *
2262  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2263  *  a specified device address.
2264  **/
2265 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2266                                           u8 dev_addr, u8 data)
2267 {
2268         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2269                                                 data, false);
2270 }
2271
2272 /**
2273  *  ixgbe_i2c_start - Sets I2C start condition
2274  *  @hw: pointer to hardware structure
2275  *
2276  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
2277  *  Set bit-bang mode on X550 hardware.
2278  **/
2279 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2280 {
2281         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2282
2283         DEBUGFUNC("ixgbe_i2c_start");
2284
2285         i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2286
2287         /* Start condition must begin with data and clock high */
2288         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2289         ixgbe_raise_i2c_clk(hw, &i2cctl);
2290
2291         /* Setup time for start condition (4.7us) */
2292         usec_delay(IXGBE_I2C_T_SU_STA);
2293
2294         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2295
2296         /* Hold time for start condition (4us) */
2297         usec_delay(IXGBE_I2C_T_HD_STA);
2298
2299         ixgbe_lower_i2c_clk(hw, &i2cctl);
2300
2301         /* Minimum low period of clock is 4.7 us */
2302         usec_delay(IXGBE_I2C_T_LOW);
2303
2304 }
2305
2306 /**
2307  *  ixgbe_i2c_stop - Sets I2C stop condition
2308  *  @hw: pointer to hardware structure
2309  *
2310  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
2311  *  Disables bit-bang mode and negates data output enable on X550
2312  *  hardware.
2313  **/
2314 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2315 {
2316         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2317         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2318         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2319         u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2320
2321         DEBUGFUNC("ixgbe_i2c_stop");
2322
2323         /* Stop condition must begin with data low and clock high */
2324         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2325         ixgbe_raise_i2c_clk(hw, &i2cctl);
2326
2327         /* Setup time for stop condition (4us) */
2328         usec_delay(IXGBE_I2C_T_SU_STO);
2329
2330         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2331
2332         /* bus free time between stop and start (4.7us)*/
2333         usec_delay(IXGBE_I2C_T_BUF);
2334
2335         if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2336                 i2cctl &= ~bb_en_bit;
2337                 i2cctl |= data_oe_bit | clk_oe_bit;
2338                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2339                 IXGBE_WRITE_FLUSH(hw);
2340         }
2341 }
2342
2343 /**
2344  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2345  *  @hw: pointer to hardware structure
2346  *  @data: data byte to clock in
2347  *
2348  *  Clocks in one byte data via I2C data/clock
2349  **/
2350 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2351 {
2352         s32 i;
2353         bool bit = 0;
2354
2355         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2356
2357         *data = 0;
2358         for (i = 7; i >= 0; i--) {
2359                 ixgbe_clock_in_i2c_bit(hw, &bit);
2360                 *data |= bit << i;
2361         }
2362
2363         return IXGBE_SUCCESS;
2364 }
2365
2366 /**
2367  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2368  *  @hw: pointer to hardware structure
2369  *  @data: data byte clocked out
2370  *
2371  *  Clocks out one byte data via I2C data/clock
2372  **/
2373 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2374 {
2375         s32 status = IXGBE_SUCCESS;
2376         s32 i;
2377         u32 i2cctl;
2378         bool bit;
2379
2380         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2381
2382         for (i = 7; i >= 0; i--) {
2383                 bit = (data >> i) & 0x1;
2384                 status = ixgbe_clock_out_i2c_bit(hw, bit);
2385
2386                 if (status != IXGBE_SUCCESS)
2387                         break;
2388         }
2389
2390         /* Release SDA line (set high) */
2391         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2392         i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2393         i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2394         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2395         IXGBE_WRITE_FLUSH(hw);
2396
2397         return status;
2398 }
2399
2400 /**
2401  *  ixgbe_get_i2c_ack - Polls for I2C ACK
2402  *  @hw: pointer to hardware structure
2403  *
2404  *  Clocks in/out one bit via I2C data/clock
2405  **/
2406 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2407 {
2408         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2409         s32 status = IXGBE_SUCCESS;
2410         u32 i = 0;
2411         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2412         u32 timeout = 10;
2413         bool ack = 1;
2414
2415         DEBUGFUNC("ixgbe_get_i2c_ack");
2416
2417         if (data_oe_bit) {
2418                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2419                 i2cctl |= data_oe_bit;
2420                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2421                 IXGBE_WRITE_FLUSH(hw);
2422         }
2423         ixgbe_raise_i2c_clk(hw, &i2cctl);
2424
2425         /* Minimum high period of clock is 4us */
2426         usec_delay(IXGBE_I2C_T_HIGH);
2427
2428         /* Poll for ACK.  Note that ACK in I2C spec is
2429          * transition from 1 to 0 */
2430         for (i = 0; i < timeout; i++) {
2431                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2432                 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2433
2434                 usec_delay(1);
2435                 if (!ack)
2436                         break;
2437         }
2438
2439         if (ack) {
2440                 DEBUGOUT("I2C ack was not received.\n");
2441                 status = IXGBE_ERR_I2C;
2442         }
2443
2444         ixgbe_lower_i2c_clk(hw, &i2cctl);
2445
2446         /* Minimum low period of clock is 4.7 us */
2447         usec_delay(IXGBE_I2C_T_LOW);
2448
2449         return status;
2450 }
2451
2452 /**
2453  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2454  *  @hw: pointer to hardware structure
2455  *  @data: read data value
2456  *
2457  *  Clocks in one bit via I2C data/clock
2458  **/
2459 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2460 {
2461         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2462         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2463
2464         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2465
2466         if (data_oe_bit) {
2467                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2468                 i2cctl |= data_oe_bit;
2469                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2470                 IXGBE_WRITE_FLUSH(hw);
2471         }
2472         ixgbe_raise_i2c_clk(hw, &i2cctl);
2473
2474         /* Minimum high period of clock is 4us */
2475         usec_delay(IXGBE_I2C_T_HIGH);
2476
2477         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2478         *data = ixgbe_get_i2c_data(hw, &i2cctl);
2479
2480         ixgbe_lower_i2c_clk(hw, &i2cctl);
2481
2482         /* Minimum low period of clock is 4.7 us */
2483         usec_delay(IXGBE_I2C_T_LOW);
2484
2485         return IXGBE_SUCCESS;
2486 }
2487
2488 /**
2489  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2490  *  @hw: pointer to hardware structure
2491  *  @data: data value to write
2492  *
2493  *  Clocks out one bit via I2C data/clock
2494  **/
2495 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2496 {
2497         s32 status;
2498         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2499
2500         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2501
2502         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2503         if (status == IXGBE_SUCCESS) {
2504                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2505
2506                 /* Minimum high period of clock is 4us */
2507                 usec_delay(IXGBE_I2C_T_HIGH);
2508
2509                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2510
2511                 /* Minimum low period of clock is 4.7 us.
2512                  * This also takes care of the data hold time.
2513                  */
2514                 usec_delay(IXGBE_I2C_T_LOW);
2515         } else {
2516                 status = IXGBE_ERR_I2C;
2517                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2518                              "I2C data was not set to %X\n", data);
2519         }
2520
2521         return status;
2522 }
2523
2524 /**
2525  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2526  *  @hw: pointer to hardware structure
2527  *  @i2cctl: Current value of I2CCTL register
2528  *
2529  *  Raises the I2C clock line '0'->'1'
2530  *  Negates the I2C clock output enable on X550 hardware.
2531  **/
2532 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2533 {
2534         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2535         u32 i = 0;
2536         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2537         u32 i2cctl_r = 0;
2538
2539         DEBUGFUNC("ixgbe_raise_i2c_clk");
2540
2541         if (clk_oe_bit) {
2542                 *i2cctl |= clk_oe_bit;
2543                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2544         }
2545
2546         for (i = 0; i < timeout; i++) {
2547                 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2548
2549                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2550                 IXGBE_WRITE_FLUSH(hw);
2551                 /* SCL rise time (1000ns) */
2552                 usec_delay(IXGBE_I2C_T_RISE);
2553
2554                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2555                 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2556                         break;
2557         }
2558 }
2559
2560 /**
2561  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2562  *  @hw: pointer to hardware structure
2563  *  @i2cctl: Current value of I2CCTL register
2564  *
2565  *  Lowers the I2C clock line '1'->'0'
2566  *  Asserts the I2C clock output enable on X550 hardware.
2567  **/
2568 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2569 {
2570         DEBUGFUNC("ixgbe_lower_i2c_clk");
2571
2572         *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2573         *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2574
2575         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2576         IXGBE_WRITE_FLUSH(hw);
2577
2578         /* SCL fall time (300ns) */
2579         usec_delay(IXGBE_I2C_T_FALL);
2580 }
2581
2582 /**
2583  *  ixgbe_set_i2c_data - Sets the I2C data bit
2584  *  @hw: pointer to hardware structure
2585  *  @i2cctl: Current value of I2CCTL register
2586  *  @data: I2C data value (0 or 1) to set
2587  *
2588  *  Sets the I2C data bit
2589  *  Asserts the I2C data output enable on X550 hardware.
2590  **/
2591 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2592 {
2593         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2594         s32 status = IXGBE_SUCCESS;
2595
2596         DEBUGFUNC("ixgbe_set_i2c_data");
2597
2598         if (data)
2599                 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2600         else
2601                 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2602         *i2cctl &= ~data_oe_bit;
2603
2604         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2605         IXGBE_WRITE_FLUSH(hw);
2606
2607         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2608         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2609
2610         if (!data)      /* Can't verify data in this case */
2611                 return IXGBE_SUCCESS;
2612         if (data_oe_bit) {
2613                 *i2cctl |= data_oe_bit;
2614                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2615                 IXGBE_WRITE_FLUSH(hw);
2616         }
2617
2618         /* Verify data was set correctly */
2619         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2620         if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2621                 status = IXGBE_ERR_I2C;
2622                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2623                              "Error - I2C data was not set to %X.\n",
2624                              data);
2625         }
2626
2627         return status;
2628 }
2629
2630 /**
2631  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2632  *  @hw: pointer to hardware structure
2633  *  @i2cctl: Current value of I2CCTL register
2634  *
2635  *  Returns the I2C data bit value
2636  *  Negates the I2C data output enable on X550 hardware.
2637  **/
2638 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2639 {
2640         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2641         bool data;
2642
2643         DEBUGFUNC("ixgbe_get_i2c_data");
2644
2645         if (data_oe_bit) {
2646                 *i2cctl |= data_oe_bit;
2647                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2648                 IXGBE_WRITE_FLUSH(hw);
2649                 usec_delay(IXGBE_I2C_T_FALL);
2650         }
2651
2652         if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2653                 data = 1;
2654         else
2655                 data = 0;
2656
2657         return data;
2658 }
2659
2660 /**
2661  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2662  *  @hw: pointer to hardware structure
2663  *
2664  *  Clears the I2C bus by sending nine clock pulses.
2665  *  Used when data line is stuck low.
2666  **/
2667 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2668 {
2669         u32 i2cctl;
2670         u32 i;
2671
2672         DEBUGFUNC("ixgbe_i2c_bus_clear");
2673
2674         ixgbe_i2c_start(hw);
2675         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2676
2677         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2678
2679         for (i = 0; i < 9; i++) {
2680                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2681
2682                 /* Min high period of clock is 4us */
2683                 usec_delay(IXGBE_I2C_T_HIGH);
2684
2685                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2686
2687                 /* Min low period of clock is 4.7us*/
2688                 usec_delay(IXGBE_I2C_T_LOW);
2689         }
2690
2691         ixgbe_i2c_start(hw);
2692
2693         /* Put the i2c bus back to default state */
2694         ixgbe_i2c_stop(hw);
2695 }
2696
2697 /**
2698  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2699  *  @hw: pointer to hardware structure
2700  *
2701  *  Checks if the LASI temp alarm status was triggered due to overtemp
2702  **/
2703 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2704 {
2705         s32 status = IXGBE_SUCCESS;
2706         u16 phy_data = 0;
2707
2708         DEBUGFUNC("ixgbe_tn_check_overtemp");
2709
2710         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2711                 goto out;
2712
2713         /* Check that the LASI temp alarm status was triggered */
2714         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2715                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2716
2717         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2718                 goto out;
2719
2720         status = IXGBE_ERR_OVERTEMP;
2721         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2722 out:
2723         return status;
2724 }
2725
2726 /**
2727  * ixgbe_set_copper_phy_power - Control power for copper phy
2728  * @hw: pointer to hardware structure
2729  * @on: true for on, false for off
2730  */
2731 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2732 {
2733         u32 status;
2734         u16 reg;
2735
2736         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2737                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2738                                       &reg);
2739         if (status)
2740                 return status;
2741
2742         if (on) {
2743                 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2744         } else {
2745                 if (ixgbe_check_reset_blocked(hw))
2746                         return 0;
2747                 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2748         }
2749
2750         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2751                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2752                                        reg);
2753         return status;
2754 }