drivers/net/ixgbe/base/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_api.h"
  35 #include "ixgbe_common.h"
  36 #include "ixgbe_phy.h"
  37
  38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
  39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  50                                           u8 *sff8472_data);
  51
  52 /**
  53  * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
  54  * @hw: pointer to the hardware structure
  55  * @byte: byte to send
  56  *
  57  * Returns an error code on error.
  58  */
  59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
  60 {
  61         s32 status;
  62
  63         status = ixgbe_clock_out_i2c_byte(hw, byte);
  64         if (status)
  65                 return status;
  66         return ixgbe_get_i2c_ack(hw);
  67 }
  68
  69 /**
  70  * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
  71  * @hw: pointer to the hardware structure
  72  * @byte: pointer to a u8 to receive the byte
  73  *
  74  * Returns an error code on error.
  75  */
  76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
  77 {
  78         s32 status;
  79
  80         status = ixgbe_clock_in_i2c_byte(hw, byte);
  81         if (status)
  82                 return status;
  83         /* ACK */
  84         return ixgbe_clock_out_i2c_bit(hw, false);
  85 }
  86
  87 /**
  88  * ixgbe_ones_comp_byte_add - Perform one's complement addition
  89  * @add1 - addend 1
  90  * @add2 - addend 2
  91  *
  92  * Returns one's complement 8-bit sum.
  93  */
  94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
  95 {
  96         u16 sum = add1 + add2;
  97
  98         sum = (sum & 0xFF) + (sum >> 8);
  99         return sum & 0xFF;
 100 }
 101
 102 /**
 103  * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
 104  * @hw: pointer to the hardware structure
 105  * @addr: I2C bus address to read from
 106  * @reg: I2C device register to read from
 107  * @val: pointer to location to receive read value
 108  * @lock: true if to take and release semaphore
 109  *
 110  * Returns an error code on error.
 111  */
 112 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 113                                         u16 *val, bool lock)
 114 {
 115         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 116         int max_retry = 3;
 117         int retry = 0;
 118         u8 csum_byte;
 119         u8 high_bits;
 120         u8 low_bits;
 121         u8 reg_high;
 122         u8 csum;
 123
 124         reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
 125         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 126         csum = ~csum;
 127         do {
 128                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 129                         return IXGBE_ERR_SWFW_SYNC;
 130                 ixgbe_i2c_start(hw);
 131                 /* Device Address and write indication */
 132                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 133                         goto fail;
 134                 /* Write bits 14:8 */
 135                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 136                         goto fail;
 137                 /* Write bits 7:0 */
 138                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 139                         goto fail;
 140                 /* Write csum */
 141                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 142                         goto fail;
 143                 /* Re-start condition */
 144                 ixgbe_i2c_start(hw);
 145                 /* Device Address and read indication */
 146                 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
 147                         goto fail;
 148                 /* Get upper bits */
 149                 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
 150                         goto fail;
 151                 /* Get low bits */
 152                 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
 153                         goto fail;
 154                 /* Get csum */
 155                 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
 156                         goto fail;
 157                 /* NACK */
 158                 if (ixgbe_clock_out_i2c_bit(hw, false))
 159                         goto fail;
 160                 ixgbe_i2c_stop(hw);
 161                 if (lock)
 162                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 163                 *val = (high_bits << 8) | low_bits;
 164                 return 0;
 165
 166 fail:
 167                 ixgbe_i2c_bus_clear(hw);
 168                 if (lock)
 169                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 170                 retry++;
 171                 if (retry < max_retry)
 172                         DEBUGOUT("I2C byte read combined error - Retrying.\n");
 173                 else
 174                         DEBUGOUT("I2C byte read combined error.\n");
 175         } while (retry < max_retry);
 176
 177         return IXGBE_ERR_I2C;
 178 }
 179
 180 /**
 181  * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
 182  * @hw: pointer to the hardware structure
 183  * @addr: I2C bus address to write to
 184  * @reg: I2C device register to write to
 185  * @val: value to write
 186  * @lock: true if to take and release semaphore
 187  *
 188  * Returns an error code on error.
 189  */
 190 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 191                                          u16 val, bool lock)
 192 {
 193         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 194         int max_retry = 1;
 195         int retry = 0;
 196         u8 reg_high;
 197         u8 csum;
 198
 199         reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
 200         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 201         csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
 202         csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
 203         csum = ~csum;
 204         do {
 205                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 206                         return IXGBE_ERR_SWFW_SYNC;
 207                 ixgbe_i2c_start(hw);
 208                 /* Device Address and write indication */
 209                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 210                         goto fail;
 211                 /* Write bits 14:8 */
 212                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 213                         goto fail;
 214                 /* Write bits 7:0 */
 215                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 216                         goto fail;
 217                 /* Write data 15:8 */
 218                 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
 219                         goto fail;
 220                 /* Write data 7:0 */
 221                 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
 222                         goto fail;
 223                 /* Write csum */
 224                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 225                         goto fail;
 226                 ixgbe_i2c_stop(hw);
 227                 if (lock)
 228                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 229                 return 0;
 230
 231 fail:
 232                 ixgbe_i2c_bus_clear(hw);
 233                 if (lock)
 234                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 235                 retry++;
 236                 if (retry < max_retry)
 237                         DEBUGOUT("I2C byte write combined error - Retrying.\n");
 238                 else
 239                         DEBUGOUT("I2C byte write combined error.\n");
 240         } while (retry < max_retry);
 241
 242         return IXGBE_ERR_I2C;
 243 }
 244
 245 /**
 246  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
 247  *  @hw: pointer to the hardware structure
 248  *
 249  *  Initialize the function pointers.
 250  **/
 251 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
 252 {
 253         struct ixgbe_phy_info *phy = &hw->phy;
 254
 255         DEBUGFUNC("ixgbe_init_phy_ops_generic");
 256
 257         /* PHY */
 258         phy->ops.identify = ixgbe_identify_phy_generic;
 259         phy->ops.reset = ixgbe_reset_phy_generic;
 260         phy->ops.read_reg = ixgbe_read_phy_reg_generic;
 261         phy->ops.write_reg = ixgbe_write_phy_reg_generic;
 262         phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
 263         phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
 264         phy->ops.setup_link = ixgbe_setup_phy_link_generic;
 265         phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
 266         phy->ops.check_link = NULL;
 267         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
 268         phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
 269         phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
 270         phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
 271         phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
 272         phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
 273         phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
 274         phy->ops.identify_sfp = ixgbe_identify_module_generic;
 275         phy->sfp_type = ixgbe_sfp_type_unknown;
 276         phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
 277         phy->ops.write_i2c_byte_unlocked =
 278                                 ixgbe_write_i2c_byte_generic_unlocked;
 279         phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
 280         return IXGBE_SUCCESS;
 281 }
 282
 283 /**
 284  * ixgbe_probe_phy - Probe a single address for a PHY
 285  * @hw: pointer to hardware structure
 286  * @phy_addr: PHY address to probe
 287  *
 288  * Returns true if PHY found
 289  */
 290 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
 291 {
 292         u16 ext_ability = 0;
 293
 294         if (!ixgbe_validate_phy_addr(hw, phy_addr))
 295                 return false;
 296
 297         if (ixgbe_get_phy_id(hw))
 298                 return false;
 299
 300         hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
 301
 302         if (hw->phy.type == ixgbe_phy_unknown) {
 303                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
 304                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
 305                 if (ext_ability &
 306                     (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 307                      IXGBE_MDIO_PHY_1000BASET_ABILITY))
 308                         hw->phy.type = ixgbe_phy_cu_unknown;
 309                 else
 310                         hw->phy.type = ixgbe_phy_generic;
 311         }
 312
 313         return true;
 314 }
 315
 316 /**
 317  *  ixgbe_identify_phy_generic - Get physical layer module
 318  *  @hw: pointer to hardware structure
 319  *
 320  *  Determines the physical layer module found on the current adapter.
 321  **/
 322 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 323 {
 324         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 325         u16 phy_addr;
 326
 327         DEBUGFUNC("ixgbe_identify_phy_generic");
 328
 329         if (!hw->phy.phy_semaphore_mask) {
 330                 if (hw->bus.lan_id)
 331                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 332                 else
 333                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 334         }
 335
 336         if (hw->phy.type != ixgbe_phy_unknown)
 337                 return IXGBE_SUCCESS;
 338
 339         if (hw->phy.nw_mng_if_sel) {
 340                 phy_addr = (hw->phy.nw_mng_if_sel &
 341                             IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
 342                            IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
 343                 if (ixgbe_probe_phy(hw, phy_addr))
 344                         return IXGBE_SUCCESS;
 345                 else
 346                         return IXGBE_ERR_PHY_ADDR_INVALID;
 347         }
 348
 349         for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 350                 if (ixgbe_probe_phy(hw, phy_addr)) {
 351                         status = IXGBE_SUCCESS;
 352                         break;
 353                 }
 354         }
 355
 356         /* Certain media types do not have a phy so an address will not
 357          * be found and the code will take this path.  Caller has to
 358          * decide if it is an error or not.
 359          */
 360         if (status != IXGBE_SUCCESS)
 361                 hw->phy.addr = 0;
 362
 363         return status;
 364 }
 365
 366 /**
 367  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 368  * @hw: pointer to the hardware structure
 369  *
 370  * This function checks the MMNGC.MNG_VETO bit to see if there are
 371  * any constraints on link from manageability.  For MAC's that don't
 372  * have this bit just return faluse since the link can not be blocked
 373  * via this method.
 374  **/
 375 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 376 {
 377         u32 mmngc;
 378
 379         DEBUGFUNC("ixgbe_check_reset_blocked");
 380
 381         /* If we don't have this bit, it can't be blocking */
 382         if (hw->mac.type == ixgbe_mac_82598EB)
 383                 return false;
 384
 385         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 386         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 387                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 388                               "MNG_VETO bit detected.\n");
 389                 return true;
 390         }
 391
 392         return false;
 393 }
 394
 395 /**
 396  *  ixgbe_validate_phy_addr - Determines phy address is valid
 397  *  @hw: pointer to hardware structure
 398  *
 399  **/
 400 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 401 {
 402         u16 phy_id = 0;
 403         bool valid = false;
 404
 405         DEBUGFUNC("ixgbe_validate_phy_addr");
 406
 407         hw->phy.addr = phy_addr;
 408         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 409                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 410
 411         if (phy_id != 0xFFFF && phy_id != 0x0)
 412                 valid = true;
 413
 414         return valid;
 415 }
 416
 417 /**
 418  *  ixgbe_get_phy_id - Get the phy type
 419  *  @hw: pointer to hardware structure
 420  *
 421  **/
 422 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 423 {
 424         u32 status;
 425         u16 phy_id_high = 0;
 426         u16 phy_id_low = 0;
 427
 428         DEBUGFUNC("ixgbe_get_phy_id");
 429
 430         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 431                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 432                                       &phy_id_high);
 433
 434         if (status == IXGBE_SUCCESS) {
 435                 hw->phy.id = (u32)(phy_id_high << 16);
 436                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 437                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 438                                               &phy_id_low);
 439                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 440                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 441         }
 442         return status;
 443 }
 444
 445 /**
 446  *  ixgbe_get_phy_type_from_id - Get the phy type
 447  *  @phy_id: PHY ID information
 448  *
 449  **/
 450 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 451 {
 452         enum ixgbe_phy_type phy_type;
 453
 454         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 455
 456         switch (phy_id) {
 457         case TN1010_PHY_ID:
 458                 phy_type = ixgbe_phy_tn;
 459                 break;
 460         case X550_PHY_ID1:
 461         case X550_PHY_ID2:
 462         case X550_PHY_ID3:
 463         case X540_PHY_ID:
 464                 phy_type = ixgbe_phy_aq;
 465                 break;
 466         case QT2022_PHY_ID:
 467                 phy_type = ixgbe_phy_qt;
 468                 break;
 469         case ATH_PHY_ID:
 470                 phy_type = ixgbe_phy_nl;
 471                 break;
 472         case X557_PHY_ID:
 473         case X557_PHY_ID2:
 474                 phy_type = ixgbe_phy_x550em_ext_t;
 475                 break;
 476         default:
 477                 phy_type = ixgbe_phy_unknown;
 478                 break;
 479         }
 480         return phy_type;
 481 }
 482
 483 /**
 484  *  ixgbe_reset_phy_generic - Performs a PHY reset
 485  *  @hw: pointer to hardware structure
 486  **/
 487 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 488 {
 489         u32 i;
 490         u16 ctrl = 0;
 491         s32 status = IXGBE_SUCCESS;
 492
 493         DEBUGFUNC("ixgbe_reset_phy_generic");
 494
 495         if (hw->phy.type == ixgbe_phy_unknown)
 496                 status = ixgbe_identify_phy_generic(hw);
 497
 498         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 499                 goto out;
 500
 501         /* Don't reset PHY if it's shut down due to overtemp. */
 502         if (!hw->phy.reset_if_overtemp &&
 503             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 504                 goto out;
 505
 506         /* Blocked by MNG FW so bail */
 507         if (ixgbe_check_reset_blocked(hw))
 508                 goto out;
 509
 510         /*
 511          * Perform soft PHY reset to the PHY_XS.
 512          * This will cause a soft reset to the PHY
 513          */
 514         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 515                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 516                               IXGBE_MDIO_PHY_XS_RESET);
 517
 518         /*
 519          * Poll for reset bit to self-clear indicating reset is complete.
 520          * Some PHYs could take up to 3 seconds to complete and need about
 521          * 1.7 usec delay after the reset is complete.
 522          */
 523         for (i = 0; i < 30; i++) {
 524                 msec_delay(100);
 525                 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
 526                         status = hw->phy.ops.read_reg(hw,
 527                                                   IXGBE_MDIO_TX_VENDOR_ALARMS_3,
 528                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 529                                                   &ctrl);
 530                         if (status != IXGBE_SUCCESS)
 531                                 return status;
 532
 533                         if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
 534                                 usec_delay(2);
 535                                 break;
 536                         }
 537                 } else {
 538                         status = hw->phy.ops.read_reg(hw,
 539                                                      IXGBE_MDIO_PHY_XS_CONTROL,
 540                                                      IXGBE_MDIO_PHY_XS_DEV_TYPE,
 541                                                      &ctrl);
 542                         if (status != IXGBE_SUCCESS)
 543                                 return status;
 544
 545                         if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 546                                 usec_delay(2);
 547                                 break;
 548                         }
 549                 }
 550         }
 551
 552         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 553                 status = IXGBE_ERR_RESET_FAILED;
 554                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 555                              "PHY reset polling failed to complete.\n");
 556         }
 557
 558 out:
 559         return status;
 560 }
 561
 562 /**
 563  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 564  *  the SWFW lock
 565  *  @hw: pointer to hardware structure
 566  *  @reg_addr: 32 bit address of PHY register to read
 567  *  @phy_data: Pointer to read data from PHY register
 568  **/
 569 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 570                        u16 *phy_data)
 571 {
 572         u32 i, data, command;
 573
 574         /* Setup and write the address cycle command */
 575         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 576                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 577                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 578                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 579
 580         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 581
 582         /*
 583          * Check every 10 usec to see if the address cycle completed.
 584          * The MDI Command bit will clear when the operation is
 585          * complete
 586          */
 587         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 588                 usec_delay(10);
 589
 590                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 591                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 592                                 break;
 593         }
 594
 595
 596         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 597                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 598                 return IXGBE_ERR_PHY;
 599         }
 600
 601         /*
 602          * Address cycle complete, setup and write the read
 603          * command
 604          */
 605         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 606                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 607                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 608                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 609
 610         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 611
 612         /*
 613          * Check every 10 usec to see if the address cycle
 614          * completed. The MDI Command bit will clear when the
 615          * operation is complete
 616          */
 617         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 618                 usec_delay(10);
 619
 620                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 621                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 622                         break;
 623         }
 624
 625         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 626                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 627                 return IXGBE_ERR_PHY;
 628         }
 629
 630         /*
 631          * Read operation is complete.  Get the data
 632          * from MSRWD
 633          */
 634         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 635         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 636         *phy_data = (u16)(data);
 637
 638         return IXGBE_SUCCESS;
 639 }
 640
 641 /**
 642  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 643  *  using the SWFW lock - this function is needed in most cases
 644  *  @hw: pointer to hardware structure
 645  *  @reg_addr: 32 bit address of PHY register to read
 646  *  @phy_data: Pointer to read data from PHY register
 647  **/
 648 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 649                                u32 device_type, u16 *phy_data)
 650 {
 651         s32 status;
 652         u32 gssr = hw->phy.phy_semaphore_mask;
 653
 654         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 655
 656         if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
 657                 return IXGBE_ERR_SWFW_SYNC;
 658
 659         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
 660
 661         hw->mac.ops.release_swfw_sync(hw, gssr);
 662
 663         return status;
 664 }
 665
 666 /**
 667  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 668  *  without SWFW lock
 669  *  @hw: pointer to hardware structure
 670  *  @reg_addr: 32 bit PHY register to write
 671  *  @device_type: 5 bit device type
 672  *  @phy_data: Data to write to the PHY register
 673  **/
 674 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 675                                 u32 device_type, u16 phy_data)
 676 {
 677         u32 i, command;
 678
 679         /* Put the data in the MDI single read and write data register*/
 680         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 681
 682         /* Setup and write the address cycle command */
 683         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 684                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 685                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 686                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 687
 688         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 689
 690         /*
 691          * Check every 10 usec to see if the address cycle completed.
 692          * The MDI Command bit will clear when the operation is
 693          * complete
 694          */
 695         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 696                 usec_delay(10);
 697
 698                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 699                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 700                         break;
 701         }
 702
 703         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 704                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 705                 return IXGBE_ERR_PHY;
 706         }
 707
 708         /*
 709          * Address cycle complete, setup and write the write
 710          * command
 711          */
 712         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 713                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 714                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 715                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 716
 717         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 718
 719         /*
 720          * Check every 10 usec to see if the address cycle
 721          * completed. The MDI Command bit will clear when the
 722          * operation is complete
 723          */
 724         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 725                 usec_delay(10);
 726
 727                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 728                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 729                         break;
 730         }
 731
 732         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 733                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 734                 return IXGBE_ERR_PHY;
 735         }
 736
 737         return IXGBE_SUCCESS;
 738 }
 739
 740 /**
 741  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 742  *  using SWFW lock- this function is needed in most cases
 743  *  @hw: pointer to hardware structure
 744  *  @reg_addr: 32 bit PHY register to write
 745  *  @device_type: 5 bit device type
 746  *  @phy_data: Data to write to the PHY register
 747  **/
 748 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 749                                 u32 device_type, u16 phy_data)
 750 {
 751         s32 status;
 752         u32 gssr = hw->phy.phy_semaphore_mask;
 753
 754         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 755
 756         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 757                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
 758                                                  phy_data);
 759                 hw->mac.ops.release_swfw_sync(hw, gssr);
 760         } else {
 761                 status = IXGBE_ERR_SWFW_SYNC;
 762         }
 763
 764         return status;
 765 }
 766
 767 /**
 768  *  ixgbe_setup_phy_link_generic - Set and restart auto-neg
 769  *  @hw: pointer to hardware structure
 770  *
 771  *  Restart auto-negotiation and PHY and waits for completion.
 772  **/
 773 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 774 {
 775         s32 status = IXGBE_SUCCESS;
 776         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 777         bool autoneg = false;
 778         ixgbe_link_speed speed;
 779
 780         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 781
 782         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 783
 784         /* Set or unset auto-negotiation 10G advertisement */
 785         hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 786                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 787                              &autoneg_reg);
 788
 789         autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 790         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
 791             (speed & IXGBE_LINK_SPEED_10GB_FULL))
 792                 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 793
 794         hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 795                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 796                               autoneg_reg);
 797
 798         hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 799                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 800                              &autoneg_reg);
 801
 802         if (hw->mac.type == ixgbe_mac_X550) {
 803                 /* Set or unset auto-negotiation 5G advertisement */
 804                 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
 805                 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
 806                     (speed & IXGBE_LINK_SPEED_5GB_FULL))
 807                         autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
 808
 809                 /* Set or unset auto-negotiation 2.5G advertisement */
 810                 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
 811                 if ((hw->phy.autoneg_advertised &
 812                      IXGBE_LINK_SPEED_2_5GB_FULL) &&
 813                     (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
 814                         autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
 815         }
 816
 817         /* Set or unset auto-negotiation 1G advertisement */
 818         autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 819         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
 820             (speed & IXGBE_LINK_SPEED_1GB_FULL))
 821                 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 822
 823         hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 824                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 825                               autoneg_reg);
 826
 827         /* Set or unset auto-negotiation 100M advertisement */
 828         hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 829                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 830                              &autoneg_reg);
 831
 832         autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 833                          IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 834         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
 835             (speed & IXGBE_LINK_SPEED_100_FULL))
 836                 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 837
 838         hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 839                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 840                               autoneg_reg);
 841
 842         /* Blocked by MNG FW so don't reset PHY */
 843         if (ixgbe_check_reset_blocked(hw))
 844                 return status;
 845
 846         /* Restart PHY auto-negotiation. */
 847         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 848                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 849
 850         autoneg_reg |= IXGBE_MII_RESTART;
 851
 852         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 853                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 854
 855         return status;
 856 }
 857
 858 /**
 859  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 860  *  @hw: pointer to hardware structure
 861  *  @speed: new link speed
 862  **/
 863 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 864                                        ixgbe_link_speed speed,
 865                                        bool autoneg_wait_to_complete)
 866 {
 867         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 868
 869         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 870
 871         /*
 872          * Clear autoneg_advertised and set new values based on input link
 873          * speed.
 874          */
 875         hw->phy.autoneg_advertised = 0;
 876
 877         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 878                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 879
 880         if (speed & IXGBE_LINK_SPEED_5GB_FULL)
 881                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
 882
 883         if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
 884                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
 885
 886         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 887                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 888
 889         if (speed & IXGBE_LINK_SPEED_100_FULL)
 890                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 891
 892         if (speed & IXGBE_LINK_SPEED_10_FULL)
 893                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
 894
 895         /* Setup link based on the new speed settings */
 896         ixgbe_setup_phy_link(hw);
 897
 898         return IXGBE_SUCCESS;
 899 }
 900
 901 /**
 902  * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
 903  * @hw: pointer to hardware structure
 904  *
 905  * Determines the supported link capabilities by reading the PHY auto
 906  * negotiation register.
 907  **/
 908 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
 909 {
 910         s32 status;
 911         u16 speed_ability;
 912
 913         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 914                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 915                                       &speed_ability);
 916         if (status)
 917                 return status;
 918
 919         if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 920                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
 921         if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 922                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
 923         if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 924                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
 925
 926         switch (hw->mac.type) {
 927         case ixgbe_mac_X550:
 928                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
 929                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
 930                 break;
 931         case ixgbe_mac_X550EM_x:
 932         case ixgbe_mac_X550EM_a:
 933                 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
 934                 break;
 935         default:
 936                 break;
 937         }
 938
 939         return status;
 940 }
 941
 942 /**
 943  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 944  *  @hw: pointer to hardware structure
 945  *  @speed: pointer to link speed
 946  *  @autoneg: boolean auto-negotiation value
 947  **/
 948 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 949                                                ixgbe_link_speed *speed,
 950                                                bool *autoneg)
 951 {
 952         s32 status = IXGBE_SUCCESS;
 953
 954         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 955
 956         *autoneg = true;
 957         if (!hw->phy.speeds_supported)
 958                 status = ixgbe_get_copper_speeds_supported(hw);
 959
 960         *speed = hw->phy.speeds_supported;
 961         return status;
 962 }
 963
 964 /**
 965  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 966  *  @hw: pointer to hardware structure
 967  *
 968  *  Reads the VS1 register to determine if link is up and the current speed for
 969  *  the PHY.
 970  **/
 971 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 972                              bool *link_up)
 973 {
 974         s32 status = IXGBE_SUCCESS;
 975         u32 time_out;
 976         u32 max_time_out = 10;
 977         u16 phy_link = 0;
 978         u16 phy_speed = 0;
 979         u16 phy_data = 0;
 980
 981         DEBUGFUNC("ixgbe_check_phy_link_tnx");
 982
 983         /* Initialize speed and link to default case */
 984         *link_up = false;
 985         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 986
 987         /*
 988          * Check current speed and link status of the PHY register.
 989          * This is a vendor specific register and may have to
 990          * be changed for other copper PHYs.
 991          */
 992         for (time_out = 0; time_out < max_time_out; time_out++) {
 993                 usec_delay(10);
 994                 status = hw->phy.ops.read_reg(hw,
 995                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
 996                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 997                                         &phy_data);
 998                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 999                 phy_speed = phy_data &
1000                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1001                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1002                         *link_up = true;
1003                         if (phy_speed ==
1004                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1005                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1006                         break;
1007                 }
1008         }
1009
1010         return status;
1011 }
1012
1013 /**
1014  *      ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1015  *      @hw: pointer to hardware structure
1016  *
1017  *      Restart auto-negotiation and PHY and waits for completion.
1018  **/
1019 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1020 {
1021         s32 status = IXGBE_SUCCESS;
1022         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1023         bool autoneg = false;
1024         ixgbe_link_speed speed;
1025
1026         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1027
1028         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1029
1030         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1031                 /* Set or unset auto-negotiation 10G advertisement */
1032                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1033                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1034                                      &autoneg_reg);
1035
1036                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1037                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1038                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1039
1040                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1041                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1042                                       autoneg_reg);
1043         }
1044
1045         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1046                 /* Set or unset auto-negotiation 1G advertisement */
1047                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1048                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1049                                      &autoneg_reg);
1050
1051                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1052                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1053                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1054
1055                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1056                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1057                                       autoneg_reg);
1058         }
1059
1060         if (speed & IXGBE_LINK_SPEED_100_FULL) {
1061                 /* Set or unset auto-negotiation 100M advertisement */
1062                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1063                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1064                                      &autoneg_reg);
1065
1066                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1067                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1068                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1069
1070                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1071                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1072                                       autoneg_reg);
1073         }
1074
1075         /* Blocked by MNG FW so don't reset PHY */
1076         if (ixgbe_check_reset_blocked(hw))
1077                 return status;
1078
1079         /* Restart PHY auto-negotiation. */
1080         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1081                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1082
1083         autoneg_reg |= IXGBE_MII_RESTART;
1084
1085         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1086                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1087
1088         return status;
1089 }
1090
1091 /**
1092  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1093  *  @hw: pointer to hardware structure
1094  *  @firmware_version: pointer to the PHY Firmware Version
1095  **/
1096 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1097                                        u16 *firmware_version)
1098 {
1099         s32 status;
1100
1101         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1102
1103         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1104                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1105                                       firmware_version);
1106
1107         return status;
1108 }
1109
1110 /**
1111  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1112  *  @hw: pointer to hardware structure
1113  *  @firmware_version: pointer to the PHY Firmware Version
1114  **/
1115 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1116                                            u16 *firmware_version)
1117 {
1118         s32 status;
1119
1120         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1121
1122         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1123                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1124                                       firmware_version);
1125
1126         return status;
1127 }
1128
1129 /**
1130  *  ixgbe_reset_phy_nl - Performs a PHY reset
1131  *  @hw: pointer to hardware structure
1132  **/
1133 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1134 {
1135         u16 phy_offset, control, eword, edata, block_crc;
1136         bool end_data = false;
1137         u16 list_offset, data_offset;
1138         u16 phy_data = 0;
1139         s32 ret_val = IXGBE_SUCCESS;
1140         u32 i;
1141
1142         DEBUGFUNC("ixgbe_reset_phy_nl");
1143
1144         /* Blocked by MNG FW so bail */
1145         if (ixgbe_check_reset_blocked(hw))
1146                 goto out;
1147
1148         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1149                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1150
1151         /* reset the PHY and poll for completion */
1152         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1153                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
1154                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1155
1156         for (i = 0; i < 100; i++) {
1157                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1158                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1159                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1160                         break;
1161                 msec_delay(10);
1162         }
1163
1164         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1165                 DEBUGOUT("PHY reset did not complete.\n");
1166                 ret_val = IXGBE_ERR_PHY;
1167                 goto out;
1168         }
1169
1170         /* Get init offsets */
1171         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1172                                                       &data_offset);
1173         if (ret_val != IXGBE_SUCCESS)
1174                 goto out;
1175
1176         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1177         data_offset++;
1178         while (!end_data) {
1179                 /*
1180                  * Read control word from PHY init contents offset
1181                  */
1182                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1183                 if (ret_val)
1184                         goto err_eeprom;
1185                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1186                            IXGBE_CONTROL_SHIFT_NL;
1187                 edata = eword & IXGBE_DATA_MASK_NL;
1188                 switch (control) {
1189                 case IXGBE_DELAY_NL:
1190                         data_offset++;
1191                         DEBUGOUT1("DELAY: %d MS\n", edata);
1192                         msec_delay(edata);
1193                         break;
1194                 case IXGBE_DATA_NL:
1195                         DEBUGOUT("DATA:\n");
1196                         data_offset++;
1197                         ret_val = hw->eeprom.ops.read(hw, data_offset,
1198                                                       &phy_offset);
1199                         if (ret_val)
1200                                 goto err_eeprom;
1201                         data_offset++;
1202                         for (i = 0; i < edata; i++) {
1203                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
1204                                                               &eword);
1205                                 if (ret_val)
1206                                         goto err_eeprom;
1207                                 hw->phy.ops.write_reg(hw, phy_offset,
1208                                                       IXGBE_TWINAX_DEV, eword);
1209                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1210                                           phy_offset);
1211                                 data_offset++;
1212                                 phy_offset++;
1213                         }
1214                         break;
1215                 case IXGBE_CONTROL_NL:
1216                         data_offset++;
1217                         DEBUGOUT("CONTROL:\n");
1218                         if (edata == IXGBE_CONTROL_EOL_NL) {
1219                                 DEBUGOUT("EOL\n");
1220                                 end_data = true;
1221                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
1222                                 DEBUGOUT("SOL\n");
1223                         } else {
1224                                 DEBUGOUT("Bad control value\n");
1225                                 ret_val = IXGBE_ERR_PHY;
1226                                 goto out;
1227                         }
1228                         break;
1229                 default:
1230                         DEBUGOUT("Bad control type\n");
1231                         ret_val = IXGBE_ERR_PHY;
1232                         goto out;
1233                 }
1234         }
1235
1236 out:
1237         return ret_val;
1238
1239 err_eeprom:
1240         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1241                       "eeprom read at offset %d failed", data_offset);
1242         return IXGBE_ERR_PHY;
1243 }
1244
1245 /**
1246  *  ixgbe_identify_module_generic - Identifies module type
1247  *  @hw: pointer to hardware structure
1248  *
1249  *  Determines HW type and calls appropriate function.
1250  **/
1251 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1252 {
1253         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1254
1255         DEBUGFUNC("ixgbe_identify_module_generic");
1256
1257         switch (hw->mac.ops.get_media_type(hw)) {
1258         case ixgbe_media_type_fiber:
1259                 status = ixgbe_identify_sfp_module_generic(hw);
1260                 break;
1261
1262         case ixgbe_media_type_fiber_qsfp:
1263                 status = ixgbe_identify_qsfp_module_generic(hw);
1264                 break;
1265
1266         default:
1267                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1268                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1269                 break;
1270         }
1271
1272         return status;
1273 }
1274
1275 /**
1276  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1277  *  @hw: pointer to hardware structure
1278  *
1279  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1280  **/
1281 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1282 {
1283         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1284         u32 vendor_oui = 0;
1285         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1286         u8 identifier = 0;
1287         u8 comp_codes_1g = 0;
1288         u8 comp_codes_10g = 0;
1289         u8 oui_bytes[3] = {0, 0, 0};
1290         u8 cable_tech = 0;
1291         u8 cable_spec = 0;
1292         u16 enforce_sfp = 0;
1293
1294         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1295
1296         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1297                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1298                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1299                 goto out;
1300         }
1301
1302         /* LAN ID is needed for I2C access */
1303         hw->mac.ops.set_lan_id(hw);
1304
1305         status = hw->phy.ops.read_i2c_eeprom(hw,
1306                                              IXGBE_SFF_IDENTIFIER,
1307                                              &identifier);
1308
1309         if (status != IXGBE_SUCCESS)
1310                 goto err_read_i2c_eeprom;
1311
1312         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1313                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1314                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1315         } else {
1316                 status = hw->phy.ops.read_i2c_eeprom(hw,
1317                                                      IXGBE_SFF_1GBE_COMP_CODES,
1318                                                      &comp_codes_1g);
1319
1320                 if (status != IXGBE_SUCCESS)
1321                         goto err_read_i2c_eeprom;
1322
1323                 status = hw->phy.ops.read_i2c_eeprom(hw,
1324                                                      IXGBE_SFF_10GBE_COMP_CODES,
1325                                                      &comp_codes_10g);
1326
1327                 if (status != IXGBE_SUCCESS)
1328                         goto err_read_i2c_eeprom;
1329                 status = hw->phy.ops.read_i2c_eeprom(hw,
1330                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1331                                                      &cable_tech);
1332
1333                 if (status != IXGBE_SUCCESS)
1334                         goto err_read_i2c_eeprom;
1335
1336                  /* ID Module
1337                   * =========
1338                   * 0   SFP_DA_CU
1339                   * 1   SFP_SR
1340                   * 2   SFP_LR
1341                   * 3   SFP_DA_CORE0 - 82599-specific
1342                   * 4   SFP_DA_CORE1 - 82599-specific
1343                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1344                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1345                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1346                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1347                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1348                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1349                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1350                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1351                   */
1352                 if (hw->mac.type == ixgbe_mac_82598EB) {
1353                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1354                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1355                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1356                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1357                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1358                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1359                         else
1360                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1361                 } else {
1362                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1363                                 if (hw->bus.lan_id == 0)
1364                                         hw->phy.sfp_type =
1365                                                      ixgbe_sfp_type_da_cu_core0;
1366                                 else
1367                                         hw->phy.sfp_type =
1368                                                      ixgbe_sfp_type_da_cu_core1;
1369                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1370                                 hw->phy.ops.read_i2c_eeprom(
1371                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1372                                                 &cable_spec);
1373                                 if (cable_spec &
1374                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1375                                         if (hw->bus.lan_id == 0)
1376                                                 hw->phy.sfp_type =
1377                                                 ixgbe_sfp_type_da_act_lmt_core0;
1378                                         else
1379                                                 hw->phy.sfp_type =
1380                                                 ixgbe_sfp_type_da_act_lmt_core1;
1381                                 } else {
1382                                         hw->phy.sfp_type =
1383                                                         ixgbe_sfp_type_unknown;
1384                                 }
1385                         } else if (comp_codes_10g &
1386                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1387                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1388                                 if (hw->bus.lan_id == 0)
1389                                         hw->phy.sfp_type =
1390                                                       ixgbe_sfp_type_srlr_core0;
1391                                 else
1392                                         hw->phy.sfp_type =
1393                                                       ixgbe_sfp_type_srlr_core1;
1394                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1395                                 if (hw->bus.lan_id == 0)
1396                                         hw->phy.sfp_type =
1397                                                 ixgbe_sfp_type_1g_cu_core0;
1398                                 else
1399                                         hw->phy.sfp_type =
1400                                                 ixgbe_sfp_type_1g_cu_core1;
1401                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1402                                 if (hw->bus.lan_id == 0)
1403                                         hw->phy.sfp_type =
1404                                                 ixgbe_sfp_type_1g_sx_core0;
1405                                 else
1406                                         hw->phy.sfp_type =
1407                                                 ixgbe_sfp_type_1g_sx_core1;
1408                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1409                                 if (hw->bus.lan_id == 0)
1410                                         hw->phy.sfp_type =
1411                                                 ixgbe_sfp_type_1g_lx_core0;
1412                                 else
1413                                         hw->phy.sfp_type =
1414                                                 ixgbe_sfp_type_1g_lx_core1;
1415                         } else {
1416                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1417                         }
1418                 }
1419
1420                 if (hw->phy.sfp_type != stored_sfp_type)
1421                         hw->phy.sfp_setup_needed = true;
1422
1423                 /* Determine if the SFP+ PHY is dual speed or not. */
1424                 hw->phy.multispeed_fiber = false;
1425                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1426                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1427                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1428                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1429                         hw->phy.multispeed_fiber = true;
1430
1431                 /* Determine PHY vendor */
1432                 if (hw->phy.type != ixgbe_phy_nl) {
1433                         hw->phy.id = identifier;
1434                         status = hw->phy.ops.read_i2c_eeprom(hw,
1435                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1436                                                     &oui_bytes[0]);
1437
1438                         if (status != IXGBE_SUCCESS)
1439                                 goto err_read_i2c_eeprom;
1440
1441                         status = hw->phy.ops.read_i2c_eeprom(hw,
1442                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1443                                                     &oui_bytes[1]);
1444
1445                         if (status != IXGBE_SUCCESS)
1446                                 goto err_read_i2c_eeprom;
1447
1448                         status = hw->phy.ops.read_i2c_eeprom(hw,
1449                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1450                                                     &oui_bytes[2]);
1451
1452                         if (status != IXGBE_SUCCESS)
1453                                 goto err_read_i2c_eeprom;
1454
1455                         vendor_oui =
1456                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1457                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1458                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1459
1460                         switch (vendor_oui) {
1461                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1462                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1463                                         hw->phy.type =
1464                                                     ixgbe_phy_sfp_passive_tyco;
1465                                 break;
1466                         case IXGBE_SFF_VENDOR_OUI_FTL:
1467                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1468                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1469                                 else
1470                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1471                                 break;
1472                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1473                                 hw->phy.type = ixgbe_phy_sfp_avago;
1474                                 break;
1475                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1476                                 hw->phy.type = ixgbe_phy_sfp_intel;
1477                                 break;
1478                         default:
1479                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1480                                         hw->phy.type =
1481                                                  ixgbe_phy_sfp_passive_unknown;
1482                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1483                                         hw->phy.type =
1484                                                 ixgbe_phy_sfp_active_unknown;
1485                                 else
1486                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1487                                 break;
1488                         }
1489                 }
1490
1491                 /* Allow any DA cable vendor */
1492                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1493                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1494                         status = IXGBE_SUCCESS;
1495                         goto out;
1496                 }
1497
1498                 /* Verify supported 1G SFP modules */
1499                 if (comp_codes_10g == 0 &&
1500                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1501                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1502                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1503                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1504                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1505                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1506                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1507                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1508                         goto out;
1509                 }
1510
1511                 /* Anything else 82598-based is supported */
1512                 if (hw->mac.type == ixgbe_mac_82598EB) {
1513                         status = IXGBE_SUCCESS;
1514                         goto out;
1515                 }
1516
1517                 ixgbe_get_device_caps(hw, &enforce_sfp);
1518                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1519                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1520                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1521                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1522                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1523                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1524                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1525                         /* Make sure we're a supported PHY type */
1526                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1527                                 status = IXGBE_SUCCESS;
1528                         } else {
1529                                 if (hw->allow_unsupported_sfp == true) {
1530                                         EWARN(hw, "WARNING: Intel (R) Network "
1531                                               "Connections are quality tested "
1532                                               "using Intel (R) Ethernet Optics."
1533                                               " Using untested modules is not "
1534                                               "supported and may cause unstable"
1535                                               " operation or damage to the "
1536                                               "module or the adapter. Intel "
1537                                               "Corporation is not responsible "
1538                                               "for any harm caused by using "
1539                                               "untested modules.\n", status);
1540                                         status = IXGBE_SUCCESS;
1541                                 } else {
1542                                         DEBUGOUT("SFP+ module not supported\n");
1543                                         hw->phy.type =
1544                                                 ixgbe_phy_sfp_unsupported;
1545                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1546                                 }
1547                         }
1548                 } else {
1549                         status = IXGBE_SUCCESS;
1550                 }
1551         }
1552
1553 out:
1554         return status;
1555
1556 err_read_i2c_eeprom:
1557         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1558         if (hw->phy.type != ixgbe_phy_nl) {
1559                 hw->phy.id = 0;
1560                 hw->phy.type = ixgbe_phy_unknown;
1561         }
1562         return IXGBE_ERR_SFP_NOT_PRESENT;
1563 }
1564
1565 /**
1566  *  ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1567  *  @hw: pointer to hardware structure
1568  *
1569  *  Determines physical layer capabilities of the current SFP.
1570  */
1571 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1572 {
1573         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1574         u8 comp_codes_10g = 0;
1575         u8 comp_codes_1g = 0;
1576
1577         DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1578
1579         hw->phy.ops.identify_sfp(hw);
1580         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1581                 return physical_layer;
1582
1583         switch (hw->phy.type) {
1584         case ixgbe_phy_sfp_passive_tyco:
1585         case ixgbe_phy_sfp_passive_unknown:
1586         case ixgbe_phy_qsfp_passive_unknown:
1587                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1588                 break;
1589         case ixgbe_phy_sfp_ftl_active:
1590         case ixgbe_phy_sfp_active_unknown:
1591         case ixgbe_phy_qsfp_active_unknown:
1592                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1593                 break;
1594         case ixgbe_phy_sfp_avago:
1595         case ixgbe_phy_sfp_ftl:
1596         case ixgbe_phy_sfp_intel:
1597         case ixgbe_phy_sfp_unknown:
1598                 hw->phy.ops.read_i2c_eeprom(hw,
1599                       IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1600                 hw->phy.ops.read_i2c_eeprom(hw,
1601                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1602                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1603                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1604                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1605                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1606                 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1607                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1608                 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1609                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1610                 break;
1611         case ixgbe_phy_qsfp_intel:
1612         case ixgbe_phy_qsfp_unknown:
1613                 hw->phy.ops.read_i2c_eeprom(hw,
1614                       IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1615                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1616                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1617                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1618                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1619                 break;
1620         default:
1621                 break;
1622         }
1623
1624         return physical_layer;
1625 }
1626
1627 /**
1628  *  ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1629  *  @hw: pointer to hardware structure
1630  *
1631  *  Searches for and identifies the QSFP module and assigns appropriate PHY type
1632  **/
1633 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1634 {
1635         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1636         u32 vendor_oui = 0;
1637         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1638         u8 identifier = 0;
1639         u8 comp_codes_1g = 0;
1640         u8 comp_codes_10g = 0;
1641         u8 oui_bytes[3] = {0, 0, 0};
1642         u16 enforce_sfp = 0;
1643         u8 connector = 0;
1644         u8 cable_length = 0;
1645         u8 device_tech = 0;
1646         bool active_cable = false;
1647
1648         DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1649
1650         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1651                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1652                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1653                 goto out;
1654         }
1655
1656         /* LAN ID is needed for I2C access */
1657         hw->mac.ops.set_lan_id(hw);
1658
1659         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1660                                              &identifier);
1661
1662         if (status != IXGBE_SUCCESS)
1663                 goto err_read_i2c_eeprom;
1664
1665         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1666                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1667                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1668                 goto out;
1669         }
1670
1671         hw->phy.id = identifier;
1672
1673         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1674                                              &comp_codes_10g);
1675
1676         if (status != IXGBE_SUCCESS)
1677                 goto err_read_i2c_eeprom;
1678
1679         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1680                                              &comp_codes_1g);
1681
1682         if (status != IXGBE_SUCCESS)
1683                 goto err_read_i2c_eeprom;
1684
1685         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1686                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1687                 if (hw->bus.lan_id == 0)
1688                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1689                 else
1690                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1691         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1692                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1693                 if (hw->bus.lan_id == 0)
1694                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1695                 else
1696                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1697         } else {
1698                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1699                         active_cable = true;
1700
1701                 if (!active_cable) {
1702                         /* check for active DA cables that pre-date
1703                          * SFF-8436 v3.6 */
1704                         hw->phy.ops.read_i2c_eeprom(hw,
1705                                         IXGBE_SFF_QSFP_CONNECTOR,
1706                                         &connector);
1707
1708                         hw->phy.ops.read_i2c_eeprom(hw,
1709                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1710                                         &cable_length);
1711
1712                         hw->phy.ops.read_i2c_eeprom(hw,
1713                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1714                                         &device_tech);
1715
1716                         if ((connector ==
1717                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1718                             (cable_length > 0) &&
1719                             ((device_tech >> 4) ==
1720                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1721                                 active_cable = true;
1722                 }
1723
1724                 if (active_cable) {
1725                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1726                         if (hw->bus.lan_id == 0)
1727                                 hw->phy.sfp_type =
1728                                                 ixgbe_sfp_type_da_act_lmt_core0;
1729                         else
1730                                 hw->phy.sfp_type =
1731                                                 ixgbe_sfp_type_da_act_lmt_core1;
1732                 } else {
1733                         /* unsupported module type */
1734                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1735                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1736                         goto out;
1737                 }
1738         }
1739
1740         if (hw->phy.sfp_type != stored_sfp_type)
1741                 hw->phy.sfp_setup_needed = true;
1742
1743         /* Determine if the QSFP+ PHY is dual speed or not. */
1744         hw->phy.multispeed_fiber = false;
1745         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1746            (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1747            ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1748            (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1749                 hw->phy.multispeed_fiber = true;
1750
1751         /* Determine PHY vendor for optical modules */
1752         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1753                               IXGBE_SFF_10GBASELR_CAPABLE))  {
1754                 status = hw->phy.ops.read_i2c_eeprom(hw,
1755                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1756                                             &oui_bytes[0]);
1757
1758                 if (status != IXGBE_SUCCESS)
1759                         goto err_read_i2c_eeprom;
1760
1761                 status = hw->phy.ops.read_i2c_eeprom(hw,
1762                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1763                                             &oui_bytes[1]);
1764
1765                 if (status != IXGBE_SUCCESS)
1766                         goto err_read_i2c_eeprom;
1767
1768                 status = hw->phy.ops.read_i2c_eeprom(hw,
1769                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1770                                             &oui_bytes[2]);
1771
1772                 if (status != IXGBE_SUCCESS)
1773                         goto err_read_i2c_eeprom;
1774
1775                 vendor_oui =
1776                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1777                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1778                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1779
1780                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1781                         hw->phy.type = ixgbe_phy_qsfp_intel;
1782                 else
1783                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1784
1785                 ixgbe_get_device_caps(hw, &enforce_sfp);
1786                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1787                         /* Make sure we're a supported PHY type */
1788                         if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1789                                 status = IXGBE_SUCCESS;
1790                         } else {
1791                                 if (hw->allow_unsupported_sfp == true) {
1792                                         EWARN(hw, "WARNING: Intel (R) Network "
1793                                               "Connections are quality tested "
1794                                               "using Intel (R) Ethernet Optics."
1795                                               " Using untested modules is not "
1796                                               "supported and may cause unstable"
1797                                               " operation or damage to the "
1798                                               "module or the adapter. Intel "
1799                                               "Corporation is not responsible "
1800                                               "for any harm caused by using "
1801                                               "untested modules.\n", status);
1802                                         status = IXGBE_SUCCESS;
1803                                 } else {
1804                                         DEBUGOUT("QSFP module not supported\n");
1805                                         hw->phy.type =
1806                                                 ixgbe_phy_sfp_unsupported;
1807                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1808                                 }
1809                         }
1810                 } else {
1811                         status = IXGBE_SUCCESS;
1812                 }
1813         }
1814
1815 out:
1816         return status;
1817
1818 err_read_i2c_eeprom:
1819         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1820         hw->phy.id = 0;
1821         hw->phy.type = ixgbe_phy_unknown;
1822
1823         return IXGBE_ERR_SFP_NOT_PRESENT;
1824 }
1825
1826
1827 /**
1828  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1829  *  @hw: pointer to hardware structure
1830  *  @list_offset: offset to the SFP ID list
1831  *  @data_offset: offset to the SFP data block
1832  *
1833  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1834  *  so it returns the offsets to the phy init sequence block.
1835  **/
1836 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1837                                         u16 *list_offset,
1838                                         u16 *data_offset)
1839 {
1840         u16 sfp_id;
1841         u16 sfp_type = hw->phy.sfp_type;
1842
1843         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1844
1845         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1846                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1847
1848         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1849                 return IXGBE_ERR_SFP_NOT_PRESENT;
1850
1851         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1852             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1853                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1854
1855         /*
1856          * Limiting active cables and 1G Phys must be initialized as
1857          * SR modules
1858          */
1859         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1860             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1861             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1862             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1863                 sfp_type = ixgbe_sfp_type_srlr_core0;
1864         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1865                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1866                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1867                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1868                 sfp_type = ixgbe_sfp_type_srlr_core1;
1869
1870         /* Read offset to PHY init contents */
1871         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1872                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1873                               "eeprom read at offset %d failed",
1874                               IXGBE_PHY_INIT_OFFSET_NL);
1875                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1876         }
1877
1878         if ((!*list_offset) || (*list_offset == 0xFFFF))
1879                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1880
1881         /* Shift offset to first ID word */
1882         (*list_offset)++;
1883
1884         /*
1885          * Find the matching SFP ID in the EEPROM
1886          * and program the init sequence
1887          */
1888         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1889                 goto err_phy;
1890
1891         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1892                 if (sfp_id == sfp_type) {
1893                         (*list_offset)++;
1894                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1895                                 goto err_phy;
1896                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1897                                 DEBUGOUT("SFP+ module not supported\n");
1898                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1899                         } else {
1900                                 break;
1901                         }
1902                 } else {
1903                         (*list_offset) += 2;
1904                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1905                                 goto err_phy;
1906                 }
1907         }
1908
1909         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1910                 DEBUGOUT("No matching SFP+ module found\n");
1911                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1912         }
1913
1914         return IXGBE_SUCCESS;
1915
1916 err_phy:
1917         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1918                       "eeprom read at offset %d failed", *list_offset);
1919         return IXGBE_ERR_PHY;
1920 }
1921
1922 /**
1923  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1924  *  @hw: pointer to hardware structure
1925  *  @byte_offset: EEPROM byte offset to read
1926  *  @eeprom_data: value read
1927  *
1928  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1929  **/
1930 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1931                                   u8 *eeprom_data)
1932 {
1933         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1934
1935         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1936                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1937                                          eeprom_data);
1938 }
1939
1940 /**
1941  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1942  *  @hw: pointer to hardware structure
1943  *  @byte_offset: byte offset at address 0xA2
1944  *  @eeprom_data: value read
1945  *
1946  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1947  **/
1948 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1949                                           u8 *sff8472_data)
1950 {
1951         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1952                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1953                                          sff8472_data);
1954 }
1955
1956 /**
1957  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1958  *  @hw: pointer to hardware structure
1959  *  @byte_offset: EEPROM byte offset to write
1960  *  @eeprom_data: value to write
1961  *
1962  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1963  **/
1964 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1965                                    u8 eeprom_data)
1966 {
1967         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1968
1969         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1970                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1971                                           eeprom_data);
1972 }
1973
1974 /**
1975  * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1976  * @hw: pointer to hardware structure
1977  * @offset: eeprom offset to be read
1978  * @addr: I2C address to be read
1979  */
1980 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1981 {
1982         if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1983             offset == IXGBE_SFF_IDENTIFIER &&
1984             hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1985                 return true;
1986         return false;
1987 }
1988
1989 /**
1990  *  ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1991  *  @hw: pointer to hardware structure
1992  *  @byte_offset: byte offset to read
1993  *  @data: value read
1994  *  @lock: true if to take and release semaphore
1995  *
1996  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1997  *  a specified device address.
1998  **/
1999 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2000                                            u8 dev_addr, u8 *data, bool lock)
2001 {
2002         s32 status;
2003         u32 max_retry = 10;
2004         u32 retry = 0;
2005         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2006         bool nack = 1;
2007         *data = 0;
2008
2009         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2010
2011         if (hw->mac.type >= ixgbe_mac_X550)
2012                 max_retry = 3;
2013         if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2014                 max_retry = IXGBE_SFP_DETECT_RETRIES;
2015
2016         do {
2017                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2018                         return IXGBE_ERR_SWFW_SYNC;
2019
2020                 ixgbe_i2c_start(hw);
2021
2022                 /* Device Address and write indication */
2023                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2024                 if (status != IXGBE_SUCCESS)
2025                         goto fail;
2026
2027                 status = ixgbe_get_i2c_ack(hw);
2028                 if (status != IXGBE_SUCCESS)
2029                         goto fail;
2030
2031                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2032                 if (status != IXGBE_SUCCESS)
2033                         goto fail;
2034
2035                 status = ixgbe_get_i2c_ack(hw);
2036                 if (status != IXGBE_SUCCESS)
2037                         goto fail;
2038
2039                 ixgbe_i2c_start(hw);
2040
2041                 /* Device Address and read indication */
2042                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2043                 if (status != IXGBE_SUCCESS)
2044                         goto fail;
2045
2046                 status = ixgbe_get_i2c_ack(hw);
2047                 if (status != IXGBE_SUCCESS)
2048                         goto fail;
2049
2050                 status = ixgbe_clock_in_i2c_byte(hw, data);
2051                 if (status != IXGBE_SUCCESS)
2052                         goto fail;
2053
2054                 status = ixgbe_clock_out_i2c_bit(hw, nack);
2055                 if (status != IXGBE_SUCCESS)
2056                         goto fail;
2057
2058                 ixgbe_i2c_stop(hw);
2059                 if (lock)
2060                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2061                 return IXGBE_SUCCESS;
2062
2063 fail:
2064                 ixgbe_i2c_bus_clear(hw);
2065                 if (lock) {
2066                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2067                         msec_delay(100);
2068                 }
2069                 retry++;
2070                 if (retry < max_retry)
2071                         DEBUGOUT("I2C byte read error - Retrying.\n");
2072                 else
2073                         DEBUGOUT("I2C byte read error.\n");
2074
2075         } while (retry < max_retry);
2076
2077         return status;
2078 }
2079
2080 /**
2081  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2082  *  @hw: pointer to hardware structure
2083  *  @byte_offset: byte offset to read
2084  *  @data: value read
2085  *
2086  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2087  *  a specified device address.
2088  **/
2089 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2090                                 u8 dev_addr, u8 *data)
2091 {
2092         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2093                                                data, true);
2094 }
2095
2096 /**
2097  *  ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2098  *  @hw: pointer to hardware structure
2099  *  @byte_offset: byte offset to read
2100  *  @data: value read
2101  *
2102  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2103  *  a specified device address.
2104  **/
2105 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2106                                          u8 dev_addr, u8 *data)
2107 {
2108         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2109                                                data, false);
2110 }
2111
2112 /**
2113  *  ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2114  *  @hw: pointer to hardware structure
2115  *  @byte_offset: byte offset to write
2116  *  @data: value to write
2117  *  @lock: true if to take and release semaphore
2118  *
2119  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2120  *  a specified device address.
2121  **/
2122 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2123                                             u8 dev_addr, u8 data, bool lock)
2124 {
2125         s32 status;
2126         u32 max_retry = 1;
2127         u32 retry = 0;
2128         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2129
2130         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2131
2132         if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2133             IXGBE_SUCCESS)
2134                 return IXGBE_ERR_SWFW_SYNC;
2135
2136         do {
2137                 ixgbe_i2c_start(hw);
2138
2139                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2140                 if (status != IXGBE_SUCCESS)
2141                         goto fail;
2142
2143                 status = ixgbe_get_i2c_ack(hw);
2144                 if (status != IXGBE_SUCCESS)
2145                         goto fail;
2146
2147                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2148                 if (status != IXGBE_SUCCESS)
2149                         goto fail;
2150
2151                 status = ixgbe_get_i2c_ack(hw);
2152                 if (status != IXGBE_SUCCESS)
2153                         goto fail;
2154
2155                 status = ixgbe_clock_out_i2c_byte(hw, data);
2156                 if (status != IXGBE_SUCCESS)
2157                         goto fail;
2158
2159                 status = ixgbe_get_i2c_ack(hw);
2160                 if (status != IXGBE_SUCCESS)
2161                         goto fail;
2162
2163                 ixgbe_i2c_stop(hw);
2164                 if (lock)
2165                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2166                 return IXGBE_SUCCESS;
2167
2168 fail:
2169                 ixgbe_i2c_bus_clear(hw);
2170                 retry++;
2171                 if (retry < max_retry)
2172                         DEBUGOUT("I2C byte write error - Retrying.\n");
2173                 else
2174                         DEBUGOUT("I2C byte write error.\n");
2175         } while (retry < max_retry);
2176
2177         if (lock)
2178                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2179
2180         return status;
2181 }
2182
2183 /**
2184  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2185  *  @hw: pointer to hardware structure
2186  *  @byte_offset: byte offset to write
2187  *  @data: value to write
2188  *
2189  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2190  *  a specified device address.
2191  **/
2192 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2193                                  u8 dev_addr, u8 data)
2194 {
2195         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2196                                                 data, true);
2197 }
2198
2199 /**
2200  *  ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2201  *  @hw: pointer to hardware structure
2202  *  @byte_offset: byte offset to write
2203  *  @data: value to write
2204  *
2205  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2206  *  a specified device address.
2207  **/
2208 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2209                                           u8 dev_addr, u8 data)
2210 {
2211         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2212                                                 data, false);
2213 }
2214
2215 /**
2216  *  ixgbe_i2c_start - Sets I2C start condition
2217  *  @hw: pointer to hardware structure
2218  *
2219  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
2220  *  Set bit-bang mode on X550 hardware.
2221  **/
2222 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2223 {
2224         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2225
2226         DEBUGFUNC("ixgbe_i2c_start");
2227
2228         i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2229
2230         /* Start condition must begin with data and clock high */
2231         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2232         ixgbe_raise_i2c_clk(hw, &i2cctl);
2233
2234         /* Setup time for start condition (4.7us) */
2235         usec_delay(IXGBE_I2C_T_SU_STA);
2236
2237         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2238
2239         /* Hold time for start condition (4us) */
2240         usec_delay(IXGBE_I2C_T_HD_STA);
2241
2242         ixgbe_lower_i2c_clk(hw, &i2cctl);
2243
2244         /* Minimum low period of clock is 4.7 us */
2245         usec_delay(IXGBE_I2C_T_LOW);
2246
2247 }
2248
2249 /**
2250  *  ixgbe_i2c_stop - Sets I2C stop condition
2251  *  @hw: pointer to hardware structure
2252  *
2253  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
2254  *  Disables bit-bang mode and negates data output enable on X550
2255  *  hardware.
2256  **/
2257 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2258 {
2259         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2260         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2261         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2262         u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2263
2264         DEBUGFUNC("ixgbe_i2c_stop");
2265
2266         /* Stop condition must begin with data low and clock high */
2267         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2268         ixgbe_raise_i2c_clk(hw, &i2cctl);
2269
2270         /* Setup time for stop condition (4us) */
2271         usec_delay(IXGBE_I2C_T_SU_STO);
2272
2273         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2274
2275         /* bus free time between stop and start (4.7us)*/
2276         usec_delay(IXGBE_I2C_T_BUF);
2277
2278         if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2279                 i2cctl &= ~bb_en_bit;
2280                 i2cctl |= data_oe_bit | clk_oe_bit;
2281                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2282                 IXGBE_WRITE_FLUSH(hw);
2283         }
2284 }
2285
2286 /**
2287  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2288  *  @hw: pointer to hardware structure
2289  *  @data: data byte to clock in
2290  *
2291  *  Clocks in one byte data via I2C data/clock
2292  **/
2293 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2294 {
2295         s32 i;
2296         bool bit = 0;
2297
2298         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2299
2300         *data = 0;
2301         for (i = 7; i >= 0; i--) {
2302                 ixgbe_clock_in_i2c_bit(hw, &bit);
2303                 *data |= bit << i;
2304         }
2305
2306         return IXGBE_SUCCESS;
2307 }
2308
2309 /**
2310  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2311  *  @hw: pointer to hardware structure
2312  *  @data: data byte clocked out
2313  *
2314  *  Clocks out one byte data via I2C data/clock
2315  **/
2316 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2317 {
2318         s32 status = IXGBE_SUCCESS;
2319         s32 i;
2320         u32 i2cctl;
2321         bool bit;
2322
2323         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2324
2325         for (i = 7; i >= 0; i--) {
2326                 bit = (data >> i) & 0x1;
2327                 status = ixgbe_clock_out_i2c_bit(hw, bit);
2328
2329                 if (status != IXGBE_SUCCESS)
2330                         break;
2331         }
2332
2333         /* Release SDA line (set high) */
2334         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2335         i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2336         i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2337         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2338         IXGBE_WRITE_FLUSH(hw);
2339
2340         return status;
2341 }
2342
2343 /**
2344  *  ixgbe_get_i2c_ack - Polls for I2C ACK
2345  *  @hw: pointer to hardware structure
2346  *
2347  *  Clocks in/out one bit via I2C data/clock
2348  **/
2349 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2350 {
2351         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2352         s32 status = IXGBE_SUCCESS;
2353         u32 i = 0;
2354         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2355         u32 timeout = 10;
2356         bool ack = 1;
2357
2358         DEBUGFUNC("ixgbe_get_i2c_ack");
2359
2360         if (data_oe_bit) {
2361                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2362                 i2cctl |= data_oe_bit;
2363                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2364                 IXGBE_WRITE_FLUSH(hw);
2365         }
2366         ixgbe_raise_i2c_clk(hw, &i2cctl);
2367
2368         /* Minimum high period of clock is 4us */
2369         usec_delay(IXGBE_I2C_T_HIGH);
2370
2371         /* Poll for ACK.  Note that ACK in I2C spec is
2372          * transition from 1 to 0 */
2373         for (i = 0; i < timeout; i++) {
2374                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2375                 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2376
2377                 usec_delay(1);
2378                 if (!ack)
2379                         break;
2380         }
2381
2382         if (ack) {
2383                 DEBUGOUT("I2C ack was not received.\n");
2384                 status = IXGBE_ERR_I2C;
2385         }
2386
2387         ixgbe_lower_i2c_clk(hw, &i2cctl);
2388
2389         /* Minimum low period of clock is 4.7 us */
2390         usec_delay(IXGBE_I2C_T_LOW);
2391
2392         return status;
2393 }
2394
2395 /**
2396  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2397  *  @hw: pointer to hardware structure
2398  *  @data: read data value
2399  *
2400  *  Clocks in one bit via I2C data/clock
2401  **/
2402 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2403 {
2404         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2405         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2406
2407         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2408
2409         if (data_oe_bit) {
2410                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2411                 i2cctl |= data_oe_bit;
2412                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2413                 IXGBE_WRITE_FLUSH(hw);
2414         }
2415         ixgbe_raise_i2c_clk(hw, &i2cctl);
2416
2417         /* Minimum high period of clock is 4us */
2418         usec_delay(IXGBE_I2C_T_HIGH);
2419
2420         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2421         *data = ixgbe_get_i2c_data(hw, &i2cctl);
2422
2423         ixgbe_lower_i2c_clk(hw, &i2cctl);
2424
2425         /* Minimum low period of clock is 4.7 us */
2426         usec_delay(IXGBE_I2C_T_LOW);
2427
2428         return IXGBE_SUCCESS;
2429 }
2430
2431 /**
2432  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2433  *  @hw: pointer to hardware structure
2434  *  @data: data value to write
2435  *
2436  *  Clocks out one bit via I2C data/clock
2437  **/
2438 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2439 {
2440         s32 status;
2441         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2442
2443         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2444
2445         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2446         if (status == IXGBE_SUCCESS) {
2447                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2448
2449                 /* Minimum high period of clock is 4us */
2450                 usec_delay(IXGBE_I2C_T_HIGH);
2451
2452                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2453
2454                 /* Minimum low period of clock is 4.7 us.
2455                  * This also takes care of the data hold time.
2456                  */
2457                 usec_delay(IXGBE_I2C_T_LOW);
2458         } else {
2459                 status = IXGBE_ERR_I2C;
2460                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2461                              "I2C data was not set to %X\n", data);
2462         }
2463
2464         return status;
2465 }
2466
2467 /**
2468  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2469  *  @hw: pointer to hardware structure
2470  *  @i2cctl: Current value of I2CCTL register
2471  *
2472  *  Raises the I2C clock line '0'->'1'
2473  *  Negates the I2C clock output enable on X550 hardware.
2474  **/
2475 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2476 {
2477         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2478         u32 i = 0;
2479         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2480         u32 i2cctl_r = 0;
2481
2482         DEBUGFUNC("ixgbe_raise_i2c_clk");
2483
2484         if (clk_oe_bit) {
2485                 *i2cctl |= clk_oe_bit;
2486                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2487         }
2488
2489         for (i = 0; i < timeout; i++) {
2490                 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2491
2492                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2493                 IXGBE_WRITE_FLUSH(hw);
2494                 /* SCL rise time (1000ns) */
2495                 usec_delay(IXGBE_I2C_T_RISE);
2496
2497                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2498                 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2499                         break;
2500         }
2501 }
2502
2503 /**
2504  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2505  *  @hw: pointer to hardware structure
2506  *  @i2cctl: Current value of I2CCTL register
2507  *
2508  *  Lowers the I2C clock line '1'->'0'
2509  *  Asserts the I2C clock output enable on X550 hardware.
2510  **/
2511 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2512 {
2513         DEBUGFUNC("ixgbe_lower_i2c_clk");
2514
2515         *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2516         *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2517
2518         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2519         IXGBE_WRITE_FLUSH(hw);
2520
2521         /* SCL fall time (300ns) */
2522         usec_delay(IXGBE_I2C_T_FALL);
2523 }
2524
2525 /**
2526  *  ixgbe_set_i2c_data - Sets the I2C data bit
2527  *  @hw: pointer to hardware structure
2528  *  @i2cctl: Current value of I2CCTL register
2529  *  @data: I2C data value (0 or 1) to set
2530  *
2531  *  Sets the I2C data bit
2532  *  Asserts the I2C data output enable on X550 hardware.
2533  **/
2534 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2535 {
2536         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2537         s32 status = IXGBE_SUCCESS;
2538
2539         DEBUGFUNC("ixgbe_set_i2c_data");
2540
2541         if (data)
2542                 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2543         else
2544                 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2545         *i2cctl &= ~data_oe_bit;
2546
2547         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2548         IXGBE_WRITE_FLUSH(hw);
2549
2550         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2551         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2552
2553         if (!data)      /* Can't verify data in this case */
2554                 return IXGBE_SUCCESS;
2555         if (data_oe_bit) {
2556                 *i2cctl |= data_oe_bit;
2557                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2558                 IXGBE_WRITE_FLUSH(hw);
2559         }
2560
2561         /* Verify data was set correctly */
2562         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2563         if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2564                 status = IXGBE_ERR_I2C;
2565                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2566                              "Error - I2C data was not set to %X.\n",
2567                              data);
2568         }
2569
2570         return status;
2571 }
2572
2573 /**
2574  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2575  *  @hw: pointer to hardware structure
2576  *  @i2cctl: Current value of I2CCTL register
2577  *
2578  *  Returns the I2C data bit value
2579  *  Negates the I2C data output enable on X550 hardware.
2580  **/
2581 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2582 {
2583         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2584         bool data;
2585
2586         DEBUGFUNC("ixgbe_get_i2c_data");
2587
2588         if (data_oe_bit) {
2589                 *i2cctl |= data_oe_bit;
2590                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2591                 IXGBE_WRITE_FLUSH(hw);
2592                 usec_delay(IXGBE_I2C_T_FALL);
2593         }
2594
2595         if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2596                 data = 1;
2597         else
2598                 data = 0;
2599
2600         return data;
2601 }
2602
2603 /**
2604  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2605  *  @hw: pointer to hardware structure
2606  *
2607  *  Clears the I2C bus by sending nine clock pulses.
2608  *  Used when data line is stuck low.
2609  **/
2610 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2611 {
2612         u32 i2cctl;
2613         u32 i;
2614
2615         DEBUGFUNC("ixgbe_i2c_bus_clear");
2616
2617         ixgbe_i2c_start(hw);
2618         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2619
2620         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2621
2622         for (i = 0; i < 9; i++) {
2623                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2624
2625                 /* Min high period of clock is 4us */
2626                 usec_delay(IXGBE_I2C_T_HIGH);
2627
2628                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2629
2630                 /* Min low period of clock is 4.7us*/
2631                 usec_delay(IXGBE_I2C_T_LOW);
2632         }
2633
2634         ixgbe_i2c_start(hw);
2635
2636         /* Put the i2c bus back to default state */
2637         ixgbe_i2c_stop(hw);
2638 }
2639
2640 /**
2641  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2642  *  @hw: pointer to hardware structure
2643  *
2644  *  Checks if the LASI temp alarm status was triggered due to overtemp
2645  **/
2646 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2647 {
2648         s32 status = IXGBE_SUCCESS;
2649         u16 phy_data = 0;
2650
2651         DEBUGFUNC("ixgbe_tn_check_overtemp");
2652
2653         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2654                 goto out;
2655
2656         /* Check that the LASI temp alarm status was triggered */
2657         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2658                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2659
2660         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2661                 goto out;
2662
2663         status = IXGBE_ERR_OVERTEMP;
2664         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2665 out:
2666         return status;
2667 }
2668
2669 /**
2670  * ixgbe_set_copper_phy_power - Control power for copper phy
2671  * @hw: pointer to hardware structure
2672  * @on: true for on, false for off
2673  */
2674 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2675 {
2676         u32 status;
2677         u16 reg;
2678
2679         if (!on && ixgbe_mng_present(hw))
2680                 return 0;
2681
2682         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2683                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2684                                       &reg);
2685         if (status)
2686                 return status;
2687
2688         if (on) {
2689                 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2690         } else {
2691                 if (ixgbe_check_reset_blocked(hw))
2692                         return 0;
2693                 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2694         }
2695
2696         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2697                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2698                                        reg);
2699         return status;
2700 }