drivers/net/ixgbe/base/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_api.h"
  35 #include "ixgbe_common.h"
  36 #include "ixgbe_phy.h"
  37
  38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
  39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  50                                           u8 *sff8472_data);
  51
  52 /**
  53  * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
  54  * @hw: pointer to the hardware structure
  55  * @byte: byte to send
  56  *
  57  * Returns an error code on error.
  58  */
  59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
  60 {
  61         s32 status;
  62
  63         status = ixgbe_clock_out_i2c_byte(hw, byte);
  64         if (status)
  65                 return status;
  66         return ixgbe_get_i2c_ack(hw);
  67 }
  68
  69 /**
  70  * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
  71  * @hw: pointer to the hardware structure
  72  * @byte: pointer to a u8 to receive the byte
  73  *
  74  * Returns an error code on error.
  75  */
  76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
  77 {
  78         s32 status;
  79
  80         status = ixgbe_clock_in_i2c_byte(hw, byte);
  81         if (status)
  82                 return status;
  83         /* ACK */
  84         return ixgbe_clock_out_i2c_bit(hw, false);
  85 }
  86
  87 /**
  88  * ixgbe_ones_comp_byte_add - Perform one's complement addition
  89  * @add1 - addend 1
  90  * @add2 - addend 2
  91  *
  92  * Returns one's complement 8-bit sum.
  93  */
  94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
  95 {
  96         u16 sum = add1 + add2;
  97
  98         sum = (sum & 0xFF) + (sum >> 8);
  99         return sum & 0xFF;
 100 }
 101
 102 /**
 103  * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
 104  * @hw: pointer to the hardware structure
 105  * @addr: I2C bus address to read from
 106  * @reg: I2C device register to read from
 107  * @val: pointer to location to receive read value
 108  * @lock: true if to take and release semaphore
 109  *
 110  * Returns an error code on error.
 111  */
 112 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 113                                         u16 *val, bool lock)
 114 {
 115         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 116         int max_retry = 10;
 117         int retry = 0;
 118         u8 csum_byte;
 119         u8 high_bits;
 120         u8 low_bits;
 121         u8 reg_high;
 122         u8 csum;
 123
 124         if (hw->mac.type >= ixgbe_mac_X550)
 125                 max_retry = 3;
 126         reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
 127         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 128         csum = ~csum;
 129         do {
 130                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 131                         return IXGBE_ERR_SWFW_SYNC;
 132                 ixgbe_i2c_start(hw);
 133                 /* Device Address and write indication */
 134                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 135                         goto fail;
 136                 /* Write bits 14:8 */
 137                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 138                         goto fail;
 139                 /* Write bits 7:0 */
 140                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 141                         goto fail;
 142                 /* Write csum */
 143                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 144                         goto fail;
 145                 /* Re-start condition */
 146                 ixgbe_i2c_start(hw);
 147                 /* Device Address and read indication */
 148                 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
 149                         goto fail;
 150                 /* Get upper bits */
 151                 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
 152                         goto fail;
 153                 /* Get low bits */
 154                 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
 155                         goto fail;
 156                 /* Get csum */
 157                 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
 158                         goto fail;
 159                 /* NACK */
 160                 if (ixgbe_clock_out_i2c_bit(hw, false))
 161                         goto fail;
 162                 ixgbe_i2c_stop(hw);
 163                 if (lock)
 164                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 165                 *val = (high_bits << 8) | low_bits;
 166                 return 0;
 167
 168 fail:
 169                 ixgbe_i2c_bus_clear(hw);
 170                 if (lock)
 171                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 172                 retry++;
 173                 if (retry < max_retry)
 174                         DEBUGOUT("I2C byte read combined error - Retrying.\n");
 175                 else
 176                         DEBUGOUT("I2C byte read combined error.\n");
 177         } while (retry < max_retry);
 178
 179         return IXGBE_ERR_I2C;
 180 }
 181
 182 /**
 183  * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
 184  * @hw: pointer to the hardware structure
 185  * @addr: I2C bus address to write to
 186  * @reg: I2C device register to write to
 187  * @val: value to write
 188  * @lock: true if to take and release semaphore
 189  *
 190  * Returns an error code on error.
 191  */
 192 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 193                                          u16 val, bool lock)
 194 {
 195         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 196         int max_retry = 1;
 197         int retry = 0;
 198         u8 reg_high;
 199         u8 csum;
 200
 201         reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
 202         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 203         csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
 204         csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
 205         csum = ~csum;
 206         do {
 207                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 208                         return IXGBE_ERR_SWFW_SYNC;
 209                 ixgbe_i2c_start(hw);
 210                 /* Device Address and write indication */
 211                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 212                         goto fail;
 213                 /* Write bits 14:8 */
 214                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 215                         goto fail;
 216                 /* Write bits 7:0 */
 217                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 218                         goto fail;
 219                 /* Write data 15:8 */
 220                 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
 221                         goto fail;
 222                 /* Write data 7:0 */
 223                 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
 224                         goto fail;
 225                 /* Write csum */
 226                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 227                         goto fail;
 228                 ixgbe_i2c_stop(hw);
 229                 if (lock)
 230                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 231                 return 0;
 232
 233 fail:
 234                 ixgbe_i2c_bus_clear(hw);
 235                 if (lock)
 236                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 237                 retry++;
 238                 if (retry < max_retry)
 239                         DEBUGOUT("I2C byte write combined error - Retrying.\n");
 240                 else
 241                         DEBUGOUT("I2C byte write combined error.\n");
 242         } while (retry < max_retry);
 243
 244         return IXGBE_ERR_I2C;
 245 }
 246
 247 /**
 248  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
 249  *  @hw: pointer to the hardware structure
 250  *
 251  *  Initialize the function pointers.
 252  **/
 253 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
 254 {
 255         struct ixgbe_phy_info *phy = &hw->phy;
 256
 257         DEBUGFUNC("ixgbe_init_phy_ops_generic");
 258
 259         /* PHY */
 260         phy->ops.identify = ixgbe_identify_phy_generic;
 261         phy->ops.reset = ixgbe_reset_phy_generic;
 262         phy->ops.read_reg = ixgbe_read_phy_reg_generic;
 263         phy->ops.write_reg = ixgbe_write_phy_reg_generic;
 264         phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
 265         phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
 266         phy->ops.setup_link = ixgbe_setup_phy_link_generic;
 267         phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
 268         phy->ops.check_link = NULL;
 269         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
 270         phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
 271         phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
 272         phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
 273         phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
 274         phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
 275         phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
 276         phy->ops.identify_sfp = ixgbe_identify_module_generic;
 277         phy->sfp_type = ixgbe_sfp_type_unknown;
 278         phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
 279         phy->ops.write_i2c_byte_unlocked =
 280                                 ixgbe_write_i2c_byte_generic_unlocked;
 281         phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
 282         return IXGBE_SUCCESS;
 283 }
 284
 285 /**
 286  * ixgbe_probe_phy - Probe a single address for a PHY
 287  * @hw: pointer to hardware structure
 288  * @phy_addr: PHY address to probe
 289  *
 290  * Returns true if PHY found
 291  */
 292 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
 293 {
 294         u16 ext_ability = 0;
 295
 296         if (!ixgbe_validate_phy_addr(hw, phy_addr))
 297                 return false;
 298
 299         if (ixgbe_get_phy_id(hw))
 300                 return false;
 301
 302         hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
 303
 304         if (hw->phy.type == ixgbe_phy_unknown) {
 305                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
 306                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
 307                 if (ext_ability &
 308                     (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 309                      IXGBE_MDIO_PHY_1000BASET_ABILITY))
 310                         hw->phy.type = ixgbe_phy_cu_unknown;
 311                 else
 312                         hw->phy.type = ixgbe_phy_generic;
 313         }
 314
 315         return true;
 316 }
 317
 318 /**
 319  *  ixgbe_identify_phy_generic - Get physical layer module
 320  *  @hw: pointer to hardware structure
 321  *
 322  *  Determines the physical layer module found on the current adapter.
 323  **/
 324 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 325 {
 326         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 327         u16 phy_addr;
 328
 329         DEBUGFUNC("ixgbe_identify_phy_generic");
 330
 331         if (!hw->phy.phy_semaphore_mask) {
 332                 if (hw->bus.lan_id)
 333                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 334                 else
 335                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 336         }
 337
 338         if (hw->phy.type == ixgbe_phy_unknown) {
 339                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 340                 if (ixgbe_probe_phy(hw, phy_addr)) {
 341                                 status = IXGBE_SUCCESS;
 342                                 break;
 343                         }
 344                 }
 345
 346                 /* Certain media types do not have a phy so an address will not
 347                  * be found and the code will take this path.  Caller has to
 348                  * decide if it is an error or not.
 349                  */
 350                 if (status != IXGBE_SUCCESS) {
 351                         hw->phy.addr = 0;
 352                 }
 353         } else {
 354                 status = IXGBE_SUCCESS;
 355         }
 356
 357         return status;
 358 }
 359
 360 /**
 361  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 362  * @hw: pointer to the hardware structure
 363  *
 364  * This function checks the MMNGC.MNG_VETO bit to see if there are
 365  * any constraints on link from manageability.  For MAC's that don't
 366  * have this bit just return faluse since the link can not be blocked
 367  * via this method.
 368  **/
 369 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 370 {
 371         u32 mmngc;
 372
 373         DEBUGFUNC("ixgbe_check_reset_blocked");
 374
 375         /* If we don't have this bit, it can't be blocking */
 376         if (hw->mac.type == ixgbe_mac_82598EB)
 377                 return false;
 378
 379         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 380         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 381                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 382                               "MNG_VETO bit detected.\n");
 383                 return true;
 384         }
 385
 386         return false;
 387 }
 388
 389 /**
 390  *  ixgbe_validate_phy_addr - Determines phy address is valid
 391  *  @hw: pointer to hardware structure
 392  *
 393  **/
 394 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 395 {
 396         u16 phy_id = 0;
 397         bool valid = false;
 398
 399         DEBUGFUNC("ixgbe_validate_phy_addr");
 400
 401         hw->phy.addr = phy_addr;
 402         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 403                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 404
 405         if (phy_id != 0xFFFF && phy_id != 0x0)
 406                 valid = true;
 407
 408         return valid;
 409 }
 410
 411 /**
 412  *  ixgbe_get_phy_id - Get the phy type
 413  *  @hw: pointer to hardware structure
 414  *
 415  **/
 416 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 417 {
 418         u32 status;
 419         u16 phy_id_high = 0;
 420         u16 phy_id_low = 0;
 421
 422         DEBUGFUNC("ixgbe_get_phy_id");
 423
 424         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 425                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 426                                       &phy_id_high);
 427
 428         if (status == IXGBE_SUCCESS) {
 429                 hw->phy.id = (u32)(phy_id_high << 16);
 430                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 431                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 432                                               &phy_id_low);
 433                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 434                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 435         }
 436         return status;
 437 }
 438
 439 /**
 440  *  ixgbe_get_phy_type_from_id - Get the phy type
 441  *  @phy_id: PHY ID information
 442  *
 443  **/
 444 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 445 {
 446         enum ixgbe_phy_type phy_type;
 447
 448         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 449
 450         switch (phy_id) {
 451         case TN1010_PHY_ID:
 452                 phy_type = ixgbe_phy_tn;
 453                 break;
 454         case X550_PHY_ID1:
 455         case X550_PHY_ID2:
 456         case X550_PHY_ID3:
 457         case X540_PHY_ID:
 458                 phy_type = ixgbe_phy_aq;
 459                 break;
 460         case QT2022_PHY_ID:
 461                 phy_type = ixgbe_phy_qt;
 462                 break;
 463         case ATH_PHY_ID:
 464                 phy_type = ixgbe_phy_nl;
 465                 break;
 466         case X557_PHY_ID:
 467                 phy_type = ixgbe_phy_x550em_ext_t;
 468                 break;
 469         case IXGBE_M88E1500_E_PHY_ID:
 470                 phy_type = ixgbe_phy_m88;
 471                 break;
 472         default:
 473                 phy_type = ixgbe_phy_unknown;
 474                 break;
 475         }
 476         return phy_type;
 477 }
 478
 479 /**
 480  *  ixgbe_reset_phy_generic - Performs a PHY reset
 481  *  @hw: pointer to hardware structure
 482  **/
 483 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 484 {
 485         u32 i;
 486         u16 ctrl = 0;
 487         s32 status = IXGBE_SUCCESS;
 488
 489         DEBUGFUNC("ixgbe_reset_phy_generic");
 490
 491         if (hw->phy.type == ixgbe_phy_unknown)
 492                 status = ixgbe_identify_phy_generic(hw);
 493
 494         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 495                 goto out;
 496
 497         /* Don't reset PHY if it's shut down due to overtemp. */
 498         if (!hw->phy.reset_if_overtemp &&
 499             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 500                 goto out;
 501
 502         /* Blocked by MNG FW so bail */
 503         if (ixgbe_check_reset_blocked(hw))
 504                 goto out;
 505
 506         /*
 507          * Perform soft PHY reset to the PHY_XS.
 508          * This will cause a soft reset to the PHY
 509          */
 510         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 511                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 512                               IXGBE_MDIO_PHY_XS_RESET);
 513
 514         /*
 515          * Poll for reset bit to self-clear indicating reset is complete.
 516          * Some PHYs could take up to 3 seconds to complete and need about
 517          * 1.7 usec delay after the reset is complete.
 518          */
 519         for (i = 0; i < 30; i++) {
 520                 msec_delay(100);
 521                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 522                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
 523                 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 524                         usec_delay(2);
 525                         break;
 526                 }
 527         }
 528
 529         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 530                 status = IXGBE_ERR_RESET_FAILED;
 531                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 532                              "PHY reset polling failed to complete.\n");
 533         }
 534
 535 out:
 536         return status;
 537 }
 538
 539 /**
 540  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 541  *  the SWFW lock
 542  *  @hw: pointer to hardware structure
 543  *  @reg_addr: 32 bit address of PHY register to read
 544  *  @phy_data: Pointer to read data from PHY register
 545  **/
 546 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 547                        u16 *phy_data)
 548 {
 549         u32 i, data, command;
 550
 551         /* Setup and write the address cycle command */
 552         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 553                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 554                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 555                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 556
 557         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 558
 559         /*
 560          * Check every 10 usec to see if the address cycle completed.
 561          * The MDI Command bit will clear when the operation is
 562          * complete
 563          */
 564         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 565                 usec_delay(10);
 566
 567                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 568                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 569                                 break;
 570         }
 571
 572
 573         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 574                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 575                 return IXGBE_ERR_PHY;
 576         }
 577
 578         /*
 579          * Address cycle complete, setup and write the read
 580          * command
 581          */
 582         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 583                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 584                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 585                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 586
 587         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 588
 589         /*
 590          * Check every 10 usec to see if the address cycle
 591          * completed. The MDI Command bit will clear when the
 592          * operation is complete
 593          */
 594         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 595                 usec_delay(10);
 596
 597                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 598                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 599                         break;
 600         }
 601
 602         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 603                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 604                 return IXGBE_ERR_PHY;
 605         }
 606
 607         /*
 608          * Read operation is complete.  Get the data
 609          * from MSRWD
 610          */
 611         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 612         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 613         *phy_data = (u16)(data);
 614
 615         return IXGBE_SUCCESS;
 616 }
 617
 618 /**
 619  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 620  *  using the SWFW lock - this function is needed in most cases
 621  *  @hw: pointer to hardware structure
 622  *  @reg_addr: 32 bit address of PHY register to read
 623  *  @phy_data: Pointer to read data from PHY register
 624  **/
 625 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 626                                u32 device_type, u16 *phy_data)
 627 {
 628         s32 status;
 629         u32 gssr = hw->phy.phy_semaphore_mask;
 630
 631         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 632
 633         if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
 634                 return IXGBE_ERR_SWFW_SYNC;
 635
 636         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
 637
 638         hw->mac.ops.release_swfw_sync(hw, gssr);
 639
 640         return status;
 641 }
 642
 643 /**
 644  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 645  *  without SWFW lock
 646  *  @hw: pointer to hardware structure
 647  *  @reg_addr: 32 bit PHY register to write
 648  *  @device_type: 5 bit device type
 649  *  @phy_data: Data to write to the PHY register
 650  **/
 651 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 652                                 u32 device_type, u16 phy_data)
 653 {
 654         u32 i, command;
 655
 656         /* Put the data in the MDI single read and write data register*/
 657         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 658
 659         /* Setup and write the address cycle command */
 660         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 661                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 662                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 663                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 664
 665         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 666
 667         /*
 668          * Check every 10 usec to see if the address cycle completed.
 669          * The MDI Command bit will clear when the operation is
 670          * complete
 671          */
 672         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 673                 usec_delay(10);
 674
 675                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 676                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 677                         break;
 678         }
 679
 680         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 681                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 682                 return IXGBE_ERR_PHY;
 683         }
 684
 685         /*
 686          * Address cycle complete, setup and write the write
 687          * command
 688          */
 689         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 690                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 691                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 692                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 693
 694         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 695
 696         /*
 697          * Check every 10 usec to see if the address cycle
 698          * completed. The MDI Command bit will clear when the
 699          * operation is complete
 700          */
 701         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 702                 usec_delay(10);
 703
 704                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 705                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 706                         break;
 707         }
 708
 709         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 710                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 711                 return IXGBE_ERR_PHY;
 712         }
 713
 714         return IXGBE_SUCCESS;
 715 }
 716
 717 /**
 718  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 719  *  using SWFW lock- this function is needed in most cases
 720  *  @hw: pointer to hardware structure
 721  *  @reg_addr: 32 bit PHY register to write
 722  *  @device_type: 5 bit device type
 723  *  @phy_data: Data to write to the PHY register
 724  **/
 725 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 726                                 u32 device_type, u16 phy_data)
 727 {
 728         s32 status;
 729         u32 gssr = hw->phy.phy_semaphore_mask;
 730
 731         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 732
 733         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 734                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
 735                                                  phy_data);
 736                 hw->mac.ops.release_swfw_sync(hw, gssr);
 737         } else {
 738                 status = IXGBE_ERR_SWFW_SYNC;
 739         }
 740
 741         return status;
 742 }
 743
 744 /**
 745  *  ixgbe_setup_phy_link_generic - Set and restart auto-neg
 746  *  @hw: pointer to hardware structure
 747  *
 748  *  Restart auto-negotiation and PHY and waits for completion.
 749  **/
 750 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 751 {
 752         s32 status = IXGBE_SUCCESS;
 753         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 754         bool autoneg = false;
 755         ixgbe_link_speed speed;
 756
 757         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 758
 759         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 760
 761         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 762                 /* Set or unset auto-negotiation 10G advertisement */
 763                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 764                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 765                                      &autoneg_reg);
 766
 767                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 768                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 769                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 770
 771                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 772                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 773                                       autoneg_reg);
 774         }
 775
 776         if (hw->mac.type == ixgbe_mac_X550) {
 777                 if (speed & IXGBE_LINK_SPEED_5GB_FULL) {
 778                         /* Set or unset auto-negotiation 5G advertisement */
 779                         hw->phy.ops.read_reg(hw,
 780                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 781                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 782                                 &autoneg_reg);
 783
 784                         autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
 785                         if (hw->phy.autoneg_advertised &
 786                              IXGBE_LINK_SPEED_5GB_FULL)
 787                                 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
 788
 789                         hw->phy.ops.write_reg(hw,
 790                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 791                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 792                                 autoneg_reg);
 793                 }
 794
 795                 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) {
 796                         /* Set or unset auto-negotiation 2.5G advertisement */
 797                         hw->phy.ops.read_reg(hw,
 798                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 799                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 800                                 &autoneg_reg);
 801
 802                         autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
 803                         if (hw->phy.autoneg_advertised &
 804                             IXGBE_LINK_SPEED_2_5GB_FULL)
 805                                 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
 806
 807                         hw->phy.ops.write_reg(hw,
 808                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 809                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 810                                 autoneg_reg);
 811                 }
 812         }
 813
 814         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 815                 /* Set or unset auto-negotiation 1G advertisement */
 816                 hw->phy.ops.read_reg(hw,
 817                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 818                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 819                                      &autoneg_reg);
 820
 821                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 822                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 823                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 824
 825                 hw->phy.ops.write_reg(hw,
 826                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 827                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 828                                       autoneg_reg);
 829         }
 830
 831         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 832                 /* Set or unset auto-negotiation 100M advertisement */
 833                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 834                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 835                                      &autoneg_reg);
 836
 837                 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 838                                  IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 839                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 840                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 841
 842                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 843                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 844                                       autoneg_reg);
 845         }
 846
 847         /* Blocked by MNG FW so don't reset PHY */
 848         if (ixgbe_check_reset_blocked(hw))
 849                 return status;
 850
 851         /* Restart PHY auto-negotiation. */
 852         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 853                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 854
 855         autoneg_reg |= IXGBE_MII_RESTART;
 856
 857         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 858                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 859
 860         return status;
 861 }
 862
 863 /**
 864  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 865  *  @hw: pointer to hardware structure
 866  *  @speed: new link speed
 867  **/
 868 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 869                                        ixgbe_link_speed speed,
 870                                        bool autoneg_wait_to_complete)
 871 {
 872         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 873
 874         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 875
 876         /*
 877          * Clear autoneg_advertised and set new values based on input link
 878          * speed.
 879          */
 880         hw->phy.autoneg_advertised = 0;
 881
 882         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 883                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 884
 885         if (speed & IXGBE_LINK_SPEED_5GB_FULL)
 886                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
 887
 888         if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
 889                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
 890
 891         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 892                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 893
 894         if (speed & IXGBE_LINK_SPEED_100_FULL)
 895                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 896
 897         /* Setup link based on the new speed settings */
 898         ixgbe_setup_phy_link(hw);
 899
 900         return IXGBE_SUCCESS;
 901 }
 902
 903 /**
 904  * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
 905  * @hw: pointer to hardware structure
 906  *
 907  * Determines the supported link capabilities by reading the PHY auto
 908  * negotiation register.
 909  **/
 910 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
 911 {
 912         s32 status;
 913         u16 speed_ability;
 914
 915         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 916                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 917                                       &speed_ability);
 918         if (status)
 919                 return status;
 920
 921         if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 922                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
 923         if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 924                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
 925         if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 926                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
 927
 928         switch (hw->mac.type) {
 929         case ixgbe_mac_X550:
 930                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
 931                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
 932                 break;
 933         case ixgbe_mac_X550EM_x:
 934                 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
 935                 break;
 936         default:
 937                 break;
 938         }
 939
 940         return status;
 941 }
 942
 943 /**
 944  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 945  *  @hw: pointer to hardware structure
 946  *  @speed: pointer to link speed
 947  *  @autoneg: boolean auto-negotiation value
 948  **/
 949 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 950                                                ixgbe_link_speed *speed,
 951                                                bool *autoneg)
 952 {
 953         s32 status = IXGBE_SUCCESS;
 954
 955         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 956
 957         *autoneg = true;
 958         if (!hw->phy.speeds_supported)
 959                 status = ixgbe_get_copper_speeds_supported(hw);
 960
 961         *speed = hw->phy.speeds_supported;
 962         return status;
 963 }
 964
 965 /**
 966  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 967  *  @hw: pointer to hardware structure
 968  *
 969  *  Reads the VS1 register to determine if link is up and the current speed for
 970  *  the PHY.
 971  **/
 972 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 973                              bool *link_up)
 974 {
 975         s32 status = IXGBE_SUCCESS;
 976         u32 time_out;
 977         u32 max_time_out = 10;
 978         u16 phy_link = 0;
 979         u16 phy_speed = 0;
 980         u16 phy_data = 0;
 981
 982         DEBUGFUNC("ixgbe_check_phy_link_tnx");
 983
 984         /* Initialize speed and link to default case */
 985         *link_up = false;
 986         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 987
 988         /*
 989          * Check current speed and link status of the PHY register.
 990          * This is a vendor specific register and may have to
 991          * be changed for other copper PHYs.
 992          */
 993         for (time_out = 0; time_out < max_time_out; time_out++) {
 994                 usec_delay(10);
 995                 status = hw->phy.ops.read_reg(hw,
 996                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
 997                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 998                                         &phy_data);
 999                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1000                 phy_speed = phy_data &
1001                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1002                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1003                         *link_up = true;
1004                         if (phy_speed ==
1005                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1006                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1007                         break;
1008                 }
1009         }
1010
1011         return status;
1012 }
1013
1014 /**
1015  *      ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1016  *      @hw: pointer to hardware structure
1017  *
1018  *      Restart auto-negotiation and PHY and waits for completion.
1019  **/
1020 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1021 {
1022         s32 status = IXGBE_SUCCESS;
1023         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1024         bool autoneg = false;
1025         ixgbe_link_speed speed;
1026
1027         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1028
1029         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1030
1031         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1032                 /* Set or unset auto-negotiation 10G advertisement */
1033                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1034                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1035                                      &autoneg_reg);
1036
1037                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1038                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1039                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1040
1041                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1042                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1043                                       autoneg_reg);
1044         }
1045
1046         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1047                 /* Set or unset auto-negotiation 1G advertisement */
1048                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1049                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1050                                      &autoneg_reg);
1051
1052                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1053                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1054                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1055
1056                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1057                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1058                                       autoneg_reg);
1059         }
1060
1061         if (speed & IXGBE_LINK_SPEED_100_FULL) {
1062                 /* Set or unset auto-negotiation 100M advertisement */
1063                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1064                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1065                                      &autoneg_reg);
1066
1067                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1068                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1069                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1070
1071                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1072                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1073                                       autoneg_reg);
1074         }
1075
1076         /* Blocked by MNG FW so don't reset PHY */
1077         if (ixgbe_check_reset_blocked(hw))
1078                 return status;
1079
1080         /* Restart PHY auto-negotiation. */
1081         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1082                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1083
1084         autoneg_reg |= IXGBE_MII_RESTART;
1085
1086         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1087                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1088
1089         return status;
1090 }
1091
1092 /**
1093  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1094  *  @hw: pointer to hardware structure
1095  *  @firmware_version: pointer to the PHY Firmware Version
1096  **/
1097 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1098                                        u16 *firmware_version)
1099 {
1100         s32 status;
1101
1102         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1103
1104         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1105                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1106                                       firmware_version);
1107
1108         return status;
1109 }
1110
1111 /**
1112  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1113  *  @hw: pointer to hardware structure
1114  *  @firmware_version: pointer to the PHY Firmware Version
1115  **/
1116 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1117                                            u16 *firmware_version)
1118 {
1119         s32 status;
1120
1121         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1122
1123         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1124                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1125                                       firmware_version);
1126
1127         return status;
1128 }
1129
1130 /**
1131  *  ixgbe_reset_phy_nl - Performs a PHY reset
1132  *  @hw: pointer to hardware structure
1133  **/
1134 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1135 {
1136         u16 phy_offset, control, eword, edata, block_crc;
1137         bool end_data = false;
1138         u16 list_offset, data_offset;
1139         u16 phy_data = 0;
1140         s32 ret_val = IXGBE_SUCCESS;
1141         u32 i;
1142
1143         DEBUGFUNC("ixgbe_reset_phy_nl");
1144
1145         /* Blocked by MNG FW so bail */
1146         if (ixgbe_check_reset_blocked(hw))
1147                 goto out;
1148
1149         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1150                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1151
1152         /* reset the PHY and poll for completion */
1153         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1154                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
1155                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1156
1157         for (i = 0; i < 100; i++) {
1158                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1159                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1160                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1161                         break;
1162                 msec_delay(10);
1163         }
1164
1165         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1166                 DEBUGOUT("PHY reset did not complete.\n");
1167                 ret_val = IXGBE_ERR_PHY;
1168                 goto out;
1169         }
1170
1171         /* Get init offsets */
1172         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1173                                                       &data_offset);
1174         if (ret_val != IXGBE_SUCCESS)
1175                 goto out;
1176
1177         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1178         data_offset++;
1179         while (!end_data) {
1180                 /*
1181                  * Read control word from PHY init contents offset
1182                  */
1183                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1184                 if (ret_val)
1185                         goto err_eeprom;
1186                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1187                            IXGBE_CONTROL_SHIFT_NL;
1188                 edata = eword & IXGBE_DATA_MASK_NL;
1189                 switch (control) {
1190                 case IXGBE_DELAY_NL:
1191                         data_offset++;
1192                         DEBUGOUT1("DELAY: %d MS\n", edata);
1193                         msec_delay(edata);
1194                         break;
1195                 case IXGBE_DATA_NL:
1196                         DEBUGOUT("DATA:\n");
1197                         data_offset++;
1198                         ret_val = hw->eeprom.ops.read(hw, data_offset,
1199                                                       &phy_offset);
1200                         if (ret_val)
1201                                 goto err_eeprom;
1202                         data_offset++;
1203                         for (i = 0; i < edata; i++) {
1204                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
1205                                                               &eword);
1206                                 if (ret_val)
1207                                         goto err_eeprom;
1208                                 hw->phy.ops.write_reg(hw, phy_offset,
1209                                                       IXGBE_TWINAX_DEV, eword);
1210                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1211                                           phy_offset);
1212                                 data_offset++;
1213                                 phy_offset++;
1214                         }
1215                         break;
1216                 case IXGBE_CONTROL_NL:
1217                         data_offset++;
1218                         DEBUGOUT("CONTROL:\n");
1219                         if (edata == IXGBE_CONTROL_EOL_NL) {
1220                                 DEBUGOUT("EOL\n");
1221                                 end_data = true;
1222                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
1223                                 DEBUGOUT("SOL\n");
1224                         } else {
1225                                 DEBUGOUT("Bad control value\n");
1226                                 ret_val = IXGBE_ERR_PHY;
1227                                 goto out;
1228                         }
1229                         break;
1230                 default:
1231                         DEBUGOUT("Bad control type\n");
1232                         ret_val = IXGBE_ERR_PHY;
1233                         goto out;
1234                 }
1235         }
1236
1237 out:
1238         return ret_val;
1239
1240 err_eeprom:
1241         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1242                       "eeprom read at offset %d failed", data_offset);
1243         return IXGBE_ERR_PHY;
1244 }
1245
1246 /**
1247  *  ixgbe_identify_module_generic - Identifies module type
1248  *  @hw: pointer to hardware structure
1249  *
1250  *  Determines HW type and calls appropriate function.
1251  **/
1252 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1253 {
1254         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1255
1256         DEBUGFUNC("ixgbe_identify_module_generic");
1257
1258         switch (hw->mac.ops.get_media_type(hw)) {
1259         case ixgbe_media_type_fiber:
1260                 status = ixgbe_identify_sfp_module_generic(hw);
1261                 break;
1262
1263         case ixgbe_media_type_fiber_qsfp:
1264                 status = ixgbe_identify_qsfp_module_generic(hw);
1265                 break;
1266
1267         default:
1268                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1269                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1270                 break;
1271         }
1272
1273         return status;
1274 }
1275
1276 /**
1277  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1278  *  @hw: pointer to hardware structure
1279  *
1280  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1281  **/
1282 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1283 {
1284         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1285         u32 vendor_oui = 0;
1286         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1287         u8 identifier = 0;
1288         u8 comp_codes_1g = 0;
1289         u8 comp_codes_10g = 0;
1290         u8 oui_bytes[3] = {0, 0, 0};
1291         u8 cable_tech = 0;
1292         u8 cable_spec = 0;
1293         u16 enforce_sfp = 0;
1294
1295         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1296
1297         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1298                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1299                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1300                 goto out;
1301         }
1302
1303         /* LAN ID is needed for I2C access */
1304         hw->mac.ops.set_lan_id(hw);
1305
1306         status = hw->phy.ops.read_i2c_eeprom(hw,
1307                                              IXGBE_SFF_IDENTIFIER,
1308                                              &identifier);
1309
1310         if (status != IXGBE_SUCCESS)
1311                 goto err_read_i2c_eeprom;
1312
1313         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1314                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1315                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1316         } else {
1317                 status = hw->phy.ops.read_i2c_eeprom(hw,
1318                                                      IXGBE_SFF_1GBE_COMP_CODES,
1319                                                      &comp_codes_1g);
1320
1321                 if (status != IXGBE_SUCCESS)
1322                         goto err_read_i2c_eeprom;
1323
1324                 status = hw->phy.ops.read_i2c_eeprom(hw,
1325                                                      IXGBE_SFF_10GBE_COMP_CODES,
1326                                                      &comp_codes_10g);
1327
1328                 if (status != IXGBE_SUCCESS)
1329                         goto err_read_i2c_eeprom;
1330                 status = hw->phy.ops.read_i2c_eeprom(hw,
1331                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1332                                                      &cable_tech);
1333
1334                 if (status != IXGBE_SUCCESS)
1335                         goto err_read_i2c_eeprom;
1336
1337                  /* ID Module
1338                   * =========
1339                   * 0   SFP_DA_CU
1340                   * 1   SFP_SR
1341                   * 2   SFP_LR
1342                   * 3   SFP_DA_CORE0 - 82599-specific
1343                   * 4   SFP_DA_CORE1 - 82599-specific
1344                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1345                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1346                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1347                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1348                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1349                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1350                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1351                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1352                   */
1353                 if (hw->mac.type == ixgbe_mac_82598EB) {
1354                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1355                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1356                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1357                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1358                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1359                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1360                         else
1361                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1362                 } else {
1363                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1364                                 if (hw->bus.lan_id == 0)
1365                                         hw->phy.sfp_type =
1366                                                      ixgbe_sfp_type_da_cu_core0;
1367                                 else
1368                                         hw->phy.sfp_type =
1369                                                      ixgbe_sfp_type_da_cu_core1;
1370                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1371                                 hw->phy.ops.read_i2c_eeprom(
1372                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1373                                                 &cable_spec);
1374                                 if (cable_spec &
1375                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1376                                         if (hw->bus.lan_id == 0)
1377                                                 hw->phy.sfp_type =
1378                                                 ixgbe_sfp_type_da_act_lmt_core0;
1379                                         else
1380                                                 hw->phy.sfp_type =
1381                                                 ixgbe_sfp_type_da_act_lmt_core1;
1382                                 } else {
1383                                         hw->phy.sfp_type =
1384                                                         ixgbe_sfp_type_unknown;
1385                                 }
1386                         } else if (comp_codes_10g &
1387                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1388                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1389                                 if (hw->bus.lan_id == 0)
1390                                         hw->phy.sfp_type =
1391                                                       ixgbe_sfp_type_srlr_core0;
1392                                 else
1393                                         hw->phy.sfp_type =
1394                                                       ixgbe_sfp_type_srlr_core1;
1395                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1396                                 if (hw->bus.lan_id == 0)
1397                                         hw->phy.sfp_type =
1398                                                 ixgbe_sfp_type_1g_cu_core0;
1399                                 else
1400                                         hw->phy.sfp_type =
1401                                                 ixgbe_sfp_type_1g_cu_core1;
1402                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1403                                 if (hw->bus.lan_id == 0)
1404                                         hw->phy.sfp_type =
1405                                                 ixgbe_sfp_type_1g_sx_core0;
1406                                 else
1407                                         hw->phy.sfp_type =
1408                                                 ixgbe_sfp_type_1g_sx_core1;
1409                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1410                                 if (hw->bus.lan_id == 0)
1411                                         hw->phy.sfp_type =
1412                                                 ixgbe_sfp_type_1g_lx_core0;
1413                                 else
1414                                         hw->phy.sfp_type =
1415                                                 ixgbe_sfp_type_1g_lx_core1;
1416                         } else {
1417                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1418                         }
1419                 }
1420
1421                 if (hw->phy.sfp_type != stored_sfp_type)
1422                         hw->phy.sfp_setup_needed = true;
1423
1424                 /* Determine if the SFP+ PHY is dual speed or not. */
1425                 hw->phy.multispeed_fiber = false;
1426                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1427                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1428                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1429                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1430                         hw->phy.multispeed_fiber = true;
1431
1432                 /* Determine PHY vendor */
1433                 if (hw->phy.type != ixgbe_phy_nl) {
1434                         hw->phy.id = identifier;
1435                         status = hw->phy.ops.read_i2c_eeprom(hw,
1436                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1437                                                     &oui_bytes[0]);
1438
1439                         if (status != IXGBE_SUCCESS)
1440                                 goto err_read_i2c_eeprom;
1441
1442                         status = hw->phy.ops.read_i2c_eeprom(hw,
1443                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1444                                                     &oui_bytes[1]);
1445
1446                         if (status != IXGBE_SUCCESS)
1447                                 goto err_read_i2c_eeprom;
1448
1449                         status = hw->phy.ops.read_i2c_eeprom(hw,
1450                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1451                                                     &oui_bytes[2]);
1452
1453                         if (status != IXGBE_SUCCESS)
1454                                 goto err_read_i2c_eeprom;
1455
1456                         vendor_oui =
1457                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1458                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1459                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1460
1461                         switch (vendor_oui) {
1462                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1463                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1464                                         hw->phy.type =
1465                                                     ixgbe_phy_sfp_passive_tyco;
1466                                 break;
1467                         case IXGBE_SFF_VENDOR_OUI_FTL:
1468                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1469                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1470                                 else
1471                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1472                                 break;
1473                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1474                                 hw->phy.type = ixgbe_phy_sfp_avago;
1475                                 break;
1476                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1477                                 hw->phy.type = ixgbe_phy_sfp_intel;
1478                                 break;
1479                         default:
1480                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1481                                         hw->phy.type =
1482                                                  ixgbe_phy_sfp_passive_unknown;
1483                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1484                                         hw->phy.type =
1485                                                 ixgbe_phy_sfp_active_unknown;
1486                                 else
1487                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1488                                 break;
1489                         }
1490                 }
1491
1492                 /* Allow any DA cable vendor */
1493                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1494                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1495                         status = IXGBE_SUCCESS;
1496                         goto out;
1497                 }
1498
1499                 /* Verify supported 1G SFP modules */
1500                 if (comp_codes_10g == 0 &&
1501                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1502                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1503                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1504                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1505                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1506                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1507                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1508                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1509                         goto out;
1510                 }
1511
1512                 /* Anything else 82598-based is supported */
1513                 if (hw->mac.type == ixgbe_mac_82598EB) {
1514                         status = IXGBE_SUCCESS;
1515                         goto out;
1516                 }
1517
1518                 ixgbe_get_device_caps(hw, &enforce_sfp);
1519                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1520                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1521                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1522                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1523                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1524                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1525                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1526                         /* Make sure we're a supported PHY type */
1527                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1528                                 status = IXGBE_SUCCESS;
1529                         } else {
1530                                 if (hw->allow_unsupported_sfp == true) {
1531                                         EWARN(hw, "WARNING: Intel (R) Network "
1532                                               "Connections are quality tested "
1533                                               "using Intel (R) Ethernet Optics."
1534                                               " Using untested modules is not "
1535                                               "supported and may cause unstable"
1536                                               " operation or damage to the "
1537                                               "module or the adapter. Intel "
1538                                               "Corporation is not responsible "
1539                                               "for any harm caused by using "
1540                                               "untested modules.\n", status);
1541                                         status = IXGBE_SUCCESS;
1542                                 } else {
1543                                         DEBUGOUT("SFP+ module not supported\n");
1544                                         hw->phy.type =
1545                                                 ixgbe_phy_sfp_unsupported;
1546                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1547                                 }
1548                         }
1549                 } else {
1550                         status = IXGBE_SUCCESS;
1551                 }
1552         }
1553
1554 out:
1555         return status;
1556
1557 err_read_i2c_eeprom:
1558         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1559         if (hw->phy.type != ixgbe_phy_nl) {
1560                 hw->phy.id = 0;
1561                 hw->phy.type = ixgbe_phy_unknown;
1562         }
1563         return IXGBE_ERR_SFP_NOT_PRESENT;
1564 }
1565
1566 /**
1567  *  ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1568  *  @hw: pointer to hardware structure
1569  *
1570  *  Determines physical layer capabilities of the current SFP.
1571  */
1572 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1573 {
1574         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1575         u8 comp_codes_10g = 0;
1576         u8 comp_codes_1g = 0;
1577
1578         DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1579
1580         hw->phy.ops.identify_sfp(hw);
1581         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1582                 return physical_layer;
1583
1584         switch (hw->phy.type) {
1585         case ixgbe_phy_sfp_passive_tyco:
1586         case ixgbe_phy_sfp_passive_unknown:
1587         case ixgbe_phy_qsfp_passive_unknown:
1588                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1589                 break;
1590         case ixgbe_phy_sfp_ftl_active:
1591         case ixgbe_phy_sfp_active_unknown:
1592         case ixgbe_phy_qsfp_active_unknown:
1593                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1594                 break;
1595         case ixgbe_phy_sfp_avago:
1596         case ixgbe_phy_sfp_ftl:
1597         case ixgbe_phy_sfp_intel:
1598         case ixgbe_phy_sfp_unknown:
1599                 hw->phy.ops.read_i2c_eeprom(hw,
1600                       IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1601                 hw->phy.ops.read_i2c_eeprom(hw,
1602                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1603                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1604                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1605                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1606                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1607                 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1608                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1609                 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1610                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1611                 break;
1612         case ixgbe_phy_qsfp_intel:
1613         case ixgbe_phy_qsfp_unknown:
1614                 hw->phy.ops.read_i2c_eeprom(hw,
1615                       IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1616                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1617                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1618                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1619                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1620                 break;
1621         default:
1622                 break;
1623         }
1624
1625         return physical_layer;
1626 }
1627
1628 /**
1629  *  ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1630  *  @hw: pointer to hardware structure
1631  *
1632  *  Searches for and identifies the QSFP module and assigns appropriate PHY type
1633  **/
1634 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1635 {
1636         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1637         u32 vendor_oui = 0;
1638         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1639         u8 identifier = 0;
1640         u8 comp_codes_1g = 0;
1641         u8 comp_codes_10g = 0;
1642         u8 oui_bytes[3] = {0, 0, 0};
1643         u16 enforce_sfp = 0;
1644         u8 connector = 0;
1645         u8 cable_length = 0;
1646         u8 device_tech = 0;
1647         bool active_cable = false;
1648
1649         DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1650
1651         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1652                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1653                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1654                 goto out;
1655         }
1656
1657         /* LAN ID is needed for I2C access */
1658         hw->mac.ops.set_lan_id(hw);
1659
1660         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1661                                              &identifier);
1662
1663         if (status != IXGBE_SUCCESS)
1664                 goto err_read_i2c_eeprom;
1665
1666         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1667                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1668                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1669                 goto out;
1670         }
1671
1672         hw->phy.id = identifier;
1673
1674         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1675                                              &comp_codes_10g);
1676
1677         if (status != IXGBE_SUCCESS)
1678                 goto err_read_i2c_eeprom;
1679
1680         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1681                                              &comp_codes_1g);
1682
1683         if (status != IXGBE_SUCCESS)
1684                 goto err_read_i2c_eeprom;
1685
1686         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1687                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1688                 if (hw->bus.lan_id == 0)
1689                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1690                 else
1691                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1692         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1693                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1694                 if (hw->bus.lan_id == 0)
1695                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1696                 else
1697                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1698         } else {
1699                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1700                         active_cable = true;
1701
1702                 if (!active_cable) {
1703                         /* check for active DA cables that pre-date
1704                          * SFF-8436 v3.6 */
1705                         hw->phy.ops.read_i2c_eeprom(hw,
1706                                         IXGBE_SFF_QSFP_CONNECTOR,
1707                                         &connector);
1708
1709                         hw->phy.ops.read_i2c_eeprom(hw,
1710                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1711                                         &cable_length);
1712
1713                         hw->phy.ops.read_i2c_eeprom(hw,
1714                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1715                                         &device_tech);
1716
1717                         if ((connector ==
1718                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1719                             (cable_length > 0) &&
1720                             ((device_tech >> 4) ==
1721                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1722                                 active_cable = true;
1723                 }
1724
1725                 if (active_cable) {
1726                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1727                         if (hw->bus.lan_id == 0)
1728                                 hw->phy.sfp_type =
1729                                                 ixgbe_sfp_type_da_act_lmt_core0;
1730                         else
1731                                 hw->phy.sfp_type =
1732                                                 ixgbe_sfp_type_da_act_lmt_core1;
1733                 } else {
1734                         /* unsupported module type */
1735                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1736                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1737                         goto out;
1738                 }
1739         }
1740
1741         if (hw->phy.sfp_type != stored_sfp_type)
1742                 hw->phy.sfp_setup_needed = true;
1743
1744         /* Determine if the QSFP+ PHY is dual speed or not. */
1745         hw->phy.multispeed_fiber = false;
1746         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1747            (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1748            ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1749            (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1750                 hw->phy.multispeed_fiber = true;
1751
1752         /* Determine PHY vendor for optical modules */
1753         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1754                               IXGBE_SFF_10GBASELR_CAPABLE))  {
1755                 status = hw->phy.ops.read_i2c_eeprom(hw,
1756                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1757                                             &oui_bytes[0]);
1758
1759                 if (status != IXGBE_SUCCESS)
1760                         goto err_read_i2c_eeprom;
1761
1762                 status = hw->phy.ops.read_i2c_eeprom(hw,
1763                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1764                                             &oui_bytes[1]);
1765
1766                 if (status != IXGBE_SUCCESS)
1767                         goto err_read_i2c_eeprom;
1768
1769                 status = hw->phy.ops.read_i2c_eeprom(hw,
1770                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1771                                             &oui_bytes[2]);
1772
1773                 if (status != IXGBE_SUCCESS)
1774                         goto err_read_i2c_eeprom;
1775
1776                 vendor_oui =
1777                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1778                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1779                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1780
1781                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1782                         hw->phy.type = ixgbe_phy_qsfp_intel;
1783                 else
1784                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1785
1786                 ixgbe_get_device_caps(hw, &enforce_sfp);
1787                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1788                         /* Make sure we're a supported PHY type */
1789                         if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1790                                 status = IXGBE_SUCCESS;
1791                         } else {
1792                                 if (hw->allow_unsupported_sfp == true) {
1793                                         EWARN(hw, "WARNING: Intel (R) Network "
1794                                               "Connections are quality tested "
1795                                               "using Intel (R) Ethernet Optics."
1796                                               " Using untested modules is not "
1797                                               "supported and may cause unstable"
1798                                               " operation or damage to the "
1799                                               "module or the adapter. Intel "
1800                                               "Corporation is not responsible "
1801                                               "for any harm caused by using "
1802                                               "untested modules.\n", status);
1803                                         status = IXGBE_SUCCESS;
1804                                 } else {
1805                                         DEBUGOUT("QSFP module not supported\n");
1806                                         hw->phy.type =
1807                                                 ixgbe_phy_sfp_unsupported;
1808                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1809                                 }
1810                         }
1811                 } else {
1812                         status = IXGBE_SUCCESS;
1813                 }
1814         }
1815
1816 out:
1817         return status;
1818
1819 err_read_i2c_eeprom:
1820         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1821         hw->phy.id = 0;
1822         hw->phy.type = ixgbe_phy_unknown;
1823
1824         return IXGBE_ERR_SFP_NOT_PRESENT;
1825 }
1826
1827
1828 /**
1829  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1830  *  @hw: pointer to hardware structure
1831  *  @list_offset: offset to the SFP ID list
1832  *  @data_offset: offset to the SFP data block
1833  *
1834  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1835  *  so it returns the offsets to the phy init sequence block.
1836  **/
1837 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1838                                         u16 *list_offset,
1839                                         u16 *data_offset)
1840 {
1841         u16 sfp_id;
1842         u16 sfp_type = hw->phy.sfp_type;
1843
1844         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1845
1846         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1847                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1848
1849         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1850                 return IXGBE_ERR_SFP_NOT_PRESENT;
1851
1852         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1853             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1854                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1855
1856         /*
1857          * Limiting active cables and 1G Phys must be initialized as
1858          * SR modules
1859          */
1860         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1861             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1862             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1863             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1864                 sfp_type = ixgbe_sfp_type_srlr_core0;
1865         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1866                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1867                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1868                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1869                 sfp_type = ixgbe_sfp_type_srlr_core1;
1870
1871         /* Read offset to PHY init contents */
1872         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1873                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1874                               "eeprom read at offset %d failed",
1875                               IXGBE_PHY_INIT_OFFSET_NL);
1876                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1877         }
1878
1879         if ((!*list_offset) || (*list_offset == 0xFFFF))
1880                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1881
1882         /* Shift offset to first ID word */
1883         (*list_offset)++;
1884
1885         /*
1886          * Find the matching SFP ID in the EEPROM
1887          * and program the init sequence
1888          */
1889         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1890                 goto err_phy;
1891
1892         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1893                 if (sfp_id == sfp_type) {
1894                         (*list_offset)++;
1895                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1896                                 goto err_phy;
1897                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1898                                 DEBUGOUT("SFP+ module not supported\n");
1899                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1900                         } else {
1901                                 break;
1902                         }
1903                 } else {
1904                         (*list_offset) += 2;
1905                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1906                                 goto err_phy;
1907                 }
1908         }
1909
1910         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1911                 DEBUGOUT("No matching SFP+ module found\n");
1912                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1913         }
1914
1915         return IXGBE_SUCCESS;
1916
1917 err_phy:
1918         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1919                       "eeprom read at offset %d failed", *list_offset);
1920         return IXGBE_ERR_PHY;
1921 }
1922
1923 /**
1924  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1925  *  @hw: pointer to hardware structure
1926  *  @byte_offset: EEPROM byte offset to read
1927  *  @eeprom_data: value read
1928  *
1929  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1930  **/
1931 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1932                                   u8 *eeprom_data)
1933 {
1934         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1935
1936         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1937                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1938                                          eeprom_data);
1939 }
1940
1941 /**
1942  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1943  *  @hw: pointer to hardware structure
1944  *  @byte_offset: byte offset at address 0xA2
1945  *  @eeprom_data: value read
1946  *
1947  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1948  **/
1949 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1950                                           u8 *sff8472_data)
1951 {
1952         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1953                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1954                                          sff8472_data);
1955 }
1956
1957 /**
1958  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1959  *  @hw: pointer to hardware structure
1960  *  @byte_offset: EEPROM byte offset to write
1961  *  @eeprom_data: value to write
1962  *
1963  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1964  **/
1965 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1966                                    u8 eeprom_data)
1967 {
1968         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1969
1970         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1971                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1972                                           eeprom_data);
1973 }
1974
1975 /**
1976  * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1977  * @hw: pointer to hardware structure
1978  * @offset: eeprom offset to be read
1979  * @addr: I2C address to be read
1980  */
1981 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1982 {
1983         if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1984             offset == IXGBE_SFF_IDENTIFIER &&
1985             hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1986                 return true;
1987         return false;
1988 }
1989
1990 /**
1991  *  ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1992  *  @hw: pointer to hardware structure
1993  *  @byte_offset: byte offset to read
1994  *  @data: value read
1995  *  @lock: true if to take and release semaphore
1996  *
1997  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1998  *  a specified device address.
1999  **/
2000 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2001                                            u8 dev_addr, u8 *data, bool lock)
2002 {
2003         s32 status;
2004         u32 max_retry = 10;
2005         u32 retry = 0;
2006         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2007         bool nack = 1;
2008         *data = 0;
2009
2010         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2011
2012         if (hw->mac.type >= ixgbe_mac_X550)
2013                 max_retry = 3;
2014         if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2015                 max_retry = IXGBE_SFP_DETECT_RETRIES;
2016
2017         do {
2018                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2019                         return IXGBE_ERR_SWFW_SYNC;
2020
2021                 ixgbe_i2c_start(hw);
2022
2023                 /* Device Address and write indication */
2024                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2025                 if (status != IXGBE_SUCCESS)
2026                         goto fail;
2027
2028                 status = ixgbe_get_i2c_ack(hw);
2029                 if (status != IXGBE_SUCCESS)
2030                         goto fail;
2031
2032                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2033                 if (status != IXGBE_SUCCESS)
2034                         goto fail;
2035
2036                 status = ixgbe_get_i2c_ack(hw);
2037                 if (status != IXGBE_SUCCESS)
2038                         goto fail;
2039
2040                 ixgbe_i2c_start(hw);
2041
2042                 /* Device Address and read indication */
2043                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2044                 if (status != IXGBE_SUCCESS)
2045                         goto fail;
2046
2047                 status = ixgbe_get_i2c_ack(hw);
2048                 if (status != IXGBE_SUCCESS)
2049                         goto fail;
2050
2051                 status = ixgbe_clock_in_i2c_byte(hw, data);
2052                 if (status != IXGBE_SUCCESS)
2053                         goto fail;
2054
2055                 status = ixgbe_clock_out_i2c_bit(hw, nack);
2056                 if (status != IXGBE_SUCCESS)
2057                         goto fail;
2058
2059                 ixgbe_i2c_stop(hw);
2060                 if (lock)
2061                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2062                 return IXGBE_SUCCESS;
2063
2064 fail:
2065                 ixgbe_i2c_bus_clear(hw);
2066                 if (lock) {
2067                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2068                         msec_delay(100);
2069                 }
2070                 retry++;
2071                 if (retry < max_retry)
2072                         DEBUGOUT("I2C byte read error - Retrying.\n");
2073                 else
2074                         DEBUGOUT("I2C byte read error.\n");
2075
2076         } while (retry < max_retry);
2077
2078         return status;
2079 }
2080
2081 /**
2082  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2083  *  @hw: pointer to hardware structure
2084  *  @byte_offset: byte offset to read
2085  *  @data: value read
2086  *
2087  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2088  *  a specified device address.
2089  **/
2090 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2091                                 u8 dev_addr, u8 *data)
2092 {
2093         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2094                                                data, true);
2095 }
2096
2097 /**
2098  *  ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2099  *  @hw: pointer to hardware structure
2100  *  @byte_offset: byte offset to read
2101  *  @data: value read
2102  *
2103  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2104  *  a specified device address.
2105  **/
2106 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2107                                          u8 dev_addr, u8 *data)
2108 {
2109         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2110                                                data, false);
2111 }
2112
2113 /**
2114  *  ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2115  *  @hw: pointer to hardware structure
2116  *  @byte_offset: byte offset to write
2117  *  @data: value to write
2118  *  @lock: true if to take and release semaphore
2119  *
2120  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2121  *  a specified device address.
2122  **/
2123 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2124                                             u8 dev_addr, u8 data, bool lock)
2125 {
2126         s32 status;
2127         u32 max_retry = 1;
2128         u32 retry = 0;
2129         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2130
2131         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2132
2133         if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2134             IXGBE_SUCCESS)
2135                 return IXGBE_ERR_SWFW_SYNC;
2136
2137         do {
2138                 ixgbe_i2c_start(hw);
2139
2140                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2141                 if (status != IXGBE_SUCCESS)
2142                         goto fail;
2143
2144                 status = ixgbe_get_i2c_ack(hw);
2145                 if (status != IXGBE_SUCCESS)
2146                         goto fail;
2147
2148                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2149                 if (status != IXGBE_SUCCESS)
2150                         goto fail;
2151
2152                 status = ixgbe_get_i2c_ack(hw);
2153                 if (status != IXGBE_SUCCESS)
2154                         goto fail;
2155
2156                 status = ixgbe_clock_out_i2c_byte(hw, data);
2157                 if (status != IXGBE_SUCCESS)
2158                         goto fail;
2159
2160                 status = ixgbe_get_i2c_ack(hw);
2161                 if (status != IXGBE_SUCCESS)
2162                         goto fail;
2163
2164                 ixgbe_i2c_stop(hw);
2165                 if (lock)
2166                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2167                 return IXGBE_SUCCESS;
2168
2169 fail:
2170                 ixgbe_i2c_bus_clear(hw);
2171                 retry++;
2172                 if (retry < max_retry)
2173                         DEBUGOUT("I2C byte write error - Retrying.\n");
2174                 else
2175                         DEBUGOUT("I2C byte write error.\n");
2176         } while (retry < max_retry);
2177
2178         if (lock)
2179                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2180
2181         return status;
2182 }
2183
2184 /**
2185  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2186  *  @hw: pointer to hardware structure
2187  *  @byte_offset: byte offset to write
2188  *  @data: value to write
2189  *
2190  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2191  *  a specified device address.
2192  **/
2193 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2194                                  u8 dev_addr, u8 data)
2195 {
2196         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2197                                                 data, true);
2198 }
2199
2200 /**
2201  *  ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2202  *  @hw: pointer to hardware structure
2203  *  @byte_offset: byte offset to write
2204  *  @data: value to write
2205  *
2206  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2207  *  a specified device address.
2208  **/
2209 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2210                                           u8 dev_addr, u8 data)
2211 {
2212         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2213                                                 data, false);
2214 }
2215
2216 /**
2217  *  ixgbe_i2c_start - Sets I2C start condition
2218  *  @hw: pointer to hardware structure
2219  *
2220  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
2221  *  Set bit-bang mode on X550 hardware.
2222  **/
2223 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2224 {
2225         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2226
2227         DEBUGFUNC("ixgbe_i2c_start");
2228
2229         i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2230
2231         /* Start condition must begin with data and clock high */
2232         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2233         ixgbe_raise_i2c_clk(hw, &i2cctl);
2234
2235         /* Setup time for start condition (4.7us) */
2236         usec_delay(IXGBE_I2C_T_SU_STA);
2237
2238         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2239
2240         /* Hold time for start condition (4us) */
2241         usec_delay(IXGBE_I2C_T_HD_STA);
2242
2243         ixgbe_lower_i2c_clk(hw, &i2cctl);
2244
2245         /* Minimum low period of clock is 4.7 us */
2246         usec_delay(IXGBE_I2C_T_LOW);
2247
2248 }
2249
2250 /**
2251  *  ixgbe_i2c_stop - Sets I2C stop condition
2252  *  @hw: pointer to hardware structure
2253  *
2254  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
2255  *  Disables bit-bang mode and negates data output enable on X550
2256  *  hardware.
2257  **/
2258 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2259 {
2260         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2261         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2262         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2263         u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2264
2265         DEBUGFUNC("ixgbe_i2c_stop");
2266
2267         /* Stop condition must begin with data low and clock high */
2268         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2269         ixgbe_raise_i2c_clk(hw, &i2cctl);
2270
2271         /* Setup time for stop condition (4us) */
2272         usec_delay(IXGBE_I2C_T_SU_STO);
2273
2274         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2275
2276         /* bus free time between stop and start (4.7us)*/
2277         usec_delay(IXGBE_I2C_T_BUF);
2278
2279         if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2280                 i2cctl &= ~bb_en_bit;
2281                 i2cctl |= data_oe_bit | clk_oe_bit;
2282                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2283                 IXGBE_WRITE_FLUSH(hw);
2284         }
2285 }
2286
2287 /**
2288  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2289  *  @hw: pointer to hardware structure
2290  *  @data: data byte to clock in
2291  *
2292  *  Clocks in one byte data via I2C data/clock
2293  **/
2294 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2295 {
2296         s32 i;
2297         bool bit = 0;
2298
2299         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2300
2301         *data = 0;
2302         for (i = 7; i >= 0; i--) {
2303                 ixgbe_clock_in_i2c_bit(hw, &bit);
2304                 *data |= bit << i;
2305         }
2306
2307         return IXGBE_SUCCESS;
2308 }
2309
2310 /**
2311  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2312  *  @hw: pointer to hardware structure
2313  *  @data: data byte clocked out
2314  *
2315  *  Clocks out one byte data via I2C data/clock
2316  **/
2317 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2318 {
2319         s32 status = IXGBE_SUCCESS;
2320         s32 i;
2321         u32 i2cctl;
2322         bool bit;
2323
2324         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2325
2326         for (i = 7; i >= 0; i--) {
2327                 bit = (data >> i) & 0x1;
2328                 status = ixgbe_clock_out_i2c_bit(hw, bit);
2329
2330                 if (status != IXGBE_SUCCESS)
2331                         break;
2332         }
2333
2334         /* Release SDA line (set high) */
2335         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2336         i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2337         i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2338         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2339         IXGBE_WRITE_FLUSH(hw);
2340
2341         return status;
2342 }
2343
2344 /**
2345  *  ixgbe_get_i2c_ack - Polls for I2C ACK
2346  *  @hw: pointer to hardware structure
2347  *
2348  *  Clocks in/out one bit via I2C data/clock
2349  **/
2350 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2351 {
2352         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2353         s32 status = IXGBE_SUCCESS;
2354         u32 i = 0;
2355         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2356         u32 timeout = 10;
2357         bool ack = 1;
2358
2359         DEBUGFUNC("ixgbe_get_i2c_ack");
2360
2361         if (data_oe_bit) {
2362                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2363                 i2cctl |= data_oe_bit;
2364                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2365                 IXGBE_WRITE_FLUSH(hw);
2366         }
2367         ixgbe_raise_i2c_clk(hw, &i2cctl);
2368
2369         /* Minimum high period of clock is 4us */
2370         usec_delay(IXGBE_I2C_T_HIGH);
2371
2372         /* Poll for ACK.  Note that ACK in I2C spec is
2373          * transition from 1 to 0 */
2374         for (i = 0; i < timeout; i++) {
2375                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2376                 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2377
2378                 usec_delay(1);
2379                 if (!ack)
2380                         break;
2381         }
2382
2383         if (ack) {
2384                 DEBUGOUT("I2C ack was not received.\n");
2385                 status = IXGBE_ERR_I2C;
2386         }
2387
2388         ixgbe_lower_i2c_clk(hw, &i2cctl);
2389
2390         /* Minimum low period of clock is 4.7 us */
2391         usec_delay(IXGBE_I2C_T_LOW);
2392
2393         return status;
2394 }
2395
2396 /**
2397  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2398  *  @hw: pointer to hardware structure
2399  *  @data: read data value
2400  *
2401  *  Clocks in one bit via I2C data/clock
2402  **/
2403 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2404 {
2405         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2406         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2407
2408         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2409
2410         if (data_oe_bit) {
2411                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2412                 i2cctl |= data_oe_bit;
2413                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2414                 IXGBE_WRITE_FLUSH(hw);
2415         }
2416         ixgbe_raise_i2c_clk(hw, &i2cctl);
2417
2418         /* Minimum high period of clock is 4us */
2419         usec_delay(IXGBE_I2C_T_HIGH);
2420
2421         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2422         *data = ixgbe_get_i2c_data(hw, &i2cctl);
2423
2424         ixgbe_lower_i2c_clk(hw, &i2cctl);
2425
2426         /* Minimum low period of clock is 4.7 us */
2427         usec_delay(IXGBE_I2C_T_LOW);
2428
2429         return IXGBE_SUCCESS;
2430 }
2431
2432 /**
2433  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2434  *  @hw: pointer to hardware structure
2435  *  @data: data value to write
2436  *
2437  *  Clocks out one bit via I2C data/clock
2438  **/
2439 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2440 {
2441         s32 status;
2442         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2443
2444         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2445
2446         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2447         if (status == IXGBE_SUCCESS) {
2448                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2449
2450                 /* Minimum high period of clock is 4us */
2451                 usec_delay(IXGBE_I2C_T_HIGH);
2452
2453                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2454
2455                 /* Minimum low period of clock is 4.7 us.
2456                  * This also takes care of the data hold time.
2457                  */
2458                 usec_delay(IXGBE_I2C_T_LOW);
2459         } else {
2460                 status = IXGBE_ERR_I2C;
2461                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2462                              "I2C data was not set to %X\n", data);
2463         }
2464
2465         return status;
2466 }
2467
2468 /**
2469  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2470  *  @hw: pointer to hardware structure
2471  *  @i2cctl: Current value of I2CCTL register
2472  *
2473  *  Raises the I2C clock line '0'->'1'
2474  *  Negates the I2C clock output enable on X550 hardware.
2475  **/
2476 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2477 {
2478         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2479         u32 i = 0;
2480         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2481         u32 i2cctl_r = 0;
2482
2483         DEBUGFUNC("ixgbe_raise_i2c_clk");
2484
2485         if (clk_oe_bit) {
2486                 *i2cctl |= clk_oe_bit;
2487                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2488         }
2489
2490         for (i = 0; i < timeout; i++) {
2491                 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2492
2493                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2494                 IXGBE_WRITE_FLUSH(hw);
2495                 /* SCL rise time (1000ns) */
2496                 usec_delay(IXGBE_I2C_T_RISE);
2497
2498                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2499                 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2500                         break;
2501         }
2502 }
2503
2504 /**
2505  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2506  *  @hw: pointer to hardware structure
2507  *  @i2cctl: Current value of I2CCTL register
2508  *
2509  *  Lowers the I2C clock line '1'->'0'
2510  *  Asserts the I2C clock output enable on X550 hardware.
2511  **/
2512 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2513 {
2514         DEBUGFUNC("ixgbe_lower_i2c_clk");
2515
2516         *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2517         *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2518
2519         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2520         IXGBE_WRITE_FLUSH(hw);
2521
2522         /* SCL fall time (300ns) */
2523         usec_delay(IXGBE_I2C_T_FALL);
2524 }
2525
2526 /**
2527  *  ixgbe_set_i2c_data - Sets the I2C data bit
2528  *  @hw: pointer to hardware structure
2529  *  @i2cctl: Current value of I2CCTL register
2530  *  @data: I2C data value (0 or 1) to set
2531  *
2532  *  Sets the I2C data bit
2533  *  Asserts the I2C data output enable on X550 hardware.
2534  **/
2535 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2536 {
2537         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2538         s32 status = IXGBE_SUCCESS;
2539
2540         DEBUGFUNC("ixgbe_set_i2c_data");
2541
2542         if (data)
2543                 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2544         else
2545                 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2546         *i2cctl &= ~data_oe_bit;
2547
2548         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2549         IXGBE_WRITE_FLUSH(hw);
2550
2551         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2552         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2553
2554         if (!data)      /* Can't verify data in this case */
2555                 return IXGBE_SUCCESS;
2556         if (data_oe_bit) {
2557                 *i2cctl |= data_oe_bit;
2558                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2559                 IXGBE_WRITE_FLUSH(hw);
2560         }
2561
2562         /* Verify data was set correctly */
2563         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2564         if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2565                 status = IXGBE_ERR_I2C;
2566                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2567                              "Error - I2C data was not set to %X.\n",
2568                              data);
2569         }
2570
2571         return status;
2572 }
2573
2574 /**
2575  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2576  *  @hw: pointer to hardware structure
2577  *  @i2cctl: Current value of I2CCTL register
2578  *
2579  *  Returns the I2C data bit value
2580  *  Negates the I2C data output enable on X550 hardware.
2581  **/
2582 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2583 {
2584         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2585         bool data;
2586
2587         DEBUGFUNC("ixgbe_get_i2c_data");
2588
2589         if (data_oe_bit) {
2590                 *i2cctl |= data_oe_bit;
2591                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2592                 IXGBE_WRITE_FLUSH(hw);
2593                 usec_delay(IXGBE_I2C_T_FALL);
2594         }
2595
2596         if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2597                 data = 1;
2598         else
2599                 data = 0;
2600
2601         return data;
2602 }
2603
2604 /**
2605  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2606  *  @hw: pointer to hardware structure
2607  *
2608  *  Clears the I2C bus by sending nine clock pulses.
2609  *  Used when data line is stuck low.
2610  **/
2611 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2612 {
2613         u32 i2cctl;
2614         u32 i;
2615
2616         DEBUGFUNC("ixgbe_i2c_bus_clear");
2617
2618         ixgbe_i2c_start(hw);
2619         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2620
2621         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2622
2623         for (i = 0; i < 9; i++) {
2624                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2625
2626                 /* Min high period of clock is 4us */
2627                 usec_delay(IXGBE_I2C_T_HIGH);
2628
2629                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2630
2631                 /* Min low period of clock is 4.7us*/
2632                 usec_delay(IXGBE_I2C_T_LOW);
2633         }
2634
2635         ixgbe_i2c_start(hw);
2636
2637         /* Put the i2c bus back to default state */
2638         ixgbe_i2c_stop(hw);
2639 }
2640
2641 /**
2642  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2643  *  @hw: pointer to hardware structure
2644  *
2645  *  Checks if the LASI temp alarm status was triggered due to overtemp
2646  **/
2647 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2648 {
2649         s32 status = IXGBE_SUCCESS;
2650         u16 phy_data = 0;
2651
2652         DEBUGFUNC("ixgbe_tn_check_overtemp");
2653
2654         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2655                 goto out;
2656
2657         /* Check that the LASI temp alarm status was triggered */
2658         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2659                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2660
2661         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2662                 goto out;
2663
2664         status = IXGBE_ERR_OVERTEMP;
2665         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2666 out:
2667         return status;
2668 }
2669
2670 /**
2671  * ixgbe_set_copper_phy_power - Control power for copper phy
2672  * @hw: pointer to hardware structure
2673  * @on: true for on, false for off
2674  */
2675 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2676 {
2677         u32 status;
2678         u16 reg;
2679
2680         if (!on && ixgbe_mng_present(hw))
2681                 return 0;
2682
2683         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2684                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2685                                       &reg);
2686         if (status)
2687                 return status;
2688
2689         if (on) {
2690                 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2691         } else {
2692                 if (ixgbe_check_reset_blocked(hw))
2693                         return 0;
2694                 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2695         }
2696
2697         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2698                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2699                                        reg);
2700         return status;
2701 }