drivers/net/ixgbe/base/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_api.h"
  35 #include "ixgbe_common.h"
  36 #include "ixgbe_phy.h"
  37
  38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
  39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  50                                           u8 *sff8472_data);
  51
  52 /**
  53  * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
  54  * @hw: pointer to the hardware structure
  55  * @byte: byte to send
  56  *
  57  * Returns an error code on error.
  58  */
  59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
  60 {
  61         s32 status;
  62
  63         status = ixgbe_clock_out_i2c_byte(hw, byte);
  64         if (status)
  65                 return status;
  66         return ixgbe_get_i2c_ack(hw);
  67 }
  68
  69 /**
  70  * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
  71  * @hw: pointer to the hardware structure
  72  * @byte: pointer to a u8 to receive the byte
  73  *
  74  * Returns an error code on error.
  75  */
  76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
  77 {
  78         s32 status;
  79
  80         status = ixgbe_clock_in_i2c_byte(hw, byte);
  81         if (status)
  82                 return status;
  83         /* ACK */
  84         return ixgbe_clock_out_i2c_bit(hw, false);
  85 }
  86
  87 /**
  88  * ixgbe_ones_comp_byte_add - Perform one's complement addition
  89  * @add1 - addend 1
  90  * @add2 - addend 2
  91  *
  92  * Returns one's complement 8-bit sum.
  93  */
  94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
  95 {
  96         u16 sum = add1 + add2;
  97
  98         sum = (sum & 0xFF) + (sum >> 8);
  99         return sum & 0xFF;
 100 }
 101
 102 /**
 103  * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
 104  * @hw: pointer to the hardware structure
 105  * @addr: I2C bus address to read from
 106  * @reg: I2C device register to read from
 107  * @val: pointer to location to receive read value
 108  * @lock: true if to take and release semaphore
 109  *
 110  * Returns an error code on error.
 111  */
 112 STATIC s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
 113                                                u16 reg, u16 *val, bool lock)
 114 {
 115         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 116         int max_retry = 10;
 117         int retry = 0;
 118         u8 csum_byte;
 119         u8 high_bits;
 120         u8 low_bits;
 121         u8 reg_high;
 122         u8 csum;
 123
 124         if (hw->mac.type >= ixgbe_mac_X550)
 125                 max_retry = 3;
 126         reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
 127         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 128         csum = ~csum;
 129         do {
 130                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 131                         return IXGBE_ERR_SWFW_SYNC;
 132                 ixgbe_i2c_start(hw);
 133                 /* Device Address and write indication */
 134                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 135                         goto fail;
 136                 /* Write bits 14:8 */
 137                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 138                         goto fail;
 139                 /* Write bits 7:0 */
 140                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 141                         goto fail;
 142                 /* Write csum */
 143                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 144                         goto fail;
 145                 /* Re-start condition */
 146                 ixgbe_i2c_start(hw);
 147                 /* Device Address and read indication */
 148                 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
 149                         goto fail;
 150                 /* Get upper bits */
 151                 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
 152                         goto fail;
 153                 /* Get low bits */
 154                 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
 155                         goto fail;
 156                 /* Get csum */
 157                 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
 158                         goto fail;
 159                 /* NACK */
 160                 if (ixgbe_clock_out_i2c_bit(hw, false))
 161                         goto fail;
 162                 ixgbe_i2c_stop(hw);
 163                 if (lock)
 164                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 165                 *val = (high_bits << 8) | low_bits;
 166                 return 0;
 167
 168 fail:
 169                 ixgbe_i2c_bus_clear(hw);
 170                 if (lock)
 171                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 172                 retry++;
 173                 if (retry < max_retry)
 174                         DEBUGOUT("I2C byte read combined error - Retrying.\n");
 175                 else
 176                         DEBUGOUT("I2C byte read combined error.\n");
 177         } while (retry < max_retry);
 178
 179         return IXGBE_ERR_I2C;
 180 }
 181
 182 /**
 183  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 184  * @hw: pointer to the hardware structure
 185  * @addr: I2C bus address to read from
 186  * @reg: I2C device register to read from
 187  * @val: pointer to location to receive read value
 188  *
 189  * Returns an error code on error.
 190  **/
 191 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 192                                            u16 reg, u16 *val)
 193 {
 194         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 195 }
 196
 197 /**
 198  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 199  * @hw: pointer to the hardware structure
 200  * @addr: I2C bus address to read from
 201  * @reg: I2C device register to read from
 202  * @val: pointer to location to receive read value
 203  *
 204  * Returns an error code on error.
 205  **/
 206 STATIC s32
 207 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 208                                          u16 reg, u16 *val)
 209 {
 210         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 211 }
 212
 213 /**
 214  * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
 215  * @hw: pointer to the hardware structure
 216  * @addr: I2C bus address to write to
 217  * @reg: I2C device register to write to
 218  * @val: value to write
 219  * @lock: true if to take and release semaphore
 220  *
 221  * Returns an error code on error.
 222  */
 223 STATIC s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
 224                                                 u16 reg, u16 val, bool lock)
 225 {
 226         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 227         int max_retry = 1;
 228         int retry = 0;
 229         u8 reg_high;
 230         u8 csum;
 231
 232         reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
 233         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 234         csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
 235         csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
 236         csum = ~csum;
 237         do {
 238                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 239                         return IXGBE_ERR_SWFW_SYNC;
 240                 ixgbe_i2c_start(hw);
 241                 /* Device Address and write indication */
 242                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 243                         goto fail;
 244                 /* Write bits 14:8 */
 245                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 246                         goto fail;
 247                 /* Write bits 7:0 */
 248                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 249                         goto fail;
 250                 /* Write data 15:8 */
 251                 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
 252                         goto fail;
 253                 /* Write data 7:0 */
 254                 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
 255                         goto fail;
 256                 /* Write csum */
 257                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 258                         goto fail;
 259                 ixgbe_i2c_stop(hw);
 260                 if (lock)
 261                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 262                 return 0;
 263
 264 fail:
 265                 ixgbe_i2c_bus_clear(hw);
 266                 if (lock)
 267                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 268                 retry++;
 269                 if (retry < max_retry)
 270                         DEBUGOUT("I2C byte write combined error - Retrying.\n");
 271                 else
 272                         DEBUGOUT("I2C byte write combined error.\n");
 273         } while (retry < max_retry);
 274
 275         return IXGBE_ERR_I2C;
 276 }
 277
 278 /**
 279  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 280  * @hw: pointer to the hardware structure
 281  * @addr: I2C bus address to write to
 282  * @reg: I2C device register to write to
 283  * @val: value to write
 284  *
 285  * Returns an error code on error.
 286  **/
 287 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 288                                             u8 addr, u16 reg, u16 val)
 289 {
 290         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 291 }
 292
 293 /**
 294  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 295  * @hw: pointer to the hardware structure
 296  * @addr: I2C bus address to write to
 297  * @reg: I2C device register to write to
 298  * @val: value to write
 299  *
 300  * Returns an error code on error.
 301  **/
 302 STATIC s32
 303 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 304                                           u8 addr, u16 reg, u16 val)
 305 {
 306         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 307 }
 308
 309 /**
 310  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
 311  *  @hw: pointer to the hardware structure
 312  *
 313  *  Initialize the function pointers.
 314  **/
 315 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
 316 {
 317         struct ixgbe_phy_info *phy = &hw->phy;
 318
 319         DEBUGFUNC("ixgbe_init_phy_ops_generic");
 320
 321         /* PHY */
 322         phy->ops.identify = ixgbe_identify_phy_generic;
 323         phy->ops.reset = ixgbe_reset_phy_generic;
 324         phy->ops.read_reg = ixgbe_read_phy_reg_generic;
 325         phy->ops.write_reg = ixgbe_write_phy_reg_generic;
 326         phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
 327         phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
 328         phy->ops.setup_link = ixgbe_setup_phy_link_generic;
 329         phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
 330         phy->ops.check_link = NULL;
 331         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
 332         phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
 333         phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
 334         phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
 335         phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
 336         phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
 337         phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
 338         phy->ops.identify_sfp = ixgbe_identify_module_generic;
 339         phy->sfp_type = ixgbe_sfp_type_unknown;
 340         phy->ops.read_i2c_combined = ixgbe_read_i2c_combined_generic;
 341         phy->ops.write_i2c_combined = ixgbe_write_i2c_combined_generic;
 342         phy->ops.read_i2c_combined_unlocked =
 343                                 ixgbe_read_i2c_combined_generic_unlocked;
 344         phy->ops.write_i2c_combined_unlocked =
 345                                 ixgbe_write_i2c_combined_generic_unlocked;
 346         phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
 347         phy->ops.write_i2c_byte_unlocked =
 348                                 ixgbe_write_i2c_byte_generic_unlocked;
 349         phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
 350         return IXGBE_SUCCESS;
 351 }
 352
 353 /**
 354  *  ixgbe_identify_phy_generic - Get physical layer module
 355  *  @hw: pointer to hardware structure
 356  *
 357  *  Determines the physical layer module found on the current adapter.
 358  **/
 359 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 360 {
 361         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 362         u32 phy_addr;
 363         u16 ext_ability = 0;
 364
 365         DEBUGFUNC("ixgbe_identify_phy_generic");
 366
 367         if (!hw->phy.phy_semaphore_mask) {
 368                 if (hw->bus.lan_id)
 369                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 370                 else
 371                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 372         }
 373
 374         if (hw->phy.type == ixgbe_phy_unknown) {
 375                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 376                         if (ixgbe_validate_phy_addr(hw, phy_addr)) {
 377                                 hw->phy.addr = phy_addr;
 378                                 ixgbe_get_phy_id(hw);
 379                                 hw->phy.type =
 380                                         ixgbe_get_phy_type_from_id(hw->phy.id);
 381
 382                                 if (hw->phy.type == ixgbe_phy_unknown) {
 383                                         hw->phy.ops.read_reg(hw,
 384                                                   IXGBE_MDIO_PHY_EXT_ABILITY,
 385                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 386                                                   &ext_ability);
 387                                         if (ext_ability &
 388                                             (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 389                                              IXGBE_MDIO_PHY_1000BASET_ABILITY))
 390                                                 hw->phy.type =
 391                                                          ixgbe_phy_cu_unknown;
 392                                         else
 393                                                 hw->phy.type =
 394                                                          ixgbe_phy_generic;
 395                                 }
 396
 397                                 status = IXGBE_SUCCESS;
 398                                 break;
 399                         }
 400                 }
 401
 402                 /* Certain media types do not have a phy so an address will not
 403                  * be found and the code will take this path.  Caller has to
 404                  * decide if it is an error or not.
 405                  */
 406                 if (status != IXGBE_SUCCESS) {
 407                         hw->phy.addr = 0;
 408                 }
 409         } else {
 410                 status = IXGBE_SUCCESS;
 411         }
 412
 413         return status;
 414 }
 415
 416 /**
 417  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 418  * @hw: pointer to the hardware structure
 419  *
 420  * This function checks the MMNGC.MNG_VETO bit to see if there are
 421  * any constraints on link from manageability.  For MAC's that don't
 422  * have this bit just return faluse since the link can not be blocked
 423  * via this method.
 424  **/
 425 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 426 {
 427         u32 mmngc;
 428
 429         DEBUGFUNC("ixgbe_check_reset_blocked");
 430
 431         /* If we don't have this bit, it can't be blocking */
 432         if (hw->mac.type == ixgbe_mac_82598EB)
 433                 return false;
 434
 435         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 436         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 437                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 438                               "MNG_VETO bit detected.\n");
 439                 return true;
 440         }
 441
 442         return false;
 443 }
 444
 445 /**
 446  *  ixgbe_validate_phy_addr - Determines phy address is valid
 447  *  @hw: pointer to hardware structure
 448  *
 449  **/
 450 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 451 {
 452         u16 phy_id = 0;
 453         bool valid = false;
 454
 455         DEBUGFUNC("ixgbe_validate_phy_addr");
 456
 457         hw->phy.addr = phy_addr;
 458         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 459                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 460
 461         if (phy_id != 0xFFFF && phy_id != 0x0)
 462                 valid = true;
 463
 464         return valid;
 465 }
 466
 467 /**
 468  *  ixgbe_get_phy_id - Get the phy type
 469  *  @hw: pointer to hardware structure
 470  *
 471  **/
 472 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 473 {
 474         u32 status;
 475         u16 phy_id_high = 0;
 476         u16 phy_id_low = 0;
 477
 478         DEBUGFUNC("ixgbe_get_phy_id");
 479
 480         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 481                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 482                                       &phy_id_high);
 483
 484         if (status == IXGBE_SUCCESS) {
 485                 hw->phy.id = (u32)(phy_id_high << 16);
 486                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 487                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 488                                               &phy_id_low);
 489                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 490                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 491         }
 492         return status;
 493 }
 494
 495 /**
 496  *  ixgbe_get_phy_type_from_id - Get the phy type
 497  *  @hw: pointer to hardware structure
 498  *
 499  **/
 500 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 501 {
 502         enum ixgbe_phy_type phy_type;
 503
 504         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 505
 506         switch (phy_id) {
 507         case TN1010_PHY_ID:
 508                 phy_type = ixgbe_phy_tn;
 509                 break;
 510         case X550_PHY_ID:
 511         case X540_PHY_ID:
 512                 phy_type = ixgbe_phy_aq;
 513                 break;
 514         case QT2022_PHY_ID:
 515                 phy_type = ixgbe_phy_qt;
 516                 break;
 517         case ATH_PHY_ID:
 518                 phy_type = ixgbe_phy_nl;
 519                 break;
 520         case X557_PHY_ID:
 521                 phy_type = ixgbe_phy_x550em_ext_t;
 522                 break;
 523         default:
 524                 phy_type = ixgbe_phy_unknown;
 525                 break;
 526         }
 527
 528         DEBUGOUT1("phy type found is %d\n", phy_type);
 529         return phy_type;
 530 }
 531
 532 /**
 533  *  ixgbe_reset_phy_generic - Performs a PHY reset
 534  *  @hw: pointer to hardware structure
 535  **/
 536 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 537 {
 538         u32 i;
 539         u16 ctrl = 0;
 540         s32 status = IXGBE_SUCCESS;
 541
 542         DEBUGFUNC("ixgbe_reset_phy_generic");
 543
 544         if (hw->phy.type == ixgbe_phy_unknown)
 545                 status = ixgbe_identify_phy_generic(hw);
 546
 547         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 548                 goto out;
 549
 550         /* Don't reset PHY if it's shut down due to overtemp. */
 551         if (!hw->phy.reset_if_overtemp &&
 552             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 553                 goto out;
 554
 555         /* Blocked by MNG FW so bail */
 556         if (ixgbe_check_reset_blocked(hw))
 557                 goto out;
 558
 559         /*
 560          * Perform soft PHY reset to the PHY_XS.
 561          * This will cause a soft reset to the PHY
 562          */
 563         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 564                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 565                               IXGBE_MDIO_PHY_XS_RESET);
 566
 567         /*
 568          * Poll for reset bit to self-clear indicating reset is complete.
 569          * Some PHYs could take up to 3 seconds to complete and need about
 570          * 1.7 usec delay after the reset is complete.
 571          */
 572         for (i = 0; i < 30; i++) {
 573                 msec_delay(100);
 574                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 575                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
 576                 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 577                         usec_delay(2);
 578                         break;
 579                 }
 580         }
 581
 582         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 583                 status = IXGBE_ERR_RESET_FAILED;
 584                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 585                              "PHY reset polling failed to complete.\n");
 586         }
 587
 588 out:
 589         return status;
 590 }
 591
 592 /**
 593  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 594  *  the SWFW lock
 595  *  @hw: pointer to hardware structure
 596  *  @reg_addr: 32 bit address of PHY register to read
 597  *  @phy_data: Pointer to read data from PHY register
 598  **/
 599 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 600                        u16 *phy_data)
 601 {
 602         u32 i, data, command;
 603
 604         /* Setup and write the address cycle command */
 605         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 606                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 607                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 608                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 609
 610         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 611
 612         /*
 613          * Check every 10 usec to see if the address cycle completed.
 614          * The MDI Command bit will clear when the operation is
 615          * complete
 616          */
 617         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 618                 usec_delay(10);
 619
 620                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 621                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 622                                 break;
 623         }
 624
 625
 626         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 627                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 628                 return IXGBE_ERR_PHY;
 629         }
 630
 631         /*
 632          * Address cycle complete, setup and write the read
 633          * command
 634          */
 635         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 636                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 637                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 638                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 639
 640         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 641
 642         /*
 643          * Check every 10 usec to see if the address cycle
 644          * completed. The MDI Command bit will clear when the
 645          * operation is complete
 646          */
 647         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 648                 usec_delay(10);
 649
 650                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 651                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 652                         break;
 653         }
 654
 655         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 656                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 657                 return IXGBE_ERR_PHY;
 658         }
 659
 660         /*
 661          * Read operation is complete.  Get the data
 662          * from MSRWD
 663          */
 664         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 665         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 666         *phy_data = (u16)(data);
 667
 668         return IXGBE_SUCCESS;
 669 }
 670
 671 /**
 672  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 673  *  using the SWFW lock - this function is needed in most cases
 674  *  @hw: pointer to hardware structure
 675  *  @reg_addr: 32 bit address of PHY register to read
 676  *  @phy_data: Pointer to read data from PHY register
 677  **/
 678 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 679                                u32 device_type, u16 *phy_data)
 680 {
 681         s32 status;
 682         u32 gssr = hw->phy.phy_semaphore_mask;
 683
 684         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 685
 686         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 687                 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
 688                                                 phy_data);
 689                 hw->mac.ops.release_swfw_sync(hw, gssr);
 690         } else {
 691                 status = IXGBE_ERR_SWFW_SYNC;
 692         }
 693
 694         return status;
 695 }
 696
 697 /**
 698  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 699  *  without SWFW lock
 700  *  @hw: pointer to hardware structure
 701  *  @reg_addr: 32 bit PHY register to write
 702  *  @device_type: 5 bit device type
 703  *  @phy_data: Data to write to the PHY register
 704  **/
 705 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 706                                 u32 device_type, u16 phy_data)
 707 {
 708         u32 i, command;
 709
 710         /* Put the data in the MDI single read and write data register*/
 711         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 712
 713         /* Setup and write the address cycle command */
 714         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 715                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 716                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 717                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 718
 719         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 720
 721         /*
 722          * Check every 10 usec to see if the address cycle completed.
 723          * The MDI Command bit will clear when the operation is
 724          * complete
 725          */
 726         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 727                 usec_delay(10);
 728
 729                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 730                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 731                         break;
 732         }
 733
 734         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 735                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 736                 return IXGBE_ERR_PHY;
 737         }
 738
 739         /*
 740          * Address cycle complete, setup and write the write
 741          * command
 742          */
 743         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 744                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 745                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 746                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 747
 748         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 749
 750         /*
 751          * Check every 10 usec to see if the address cycle
 752          * completed. The MDI Command bit will clear when the
 753          * operation is complete
 754          */
 755         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 756                 usec_delay(10);
 757
 758                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 759                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 760                         break;
 761         }
 762
 763         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 764                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 765                 return IXGBE_ERR_PHY;
 766         }
 767
 768         return IXGBE_SUCCESS;
 769 }
 770
 771 /**
 772  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 773  *  using SWFW lock- this function is needed in most cases
 774  *  @hw: pointer to hardware structure
 775  *  @reg_addr: 32 bit PHY register to write
 776  *  @device_type: 5 bit device type
 777  *  @phy_data: Data to write to the PHY register
 778  **/
 779 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 780                                 u32 device_type, u16 phy_data)
 781 {
 782         s32 status;
 783         u32 gssr = hw->phy.phy_semaphore_mask;
 784
 785         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 786
 787         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 788                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
 789                                                  phy_data);
 790                 hw->mac.ops.release_swfw_sync(hw, gssr);
 791         } else {
 792                 status = IXGBE_ERR_SWFW_SYNC;
 793         }
 794
 795         return status;
 796 }
 797
 798 /**
 799  *  ixgbe_setup_phy_link_generic - Set and restart auto-neg
 800  *  @hw: pointer to hardware structure
 801  *
 802  *  Restart auto-negotiation and PHY and waits for completion.
 803  **/
 804 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 805 {
 806         s32 status = IXGBE_SUCCESS;
 807         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 808         bool autoneg = false;
 809         ixgbe_link_speed speed;
 810
 811         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 812
 813         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 814
 815         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 816                 /* Set or unset auto-negotiation 10G advertisement */
 817                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 818                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 819                                      &autoneg_reg);
 820
 821                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 822                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 823                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 824
 825                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 826                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 827                                       autoneg_reg);
 828         }
 829
 830         if (hw->mac.type == ixgbe_mac_X550) {
 831                 if (speed & IXGBE_LINK_SPEED_5GB_FULL) {
 832                         /* Set or unset auto-negotiation 1G advertisement */
 833                         hw->phy.ops.read_reg(hw,
 834                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 835                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 836                                 &autoneg_reg);
 837
 838                         autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
 839                         if (hw->phy.autoneg_advertised &
 840                              IXGBE_LINK_SPEED_5GB_FULL)
 841                                 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
 842
 843                         hw->phy.ops.write_reg(hw,
 844                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 845                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 846                                 autoneg_reg);
 847                 }
 848
 849                 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) {
 850                         /* Set or unset auto-negotiation 1G advertisement */
 851                         hw->phy.ops.read_reg(hw,
 852                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 853                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 854                                 &autoneg_reg);
 855
 856                         autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
 857                         if (hw->phy.autoneg_advertised &
 858                             IXGBE_LINK_SPEED_2_5GB_FULL)
 859                                 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
 860
 861                         hw->phy.ops.write_reg(hw,
 862                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 863                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 864                                 autoneg_reg);
 865                 }
 866         }
 867
 868         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 869                 /* Set or unset auto-negotiation 1G advertisement */
 870                 hw->phy.ops.read_reg(hw,
 871                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 872                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 873                                      &autoneg_reg);
 874
 875                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 876                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 877                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 878
 879                 hw->phy.ops.write_reg(hw,
 880                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 881                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 882                                       autoneg_reg);
 883         }
 884
 885         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 886                 /* Set or unset auto-negotiation 100M advertisement */
 887                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 888                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 889                                      &autoneg_reg);
 890
 891                 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 892                                  IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 893                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 894                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 895
 896                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 897                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 898                                       autoneg_reg);
 899         }
 900
 901         /* Blocked by MNG FW so don't reset PHY */
 902         if (ixgbe_check_reset_blocked(hw))
 903                 return status;
 904
 905         /* Restart PHY auto-negotiation. */
 906         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 907                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 908
 909         autoneg_reg |= IXGBE_MII_RESTART;
 910
 911         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 912                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 913
 914         return status;
 915 }
 916
 917 /**
 918  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 919  *  @hw: pointer to hardware structure
 920  *  @speed: new link speed
 921  **/
 922 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 923                                        ixgbe_link_speed speed,
 924                                        bool autoneg_wait_to_complete)
 925 {
 926         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 927
 928         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 929
 930         /*
 931          * Clear autoneg_advertised and set new values based on input link
 932          * speed.
 933          */
 934         hw->phy.autoneg_advertised = 0;
 935
 936         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 937                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 938
 939         if (speed & IXGBE_LINK_SPEED_5GB_FULL)
 940                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
 941
 942         if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
 943                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
 944
 945         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 946                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 947
 948         if (speed & IXGBE_LINK_SPEED_100_FULL)
 949                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 950
 951         /* Setup link based on the new speed settings */
 952         hw->phy.ops.setup_link(hw);
 953
 954         return IXGBE_SUCCESS;
 955 }
 956
 957 /**
 958  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 959  *  @hw: pointer to hardware structure
 960  *  @speed: pointer to link speed
 961  *  @autoneg: boolean auto-negotiation value
 962  *
 963  *  Determines the supported link capabilities by reading the PHY auto
 964  *  negotiation register.
 965  **/
 966 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 967                                                ixgbe_link_speed *speed,
 968                                                bool *autoneg)
 969 {
 970         s32 status;
 971         u16 speed_ability;
 972
 973         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 974
 975         *speed = 0;
 976         *autoneg = true;
 977
 978         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 979                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 980                                       &speed_ability);
 981
 982         if (status == IXGBE_SUCCESS) {
 983                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 984                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 985                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 986                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 987                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 988                         *speed |= IXGBE_LINK_SPEED_100_FULL;
 989         }
 990
 991         /* Internal PHY does not support 100 Mbps */
 992         if (hw->mac.type == ixgbe_mac_X550EM_x)
 993                 *speed &= ~IXGBE_LINK_SPEED_100_FULL;
 994
 995         if (hw->mac.type == ixgbe_mac_X550) {
 996                 *speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
 997                 *speed |= IXGBE_LINK_SPEED_5GB_FULL;
 998         }
 999
1000         return status;
1001 }
1002
1003 /**
1004  *  ixgbe_check_phy_link_tnx - Determine link and speed status
1005  *  @hw: pointer to hardware structure
1006  *
1007  *  Reads the VS1 register to determine if link is up and the current speed for
1008  *  the PHY.
1009  **/
1010 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1011                              bool *link_up)
1012 {
1013         s32 status = IXGBE_SUCCESS;
1014         u32 time_out;
1015         u32 max_time_out = 10;
1016         u16 phy_link = 0;
1017         u16 phy_speed = 0;
1018         u16 phy_data = 0;
1019
1020         DEBUGFUNC("ixgbe_check_phy_link_tnx");
1021
1022         /* Initialize speed and link to default case */
1023         *link_up = false;
1024         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1025
1026         /*
1027          * Check current speed and link status of the PHY register.
1028          * This is a vendor specific register and may have to
1029          * be changed for other copper PHYs.
1030          */
1031         for (time_out = 0; time_out < max_time_out; time_out++) {
1032                 usec_delay(10);
1033                 status = hw->phy.ops.read_reg(hw,
1034                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1035                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1036                                         &phy_data);
1037                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1038                 phy_speed = phy_data &
1039                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1040                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1041                         *link_up = true;
1042                         if (phy_speed ==
1043                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1044                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1045                         break;
1046                 }
1047         }
1048
1049         return status;
1050 }
1051
1052 /**
1053  *      ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1054  *      @hw: pointer to hardware structure
1055  *
1056  *      Restart auto-negotiation and PHY and waits for completion.
1057  **/
1058 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1059 {
1060         s32 status = IXGBE_SUCCESS;
1061         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1062         bool autoneg = false;
1063         ixgbe_link_speed speed;
1064
1065         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1066
1067         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1068
1069         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1070                 /* Set or unset auto-negotiation 10G advertisement */
1071                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1072                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1073                                      &autoneg_reg);
1074
1075                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1076                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1077                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1078
1079                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1080                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1081                                       autoneg_reg);
1082         }
1083
1084         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1085                 /* Set or unset auto-negotiation 1G advertisement */
1086                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1087                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1088                                      &autoneg_reg);
1089
1090                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1091                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1092                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1093
1094                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1095                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1096                                       autoneg_reg);
1097         }
1098
1099         if (speed & IXGBE_LINK_SPEED_100_FULL) {
1100                 /* Set or unset auto-negotiation 100M advertisement */
1101                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1102                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1103                                      &autoneg_reg);
1104
1105                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1106                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1107                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1108
1109                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1110                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1111                                       autoneg_reg);
1112         }
1113
1114         /* Blocked by MNG FW so don't reset PHY */
1115         if (ixgbe_check_reset_blocked(hw))
1116                 return status;
1117
1118         /* Restart PHY auto-negotiation. */
1119         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1120                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1121
1122         autoneg_reg |= IXGBE_MII_RESTART;
1123
1124         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1125                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1126
1127         return status;
1128 }
1129
1130 /**
1131  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1132  *  @hw: pointer to hardware structure
1133  *  @firmware_version: pointer to the PHY Firmware Version
1134  **/
1135 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1136                                        u16 *firmware_version)
1137 {
1138         s32 status;
1139
1140         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1141
1142         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1143                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1144                                       firmware_version);
1145
1146         return status;
1147 }
1148
1149 /**
1150  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1151  *  @hw: pointer to hardware structure
1152  *  @firmware_version: pointer to the PHY Firmware Version
1153  **/
1154 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1155                                            u16 *firmware_version)
1156 {
1157         s32 status;
1158
1159         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1160
1161         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1162                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1163                                       firmware_version);
1164
1165         return status;
1166 }
1167
1168 /**
1169  *  ixgbe_reset_phy_nl - Performs a PHY reset
1170  *  @hw: pointer to hardware structure
1171  **/
1172 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1173 {
1174         u16 phy_offset, control, eword, edata, block_crc;
1175         bool end_data = false;
1176         u16 list_offset, data_offset;
1177         u16 phy_data = 0;
1178         s32 ret_val = IXGBE_SUCCESS;
1179         u32 i;
1180
1181         DEBUGFUNC("ixgbe_reset_phy_nl");
1182
1183         /* Blocked by MNG FW so bail */
1184         if (ixgbe_check_reset_blocked(hw))
1185                 goto out;
1186
1187         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1188                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1189
1190         /* reset the PHY and poll for completion */
1191         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1192                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
1193                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1194
1195         for (i = 0; i < 100; i++) {
1196                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1197                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1198                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1199                         break;
1200                 msec_delay(10);
1201         }
1202
1203         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1204                 DEBUGOUT("PHY reset did not complete.\n");
1205                 ret_val = IXGBE_ERR_PHY;
1206                 goto out;
1207         }
1208
1209         /* Get init offsets */
1210         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1211                                                       &data_offset);
1212         if (ret_val != IXGBE_SUCCESS)
1213                 goto out;
1214
1215         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1216         data_offset++;
1217         while (!end_data) {
1218                 /*
1219                  * Read control word from PHY init contents offset
1220                  */
1221                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1222                 if (ret_val)
1223                         goto err_eeprom;
1224                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1225                            IXGBE_CONTROL_SHIFT_NL;
1226                 edata = eword & IXGBE_DATA_MASK_NL;
1227                 switch (control) {
1228                 case IXGBE_DELAY_NL:
1229                         data_offset++;
1230                         DEBUGOUT1("DELAY: %d MS\n", edata);
1231                         msec_delay(edata);
1232                         break;
1233                 case IXGBE_DATA_NL:
1234                         DEBUGOUT("DATA:\n");
1235                         data_offset++;
1236                         ret_val = hw->eeprom.ops.read(hw, data_offset,
1237                                                       &phy_offset);
1238                         if (ret_val)
1239                                 goto err_eeprom;
1240                         data_offset++;
1241                         for (i = 0; i < edata; i++) {
1242                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
1243                                                               &eword);
1244                                 if (ret_val)
1245                                         goto err_eeprom;
1246                                 hw->phy.ops.write_reg(hw, phy_offset,
1247                                                       IXGBE_TWINAX_DEV, eword);
1248                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1249                                           phy_offset);
1250                                 data_offset++;
1251                                 phy_offset++;
1252                         }
1253                         break;
1254                 case IXGBE_CONTROL_NL:
1255                         data_offset++;
1256                         DEBUGOUT("CONTROL:\n");
1257                         if (edata == IXGBE_CONTROL_EOL_NL) {
1258                                 DEBUGOUT("EOL\n");
1259                                 end_data = true;
1260                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
1261                                 DEBUGOUT("SOL\n");
1262                         } else {
1263                                 DEBUGOUT("Bad control value\n");
1264                                 ret_val = IXGBE_ERR_PHY;
1265                                 goto out;
1266                         }
1267                         break;
1268                 default:
1269                         DEBUGOUT("Bad control type\n");
1270                         ret_val = IXGBE_ERR_PHY;
1271                         goto out;
1272                 }
1273         }
1274
1275 out:
1276         return ret_val;
1277
1278 err_eeprom:
1279         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1280                       "eeprom read at offset %d failed", data_offset);
1281         return IXGBE_ERR_PHY;
1282 }
1283
1284 /**
1285  *  ixgbe_identify_module_generic - Identifies module type
1286  *  @hw: pointer to hardware structure
1287  *
1288  *  Determines HW type and calls appropriate function.
1289  **/
1290 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1291 {
1292         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1293
1294         DEBUGFUNC("ixgbe_identify_module_generic");
1295
1296         switch (hw->mac.ops.get_media_type(hw)) {
1297         case ixgbe_media_type_fiber:
1298                 status = ixgbe_identify_sfp_module_generic(hw);
1299                 break;
1300
1301         case ixgbe_media_type_fiber_qsfp:
1302                 status = ixgbe_identify_qsfp_module_generic(hw);
1303                 break;
1304
1305         default:
1306                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1307                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1308                 break;
1309         }
1310
1311         return status;
1312 }
1313
1314 /**
1315  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1316  *  @hw: pointer to hardware structure
1317  *
1318  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1319  **/
1320 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1321 {
1322         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1323         u32 vendor_oui = 0;
1324         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1325         u8 identifier = 0;
1326         u8 comp_codes_1g = 0;
1327         u8 comp_codes_10g = 0;
1328         u8 oui_bytes[3] = {0, 0, 0};
1329         u8 cable_tech = 0;
1330         u8 cable_spec = 0;
1331         u16 enforce_sfp = 0;
1332
1333         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1334
1335         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1336                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1337                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1338                 goto out;
1339         }
1340
1341         /* LAN ID is needed for I2C access */
1342         hw->mac.ops.set_lan_id(hw);
1343
1344         status = hw->phy.ops.read_i2c_eeprom(hw,
1345                                              IXGBE_SFF_IDENTIFIER,
1346                                              &identifier);
1347
1348         if (status != IXGBE_SUCCESS)
1349                 goto err_read_i2c_eeprom;
1350
1351         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1352                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1353                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1354         } else {
1355                 status = hw->phy.ops.read_i2c_eeprom(hw,
1356                                                      IXGBE_SFF_1GBE_COMP_CODES,
1357                                                      &comp_codes_1g);
1358
1359                 if (status != IXGBE_SUCCESS)
1360                         goto err_read_i2c_eeprom;
1361
1362                 status = hw->phy.ops.read_i2c_eeprom(hw,
1363                                                      IXGBE_SFF_10GBE_COMP_CODES,
1364                                                      &comp_codes_10g);
1365
1366                 if (status != IXGBE_SUCCESS)
1367                         goto err_read_i2c_eeprom;
1368                 status = hw->phy.ops.read_i2c_eeprom(hw,
1369                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1370                                                      &cable_tech);
1371
1372                 if (status != IXGBE_SUCCESS)
1373                         goto err_read_i2c_eeprom;
1374
1375                  /* ID Module
1376                   * =========
1377                   * 0   SFP_DA_CU
1378                   * 1   SFP_SR
1379                   * 2   SFP_LR
1380                   * 3   SFP_DA_CORE0 - 82599-specific
1381                   * 4   SFP_DA_CORE1 - 82599-specific
1382                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1383                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1384                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1385                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1386                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1387                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1388                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1389                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1390                   */
1391                 if (hw->mac.type == ixgbe_mac_82598EB) {
1392                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1393                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1394                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1395                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1396                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1397                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1398                         else
1399                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1400                 } else {
1401                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1402                                 if (hw->bus.lan_id == 0)
1403                                         hw->phy.sfp_type =
1404                                                      ixgbe_sfp_type_da_cu_core0;
1405                                 else
1406                                         hw->phy.sfp_type =
1407                                                      ixgbe_sfp_type_da_cu_core1;
1408                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1409                                 hw->phy.ops.read_i2c_eeprom(
1410                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1411                                                 &cable_spec);
1412                                 if (cable_spec &
1413                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1414                                         if (hw->bus.lan_id == 0)
1415                                                 hw->phy.sfp_type =
1416                                                 ixgbe_sfp_type_da_act_lmt_core0;
1417                                         else
1418                                                 hw->phy.sfp_type =
1419                                                 ixgbe_sfp_type_da_act_lmt_core1;
1420                                 } else {
1421                                         hw->phy.sfp_type =
1422                                                         ixgbe_sfp_type_unknown;
1423                                 }
1424                         } else if (comp_codes_10g &
1425                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1426                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1427                                 if (hw->bus.lan_id == 0)
1428                                         hw->phy.sfp_type =
1429                                                       ixgbe_sfp_type_srlr_core0;
1430                                 else
1431                                         hw->phy.sfp_type =
1432                                                       ixgbe_sfp_type_srlr_core1;
1433                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1434                                 if (hw->bus.lan_id == 0)
1435                                         hw->phy.sfp_type =
1436                                                 ixgbe_sfp_type_1g_cu_core0;
1437                                 else
1438                                         hw->phy.sfp_type =
1439                                                 ixgbe_sfp_type_1g_cu_core1;
1440                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1441                                 if (hw->bus.lan_id == 0)
1442                                         hw->phy.sfp_type =
1443                                                 ixgbe_sfp_type_1g_sx_core0;
1444                                 else
1445                                         hw->phy.sfp_type =
1446                                                 ixgbe_sfp_type_1g_sx_core1;
1447                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1448                                 if (hw->bus.lan_id == 0)
1449                                         hw->phy.sfp_type =
1450                                                 ixgbe_sfp_type_1g_lx_core0;
1451                                 else
1452                                         hw->phy.sfp_type =
1453                                                 ixgbe_sfp_type_1g_lx_core1;
1454                         } else {
1455                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1456                         }
1457                 }
1458
1459                 if (hw->phy.sfp_type != stored_sfp_type)
1460                         hw->phy.sfp_setup_needed = true;
1461
1462                 /* Determine if the SFP+ PHY is dual speed or not. */
1463                 hw->phy.multispeed_fiber = false;
1464                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1465                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1466                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1467                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1468                         hw->phy.multispeed_fiber = true;
1469
1470                 /* Determine PHY vendor */
1471                 if (hw->phy.type != ixgbe_phy_nl) {
1472                         hw->phy.id = identifier;
1473                         status = hw->phy.ops.read_i2c_eeprom(hw,
1474                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1475                                                     &oui_bytes[0]);
1476
1477                         if (status != IXGBE_SUCCESS)
1478                                 goto err_read_i2c_eeprom;
1479
1480                         status = hw->phy.ops.read_i2c_eeprom(hw,
1481                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1482                                                     &oui_bytes[1]);
1483
1484                         if (status != IXGBE_SUCCESS)
1485                                 goto err_read_i2c_eeprom;
1486
1487                         status = hw->phy.ops.read_i2c_eeprom(hw,
1488                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1489                                                     &oui_bytes[2]);
1490
1491                         if (status != IXGBE_SUCCESS)
1492                                 goto err_read_i2c_eeprom;
1493
1494                         vendor_oui =
1495                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1496                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1497                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1498
1499                         switch (vendor_oui) {
1500                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1501                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1502                                         hw->phy.type =
1503                                                     ixgbe_phy_sfp_passive_tyco;
1504                                 break;
1505                         case IXGBE_SFF_VENDOR_OUI_FTL:
1506                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1507                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1508                                 else
1509                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1510                                 break;
1511                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1512                                 hw->phy.type = ixgbe_phy_sfp_avago;
1513                                 break;
1514                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1515                                 hw->phy.type = ixgbe_phy_sfp_intel;
1516                                 break;
1517                         default:
1518                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1519                                         hw->phy.type =
1520                                                  ixgbe_phy_sfp_passive_unknown;
1521                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1522                                         hw->phy.type =
1523                                                 ixgbe_phy_sfp_active_unknown;
1524                                 else
1525                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1526                                 break;
1527                         }
1528                 }
1529
1530                 /* Allow any DA cable vendor */
1531                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1532                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1533                         status = IXGBE_SUCCESS;
1534                         goto out;
1535                 }
1536
1537                 /* Verify supported 1G SFP modules */
1538                 if (comp_codes_10g == 0 &&
1539                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1540                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1541                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1542                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1543                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1544                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1545                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1546                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1547                         goto out;
1548                 }
1549
1550                 /* Anything else 82598-based is supported */
1551                 if (hw->mac.type == ixgbe_mac_82598EB) {
1552                         status = IXGBE_SUCCESS;
1553                         goto out;
1554                 }
1555
1556                 ixgbe_get_device_caps(hw, &enforce_sfp);
1557                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1558                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1559                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1560                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1561                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1562                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1563                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1564                         /* Make sure we're a supported PHY type */
1565                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1566                                 status = IXGBE_SUCCESS;
1567                         } else {
1568                                 if (hw->allow_unsupported_sfp == true) {
1569                                         EWARN(hw, "WARNING: Intel (R) Network "
1570                                               "Connections are quality tested "
1571                                               "using Intel (R) Ethernet Optics."
1572                                               " Using untested modules is not "
1573                                               "supported and may cause unstable"
1574                                               " operation or damage to the "
1575                                               "module or the adapter. Intel "
1576                                               "Corporation is not responsible "
1577                                               "for any harm caused by using "
1578                                               "untested modules.\n", status);
1579                                         status = IXGBE_SUCCESS;
1580                                 } else {
1581                                         DEBUGOUT("SFP+ module not supported\n");
1582                                         hw->phy.type =
1583                                                 ixgbe_phy_sfp_unsupported;
1584                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1585                                 }
1586                         }
1587                 } else {
1588                         status = IXGBE_SUCCESS;
1589                 }
1590         }
1591
1592 out:
1593         return status;
1594
1595 err_read_i2c_eeprom:
1596         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1597         if (hw->phy.type != ixgbe_phy_nl) {
1598                 hw->phy.id = 0;
1599                 hw->phy.type = ixgbe_phy_unknown;
1600         }
1601         return IXGBE_ERR_SFP_NOT_PRESENT;
1602 }
1603
1604 /**
1605  *  ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1606  *  @hw: pointer to hardware structure
1607  *
1608  *  Determines physical layer capabilities of the current SFP.
1609  */
1610 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1611 {
1612         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1613         u8 comp_codes_10g = 0;
1614         u8 comp_codes_1g = 0;
1615
1616         DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1617
1618         hw->phy.ops.identify_sfp(hw);
1619         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1620                 return physical_layer;
1621
1622         switch (hw->phy.type) {
1623         case ixgbe_phy_sfp_passive_tyco:
1624         case ixgbe_phy_sfp_passive_unknown:
1625         case ixgbe_phy_qsfp_passive_unknown:
1626                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1627                 break;
1628         case ixgbe_phy_sfp_ftl_active:
1629         case ixgbe_phy_sfp_active_unknown:
1630         case ixgbe_phy_qsfp_active_unknown:
1631                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1632                 break;
1633         case ixgbe_phy_sfp_avago:
1634         case ixgbe_phy_sfp_ftl:
1635         case ixgbe_phy_sfp_intel:
1636         case ixgbe_phy_sfp_unknown:
1637                 hw->phy.ops.read_i2c_eeprom(hw,
1638                       IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1639                 hw->phy.ops.read_i2c_eeprom(hw,
1640                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1641                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1642                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1643                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1644                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1645                 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1646                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1647                 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1648                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1649                 break;
1650         case ixgbe_phy_qsfp_intel:
1651         case ixgbe_phy_qsfp_unknown:
1652                 hw->phy.ops.read_i2c_eeprom(hw,
1653                       IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1654                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1655                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1656                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1657                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1658                 break;
1659         default:
1660                 break;
1661         }
1662
1663         return physical_layer;
1664 }
1665
1666 /**
1667  *  ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1668  *  @hw: pointer to hardware structure
1669  *
1670  *  Searches for and identifies the QSFP module and assigns appropriate PHY type
1671  **/
1672 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1673 {
1674         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1675         u32 vendor_oui = 0;
1676         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1677         u8 identifier = 0;
1678         u8 comp_codes_1g = 0;
1679         u8 comp_codes_10g = 0;
1680         u8 oui_bytes[3] = {0, 0, 0};
1681         u16 enforce_sfp = 0;
1682         u8 connector = 0;
1683         u8 cable_length = 0;
1684         u8 device_tech = 0;
1685         bool active_cable = false;
1686
1687         DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1688
1689         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1690                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1691                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1692                 goto out;
1693         }
1694
1695         /* LAN ID is needed for I2C access */
1696         hw->mac.ops.set_lan_id(hw);
1697
1698         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1699                                              &identifier);
1700
1701         if (status != IXGBE_SUCCESS)
1702                 goto err_read_i2c_eeprom;
1703
1704         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1705                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1706                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1707                 goto out;
1708         }
1709
1710         hw->phy.id = identifier;
1711
1712         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1713                                              &comp_codes_10g);
1714
1715         if (status != IXGBE_SUCCESS)
1716                 goto err_read_i2c_eeprom;
1717
1718         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1719                                              &comp_codes_1g);
1720
1721         if (status != IXGBE_SUCCESS)
1722                 goto err_read_i2c_eeprom;
1723
1724         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1725                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1726                 if (hw->bus.lan_id == 0)
1727                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1728                 else
1729                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1730         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1731                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1732                 if (hw->bus.lan_id == 0)
1733                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1734                 else
1735                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1736         } else {
1737                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1738                         active_cable = true;
1739
1740                 if (!active_cable) {
1741                         /* check for active DA cables that pre-date
1742                          * SFF-8436 v3.6 */
1743                         hw->phy.ops.read_i2c_eeprom(hw,
1744                                         IXGBE_SFF_QSFP_CONNECTOR,
1745                                         &connector);
1746
1747                         hw->phy.ops.read_i2c_eeprom(hw,
1748                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1749                                         &cable_length);
1750
1751                         hw->phy.ops.read_i2c_eeprom(hw,
1752                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1753                                         &device_tech);
1754
1755                         if ((connector ==
1756                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1757                             (cable_length > 0) &&
1758                             ((device_tech >> 4) ==
1759                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1760                                 active_cable = true;
1761                 }
1762
1763                 if (active_cable) {
1764                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1765                         if (hw->bus.lan_id == 0)
1766                                 hw->phy.sfp_type =
1767                                                 ixgbe_sfp_type_da_act_lmt_core0;
1768                         else
1769                                 hw->phy.sfp_type =
1770                                                 ixgbe_sfp_type_da_act_lmt_core1;
1771                 } else {
1772                         /* unsupported module type */
1773                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1774                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1775                         goto out;
1776                 }
1777         }
1778
1779         if (hw->phy.sfp_type != stored_sfp_type)
1780                 hw->phy.sfp_setup_needed = true;
1781
1782         /* Determine if the QSFP+ PHY is dual speed or not. */
1783         hw->phy.multispeed_fiber = false;
1784         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1785            (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1786            ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1787            (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1788                 hw->phy.multispeed_fiber = true;
1789
1790         /* Determine PHY vendor for optical modules */
1791         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1792                               IXGBE_SFF_10GBASELR_CAPABLE))  {
1793                 status = hw->phy.ops.read_i2c_eeprom(hw,
1794                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1795                                             &oui_bytes[0]);
1796
1797                 if (status != IXGBE_SUCCESS)
1798                         goto err_read_i2c_eeprom;
1799
1800                 status = hw->phy.ops.read_i2c_eeprom(hw,
1801                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1802                                             &oui_bytes[1]);
1803
1804                 if (status != IXGBE_SUCCESS)
1805                         goto err_read_i2c_eeprom;
1806
1807                 status = hw->phy.ops.read_i2c_eeprom(hw,
1808                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1809                                             &oui_bytes[2]);
1810
1811                 if (status != IXGBE_SUCCESS)
1812                         goto err_read_i2c_eeprom;
1813
1814                 vendor_oui =
1815                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1816                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1817                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1818
1819                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1820                         hw->phy.type = ixgbe_phy_qsfp_intel;
1821                 else
1822                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1823
1824                 ixgbe_get_device_caps(hw, &enforce_sfp);
1825                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1826                         /* Make sure we're a supported PHY type */
1827                         if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1828                                 status = IXGBE_SUCCESS;
1829                         } else {
1830                                 if (hw->allow_unsupported_sfp == true) {
1831                                         EWARN(hw, "WARNING: Intel (R) Network "
1832                                               "Connections are quality tested "
1833                                               "using Intel (R) Ethernet Optics."
1834                                               " Using untested modules is not "
1835                                               "supported and may cause unstable"
1836                                               " operation or damage to the "
1837                                               "module or the adapter. Intel "
1838                                               "Corporation is not responsible "
1839                                               "for any harm caused by using "
1840                                               "untested modules.\n", status);
1841                                         status = IXGBE_SUCCESS;
1842                                 } else {
1843                                         DEBUGOUT("QSFP module not supported\n");
1844                                         hw->phy.type =
1845                                                 ixgbe_phy_sfp_unsupported;
1846                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1847                                 }
1848                         }
1849                 } else {
1850                         status = IXGBE_SUCCESS;
1851                 }
1852         }
1853
1854 out:
1855         return status;
1856
1857 err_read_i2c_eeprom:
1858         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1859         hw->phy.id = 0;
1860         hw->phy.type = ixgbe_phy_unknown;
1861
1862         return IXGBE_ERR_SFP_NOT_PRESENT;
1863 }
1864
1865
1866 /**
1867  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1868  *  @hw: pointer to hardware structure
1869  *  @list_offset: offset to the SFP ID list
1870  *  @data_offset: offset to the SFP data block
1871  *
1872  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1873  *  so it returns the offsets to the phy init sequence block.
1874  **/
1875 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1876                                         u16 *list_offset,
1877                                         u16 *data_offset)
1878 {
1879         u16 sfp_id;
1880         u16 sfp_type = hw->phy.sfp_type;
1881
1882         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1883
1884         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1885                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1886
1887         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1888                 return IXGBE_ERR_SFP_NOT_PRESENT;
1889
1890         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1891             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1892                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1893
1894         /*
1895          * Limiting active cables and 1G Phys must be initialized as
1896          * SR modules
1897          */
1898         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1899             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1900             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1901             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1902                 sfp_type = ixgbe_sfp_type_srlr_core0;
1903         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1904                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1905                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1906                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1907                 sfp_type = ixgbe_sfp_type_srlr_core1;
1908
1909         /* Read offset to PHY init contents */
1910         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1911                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1912                               "eeprom read at offset %d failed",
1913                               IXGBE_PHY_INIT_OFFSET_NL);
1914                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1915         }
1916
1917         if ((!*list_offset) || (*list_offset == 0xFFFF))
1918                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1919
1920         /* Shift offset to first ID word */
1921         (*list_offset)++;
1922
1923         /*
1924          * Find the matching SFP ID in the EEPROM
1925          * and program the init sequence
1926          */
1927         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1928                 goto err_phy;
1929
1930         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1931                 if (sfp_id == sfp_type) {
1932                         (*list_offset)++;
1933                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1934                                 goto err_phy;
1935                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1936                                 DEBUGOUT("SFP+ module not supported\n");
1937                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1938                         } else {
1939                                 break;
1940                         }
1941                 } else {
1942                         (*list_offset) += 2;
1943                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1944                                 goto err_phy;
1945                 }
1946         }
1947
1948         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1949                 DEBUGOUT("No matching SFP+ module found\n");
1950                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1951         }
1952
1953         return IXGBE_SUCCESS;
1954
1955 err_phy:
1956         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1957                       "eeprom read at offset %d failed", *list_offset);
1958         return IXGBE_ERR_PHY;
1959 }
1960
1961 /**
1962  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1963  *  @hw: pointer to hardware structure
1964  *  @byte_offset: EEPROM byte offset to read
1965  *  @eeprom_data: value read
1966  *
1967  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1968  **/
1969 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1970                                   u8 *eeprom_data)
1971 {
1972         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1973
1974         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1975                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1976                                          eeprom_data);
1977 }
1978
1979 /**
1980  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1981  *  @hw: pointer to hardware structure
1982  *  @byte_offset: byte offset at address 0xA2
1983  *  @eeprom_data: value read
1984  *
1985  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1986  **/
1987 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1988                                           u8 *sff8472_data)
1989 {
1990         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1991                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1992                                          sff8472_data);
1993 }
1994
1995 /**
1996  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1997  *  @hw: pointer to hardware structure
1998  *  @byte_offset: EEPROM byte offset to write
1999  *  @eeprom_data: value to write
2000  *
2001  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
2002  **/
2003 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
2004                                    u8 eeprom_data)
2005 {
2006         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
2007
2008         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
2009                                           IXGBE_I2C_EEPROM_DEV_ADDR,
2010                                           eeprom_data);
2011 }
2012
2013 /**
2014  * ixgbe_is_sfp_probe - Returns true if SFP is being detected
2015  * @hw: pointer to hardware structure
2016  * @offset: eeprom offset to be read
2017  * @addr: I2C address to be read
2018  */
2019 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
2020 {
2021         if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
2022             offset == IXGBE_SFF_IDENTIFIER &&
2023             hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2024                 return true;
2025         return false;
2026 }
2027
2028 /**
2029  *  ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
2030  *  @hw: pointer to hardware structure
2031  *  @byte_offset: byte offset to read
2032  *  @data: value read
2033  *  @lock: true if to take and release semaphore
2034  *
2035  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2036  *  a specified device address.
2037  **/
2038 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2039                                            u8 dev_addr, u8 *data, bool lock)
2040 {
2041         s32 status;
2042         u32 max_retry = 10;
2043         u32 retry = 0;
2044         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2045         bool nack = 1;
2046         *data = 0;
2047
2048         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2049
2050         if (hw->mac.type >= ixgbe_mac_X550)
2051                 max_retry = 3;
2052         if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2053                 max_retry = IXGBE_SFP_DETECT_RETRIES;
2054
2055         do {
2056                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2057                         return IXGBE_ERR_SWFW_SYNC;
2058
2059                 ixgbe_i2c_start(hw);
2060
2061                 /* Device Address and write indication */
2062                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2063                 if (status != IXGBE_SUCCESS)
2064                         goto fail;
2065
2066                 status = ixgbe_get_i2c_ack(hw);
2067                 if (status != IXGBE_SUCCESS)
2068                         goto fail;
2069
2070                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2071                 if (status != IXGBE_SUCCESS)
2072                         goto fail;
2073
2074                 status = ixgbe_get_i2c_ack(hw);
2075                 if (status != IXGBE_SUCCESS)
2076                         goto fail;
2077
2078                 ixgbe_i2c_start(hw);
2079
2080                 /* Device Address and read indication */
2081                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2082                 if (status != IXGBE_SUCCESS)
2083                         goto fail;
2084
2085                 status = ixgbe_get_i2c_ack(hw);
2086                 if (status != IXGBE_SUCCESS)
2087                         goto fail;
2088
2089                 status = ixgbe_clock_in_i2c_byte(hw, data);
2090                 if (status != IXGBE_SUCCESS)
2091                         goto fail;
2092
2093                 status = ixgbe_clock_out_i2c_bit(hw, nack);
2094                 if (status != IXGBE_SUCCESS)
2095                         goto fail;
2096
2097                 ixgbe_i2c_stop(hw);
2098                 if (lock)
2099                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2100                 return IXGBE_SUCCESS;
2101
2102 fail:
2103                 ixgbe_i2c_bus_clear(hw);
2104                 if (lock) {
2105                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2106                         msec_delay(100);
2107                 }
2108                 retry++;
2109                 if (retry < max_retry)
2110                         DEBUGOUT("I2C byte read error - Retrying.\n");
2111                 else
2112                         DEBUGOUT("I2C byte read error.\n");
2113
2114         } while (retry < max_retry);
2115
2116         return status;
2117 }
2118
2119 /**
2120  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2121  *  @hw: pointer to hardware structure
2122  *  @byte_offset: byte offset to read
2123  *  @data: value read
2124  *
2125  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2126  *  a specified device address.
2127  **/
2128 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2129                                 u8 dev_addr, u8 *data)
2130 {
2131         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2132                                                data, true);
2133 }
2134
2135 /**
2136  *  ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2137  *  @hw: pointer to hardware structure
2138  *  @byte_offset: byte offset to read
2139  *  @data: value read
2140  *
2141  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2142  *  a specified device address.
2143  **/
2144 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2145                                          u8 dev_addr, u8 *data)
2146 {
2147         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2148                                                data, false);
2149 }
2150
2151 /**
2152  *  ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2153  *  @hw: pointer to hardware structure
2154  *  @byte_offset: byte offset to write
2155  *  @data: value to write
2156  *  @lock: true if to take and release semaphore
2157  *
2158  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2159  *  a specified device address.
2160  **/
2161 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2162                                             u8 dev_addr, u8 data, bool lock)
2163 {
2164         s32 status;
2165         u32 max_retry = 1;
2166         u32 retry = 0;
2167         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2168
2169         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2170
2171         if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2172             IXGBE_SUCCESS)
2173                 return IXGBE_ERR_SWFW_SYNC;
2174
2175         do {
2176                 ixgbe_i2c_start(hw);
2177
2178                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2179                 if (status != IXGBE_SUCCESS)
2180                         goto fail;
2181
2182                 status = ixgbe_get_i2c_ack(hw);
2183                 if (status != IXGBE_SUCCESS)
2184                         goto fail;
2185
2186                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2187                 if (status != IXGBE_SUCCESS)
2188                         goto fail;
2189
2190                 status = ixgbe_get_i2c_ack(hw);
2191                 if (status != IXGBE_SUCCESS)
2192                         goto fail;
2193
2194                 status = ixgbe_clock_out_i2c_byte(hw, data);
2195                 if (status != IXGBE_SUCCESS)
2196                         goto fail;
2197
2198                 status = ixgbe_get_i2c_ack(hw);
2199                 if (status != IXGBE_SUCCESS)
2200                         goto fail;
2201
2202                 ixgbe_i2c_stop(hw);
2203                 if (lock)
2204                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2205                 return IXGBE_SUCCESS;
2206
2207 fail:
2208                 ixgbe_i2c_bus_clear(hw);
2209                 retry++;
2210                 if (retry < max_retry)
2211                         DEBUGOUT("I2C byte write error - Retrying.\n");
2212                 else
2213                         DEBUGOUT("I2C byte write error.\n");
2214         } while (retry < max_retry);
2215
2216         if (lock)
2217                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2218
2219         return status;
2220 }
2221
2222 /**
2223  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2224  *  @hw: pointer to hardware structure
2225  *  @byte_offset: byte offset to write
2226  *  @data: value to write
2227  *
2228  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2229  *  a specified device address.
2230  **/
2231 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2232                                  u8 dev_addr, u8 data)
2233 {
2234         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2235                                                 data, true);
2236 }
2237
2238 /**
2239  *  ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2240  *  @hw: pointer to hardware structure
2241  *  @byte_offset: byte offset to write
2242  *  @data: value to write
2243  *
2244  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2245  *  a specified device address.
2246  **/
2247 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2248                                           u8 dev_addr, u8 data)
2249 {
2250         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2251                                                 data, false);
2252 }
2253
2254 /**
2255  *  ixgbe_i2c_start - Sets I2C start condition
2256  *  @hw: pointer to hardware structure
2257  *
2258  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
2259  *  Set bit-bang mode on X550 hardware.
2260  **/
2261 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2262 {
2263         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2264
2265         DEBUGFUNC("ixgbe_i2c_start");
2266
2267         i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2268
2269         /* Start condition must begin with data and clock high */
2270         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2271         ixgbe_raise_i2c_clk(hw, &i2cctl);
2272
2273         /* Setup time for start condition (4.7us) */
2274         usec_delay(IXGBE_I2C_T_SU_STA);
2275
2276         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2277
2278         /* Hold time for start condition (4us) */
2279         usec_delay(IXGBE_I2C_T_HD_STA);
2280
2281         ixgbe_lower_i2c_clk(hw, &i2cctl);
2282
2283         /* Minimum low period of clock is 4.7 us */
2284         usec_delay(IXGBE_I2C_T_LOW);
2285
2286 }
2287
2288 /**
2289  *  ixgbe_i2c_stop - Sets I2C stop condition
2290  *  @hw: pointer to hardware structure
2291  *
2292  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
2293  *  Disables bit-bang mode and negates data output enable on X550
2294  *  hardware.
2295  **/
2296 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2297 {
2298         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2299         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2300         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2301         u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2302
2303         DEBUGFUNC("ixgbe_i2c_stop");
2304
2305         /* Stop condition must begin with data low and clock high */
2306         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2307         ixgbe_raise_i2c_clk(hw, &i2cctl);
2308
2309         /* Setup time for stop condition (4us) */
2310         usec_delay(IXGBE_I2C_T_SU_STO);
2311
2312         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2313
2314         /* bus free time between stop and start (4.7us)*/
2315         usec_delay(IXGBE_I2C_T_BUF);
2316
2317         if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2318                 i2cctl &= ~bb_en_bit;
2319                 i2cctl |= data_oe_bit | clk_oe_bit;
2320                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2321                 IXGBE_WRITE_FLUSH(hw);
2322         }
2323 }
2324
2325 /**
2326  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2327  *  @hw: pointer to hardware structure
2328  *  @data: data byte to clock in
2329  *
2330  *  Clocks in one byte data via I2C data/clock
2331  **/
2332 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2333 {
2334         s32 i;
2335         bool bit = 0;
2336
2337         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2338
2339         *data = 0;
2340         for (i = 7; i >= 0; i--) {
2341                 ixgbe_clock_in_i2c_bit(hw, &bit);
2342                 *data |= bit << i;
2343         }
2344
2345         return IXGBE_SUCCESS;
2346 }
2347
2348 /**
2349  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2350  *  @hw: pointer to hardware structure
2351  *  @data: data byte clocked out
2352  *
2353  *  Clocks out one byte data via I2C data/clock
2354  **/
2355 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2356 {
2357         s32 status = IXGBE_SUCCESS;
2358         s32 i;
2359         u32 i2cctl;
2360         bool bit;
2361
2362         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2363
2364         for (i = 7; i >= 0; i--) {
2365                 bit = (data >> i) & 0x1;
2366                 status = ixgbe_clock_out_i2c_bit(hw, bit);
2367
2368                 if (status != IXGBE_SUCCESS)
2369                         break;
2370         }
2371
2372         /* Release SDA line (set high) */
2373         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2374         i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2375         i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2376         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2377         IXGBE_WRITE_FLUSH(hw);
2378
2379         return status;
2380 }
2381
2382 /**
2383  *  ixgbe_get_i2c_ack - Polls for I2C ACK
2384  *  @hw: pointer to hardware structure
2385  *
2386  *  Clocks in/out one bit via I2C data/clock
2387  **/
2388 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2389 {
2390         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2391         s32 status = IXGBE_SUCCESS;
2392         u32 i = 0;
2393         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2394         u32 timeout = 10;
2395         bool ack = 1;
2396
2397         DEBUGFUNC("ixgbe_get_i2c_ack");
2398
2399         if (data_oe_bit) {
2400                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2401                 i2cctl |= data_oe_bit;
2402                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2403                 IXGBE_WRITE_FLUSH(hw);
2404         }
2405         ixgbe_raise_i2c_clk(hw, &i2cctl);
2406
2407         /* Minimum high period of clock is 4us */
2408         usec_delay(IXGBE_I2C_T_HIGH);
2409
2410         /* Poll for ACK.  Note that ACK in I2C spec is
2411          * transition from 1 to 0 */
2412         for (i = 0; i < timeout; i++) {
2413                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2414                 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2415
2416                 usec_delay(1);
2417                 if (!ack)
2418                         break;
2419         }
2420
2421         if (ack) {
2422                 DEBUGOUT("I2C ack was not received.\n");
2423                 status = IXGBE_ERR_I2C;
2424         }
2425
2426         ixgbe_lower_i2c_clk(hw, &i2cctl);
2427
2428         /* Minimum low period of clock is 4.7 us */
2429         usec_delay(IXGBE_I2C_T_LOW);
2430
2431         return status;
2432 }
2433
2434 /**
2435  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2436  *  @hw: pointer to hardware structure
2437  *  @data: read data value
2438  *
2439  *  Clocks in one bit via I2C data/clock
2440  **/
2441 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2442 {
2443         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2444         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2445
2446         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2447
2448         if (data_oe_bit) {
2449                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2450                 i2cctl |= data_oe_bit;
2451                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2452                 IXGBE_WRITE_FLUSH(hw);
2453         }
2454         ixgbe_raise_i2c_clk(hw, &i2cctl);
2455
2456         /* Minimum high period of clock is 4us */
2457         usec_delay(IXGBE_I2C_T_HIGH);
2458
2459         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2460         *data = ixgbe_get_i2c_data(hw, &i2cctl);
2461
2462         ixgbe_lower_i2c_clk(hw, &i2cctl);
2463
2464         /* Minimum low period of clock is 4.7 us */
2465         usec_delay(IXGBE_I2C_T_LOW);
2466
2467         return IXGBE_SUCCESS;
2468 }
2469
2470 /**
2471  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2472  *  @hw: pointer to hardware structure
2473  *  @data: data value to write
2474  *
2475  *  Clocks out one bit via I2C data/clock
2476  **/
2477 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2478 {
2479         s32 status;
2480         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2481
2482         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2483
2484         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2485         if (status == IXGBE_SUCCESS) {
2486                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2487
2488                 /* Minimum high period of clock is 4us */
2489                 usec_delay(IXGBE_I2C_T_HIGH);
2490
2491                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2492
2493                 /* Minimum low period of clock is 4.7 us.
2494                  * This also takes care of the data hold time.
2495                  */
2496                 usec_delay(IXGBE_I2C_T_LOW);
2497         } else {
2498                 status = IXGBE_ERR_I2C;
2499                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2500                              "I2C data was not set to %X\n", data);
2501         }
2502
2503         return status;
2504 }
2505
2506 /**
2507  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2508  *  @hw: pointer to hardware structure
2509  *  @i2cctl: Current value of I2CCTL register
2510  *
2511  *  Raises the I2C clock line '0'->'1'
2512  *  Negates the I2C clock output enable on X550 hardware.
2513  **/
2514 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2515 {
2516         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2517         u32 i = 0;
2518         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2519         u32 i2cctl_r = 0;
2520
2521         DEBUGFUNC("ixgbe_raise_i2c_clk");
2522
2523         if (clk_oe_bit) {
2524                 *i2cctl |= clk_oe_bit;
2525                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2526         }
2527
2528         for (i = 0; i < timeout; i++) {
2529                 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2530
2531                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2532                 IXGBE_WRITE_FLUSH(hw);
2533                 /* SCL rise time (1000ns) */
2534                 usec_delay(IXGBE_I2C_T_RISE);
2535
2536                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2537                 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2538                         break;
2539         }
2540 }
2541
2542 /**
2543  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2544  *  @hw: pointer to hardware structure
2545  *  @i2cctl: Current value of I2CCTL register
2546  *
2547  *  Lowers the I2C clock line '1'->'0'
2548  *  Asserts the I2C clock output enable on X550 hardware.
2549  **/
2550 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2551 {
2552         DEBUGFUNC("ixgbe_lower_i2c_clk");
2553
2554         *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2555         *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2556
2557         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2558         IXGBE_WRITE_FLUSH(hw);
2559
2560         /* SCL fall time (300ns) */
2561         usec_delay(IXGBE_I2C_T_FALL);
2562 }
2563
2564 /**
2565  *  ixgbe_set_i2c_data - Sets the I2C data bit
2566  *  @hw: pointer to hardware structure
2567  *  @i2cctl: Current value of I2CCTL register
2568  *  @data: I2C data value (0 or 1) to set
2569  *
2570  *  Sets the I2C data bit
2571  *  Asserts the I2C data output enable on X550 hardware.
2572  **/
2573 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2574 {
2575         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2576         s32 status = IXGBE_SUCCESS;
2577
2578         DEBUGFUNC("ixgbe_set_i2c_data");
2579
2580         if (data)
2581                 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2582         else
2583                 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2584         *i2cctl &= ~data_oe_bit;
2585
2586         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2587         IXGBE_WRITE_FLUSH(hw);
2588
2589         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2590         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2591
2592         if (!data)      /* Can't verify data in this case */
2593                 return IXGBE_SUCCESS;
2594         if (data_oe_bit) {
2595                 *i2cctl |= data_oe_bit;
2596                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2597                 IXGBE_WRITE_FLUSH(hw);
2598         }
2599
2600         /* Verify data was set correctly */
2601         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2602         if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2603                 status = IXGBE_ERR_I2C;
2604                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2605                              "Error - I2C data was not set to %X.\n",
2606                              data);
2607         }
2608
2609         return status;
2610 }
2611
2612 /**
2613  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2614  *  @hw: pointer to hardware structure
2615  *  @i2cctl: Current value of I2CCTL register
2616  *
2617  *  Returns the I2C data bit value
2618  *  Negates the I2C data output enable on X550 hardware.
2619  **/
2620 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2621 {
2622         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2623         bool data;
2624
2625         DEBUGFUNC("ixgbe_get_i2c_data");
2626
2627         if (data_oe_bit) {
2628                 *i2cctl |= data_oe_bit;
2629                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2630                 IXGBE_WRITE_FLUSH(hw);
2631                 usec_delay(IXGBE_I2C_T_FALL);
2632         }
2633
2634         if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2635                 data = 1;
2636         else
2637                 data = 0;
2638
2639         return data;
2640 }
2641
2642 /**
2643  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2644  *  @hw: pointer to hardware structure
2645  *
2646  *  Clears the I2C bus by sending nine clock pulses.
2647  *  Used when data line is stuck low.
2648  **/
2649 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2650 {
2651         u32 i2cctl;
2652         u32 i;
2653
2654         DEBUGFUNC("ixgbe_i2c_bus_clear");
2655
2656         ixgbe_i2c_start(hw);
2657         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2658
2659         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2660
2661         for (i = 0; i < 9; i++) {
2662                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2663
2664                 /* Min high period of clock is 4us */
2665                 usec_delay(IXGBE_I2C_T_HIGH);
2666
2667                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2668
2669                 /* Min low period of clock is 4.7us*/
2670                 usec_delay(IXGBE_I2C_T_LOW);
2671         }
2672
2673         ixgbe_i2c_start(hw);
2674
2675         /* Put the i2c bus back to default state */
2676         ixgbe_i2c_stop(hw);
2677 }
2678
2679 /**
2680  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2681  *  @hw: pointer to hardware structure
2682  *
2683  *  Checks if the LASI temp alarm status was triggered due to overtemp
2684  **/
2685 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2686 {
2687         s32 status = IXGBE_SUCCESS;
2688         u16 phy_data = 0;
2689
2690         DEBUGFUNC("ixgbe_tn_check_overtemp");
2691
2692         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2693                 goto out;
2694
2695         /* Check that the LASI temp alarm status was triggered */
2696         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2697                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2698
2699         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2700                 goto out;
2701
2702         status = IXGBE_ERR_OVERTEMP;
2703         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2704 out:
2705         return status;
2706 }
2707
2708 /**
2709  * ixgbe_set_copper_phy_power - Control power for copper phy
2710  * @hw: pointer to hardware structure
2711  * @on: true for on, false for off
2712  */
2713 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2714 {
2715         u32 status;
2716         u16 reg;
2717
2718         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2719                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2720                                       &reg);
2721         if (status)
2722                 return status;
2723
2724         if (on) {
2725                 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2726         } else {
2727                 if (ixgbe_check_reset_blocked(hw))
2728                         return 0;
2729                 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2730         }
2731
2732         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2733                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2734                                        reg);
2735         return status;
2736 }