drivers/net/ixgbe/base/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_api.h"
  35 #include "ixgbe_common.h"
  36 #include "ixgbe_phy.h"
  37
  38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
  39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  50                                           u8 *sff8472_data);
  51
  52 /**
  53  * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
  54  * @hw: pointer to the hardware structure
  55  * @byte: byte to send
  56  *
  57  * Returns an error code on error.
  58  */
  59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
  60 {
  61         s32 status;
  62
  63         status = ixgbe_clock_out_i2c_byte(hw, byte);
  64         if (status)
  65                 return status;
  66         return ixgbe_get_i2c_ack(hw);
  67 }
  68
  69 /**
  70  * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
  71  * @hw: pointer to the hardware structure
  72  * @byte: pointer to a u8 to receive the byte
  73  *
  74  * Returns an error code on error.
  75  */
  76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
  77 {
  78         s32 status;
  79
  80         status = ixgbe_clock_in_i2c_byte(hw, byte);
  81         if (status)
  82                 return status;
  83         /* ACK */
  84         return ixgbe_clock_out_i2c_bit(hw, false);
  85 }
  86
  87 /**
  88  * ixgbe_ones_comp_byte_add - Perform one's complement addition
  89  * @add1 - addend 1
  90  * @add2 - addend 2
  91  *
  92  * Returns one's complement 8-bit sum.
  93  */
  94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
  95 {
  96         u16 sum = add1 + add2;
  97
  98         sum = (sum & 0xFF) + (sum >> 8);
  99         return sum & 0xFF;
 100 }
 101
 102 /**
 103  * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
 104  * @hw: pointer to the hardware structure
 105  * @addr: I2C bus address to read from
 106  * @reg: I2C device register to read from
 107  * @val: pointer to location to receive read value
 108  * @lock: true if to take and release semaphore
 109  *
 110  * Returns an error code on error.
 111  */
 112 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 113                                         u16 *val, bool lock)
 114 {
 115         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 116         int max_retry = 10;
 117         int retry = 0;
 118         u8 csum_byte;
 119         u8 high_bits;
 120         u8 low_bits;
 121         u8 reg_high;
 122         u8 csum;
 123
 124         if (hw->mac.type >= ixgbe_mac_X550)
 125                 max_retry = 3;
 126         reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
 127         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 128         csum = ~csum;
 129         do {
 130                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 131                         return IXGBE_ERR_SWFW_SYNC;
 132                 ixgbe_i2c_start(hw);
 133                 /* Device Address and write indication */
 134                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 135                         goto fail;
 136                 /* Write bits 14:8 */
 137                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 138                         goto fail;
 139                 /* Write bits 7:0 */
 140                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 141                         goto fail;
 142                 /* Write csum */
 143                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 144                         goto fail;
 145                 /* Re-start condition */
 146                 ixgbe_i2c_start(hw);
 147                 /* Device Address and read indication */
 148                 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
 149                         goto fail;
 150                 /* Get upper bits */
 151                 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
 152                         goto fail;
 153                 /* Get low bits */
 154                 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
 155                         goto fail;
 156                 /* Get csum */
 157                 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
 158                         goto fail;
 159                 /* NACK */
 160                 if (ixgbe_clock_out_i2c_bit(hw, false))
 161                         goto fail;
 162                 ixgbe_i2c_stop(hw);
 163                 if (lock)
 164                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 165                 *val = (high_bits << 8) | low_bits;
 166                 return 0;
 167
 168 fail:
 169                 ixgbe_i2c_bus_clear(hw);
 170                 if (lock)
 171                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 172                 retry++;
 173                 if (retry < max_retry)
 174                         DEBUGOUT("I2C byte read combined error - Retrying.\n");
 175                 else
 176                         DEBUGOUT("I2C byte read combined error.\n");
 177         } while (retry < max_retry);
 178
 179         return IXGBE_ERR_I2C;
 180 }
 181
 182 /**
 183  * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
 184  * @hw: pointer to the hardware structure
 185  * @addr: I2C bus address to write to
 186  * @reg: I2C device register to write to
 187  * @val: value to write
 188  * @lock: true if to take and release semaphore
 189  *
 190  * Returns an error code on error.
 191  */
 192 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 193                                          u16 val, bool lock)
 194 {
 195         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 196         int max_retry = 1;
 197         int retry = 0;
 198         u8 reg_high;
 199         u8 csum;
 200
 201         reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
 202         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 203         csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
 204         csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
 205         csum = ~csum;
 206         do {
 207                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 208                         return IXGBE_ERR_SWFW_SYNC;
 209                 ixgbe_i2c_start(hw);
 210                 /* Device Address and write indication */
 211                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 212                         goto fail;
 213                 /* Write bits 14:8 */
 214                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 215                         goto fail;
 216                 /* Write bits 7:0 */
 217                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 218                         goto fail;
 219                 /* Write data 15:8 */
 220                 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
 221                         goto fail;
 222                 /* Write data 7:0 */
 223                 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
 224                         goto fail;
 225                 /* Write csum */
 226                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 227                         goto fail;
 228                 ixgbe_i2c_stop(hw);
 229                 if (lock)
 230                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 231                 return 0;
 232
 233 fail:
 234                 ixgbe_i2c_bus_clear(hw);
 235                 if (lock)
 236                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 237                 retry++;
 238                 if (retry < max_retry)
 239                         DEBUGOUT("I2C byte write combined error - Retrying.\n");
 240                 else
 241                         DEBUGOUT("I2C byte write combined error.\n");
 242         } while (retry < max_retry);
 243
 244         return IXGBE_ERR_I2C;
 245 }
 246
 247 /**
 248  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
 249  *  @hw: pointer to the hardware structure
 250  *
 251  *  Initialize the function pointers.
 252  **/
 253 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
 254 {
 255         struct ixgbe_phy_info *phy = &hw->phy;
 256
 257         DEBUGFUNC("ixgbe_init_phy_ops_generic");
 258
 259         /* PHY */
 260         phy->ops.identify = ixgbe_identify_phy_generic;
 261         phy->ops.reset = ixgbe_reset_phy_generic;
 262         phy->ops.read_reg = ixgbe_read_phy_reg_generic;
 263         phy->ops.write_reg = ixgbe_write_phy_reg_generic;
 264         phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
 265         phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
 266         phy->ops.setup_link = ixgbe_setup_phy_link_generic;
 267         phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
 268         phy->ops.check_link = NULL;
 269         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
 270         phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
 271         phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
 272         phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
 273         phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
 274         phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
 275         phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
 276         phy->ops.identify_sfp = ixgbe_identify_module_generic;
 277         phy->sfp_type = ixgbe_sfp_type_unknown;
 278         phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
 279         phy->ops.write_i2c_byte_unlocked =
 280                                 ixgbe_write_i2c_byte_generic_unlocked;
 281         phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
 282         return IXGBE_SUCCESS;
 283 }
 284
 285 /**
 286  * ixgbe_probe_phy - Probe a single address for a PHY
 287  * @hw: pointer to hardware structure
 288  * @phy_addr: PHY address to probe
 289  *
 290  * Returns true if PHY found
 291  */
 292 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
 293 {
 294         u16 ext_ability = 0;
 295
 296         if (!ixgbe_validate_phy_addr(hw, phy_addr))
 297                 return false;
 298
 299         if (ixgbe_get_phy_id(hw))
 300                 return false;
 301
 302         hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
 303
 304         if (hw->phy.type == ixgbe_phy_unknown) {
 305                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
 306                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
 307                 if (ext_ability &
 308                     (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 309                      IXGBE_MDIO_PHY_1000BASET_ABILITY))
 310                         hw->phy.type = ixgbe_phy_cu_unknown;
 311                 else
 312                         hw->phy.type = ixgbe_phy_generic;
 313         }
 314
 315         return true;
 316 }
 317
 318 /**
 319  *  ixgbe_identify_phy_generic - Get physical layer module
 320  *  @hw: pointer to hardware structure
 321  *
 322  *  Determines the physical layer module found on the current adapter.
 323  **/
 324 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 325 {
 326         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 327         u16 phy_addr;
 328
 329         DEBUGFUNC("ixgbe_identify_phy_generic");
 330
 331         if (!hw->phy.phy_semaphore_mask) {
 332                 if (hw->bus.lan_id)
 333                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 334                 else
 335                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 336         }
 337
 338         if (hw->phy.type != ixgbe_phy_unknown)
 339                 return IXGBE_SUCCESS;
 340
 341         if (hw->phy.nw_mng_if_sel) {
 342                 phy_addr = (hw->phy.nw_mng_if_sel &
 343                             IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
 344                            IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
 345                 if (ixgbe_probe_phy(hw, phy_addr))
 346                         return IXGBE_SUCCESS;
 347                 else
 348                         return IXGBE_ERR_PHY_ADDR_INVALID;
 349         }
 350
 351         for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 352                 if (ixgbe_probe_phy(hw, phy_addr)) {
 353                         status = IXGBE_SUCCESS;
 354                         break;
 355                 }
 356         }
 357
 358         /* Certain media types do not have a phy so an address will not
 359          * be found and the code will take this path.  Caller has to
 360          * decide if it is an error or not.
 361          */
 362         if (status != IXGBE_SUCCESS)
 363                 hw->phy.addr = 0;
 364
 365         return status;
 366 }
 367
 368 /**
 369  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 370  * @hw: pointer to the hardware structure
 371  *
 372  * This function checks the MMNGC.MNG_VETO bit to see if there are
 373  * any constraints on link from manageability.  For MAC's that don't
 374  * have this bit just return faluse since the link can not be blocked
 375  * via this method.
 376  **/
 377 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 378 {
 379         u32 mmngc;
 380
 381         DEBUGFUNC("ixgbe_check_reset_blocked");
 382
 383         /* If we don't have this bit, it can't be blocking */
 384         if (hw->mac.type == ixgbe_mac_82598EB)
 385                 return false;
 386
 387         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 388         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 389                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 390                               "MNG_VETO bit detected.\n");
 391                 return true;
 392         }
 393
 394         return false;
 395 }
 396
 397 /**
 398  *  ixgbe_validate_phy_addr - Determines phy address is valid
 399  *  @hw: pointer to hardware structure
 400  *
 401  **/
 402 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 403 {
 404         u16 phy_id = 0;
 405         bool valid = false;
 406
 407         DEBUGFUNC("ixgbe_validate_phy_addr");
 408
 409         hw->phy.addr = phy_addr;
 410         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 411                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 412
 413         if (phy_id != 0xFFFF && phy_id != 0x0)
 414                 valid = true;
 415
 416         return valid;
 417 }
 418
 419 /**
 420  *  ixgbe_get_phy_id - Get the phy type
 421  *  @hw: pointer to hardware structure
 422  *
 423  **/
 424 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 425 {
 426         u32 status;
 427         u16 phy_id_high = 0;
 428         u16 phy_id_low = 0;
 429
 430         DEBUGFUNC("ixgbe_get_phy_id");
 431
 432         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 433                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 434                                       &phy_id_high);
 435
 436         if (status == IXGBE_SUCCESS) {
 437                 hw->phy.id = (u32)(phy_id_high << 16);
 438                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 439                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 440                                               &phy_id_low);
 441                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 442                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 443         }
 444         return status;
 445 }
 446
 447 /**
 448  *  ixgbe_get_phy_type_from_id - Get the phy type
 449  *  @phy_id: PHY ID information
 450  *
 451  **/
 452 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 453 {
 454         enum ixgbe_phy_type phy_type;
 455
 456         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 457
 458         switch (phy_id) {
 459         case TN1010_PHY_ID:
 460                 phy_type = ixgbe_phy_tn;
 461                 break;
 462         case X550_PHY_ID1:
 463         case X550_PHY_ID2:
 464         case X550_PHY_ID3:
 465         case X540_PHY_ID:
 466                 phy_type = ixgbe_phy_aq;
 467                 break;
 468         case QT2022_PHY_ID:
 469                 phy_type = ixgbe_phy_qt;
 470                 break;
 471         case ATH_PHY_ID:
 472                 phy_type = ixgbe_phy_nl;
 473                 break;
 474         case X557_PHY_ID:
 475         case X557_PHY_ID2:
 476                 phy_type = ixgbe_phy_x550em_ext_t;
 477                 break;
 478         case IXGBE_M88E1500_E_PHY_ID:
 479         case IXGBE_M88E1543_E_PHY_ID:
 480                 phy_type = ixgbe_phy_m88;
 481                 break;
 482         default:
 483                 phy_type = ixgbe_phy_unknown;
 484                 break;
 485         }
 486         return phy_type;
 487 }
 488
 489 /**
 490  *  ixgbe_reset_phy_generic - Performs a PHY reset
 491  *  @hw: pointer to hardware structure
 492  **/
 493 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 494 {
 495         u32 i;
 496         u16 ctrl = 0;
 497         s32 status = IXGBE_SUCCESS;
 498
 499         DEBUGFUNC("ixgbe_reset_phy_generic");
 500
 501         if (hw->phy.type == ixgbe_phy_unknown)
 502                 status = ixgbe_identify_phy_generic(hw);
 503
 504         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 505                 goto out;
 506
 507         /* Don't reset PHY if it's shut down due to overtemp. */
 508         if (!hw->phy.reset_if_overtemp &&
 509             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 510                 goto out;
 511
 512         /* Blocked by MNG FW so bail */
 513         if (ixgbe_check_reset_blocked(hw))
 514                 goto out;
 515
 516         /*
 517          * Perform soft PHY reset to the PHY_XS.
 518          * This will cause a soft reset to the PHY
 519          */
 520         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 521                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 522                               IXGBE_MDIO_PHY_XS_RESET);
 523
 524         /*
 525          * Poll for reset bit to self-clear indicating reset is complete.
 526          * Some PHYs could take up to 3 seconds to complete and need about
 527          * 1.7 usec delay after the reset is complete.
 528          */
 529         for (i = 0; i < 30; i++) {
 530                 msec_delay(100);
 531                 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
 532                         status = hw->phy.ops.read_reg(hw,
 533                                                   IXGBE_MDIO_TX_VENDOR_ALARMS_3,
 534                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 535                                                   &ctrl);
 536                         if (status != IXGBE_SUCCESS)
 537                                 return status;
 538
 539                         if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
 540                                 usec_delay(2);
 541                                 break;
 542                         }
 543                 } else {
 544                         status = hw->phy.ops.read_reg(hw,
 545                                                      IXGBE_MDIO_PHY_XS_CONTROL,
 546                                                      IXGBE_MDIO_PHY_XS_DEV_TYPE,
 547                                                      &ctrl);
 548                         if (status != IXGBE_SUCCESS)
 549                                 return status;
 550
 551                         if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 552                                 usec_delay(2);
 553                                 break;
 554                         }
 555                 }
 556         }
 557
 558         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 559                 status = IXGBE_ERR_RESET_FAILED;
 560                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 561                              "PHY reset polling failed to complete.\n");
 562         }
 563
 564 out:
 565         return status;
 566 }
 567
 568 /**
 569  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 570  *  the SWFW lock
 571  *  @hw: pointer to hardware structure
 572  *  @reg_addr: 32 bit address of PHY register to read
 573  *  @phy_data: Pointer to read data from PHY register
 574  **/
 575 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 576                        u16 *phy_data)
 577 {
 578         u32 i, data, command;
 579
 580         /* Setup and write the address cycle command */
 581         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 582                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 583                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 584                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 585
 586         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 587
 588         /*
 589          * Check every 10 usec to see if the address cycle completed.
 590          * The MDI Command bit will clear when the operation is
 591          * complete
 592          */
 593         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 594                 usec_delay(10);
 595
 596                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 597                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 598                                 break;
 599         }
 600
 601
 602         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 603                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 604                 return IXGBE_ERR_PHY;
 605         }
 606
 607         /*
 608          * Address cycle complete, setup and write the read
 609          * command
 610          */
 611         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 612                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 613                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 614                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 615
 616         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 617
 618         /*
 619          * Check every 10 usec to see if the address cycle
 620          * completed. The MDI Command bit will clear when the
 621          * operation is complete
 622          */
 623         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 624                 usec_delay(10);
 625
 626                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 627                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 628                         break;
 629         }
 630
 631         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 632                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 633                 return IXGBE_ERR_PHY;
 634         }
 635
 636         /*
 637          * Read operation is complete.  Get the data
 638          * from MSRWD
 639          */
 640         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 641         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 642         *phy_data = (u16)(data);
 643
 644         return IXGBE_SUCCESS;
 645 }
 646
 647 /**
 648  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 649  *  using the SWFW lock - this function is needed in most cases
 650  *  @hw: pointer to hardware structure
 651  *  @reg_addr: 32 bit address of PHY register to read
 652  *  @phy_data: Pointer to read data from PHY register
 653  **/
 654 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 655                                u32 device_type, u16 *phy_data)
 656 {
 657         s32 status;
 658         u32 gssr = hw->phy.phy_semaphore_mask;
 659
 660         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 661
 662         if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
 663                 return IXGBE_ERR_SWFW_SYNC;
 664
 665         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
 666
 667         hw->mac.ops.release_swfw_sync(hw, gssr);
 668
 669         return status;
 670 }
 671
 672 /**
 673  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 674  *  without SWFW lock
 675  *  @hw: pointer to hardware structure
 676  *  @reg_addr: 32 bit PHY register to write
 677  *  @device_type: 5 bit device type
 678  *  @phy_data: Data to write to the PHY register
 679  **/
 680 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 681                                 u32 device_type, u16 phy_data)
 682 {
 683         u32 i, command;
 684
 685         /* Put the data in the MDI single read and write data register*/
 686         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 687
 688         /* Setup and write the address cycle command */
 689         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 690                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 691                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 692                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 693
 694         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 695
 696         /*
 697          * Check every 10 usec to see if the address cycle completed.
 698          * The MDI Command bit will clear when the operation is
 699          * complete
 700          */
 701         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 702                 usec_delay(10);
 703
 704                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 705                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 706                         break;
 707         }
 708
 709         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 710                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 711                 return IXGBE_ERR_PHY;
 712         }
 713
 714         /*
 715          * Address cycle complete, setup and write the write
 716          * command
 717          */
 718         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 719                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 720                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 721                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 722
 723         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 724
 725         /*
 726          * Check every 10 usec to see if the address cycle
 727          * completed. The MDI Command bit will clear when the
 728          * operation is complete
 729          */
 730         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 731                 usec_delay(10);
 732
 733                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 734                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 735                         break;
 736         }
 737
 738         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 739                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 740                 return IXGBE_ERR_PHY;
 741         }
 742
 743         return IXGBE_SUCCESS;
 744 }
 745
 746 /**
 747  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 748  *  using SWFW lock- this function is needed in most cases
 749  *  @hw: pointer to hardware structure
 750  *  @reg_addr: 32 bit PHY register to write
 751  *  @device_type: 5 bit device type
 752  *  @phy_data: Data to write to the PHY register
 753  **/
 754 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 755                                 u32 device_type, u16 phy_data)
 756 {
 757         s32 status;
 758         u32 gssr = hw->phy.phy_semaphore_mask;
 759
 760         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 761
 762         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 763                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
 764                                                  phy_data);
 765                 hw->mac.ops.release_swfw_sync(hw, gssr);
 766         } else {
 767                 status = IXGBE_ERR_SWFW_SYNC;
 768         }
 769
 770         return status;
 771 }
 772
 773 /**
 774  *  ixgbe_setup_phy_link_generic - Set and restart auto-neg
 775  *  @hw: pointer to hardware structure
 776  *
 777  *  Restart auto-negotiation and PHY and waits for completion.
 778  **/
 779 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 780 {
 781         s32 status = IXGBE_SUCCESS;
 782         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 783         bool autoneg = false;
 784         ixgbe_link_speed speed;
 785
 786         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 787
 788         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 789
 790         /* Set or unset auto-negotiation 10G advertisement */
 791         hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 792                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 793                              &autoneg_reg);
 794
 795         autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 796         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
 797             (speed & IXGBE_LINK_SPEED_10GB_FULL))
 798                 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 799
 800         hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 801                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 802                               autoneg_reg);
 803
 804         hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 805                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 806                              &autoneg_reg);
 807
 808         if (hw->mac.type == ixgbe_mac_X550) {
 809                 /* Set or unset auto-negotiation 5G advertisement */
 810                 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
 811                 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
 812                     (speed & IXGBE_LINK_SPEED_5GB_FULL))
 813                         autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
 814
 815                 /* Set or unset auto-negotiation 2.5G advertisement */
 816                 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
 817                 if ((hw->phy.autoneg_advertised &
 818                      IXGBE_LINK_SPEED_2_5GB_FULL) &&
 819                     (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
 820                         autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
 821         }
 822
 823         /* Set or unset auto-negotiation 1G advertisement */
 824         autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 825         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
 826             (speed & IXGBE_LINK_SPEED_1GB_FULL))
 827                 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 828
 829         hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 830                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 831                               autoneg_reg);
 832
 833         /* Set or unset auto-negotiation 100M advertisement */
 834         hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 835                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 836                              &autoneg_reg);
 837
 838         autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 839                          IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 840         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
 841             (speed & IXGBE_LINK_SPEED_100_FULL))
 842                 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 843
 844         hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 845                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 846                               autoneg_reg);
 847
 848         /* Blocked by MNG FW so don't reset PHY */
 849         if (ixgbe_check_reset_blocked(hw))
 850                 return status;
 851
 852         /* Restart PHY auto-negotiation. */
 853         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 854                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 855
 856         autoneg_reg |= IXGBE_MII_RESTART;
 857
 858         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 859                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 860
 861         return status;
 862 }
 863
 864 /**
 865  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 866  *  @hw: pointer to hardware structure
 867  *  @speed: new link speed
 868  **/
 869 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 870                                        ixgbe_link_speed speed,
 871                                        bool autoneg_wait_to_complete)
 872 {
 873         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 874
 875         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 876
 877         /*
 878          * Clear autoneg_advertised and set new values based on input link
 879          * speed.
 880          */
 881         hw->phy.autoneg_advertised = 0;
 882
 883         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 884                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 885
 886         if (speed & IXGBE_LINK_SPEED_5GB_FULL)
 887                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
 888
 889         if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
 890                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
 891
 892         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 893                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 894
 895         if (speed & IXGBE_LINK_SPEED_100_FULL)
 896                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 897
 898         if (speed & IXGBE_LINK_SPEED_10_FULL)
 899                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
 900
 901         /* Setup link based on the new speed settings */
 902         ixgbe_setup_phy_link(hw);
 903
 904         return IXGBE_SUCCESS;
 905 }
 906
 907 /**
 908  * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
 909  * @hw: pointer to hardware structure
 910  *
 911  * Determines the supported link capabilities by reading the PHY auto
 912  * negotiation register.
 913  **/
 914 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
 915 {
 916         s32 status;
 917         u16 speed_ability;
 918
 919         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 920                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 921                                       &speed_ability);
 922         if (status)
 923                 return status;
 924
 925         if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 926                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
 927         if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 928                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
 929         if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 930                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
 931
 932         switch (hw->mac.type) {
 933         case ixgbe_mac_X550:
 934                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
 935                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
 936                 break;
 937         case ixgbe_mac_X550EM_x:
 938         case ixgbe_mac_X550EM_a:
 939                 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
 940                 break;
 941         default:
 942                 break;
 943         }
 944
 945         return status;
 946 }
 947
 948 /**
 949  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 950  *  @hw: pointer to hardware structure
 951  *  @speed: pointer to link speed
 952  *  @autoneg: boolean auto-negotiation value
 953  **/
 954 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 955                                                ixgbe_link_speed *speed,
 956                                                bool *autoneg)
 957 {
 958         s32 status = IXGBE_SUCCESS;
 959
 960         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 961
 962         *autoneg = true;
 963         if (!hw->phy.speeds_supported)
 964                 status = ixgbe_get_copper_speeds_supported(hw);
 965
 966         *speed = hw->phy.speeds_supported;
 967         return status;
 968 }
 969
 970 /**
 971  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 972  *  @hw: pointer to hardware structure
 973  *
 974  *  Reads the VS1 register to determine if link is up and the current speed for
 975  *  the PHY.
 976  **/
 977 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 978                              bool *link_up)
 979 {
 980         s32 status = IXGBE_SUCCESS;
 981         u32 time_out;
 982         u32 max_time_out = 10;
 983         u16 phy_link = 0;
 984         u16 phy_speed = 0;
 985         u16 phy_data = 0;
 986
 987         DEBUGFUNC("ixgbe_check_phy_link_tnx");
 988
 989         /* Initialize speed and link to default case */
 990         *link_up = false;
 991         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 992
 993         /*
 994          * Check current speed and link status of the PHY register.
 995          * This is a vendor specific register and may have to
 996          * be changed for other copper PHYs.
 997          */
 998         for (time_out = 0; time_out < max_time_out; time_out++) {
 999                 usec_delay(10);
1000                 status = hw->phy.ops.read_reg(hw,
1001                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1002                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1003                                         &phy_data);
1004                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1005                 phy_speed = phy_data &
1006                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1007                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1008                         *link_up = true;
1009                         if (phy_speed ==
1010                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1011                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1012                         break;
1013                 }
1014         }
1015
1016         return status;
1017 }
1018
1019 /**
1020  *      ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1021  *      @hw: pointer to hardware structure
1022  *
1023  *      Restart auto-negotiation and PHY and waits for completion.
1024  **/
1025 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1026 {
1027         s32 status = IXGBE_SUCCESS;
1028         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1029         bool autoneg = false;
1030         ixgbe_link_speed speed;
1031
1032         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1033
1034         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1035
1036         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1037                 /* Set or unset auto-negotiation 10G advertisement */
1038                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1039                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1040                                      &autoneg_reg);
1041
1042                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1043                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1044                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1045
1046                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1047                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1048                                       autoneg_reg);
1049         }
1050
1051         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1052                 /* Set or unset auto-negotiation 1G advertisement */
1053                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1054                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1055                                      &autoneg_reg);
1056
1057                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1058                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1059                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1060
1061                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1062                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1063                                       autoneg_reg);
1064         }
1065
1066         if (speed & IXGBE_LINK_SPEED_100_FULL) {
1067                 /* Set or unset auto-negotiation 100M advertisement */
1068                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1069                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1070                                      &autoneg_reg);
1071
1072                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1073                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1074                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1075
1076                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1077                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1078                                       autoneg_reg);
1079         }
1080
1081         /* Blocked by MNG FW so don't reset PHY */
1082         if (ixgbe_check_reset_blocked(hw))
1083                 return status;
1084
1085         /* Restart PHY auto-negotiation. */
1086         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1087                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1088
1089         autoneg_reg |= IXGBE_MII_RESTART;
1090
1091         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1092                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1093
1094         return status;
1095 }
1096
1097 /**
1098  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1099  *  @hw: pointer to hardware structure
1100  *  @firmware_version: pointer to the PHY Firmware Version
1101  **/
1102 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1103                                        u16 *firmware_version)
1104 {
1105         s32 status;
1106
1107         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1108
1109         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1110                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1111                                       firmware_version);
1112
1113         return status;
1114 }
1115
1116 /**
1117  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1118  *  @hw: pointer to hardware structure
1119  *  @firmware_version: pointer to the PHY Firmware Version
1120  **/
1121 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1122                                            u16 *firmware_version)
1123 {
1124         s32 status;
1125
1126         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1127
1128         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1129                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1130                                       firmware_version);
1131
1132         return status;
1133 }
1134
1135 /**
1136  *  ixgbe_reset_phy_nl - Performs a PHY reset
1137  *  @hw: pointer to hardware structure
1138  **/
1139 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1140 {
1141         u16 phy_offset, control, eword, edata, block_crc;
1142         bool end_data = false;
1143         u16 list_offset, data_offset;
1144         u16 phy_data = 0;
1145         s32 ret_val = IXGBE_SUCCESS;
1146         u32 i;
1147
1148         DEBUGFUNC("ixgbe_reset_phy_nl");
1149
1150         /* Blocked by MNG FW so bail */
1151         if (ixgbe_check_reset_blocked(hw))
1152                 goto out;
1153
1154         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1155                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1156
1157         /* reset the PHY and poll for completion */
1158         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1159                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
1160                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1161
1162         for (i = 0; i < 100; i++) {
1163                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1164                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1165                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1166                         break;
1167                 msec_delay(10);
1168         }
1169
1170         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1171                 DEBUGOUT("PHY reset did not complete.\n");
1172                 ret_val = IXGBE_ERR_PHY;
1173                 goto out;
1174         }
1175
1176         /* Get init offsets */
1177         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1178                                                       &data_offset);
1179         if (ret_val != IXGBE_SUCCESS)
1180                 goto out;
1181
1182         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1183         data_offset++;
1184         while (!end_data) {
1185                 /*
1186                  * Read control word from PHY init contents offset
1187                  */
1188                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1189                 if (ret_val)
1190                         goto err_eeprom;
1191                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1192                            IXGBE_CONTROL_SHIFT_NL;
1193                 edata = eword & IXGBE_DATA_MASK_NL;
1194                 switch (control) {
1195                 case IXGBE_DELAY_NL:
1196                         data_offset++;
1197                         DEBUGOUT1("DELAY: %d MS\n", edata);
1198                         msec_delay(edata);
1199                         break;
1200                 case IXGBE_DATA_NL:
1201                         DEBUGOUT("DATA:\n");
1202                         data_offset++;
1203                         ret_val = hw->eeprom.ops.read(hw, data_offset,
1204                                                       &phy_offset);
1205                         if (ret_val)
1206                                 goto err_eeprom;
1207                         data_offset++;
1208                         for (i = 0; i < edata; i++) {
1209                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
1210                                                               &eword);
1211                                 if (ret_val)
1212                                         goto err_eeprom;
1213                                 hw->phy.ops.write_reg(hw, phy_offset,
1214                                                       IXGBE_TWINAX_DEV, eword);
1215                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1216                                           phy_offset);
1217                                 data_offset++;
1218                                 phy_offset++;
1219                         }
1220                         break;
1221                 case IXGBE_CONTROL_NL:
1222                         data_offset++;
1223                         DEBUGOUT("CONTROL:\n");
1224                         if (edata == IXGBE_CONTROL_EOL_NL) {
1225                                 DEBUGOUT("EOL\n");
1226                                 end_data = true;
1227                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
1228                                 DEBUGOUT("SOL\n");
1229                         } else {
1230                                 DEBUGOUT("Bad control value\n");
1231                                 ret_val = IXGBE_ERR_PHY;
1232                                 goto out;
1233                         }
1234                         break;
1235                 default:
1236                         DEBUGOUT("Bad control type\n");
1237                         ret_val = IXGBE_ERR_PHY;
1238                         goto out;
1239                 }
1240         }
1241
1242 out:
1243         return ret_val;
1244
1245 err_eeprom:
1246         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1247                       "eeprom read at offset %d failed", data_offset);
1248         return IXGBE_ERR_PHY;
1249 }
1250
1251 /**
1252  *  ixgbe_identify_module_generic - Identifies module type
1253  *  @hw: pointer to hardware structure
1254  *
1255  *  Determines HW type and calls appropriate function.
1256  **/
1257 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1258 {
1259         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1260
1261         DEBUGFUNC("ixgbe_identify_module_generic");
1262
1263         switch (hw->mac.ops.get_media_type(hw)) {
1264         case ixgbe_media_type_fiber:
1265                 status = ixgbe_identify_sfp_module_generic(hw);
1266                 break;
1267
1268         case ixgbe_media_type_fiber_qsfp:
1269                 status = ixgbe_identify_qsfp_module_generic(hw);
1270                 break;
1271
1272         default:
1273                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1274                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1275                 break;
1276         }
1277
1278         return status;
1279 }
1280
1281 /**
1282  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1283  *  @hw: pointer to hardware structure
1284  *
1285  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1286  **/
1287 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1288 {
1289         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1290         u32 vendor_oui = 0;
1291         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1292         u8 identifier = 0;
1293         u8 comp_codes_1g = 0;
1294         u8 comp_codes_10g = 0;
1295         u8 oui_bytes[3] = {0, 0, 0};
1296         u8 cable_tech = 0;
1297         u8 cable_spec = 0;
1298         u16 enforce_sfp = 0;
1299
1300         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1301
1302         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1303                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1304                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1305                 goto out;
1306         }
1307
1308         /* LAN ID is needed for I2C access */
1309         hw->mac.ops.set_lan_id(hw);
1310
1311         status = hw->phy.ops.read_i2c_eeprom(hw,
1312                                              IXGBE_SFF_IDENTIFIER,
1313                                              &identifier);
1314
1315         if (status != IXGBE_SUCCESS)
1316                 goto err_read_i2c_eeprom;
1317
1318         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1319                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1320                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1321         } else {
1322                 status = hw->phy.ops.read_i2c_eeprom(hw,
1323                                                      IXGBE_SFF_1GBE_COMP_CODES,
1324                                                      &comp_codes_1g);
1325
1326                 if (status != IXGBE_SUCCESS)
1327                         goto err_read_i2c_eeprom;
1328
1329                 status = hw->phy.ops.read_i2c_eeprom(hw,
1330                                                      IXGBE_SFF_10GBE_COMP_CODES,
1331                                                      &comp_codes_10g);
1332
1333                 if (status != IXGBE_SUCCESS)
1334                         goto err_read_i2c_eeprom;
1335                 status = hw->phy.ops.read_i2c_eeprom(hw,
1336                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1337                                                      &cable_tech);
1338
1339                 if (status != IXGBE_SUCCESS)
1340                         goto err_read_i2c_eeprom;
1341
1342                  /* ID Module
1343                   * =========
1344                   * 0   SFP_DA_CU
1345                   * 1   SFP_SR
1346                   * 2   SFP_LR
1347                   * 3   SFP_DA_CORE0 - 82599-specific
1348                   * 4   SFP_DA_CORE1 - 82599-specific
1349                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1350                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1351                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1352                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1353                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1354                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1355                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1356                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1357                   */
1358                 if (hw->mac.type == ixgbe_mac_82598EB) {
1359                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1360                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1361                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1362                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1363                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1364                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1365                         else
1366                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1367                 } else {
1368                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1369                                 if (hw->bus.lan_id == 0)
1370                                         hw->phy.sfp_type =
1371                                                      ixgbe_sfp_type_da_cu_core0;
1372                                 else
1373                                         hw->phy.sfp_type =
1374                                                      ixgbe_sfp_type_da_cu_core1;
1375                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1376                                 hw->phy.ops.read_i2c_eeprom(
1377                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1378                                                 &cable_spec);
1379                                 if (cable_spec &
1380                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1381                                         if (hw->bus.lan_id == 0)
1382                                                 hw->phy.sfp_type =
1383                                                 ixgbe_sfp_type_da_act_lmt_core0;
1384                                         else
1385                                                 hw->phy.sfp_type =
1386                                                 ixgbe_sfp_type_da_act_lmt_core1;
1387                                 } else {
1388                                         hw->phy.sfp_type =
1389                                                         ixgbe_sfp_type_unknown;
1390                                 }
1391                         } else if (comp_codes_10g &
1392                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1393                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1394                                 if (hw->bus.lan_id == 0)
1395                                         hw->phy.sfp_type =
1396                                                       ixgbe_sfp_type_srlr_core0;
1397                                 else
1398                                         hw->phy.sfp_type =
1399                                                       ixgbe_sfp_type_srlr_core1;
1400                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1401                                 if (hw->bus.lan_id == 0)
1402                                         hw->phy.sfp_type =
1403                                                 ixgbe_sfp_type_1g_cu_core0;
1404                                 else
1405                                         hw->phy.sfp_type =
1406                                                 ixgbe_sfp_type_1g_cu_core1;
1407                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1408                                 if (hw->bus.lan_id == 0)
1409                                         hw->phy.sfp_type =
1410                                                 ixgbe_sfp_type_1g_sx_core0;
1411                                 else
1412                                         hw->phy.sfp_type =
1413                                                 ixgbe_sfp_type_1g_sx_core1;
1414                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1415                                 if (hw->bus.lan_id == 0)
1416                                         hw->phy.sfp_type =
1417                                                 ixgbe_sfp_type_1g_lx_core0;
1418                                 else
1419                                         hw->phy.sfp_type =
1420                                                 ixgbe_sfp_type_1g_lx_core1;
1421                         } else {
1422                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1423                         }
1424                 }
1425
1426                 if (hw->phy.sfp_type != stored_sfp_type)
1427                         hw->phy.sfp_setup_needed = true;
1428
1429                 /* Determine if the SFP+ PHY is dual speed or not. */
1430                 hw->phy.multispeed_fiber = false;
1431                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1432                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1433                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1434                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1435                         hw->phy.multispeed_fiber = true;
1436
1437                 /* Determine PHY vendor */
1438                 if (hw->phy.type != ixgbe_phy_nl) {
1439                         hw->phy.id = identifier;
1440                         status = hw->phy.ops.read_i2c_eeprom(hw,
1441                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1442                                                     &oui_bytes[0]);
1443
1444                         if (status != IXGBE_SUCCESS)
1445                                 goto err_read_i2c_eeprom;
1446
1447                         status = hw->phy.ops.read_i2c_eeprom(hw,
1448                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1449                                                     &oui_bytes[1]);
1450
1451                         if (status != IXGBE_SUCCESS)
1452                                 goto err_read_i2c_eeprom;
1453
1454                         status = hw->phy.ops.read_i2c_eeprom(hw,
1455                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1456                                                     &oui_bytes[2]);
1457
1458                         if (status != IXGBE_SUCCESS)
1459                                 goto err_read_i2c_eeprom;
1460
1461                         vendor_oui =
1462                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1463                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1464                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1465
1466                         switch (vendor_oui) {
1467                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1468                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1469                                         hw->phy.type =
1470                                                     ixgbe_phy_sfp_passive_tyco;
1471                                 break;
1472                         case IXGBE_SFF_VENDOR_OUI_FTL:
1473                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1474                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1475                                 else
1476                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1477                                 break;
1478                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1479                                 hw->phy.type = ixgbe_phy_sfp_avago;
1480                                 break;
1481                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1482                                 hw->phy.type = ixgbe_phy_sfp_intel;
1483                                 break;
1484                         default:
1485                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1486                                         hw->phy.type =
1487                                                  ixgbe_phy_sfp_passive_unknown;
1488                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1489                                         hw->phy.type =
1490                                                 ixgbe_phy_sfp_active_unknown;
1491                                 else
1492                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1493                                 break;
1494                         }
1495                 }
1496
1497                 /* Allow any DA cable vendor */
1498                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1499                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1500                         status = IXGBE_SUCCESS;
1501                         goto out;
1502                 }
1503
1504                 /* Verify supported 1G SFP modules */
1505                 if (comp_codes_10g == 0 &&
1506                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1507                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1508                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1509                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1510                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1511                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1512                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1513                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1514                         goto out;
1515                 }
1516
1517                 /* Anything else 82598-based is supported */
1518                 if (hw->mac.type == ixgbe_mac_82598EB) {
1519                         status = IXGBE_SUCCESS;
1520                         goto out;
1521                 }
1522
1523                 ixgbe_get_device_caps(hw, &enforce_sfp);
1524                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1525                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1526                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1527                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1528                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1529                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1530                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1531                         /* Make sure we're a supported PHY type */
1532                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1533                                 status = IXGBE_SUCCESS;
1534                         } else {
1535                                 if (hw->allow_unsupported_sfp == true) {
1536                                         EWARN(hw, "WARNING: Intel (R) Network "
1537                                               "Connections are quality tested "
1538                                               "using Intel (R) Ethernet Optics."
1539                                               " Using untested modules is not "
1540                                               "supported and may cause unstable"
1541                                               " operation or damage to the "
1542                                               "module or the adapter. Intel "
1543                                               "Corporation is not responsible "
1544                                               "for any harm caused by using "
1545                                               "untested modules.\n", status);
1546                                         status = IXGBE_SUCCESS;
1547                                 } else {
1548                                         DEBUGOUT("SFP+ module not supported\n");
1549                                         hw->phy.type =
1550                                                 ixgbe_phy_sfp_unsupported;
1551                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1552                                 }
1553                         }
1554                 } else {
1555                         status = IXGBE_SUCCESS;
1556                 }
1557         }
1558
1559 out:
1560         return status;
1561
1562 err_read_i2c_eeprom:
1563         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1564         if (hw->phy.type != ixgbe_phy_nl) {
1565                 hw->phy.id = 0;
1566                 hw->phy.type = ixgbe_phy_unknown;
1567         }
1568         return IXGBE_ERR_SFP_NOT_PRESENT;
1569 }
1570
1571 /**
1572  *  ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1573  *  @hw: pointer to hardware structure
1574  *
1575  *  Determines physical layer capabilities of the current SFP.
1576  */
1577 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1578 {
1579         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1580         u8 comp_codes_10g = 0;
1581         u8 comp_codes_1g = 0;
1582
1583         DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1584
1585         hw->phy.ops.identify_sfp(hw);
1586         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1587                 return physical_layer;
1588
1589         switch (hw->phy.type) {
1590         case ixgbe_phy_sfp_passive_tyco:
1591         case ixgbe_phy_sfp_passive_unknown:
1592         case ixgbe_phy_qsfp_passive_unknown:
1593                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1594                 break;
1595         case ixgbe_phy_sfp_ftl_active:
1596         case ixgbe_phy_sfp_active_unknown:
1597         case ixgbe_phy_qsfp_active_unknown:
1598                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1599                 break;
1600         case ixgbe_phy_sfp_avago:
1601         case ixgbe_phy_sfp_ftl:
1602         case ixgbe_phy_sfp_intel:
1603         case ixgbe_phy_sfp_unknown:
1604                 hw->phy.ops.read_i2c_eeprom(hw,
1605                       IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1606                 hw->phy.ops.read_i2c_eeprom(hw,
1607                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1608                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1609                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1610                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1611                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1612                 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1613                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1614                 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1615                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1616                 break;
1617         case ixgbe_phy_qsfp_intel:
1618         case ixgbe_phy_qsfp_unknown:
1619                 hw->phy.ops.read_i2c_eeprom(hw,
1620                       IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1621                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1622                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1623                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1624                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1625                 break;
1626         default:
1627                 break;
1628         }
1629
1630         return physical_layer;
1631 }
1632
1633 /**
1634  *  ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1635  *  @hw: pointer to hardware structure
1636  *
1637  *  Searches for and identifies the QSFP module and assigns appropriate PHY type
1638  **/
1639 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1640 {
1641         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1642         u32 vendor_oui = 0;
1643         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1644         u8 identifier = 0;
1645         u8 comp_codes_1g = 0;
1646         u8 comp_codes_10g = 0;
1647         u8 oui_bytes[3] = {0, 0, 0};
1648         u16 enforce_sfp = 0;
1649         u8 connector = 0;
1650         u8 cable_length = 0;
1651         u8 device_tech = 0;
1652         bool active_cable = false;
1653
1654         DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1655
1656         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1657                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1658                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1659                 goto out;
1660         }
1661
1662         /* LAN ID is needed for I2C access */
1663         hw->mac.ops.set_lan_id(hw);
1664
1665         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1666                                              &identifier);
1667
1668         if (status != IXGBE_SUCCESS)
1669                 goto err_read_i2c_eeprom;
1670
1671         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1672                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1673                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1674                 goto out;
1675         }
1676
1677         hw->phy.id = identifier;
1678
1679         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1680                                              &comp_codes_10g);
1681
1682         if (status != IXGBE_SUCCESS)
1683                 goto err_read_i2c_eeprom;
1684
1685         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1686                                              &comp_codes_1g);
1687
1688         if (status != IXGBE_SUCCESS)
1689                 goto err_read_i2c_eeprom;
1690
1691         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1692                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1693                 if (hw->bus.lan_id == 0)
1694                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1695                 else
1696                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1697         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1698                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1699                 if (hw->bus.lan_id == 0)
1700                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1701                 else
1702                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1703         } else {
1704                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1705                         active_cable = true;
1706
1707                 if (!active_cable) {
1708                         /* check for active DA cables that pre-date
1709                          * SFF-8436 v3.6 */
1710                         hw->phy.ops.read_i2c_eeprom(hw,
1711                                         IXGBE_SFF_QSFP_CONNECTOR,
1712                                         &connector);
1713
1714                         hw->phy.ops.read_i2c_eeprom(hw,
1715                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1716                                         &cable_length);
1717
1718                         hw->phy.ops.read_i2c_eeprom(hw,
1719                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1720                                         &device_tech);
1721
1722                         if ((connector ==
1723                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1724                             (cable_length > 0) &&
1725                             ((device_tech >> 4) ==
1726                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1727                                 active_cable = true;
1728                 }
1729
1730                 if (active_cable) {
1731                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1732                         if (hw->bus.lan_id == 0)
1733                                 hw->phy.sfp_type =
1734                                                 ixgbe_sfp_type_da_act_lmt_core0;
1735                         else
1736                                 hw->phy.sfp_type =
1737                                                 ixgbe_sfp_type_da_act_lmt_core1;
1738                 } else {
1739                         /* unsupported module type */
1740                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1741                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1742                         goto out;
1743                 }
1744         }
1745
1746         if (hw->phy.sfp_type != stored_sfp_type)
1747                 hw->phy.sfp_setup_needed = true;
1748
1749         /* Determine if the QSFP+ PHY is dual speed or not. */
1750         hw->phy.multispeed_fiber = false;
1751         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1752            (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1753            ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1754            (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1755                 hw->phy.multispeed_fiber = true;
1756
1757         /* Determine PHY vendor for optical modules */
1758         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1759                               IXGBE_SFF_10GBASELR_CAPABLE))  {
1760                 status = hw->phy.ops.read_i2c_eeprom(hw,
1761                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1762                                             &oui_bytes[0]);
1763
1764                 if (status != IXGBE_SUCCESS)
1765                         goto err_read_i2c_eeprom;
1766
1767                 status = hw->phy.ops.read_i2c_eeprom(hw,
1768                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1769                                             &oui_bytes[1]);
1770
1771                 if (status != IXGBE_SUCCESS)
1772                         goto err_read_i2c_eeprom;
1773
1774                 status = hw->phy.ops.read_i2c_eeprom(hw,
1775                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1776                                             &oui_bytes[2]);
1777
1778                 if (status != IXGBE_SUCCESS)
1779                         goto err_read_i2c_eeprom;
1780
1781                 vendor_oui =
1782                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1783                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1784                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1785
1786                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1787                         hw->phy.type = ixgbe_phy_qsfp_intel;
1788                 else
1789                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1790
1791                 ixgbe_get_device_caps(hw, &enforce_sfp);
1792                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1793                         /* Make sure we're a supported PHY type */
1794                         if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1795                                 status = IXGBE_SUCCESS;
1796                         } else {
1797                                 if (hw->allow_unsupported_sfp == true) {
1798                                         EWARN(hw, "WARNING: Intel (R) Network "
1799                                               "Connections are quality tested "
1800                                               "using Intel (R) Ethernet Optics."
1801                                               " Using untested modules is not "
1802                                               "supported and may cause unstable"
1803                                               " operation or damage to the "
1804                                               "module or the adapter. Intel "
1805                                               "Corporation is not responsible "
1806                                               "for any harm caused by using "
1807                                               "untested modules.\n", status);
1808                                         status = IXGBE_SUCCESS;
1809                                 } else {
1810                                         DEBUGOUT("QSFP module not supported\n");
1811                                         hw->phy.type =
1812                                                 ixgbe_phy_sfp_unsupported;
1813                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1814                                 }
1815                         }
1816                 } else {
1817                         status = IXGBE_SUCCESS;
1818                 }
1819         }
1820
1821 out:
1822         return status;
1823
1824 err_read_i2c_eeprom:
1825         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1826         hw->phy.id = 0;
1827         hw->phy.type = ixgbe_phy_unknown;
1828
1829         return IXGBE_ERR_SFP_NOT_PRESENT;
1830 }
1831
1832
1833 /**
1834  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1835  *  @hw: pointer to hardware structure
1836  *  @list_offset: offset to the SFP ID list
1837  *  @data_offset: offset to the SFP data block
1838  *
1839  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1840  *  so it returns the offsets to the phy init sequence block.
1841  **/
1842 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1843                                         u16 *list_offset,
1844                                         u16 *data_offset)
1845 {
1846         u16 sfp_id;
1847         u16 sfp_type = hw->phy.sfp_type;
1848
1849         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1850
1851         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1852                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1853
1854         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1855                 return IXGBE_ERR_SFP_NOT_PRESENT;
1856
1857         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1858             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1859                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1860
1861         /*
1862          * Limiting active cables and 1G Phys must be initialized as
1863          * SR modules
1864          */
1865         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1866             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1867             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1868             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1869                 sfp_type = ixgbe_sfp_type_srlr_core0;
1870         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1871                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1872                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1873                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1874                 sfp_type = ixgbe_sfp_type_srlr_core1;
1875
1876         /* Read offset to PHY init contents */
1877         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1878                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1879                               "eeprom read at offset %d failed",
1880                               IXGBE_PHY_INIT_OFFSET_NL);
1881                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1882         }
1883
1884         if ((!*list_offset) || (*list_offset == 0xFFFF))
1885                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1886
1887         /* Shift offset to first ID word */
1888         (*list_offset)++;
1889
1890         /*
1891          * Find the matching SFP ID in the EEPROM
1892          * and program the init sequence
1893          */
1894         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1895                 goto err_phy;
1896
1897         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1898                 if (sfp_id == sfp_type) {
1899                         (*list_offset)++;
1900                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1901                                 goto err_phy;
1902                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1903                                 DEBUGOUT("SFP+ module not supported\n");
1904                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1905                         } else {
1906                                 break;
1907                         }
1908                 } else {
1909                         (*list_offset) += 2;
1910                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1911                                 goto err_phy;
1912                 }
1913         }
1914
1915         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1916                 DEBUGOUT("No matching SFP+ module found\n");
1917                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1918         }
1919
1920         return IXGBE_SUCCESS;
1921
1922 err_phy:
1923         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1924                       "eeprom read at offset %d failed", *list_offset);
1925         return IXGBE_ERR_PHY;
1926 }
1927
1928 /**
1929  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1930  *  @hw: pointer to hardware structure
1931  *  @byte_offset: EEPROM byte offset to read
1932  *  @eeprom_data: value read
1933  *
1934  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1935  **/
1936 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1937                                   u8 *eeprom_data)
1938 {
1939         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1940
1941         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1942                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1943                                          eeprom_data);
1944 }
1945
1946 /**
1947  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1948  *  @hw: pointer to hardware structure
1949  *  @byte_offset: byte offset at address 0xA2
1950  *  @eeprom_data: value read
1951  *
1952  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1953  **/
1954 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1955                                           u8 *sff8472_data)
1956 {
1957         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1958                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1959                                          sff8472_data);
1960 }
1961
1962 /**
1963  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1964  *  @hw: pointer to hardware structure
1965  *  @byte_offset: EEPROM byte offset to write
1966  *  @eeprom_data: value to write
1967  *
1968  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1969  **/
1970 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1971                                    u8 eeprom_data)
1972 {
1973         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1974
1975         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1976                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1977                                           eeprom_data);
1978 }
1979
1980 /**
1981  * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1982  * @hw: pointer to hardware structure
1983  * @offset: eeprom offset to be read
1984  * @addr: I2C address to be read
1985  */
1986 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1987 {
1988         if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1989             offset == IXGBE_SFF_IDENTIFIER &&
1990             hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1991                 return true;
1992         return false;
1993 }
1994
1995 /**
1996  *  ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1997  *  @hw: pointer to hardware structure
1998  *  @byte_offset: byte offset to read
1999  *  @data: value read
2000  *  @lock: true if to take and release semaphore
2001  *
2002  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2003  *  a specified device address.
2004  **/
2005 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2006                                            u8 dev_addr, u8 *data, bool lock)
2007 {
2008         s32 status;
2009         u32 max_retry = 10;
2010         u32 retry = 0;
2011         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2012         bool nack = 1;
2013         *data = 0;
2014
2015         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2016
2017         if (hw->mac.type >= ixgbe_mac_X550)
2018                 max_retry = 3;
2019         if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2020                 max_retry = IXGBE_SFP_DETECT_RETRIES;
2021
2022         do {
2023                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2024                         return IXGBE_ERR_SWFW_SYNC;
2025
2026                 ixgbe_i2c_start(hw);
2027
2028                 /* Device Address and write indication */
2029                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2030                 if (status != IXGBE_SUCCESS)
2031                         goto fail;
2032
2033                 status = ixgbe_get_i2c_ack(hw);
2034                 if (status != IXGBE_SUCCESS)
2035                         goto fail;
2036
2037                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2038                 if (status != IXGBE_SUCCESS)
2039                         goto fail;
2040
2041                 status = ixgbe_get_i2c_ack(hw);
2042                 if (status != IXGBE_SUCCESS)
2043                         goto fail;
2044
2045                 ixgbe_i2c_start(hw);
2046
2047                 /* Device Address and read indication */
2048                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2049                 if (status != IXGBE_SUCCESS)
2050                         goto fail;
2051
2052                 status = ixgbe_get_i2c_ack(hw);
2053                 if (status != IXGBE_SUCCESS)
2054                         goto fail;
2055
2056                 status = ixgbe_clock_in_i2c_byte(hw, data);
2057                 if (status != IXGBE_SUCCESS)
2058                         goto fail;
2059
2060                 status = ixgbe_clock_out_i2c_bit(hw, nack);
2061                 if (status != IXGBE_SUCCESS)
2062                         goto fail;
2063
2064                 ixgbe_i2c_stop(hw);
2065                 if (lock)
2066                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2067                 return IXGBE_SUCCESS;
2068
2069 fail:
2070                 ixgbe_i2c_bus_clear(hw);
2071                 if (lock) {
2072                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2073                         msec_delay(100);
2074                 }
2075                 retry++;
2076                 if (retry < max_retry)
2077                         DEBUGOUT("I2C byte read error - Retrying.\n");
2078                 else
2079                         DEBUGOUT("I2C byte read error.\n");
2080
2081         } while (retry < max_retry);
2082
2083         return status;
2084 }
2085
2086 /**
2087  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2088  *  @hw: pointer to hardware structure
2089  *  @byte_offset: byte offset to read
2090  *  @data: value read
2091  *
2092  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2093  *  a specified device address.
2094  **/
2095 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2096                                 u8 dev_addr, u8 *data)
2097 {
2098         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2099                                                data, true);
2100 }
2101
2102 /**
2103  *  ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2104  *  @hw: pointer to hardware structure
2105  *  @byte_offset: byte offset to read
2106  *  @data: value read
2107  *
2108  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2109  *  a specified device address.
2110  **/
2111 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2112                                          u8 dev_addr, u8 *data)
2113 {
2114         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2115                                                data, false);
2116 }
2117
2118 /**
2119  *  ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2120  *  @hw: pointer to hardware structure
2121  *  @byte_offset: byte offset to write
2122  *  @data: value to write
2123  *  @lock: true if to take and release semaphore
2124  *
2125  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2126  *  a specified device address.
2127  **/
2128 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2129                                             u8 dev_addr, u8 data, bool lock)
2130 {
2131         s32 status;
2132         u32 max_retry = 1;
2133         u32 retry = 0;
2134         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2135
2136         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2137
2138         if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2139             IXGBE_SUCCESS)
2140                 return IXGBE_ERR_SWFW_SYNC;
2141
2142         do {
2143                 ixgbe_i2c_start(hw);
2144
2145                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2146                 if (status != IXGBE_SUCCESS)
2147                         goto fail;
2148
2149                 status = ixgbe_get_i2c_ack(hw);
2150                 if (status != IXGBE_SUCCESS)
2151                         goto fail;
2152
2153                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2154                 if (status != IXGBE_SUCCESS)
2155                         goto fail;
2156
2157                 status = ixgbe_get_i2c_ack(hw);
2158                 if (status != IXGBE_SUCCESS)
2159                         goto fail;
2160
2161                 status = ixgbe_clock_out_i2c_byte(hw, data);
2162                 if (status != IXGBE_SUCCESS)
2163                         goto fail;
2164
2165                 status = ixgbe_get_i2c_ack(hw);
2166                 if (status != IXGBE_SUCCESS)
2167                         goto fail;
2168
2169                 ixgbe_i2c_stop(hw);
2170                 if (lock)
2171                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2172                 return IXGBE_SUCCESS;
2173
2174 fail:
2175                 ixgbe_i2c_bus_clear(hw);
2176                 retry++;
2177                 if (retry < max_retry)
2178                         DEBUGOUT("I2C byte write error - Retrying.\n");
2179                 else
2180                         DEBUGOUT("I2C byte write error.\n");
2181         } while (retry < max_retry);
2182
2183         if (lock)
2184                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2185
2186         return status;
2187 }
2188
2189 /**
2190  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2191  *  @hw: pointer to hardware structure
2192  *  @byte_offset: byte offset to write
2193  *  @data: value to write
2194  *
2195  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2196  *  a specified device address.
2197  **/
2198 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2199                                  u8 dev_addr, u8 data)
2200 {
2201         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2202                                                 data, true);
2203 }
2204
2205 /**
2206  *  ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2207  *  @hw: pointer to hardware structure
2208  *  @byte_offset: byte offset to write
2209  *  @data: value to write
2210  *
2211  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2212  *  a specified device address.
2213  **/
2214 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2215                                           u8 dev_addr, u8 data)
2216 {
2217         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2218                                                 data, false);
2219 }
2220
2221 /**
2222  *  ixgbe_i2c_start - Sets I2C start condition
2223  *  @hw: pointer to hardware structure
2224  *
2225  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
2226  *  Set bit-bang mode on X550 hardware.
2227  **/
2228 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2229 {
2230         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2231
2232         DEBUGFUNC("ixgbe_i2c_start");
2233
2234         i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2235
2236         /* Start condition must begin with data and clock high */
2237         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2238         ixgbe_raise_i2c_clk(hw, &i2cctl);
2239
2240         /* Setup time for start condition (4.7us) */
2241         usec_delay(IXGBE_I2C_T_SU_STA);
2242
2243         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2244
2245         /* Hold time for start condition (4us) */
2246         usec_delay(IXGBE_I2C_T_HD_STA);
2247
2248         ixgbe_lower_i2c_clk(hw, &i2cctl);
2249
2250         /* Minimum low period of clock is 4.7 us */
2251         usec_delay(IXGBE_I2C_T_LOW);
2252
2253 }
2254
2255 /**
2256  *  ixgbe_i2c_stop - Sets I2C stop condition
2257  *  @hw: pointer to hardware structure
2258  *
2259  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
2260  *  Disables bit-bang mode and negates data output enable on X550
2261  *  hardware.
2262  **/
2263 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2264 {
2265         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2266         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2267         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2268         u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2269
2270         DEBUGFUNC("ixgbe_i2c_stop");
2271
2272         /* Stop condition must begin with data low and clock high */
2273         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2274         ixgbe_raise_i2c_clk(hw, &i2cctl);
2275
2276         /* Setup time for stop condition (4us) */
2277         usec_delay(IXGBE_I2C_T_SU_STO);
2278
2279         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2280
2281         /* bus free time between stop and start (4.7us)*/
2282         usec_delay(IXGBE_I2C_T_BUF);
2283
2284         if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2285                 i2cctl &= ~bb_en_bit;
2286                 i2cctl |= data_oe_bit | clk_oe_bit;
2287                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2288                 IXGBE_WRITE_FLUSH(hw);
2289         }
2290 }
2291
2292 /**
2293  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2294  *  @hw: pointer to hardware structure
2295  *  @data: data byte to clock in
2296  *
2297  *  Clocks in one byte data via I2C data/clock
2298  **/
2299 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2300 {
2301         s32 i;
2302         bool bit = 0;
2303
2304         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2305
2306         *data = 0;
2307         for (i = 7; i >= 0; i--) {
2308                 ixgbe_clock_in_i2c_bit(hw, &bit);
2309                 *data |= bit << i;
2310         }
2311
2312         return IXGBE_SUCCESS;
2313 }
2314
2315 /**
2316  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2317  *  @hw: pointer to hardware structure
2318  *  @data: data byte clocked out
2319  *
2320  *  Clocks out one byte data via I2C data/clock
2321  **/
2322 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2323 {
2324         s32 status = IXGBE_SUCCESS;
2325         s32 i;
2326         u32 i2cctl;
2327         bool bit;
2328
2329         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2330
2331         for (i = 7; i >= 0; i--) {
2332                 bit = (data >> i) & 0x1;
2333                 status = ixgbe_clock_out_i2c_bit(hw, bit);
2334
2335                 if (status != IXGBE_SUCCESS)
2336                         break;
2337         }
2338
2339         /* Release SDA line (set high) */
2340         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2341         i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2342         i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2343         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2344         IXGBE_WRITE_FLUSH(hw);
2345
2346         return status;
2347 }
2348
2349 /**
2350  *  ixgbe_get_i2c_ack - Polls for I2C ACK
2351  *  @hw: pointer to hardware structure
2352  *
2353  *  Clocks in/out one bit via I2C data/clock
2354  **/
2355 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2356 {
2357         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2358         s32 status = IXGBE_SUCCESS;
2359         u32 i = 0;
2360         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2361         u32 timeout = 10;
2362         bool ack = 1;
2363
2364         DEBUGFUNC("ixgbe_get_i2c_ack");
2365
2366         if (data_oe_bit) {
2367                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2368                 i2cctl |= data_oe_bit;
2369                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2370                 IXGBE_WRITE_FLUSH(hw);
2371         }
2372         ixgbe_raise_i2c_clk(hw, &i2cctl);
2373
2374         /* Minimum high period of clock is 4us */
2375         usec_delay(IXGBE_I2C_T_HIGH);
2376
2377         /* Poll for ACK.  Note that ACK in I2C spec is
2378          * transition from 1 to 0 */
2379         for (i = 0; i < timeout; i++) {
2380                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2381                 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2382
2383                 usec_delay(1);
2384                 if (!ack)
2385                         break;
2386         }
2387
2388         if (ack) {
2389                 DEBUGOUT("I2C ack was not received.\n");
2390                 status = IXGBE_ERR_I2C;
2391         }
2392
2393         ixgbe_lower_i2c_clk(hw, &i2cctl);
2394
2395         /* Minimum low period of clock is 4.7 us */
2396         usec_delay(IXGBE_I2C_T_LOW);
2397
2398         return status;
2399 }
2400
2401 /**
2402  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2403  *  @hw: pointer to hardware structure
2404  *  @data: read data value
2405  *
2406  *  Clocks in one bit via I2C data/clock
2407  **/
2408 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2409 {
2410         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2411         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2412
2413         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2414
2415         if (data_oe_bit) {
2416                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2417                 i2cctl |= data_oe_bit;
2418                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2419                 IXGBE_WRITE_FLUSH(hw);
2420         }
2421         ixgbe_raise_i2c_clk(hw, &i2cctl);
2422
2423         /* Minimum high period of clock is 4us */
2424         usec_delay(IXGBE_I2C_T_HIGH);
2425
2426         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2427         *data = ixgbe_get_i2c_data(hw, &i2cctl);
2428
2429         ixgbe_lower_i2c_clk(hw, &i2cctl);
2430
2431         /* Minimum low period of clock is 4.7 us */
2432         usec_delay(IXGBE_I2C_T_LOW);
2433
2434         return IXGBE_SUCCESS;
2435 }
2436
2437 /**
2438  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2439  *  @hw: pointer to hardware structure
2440  *  @data: data value to write
2441  *
2442  *  Clocks out one bit via I2C data/clock
2443  **/
2444 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2445 {
2446         s32 status;
2447         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2448
2449         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2450
2451         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2452         if (status == IXGBE_SUCCESS) {
2453                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2454
2455                 /* Minimum high period of clock is 4us */
2456                 usec_delay(IXGBE_I2C_T_HIGH);
2457
2458                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2459
2460                 /* Minimum low period of clock is 4.7 us.
2461                  * This also takes care of the data hold time.
2462                  */
2463                 usec_delay(IXGBE_I2C_T_LOW);
2464         } else {
2465                 status = IXGBE_ERR_I2C;
2466                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2467                              "I2C data was not set to %X\n", data);
2468         }
2469
2470         return status;
2471 }
2472
2473 /**
2474  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2475  *  @hw: pointer to hardware structure
2476  *  @i2cctl: Current value of I2CCTL register
2477  *
2478  *  Raises the I2C clock line '0'->'1'
2479  *  Negates the I2C clock output enable on X550 hardware.
2480  **/
2481 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2482 {
2483         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2484         u32 i = 0;
2485         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2486         u32 i2cctl_r = 0;
2487
2488         DEBUGFUNC("ixgbe_raise_i2c_clk");
2489
2490         if (clk_oe_bit) {
2491                 *i2cctl |= clk_oe_bit;
2492                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2493         }
2494
2495         for (i = 0; i < timeout; i++) {
2496                 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2497
2498                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2499                 IXGBE_WRITE_FLUSH(hw);
2500                 /* SCL rise time (1000ns) */
2501                 usec_delay(IXGBE_I2C_T_RISE);
2502
2503                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2504                 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2505                         break;
2506         }
2507 }
2508
2509 /**
2510  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2511  *  @hw: pointer to hardware structure
2512  *  @i2cctl: Current value of I2CCTL register
2513  *
2514  *  Lowers the I2C clock line '1'->'0'
2515  *  Asserts the I2C clock output enable on X550 hardware.
2516  **/
2517 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2518 {
2519         DEBUGFUNC("ixgbe_lower_i2c_clk");
2520
2521         *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2522         *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2523
2524         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2525         IXGBE_WRITE_FLUSH(hw);
2526
2527         /* SCL fall time (300ns) */
2528         usec_delay(IXGBE_I2C_T_FALL);
2529 }
2530
2531 /**
2532  *  ixgbe_set_i2c_data - Sets the I2C data bit
2533  *  @hw: pointer to hardware structure
2534  *  @i2cctl: Current value of I2CCTL register
2535  *  @data: I2C data value (0 or 1) to set
2536  *
2537  *  Sets the I2C data bit
2538  *  Asserts the I2C data output enable on X550 hardware.
2539  **/
2540 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2541 {
2542         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2543         s32 status = IXGBE_SUCCESS;
2544
2545         DEBUGFUNC("ixgbe_set_i2c_data");
2546
2547         if (data)
2548                 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2549         else
2550                 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2551         *i2cctl &= ~data_oe_bit;
2552
2553         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2554         IXGBE_WRITE_FLUSH(hw);
2555
2556         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2557         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2558
2559         if (!data)      /* Can't verify data in this case */
2560                 return IXGBE_SUCCESS;
2561         if (data_oe_bit) {
2562                 *i2cctl |= data_oe_bit;
2563                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2564                 IXGBE_WRITE_FLUSH(hw);
2565         }
2566
2567         /* Verify data was set correctly */
2568         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2569         if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2570                 status = IXGBE_ERR_I2C;
2571                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2572                              "Error - I2C data was not set to %X.\n",
2573                              data);
2574         }
2575
2576         return status;
2577 }
2578
2579 /**
2580  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2581  *  @hw: pointer to hardware structure
2582  *  @i2cctl: Current value of I2CCTL register
2583  *
2584  *  Returns the I2C data bit value
2585  *  Negates the I2C data output enable on X550 hardware.
2586  **/
2587 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2588 {
2589         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2590         bool data;
2591
2592         DEBUGFUNC("ixgbe_get_i2c_data");
2593
2594         if (data_oe_bit) {
2595                 *i2cctl |= data_oe_bit;
2596                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2597                 IXGBE_WRITE_FLUSH(hw);
2598                 usec_delay(IXGBE_I2C_T_FALL);
2599         }
2600
2601         if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2602                 data = 1;
2603         else
2604                 data = 0;
2605
2606         return data;
2607 }
2608
2609 /**
2610  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2611  *  @hw: pointer to hardware structure
2612  *
2613  *  Clears the I2C bus by sending nine clock pulses.
2614  *  Used when data line is stuck low.
2615  **/
2616 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2617 {
2618         u32 i2cctl;
2619         u32 i;
2620
2621         DEBUGFUNC("ixgbe_i2c_bus_clear");
2622
2623         ixgbe_i2c_start(hw);
2624         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2625
2626         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2627
2628         for (i = 0; i < 9; i++) {
2629                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2630
2631                 /* Min high period of clock is 4us */
2632                 usec_delay(IXGBE_I2C_T_HIGH);
2633
2634                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2635
2636                 /* Min low period of clock is 4.7us*/
2637                 usec_delay(IXGBE_I2C_T_LOW);
2638         }
2639
2640         ixgbe_i2c_start(hw);
2641
2642         /* Put the i2c bus back to default state */
2643         ixgbe_i2c_stop(hw);
2644 }
2645
2646 /**
2647  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2648  *  @hw: pointer to hardware structure
2649  *
2650  *  Checks if the LASI temp alarm status was triggered due to overtemp
2651  **/
2652 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2653 {
2654         s32 status = IXGBE_SUCCESS;
2655         u16 phy_data = 0;
2656
2657         DEBUGFUNC("ixgbe_tn_check_overtemp");
2658
2659         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2660                 goto out;
2661
2662         /* Check that the LASI temp alarm status was triggered */
2663         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2664                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2665
2666         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2667                 goto out;
2668
2669         status = IXGBE_ERR_OVERTEMP;
2670         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2671 out:
2672         return status;
2673 }
2674
2675 /**
2676  * ixgbe_set_copper_phy_power - Control power for copper phy
2677  * @hw: pointer to hardware structure
2678  * @on: true for on, false for off
2679  */
2680 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2681 {
2682         u32 status;
2683         u16 reg;
2684
2685         if (!on && ixgbe_mng_present(hw))
2686                 return 0;
2687
2688         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2689                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2690                                       &reg);
2691         if (status)
2692                 return status;
2693
2694         if (on) {
2695                 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2696         } else {
2697                 if (ixgbe_check_reset_blocked(hw))
2698                         return 0;
2699                 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2700         }
2701
2702         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2703                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2704                                        reg);
2705         return status;
2706 }