1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_api.h"
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
53 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
54 * @hw: pointer to the hardware structure
57 * Returns an error code on error.
59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
63 status = ixgbe_clock_out_i2c_byte(hw, byte);
66 return ixgbe_get_i2c_ack(hw);
70 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
71 * @hw: pointer to the hardware structure
72 * @byte: pointer to a u8 to receive the byte
74 * Returns an error code on error.
76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
80 status = ixgbe_clock_in_i2c_byte(hw, byte);
84 return ixgbe_clock_out_i2c_bit(hw, false);
88 * ixgbe_ones_comp_byte_add - Perform one's complement addition
92 * Returns one's complement 8-bit sum.
94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
96 u16 sum = add1 + add2;
98 sum = (sum & 0xFF) + (sum >> 8);
103 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
104 * @hw: pointer to the hardware structure
105 * @addr: I2C bus address to read from
106 * @reg: I2C device register to read from
107 * @val: pointer to location to receive read value
108 * @lock: true if to take and release semaphore
110 * Returns an error code on error.
112 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
115 u32 swfw_mask = hw->phy.phy_semaphore_mask;
124 if (hw->mac.type >= ixgbe_mac_X550)
126 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
127 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
130 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
131 return IXGBE_ERR_SWFW_SYNC;
133 /* Device Address and write indication */
134 if (ixgbe_out_i2c_byte_ack(hw, addr))
136 /* Write bits 14:8 */
137 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
140 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
143 if (ixgbe_out_i2c_byte_ack(hw, csum))
145 /* Re-start condition */
147 /* Device Address and read indication */
148 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
151 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
154 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
157 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
160 if (ixgbe_clock_out_i2c_bit(hw, false))
164 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
165 *val = (high_bits << 8) | low_bits;
169 ixgbe_i2c_bus_clear(hw);
171 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
173 if (retry < max_retry)
174 DEBUGOUT("I2C byte read combined error - Retrying.\n");
176 DEBUGOUT("I2C byte read combined error.\n");
177 } while (retry < max_retry);
179 return IXGBE_ERR_I2C;
183 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
184 * @hw: pointer to the hardware structure
185 * @addr: I2C bus address to write to
186 * @reg: I2C device register to write to
187 * @val: value to write
188 * @lock: true if to take and release semaphore
190 * Returns an error code on error.
192 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
195 u32 swfw_mask = hw->phy.phy_semaphore_mask;
201 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
202 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
203 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
204 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
207 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
208 return IXGBE_ERR_SWFW_SYNC;
210 /* Device Address and write indication */
211 if (ixgbe_out_i2c_byte_ack(hw, addr))
213 /* Write bits 14:8 */
214 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
217 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
219 /* Write data 15:8 */
220 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
223 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
226 if (ixgbe_out_i2c_byte_ack(hw, csum))
230 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
234 ixgbe_i2c_bus_clear(hw);
236 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
238 if (retry < max_retry)
239 DEBUGOUT("I2C byte write combined error - Retrying.\n");
241 DEBUGOUT("I2C byte write combined error.\n");
242 } while (retry < max_retry);
244 return IXGBE_ERR_I2C;
248 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
249 * @hw: pointer to the hardware structure
251 * Initialize the function pointers.
253 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
255 struct ixgbe_phy_info *phy = &hw->phy;
257 DEBUGFUNC("ixgbe_init_phy_ops_generic");
260 phy->ops.identify = ixgbe_identify_phy_generic;
261 phy->ops.reset = ixgbe_reset_phy_generic;
262 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
263 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
264 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
265 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
266 phy->ops.setup_link = ixgbe_setup_phy_link_generic;
267 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
268 phy->ops.check_link = NULL;
269 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
270 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
271 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
272 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
273 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
274 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
275 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
276 phy->ops.identify_sfp = ixgbe_identify_module_generic;
277 phy->sfp_type = ixgbe_sfp_type_unknown;
278 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
279 phy->ops.write_i2c_byte_unlocked =
280 ixgbe_write_i2c_byte_generic_unlocked;
281 phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
282 return IXGBE_SUCCESS;
286 * ixgbe_probe_phy - Probe a single address for a PHY
287 * @hw: pointer to hardware structure
288 * @phy_addr: PHY address to probe
290 * Returns true if PHY found
292 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
296 if (!ixgbe_validate_phy_addr(hw, phy_addr))
299 if (ixgbe_get_phy_id(hw))
302 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
304 if (hw->phy.type == ixgbe_phy_unknown) {
305 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
306 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
308 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
309 IXGBE_MDIO_PHY_1000BASET_ABILITY))
310 hw->phy.type = ixgbe_phy_cu_unknown;
312 hw->phy.type = ixgbe_phy_generic;
319 * ixgbe_identify_phy_generic - Get physical layer module
320 * @hw: pointer to hardware structure
322 * Determines the physical layer module found on the current adapter.
324 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
326 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
329 DEBUGFUNC("ixgbe_identify_phy_generic");
331 if (!hw->phy.phy_semaphore_mask) {
333 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
335 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
338 if (hw->phy.type != ixgbe_phy_unknown)
339 return IXGBE_SUCCESS;
341 if (hw->phy.nw_mng_if_sel) {
342 phy_addr = (hw->phy.nw_mng_if_sel &
343 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
344 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
345 if (ixgbe_probe_phy(hw, phy_addr))
346 return IXGBE_SUCCESS;
348 return IXGBE_ERR_PHY_ADDR_INVALID;
351 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
352 if (ixgbe_probe_phy(hw, phy_addr)) {
353 status = IXGBE_SUCCESS;
358 /* Certain media types do not have a phy so an address will not
359 * be found and the code will take this path. Caller has to
360 * decide if it is an error or not.
362 if (status != IXGBE_SUCCESS)
369 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
370 * @hw: pointer to the hardware structure
372 * This function checks the MMNGC.MNG_VETO bit to see if there are
373 * any constraints on link from manageability. For MAC's that don't
374 * have this bit just return faluse since the link can not be blocked
377 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
381 DEBUGFUNC("ixgbe_check_reset_blocked");
383 /* If we don't have this bit, it can't be blocking */
384 if (hw->mac.type == ixgbe_mac_82598EB)
387 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
388 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
389 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
390 "MNG_VETO bit detected.\n");
398 * ixgbe_validate_phy_addr - Determines phy address is valid
399 * @hw: pointer to hardware structure
402 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
407 DEBUGFUNC("ixgbe_validate_phy_addr");
409 hw->phy.addr = phy_addr;
410 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
411 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
413 if (phy_id != 0xFFFF && phy_id != 0x0)
420 * ixgbe_get_phy_id - Get the phy type
421 * @hw: pointer to hardware structure
424 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
430 DEBUGFUNC("ixgbe_get_phy_id");
432 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
433 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
436 if (status == IXGBE_SUCCESS) {
437 hw->phy.id = (u32)(phy_id_high << 16);
438 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
439 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
441 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
442 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
448 * ixgbe_get_phy_type_from_id - Get the phy type
449 * @phy_id: PHY ID information
452 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
454 enum ixgbe_phy_type phy_type;
456 DEBUGFUNC("ixgbe_get_phy_type_from_id");
460 phy_type = ixgbe_phy_tn;
466 phy_type = ixgbe_phy_aq;
469 phy_type = ixgbe_phy_qt;
472 phy_type = ixgbe_phy_nl;
476 phy_type = ixgbe_phy_x550em_ext_t;
478 case IXGBE_M88E1500_E_PHY_ID:
479 case IXGBE_M88E1543_E_PHY_ID:
480 phy_type = ixgbe_phy_m88;
483 phy_type = ixgbe_phy_unknown;
490 * ixgbe_reset_phy_generic - Performs a PHY reset
491 * @hw: pointer to hardware structure
493 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
497 s32 status = IXGBE_SUCCESS;
499 DEBUGFUNC("ixgbe_reset_phy_generic");
501 if (hw->phy.type == ixgbe_phy_unknown)
502 status = ixgbe_identify_phy_generic(hw);
504 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
507 /* Don't reset PHY if it's shut down due to overtemp. */
508 if (!hw->phy.reset_if_overtemp &&
509 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
512 /* Blocked by MNG FW so bail */
513 if (ixgbe_check_reset_blocked(hw))
517 * Perform soft PHY reset to the PHY_XS.
518 * This will cause a soft reset to the PHY
520 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
521 IXGBE_MDIO_PHY_XS_DEV_TYPE,
522 IXGBE_MDIO_PHY_XS_RESET);
525 * Poll for reset bit to self-clear indicating reset is complete.
526 * Some PHYs could take up to 3 seconds to complete and need about
527 * 1.7 usec delay after the reset is complete.
529 for (i = 0; i < 30; i++) {
531 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
532 status = hw->phy.ops.read_reg(hw,
533 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
534 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
536 if (status != IXGBE_SUCCESS)
539 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
544 status = hw->phy.ops.read_reg(hw,
545 IXGBE_MDIO_PHY_XS_CONTROL,
546 IXGBE_MDIO_PHY_XS_DEV_TYPE,
548 if (status != IXGBE_SUCCESS)
551 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
558 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
559 status = IXGBE_ERR_RESET_FAILED;
560 ERROR_REPORT1(IXGBE_ERROR_POLLING,
561 "PHY reset polling failed to complete.\n");
569 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
571 * @hw: pointer to hardware structure
572 * @reg_addr: 32 bit address of PHY register to read
573 * @phy_data: Pointer to read data from PHY register
575 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
578 u32 i, data, command;
580 /* Setup and write the address cycle command */
581 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
582 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
583 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
584 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
586 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
589 * Check every 10 usec to see if the address cycle completed.
590 * The MDI Command bit will clear when the operation is
593 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
596 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
597 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
602 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
603 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
604 return IXGBE_ERR_PHY;
608 * Address cycle complete, setup and write the read
611 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
612 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
613 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
614 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
616 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
619 * Check every 10 usec to see if the address cycle
620 * completed. The MDI Command bit will clear when the
621 * operation is complete
623 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
626 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
627 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
631 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
632 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
633 return IXGBE_ERR_PHY;
637 * Read operation is complete. Get the data
640 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
641 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
642 *phy_data = (u16)(data);
644 return IXGBE_SUCCESS;
648 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
649 * using the SWFW lock - this function is needed in most cases
650 * @hw: pointer to hardware structure
651 * @reg_addr: 32 bit address of PHY register to read
652 * @phy_data: Pointer to read data from PHY register
654 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
655 u32 device_type, u16 *phy_data)
658 u32 gssr = hw->phy.phy_semaphore_mask;
660 DEBUGFUNC("ixgbe_read_phy_reg_generic");
662 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
663 return IXGBE_ERR_SWFW_SYNC;
665 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
667 hw->mac.ops.release_swfw_sync(hw, gssr);
673 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
675 * @hw: pointer to hardware structure
676 * @reg_addr: 32 bit PHY register to write
677 * @device_type: 5 bit device type
678 * @phy_data: Data to write to the PHY register
680 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
681 u32 device_type, u16 phy_data)
685 /* Put the data in the MDI single read and write data register*/
686 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
688 /* Setup and write the address cycle command */
689 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
690 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
691 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
692 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
694 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
697 * Check every 10 usec to see if the address cycle completed.
698 * The MDI Command bit will clear when the operation is
701 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
704 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
705 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
709 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
710 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
711 return IXGBE_ERR_PHY;
715 * Address cycle complete, setup and write the write
718 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
719 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
720 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
721 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
723 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
726 * Check every 10 usec to see if the address cycle
727 * completed. The MDI Command bit will clear when the
728 * operation is complete
730 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
733 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
734 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
738 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
739 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
740 return IXGBE_ERR_PHY;
743 return IXGBE_SUCCESS;
747 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
748 * using SWFW lock- this function is needed in most cases
749 * @hw: pointer to hardware structure
750 * @reg_addr: 32 bit PHY register to write
751 * @device_type: 5 bit device type
752 * @phy_data: Data to write to the PHY register
754 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
755 u32 device_type, u16 phy_data)
758 u32 gssr = hw->phy.phy_semaphore_mask;
760 DEBUGFUNC("ixgbe_write_phy_reg_generic");
762 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
763 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
765 hw->mac.ops.release_swfw_sync(hw, gssr);
767 status = IXGBE_ERR_SWFW_SYNC;
774 * ixgbe_setup_phy_link_generic - Set and restart auto-neg
775 * @hw: pointer to hardware structure
777 * Restart auto-negotiation and PHY and waits for completion.
779 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
781 s32 status = IXGBE_SUCCESS;
782 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
783 bool autoneg = false;
784 ixgbe_link_speed speed;
786 DEBUGFUNC("ixgbe_setup_phy_link_generic");
788 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
790 /* Set or unset auto-negotiation 10G advertisement */
791 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
792 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
795 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
796 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
797 (speed & IXGBE_LINK_SPEED_10GB_FULL))
798 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
800 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
801 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
804 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
805 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
808 if (hw->mac.type == ixgbe_mac_X550) {
809 /* Set or unset auto-negotiation 5G advertisement */
810 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
811 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
812 (speed & IXGBE_LINK_SPEED_5GB_FULL))
813 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
815 /* Set or unset auto-negotiation 2.5G advertisement */
816 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
817 if ((hw->phy.autoneg_advertised &
818 IXGBE_LINK_SPEED_2_5GB_FULL) &&
819 (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
820 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
823 /* Set or unset auto-negotiation 1G advertisement */
824 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
825 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
826 (speed & IXGBE_LINK_SPEED_1GB_FULL))
827 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
829 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
830 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
833 /* Set or unset auto-negotiation 100M advertisement */
834 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
835 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
838 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
839 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
840 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
841 (speed & IXGBE_LINK_SPEED_100_FULL))
842 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
844 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
845 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
848 /* Blocked by MNG FW so don't reset PHY */
849 if (ixgbe_check_reset_blocked(hw))
852 /* Restart PHY auto-negotiation. */
853 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
854 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
856 autoneg_reg |= IXGBE_MII_RESTART;
858 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
859 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
865 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
866 * @hw: pointer to hardware structure
867 * @speed: new link speed
869 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
870 ixgbe_link_speed speed,
871 bool autoneg_wait_to_complete)
873 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
875 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
878 * Clear autoneg_advertised and set new values based on input link
881 hw->phy.autoneg_advertised = 0;
883 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
884 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
886 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
887 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
889 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
890 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
892 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
893 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
895 if (speed & IXGBE_LINK_SPEED_100_FULL)
896 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
898 if (speed & IXGBE_LINK_SPEED_10_FULL)
899 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
901 /* Setup link based on the new speed settings */
902 ixgbe_setup_phy_link(hw);
904 return IXGBE_SUCCESS;
908 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
909 * @hw: pointer to hardware structure
911 * Determines the supported link capabilities by reading the PHY auto
912 * negotiation register.
914 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
919 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
920 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
925 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
926 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
927 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
928 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
929 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
930 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
932 switch (hw->mac.type) {
934 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
935 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
937 case ixgbe_mac_X550EM_x:
938 case ixgbe_mac_X550EM_a:
939 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
949 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
950 * @hw: pointer to hardware structure
951 * @speed: pointer to link speed
952 * @autoneg: boolean auto-negotiation value
954 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
955 ixgbe_link_speed *speed,
958 s32 status = IXGBE_SUCCESS;
960 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
963 if (!hw->phy.speeds_supported)
964 status = ixgbe_get_copper_speeds_supported(hw);
966 *speed = hw->phy.speeds_supported;
971 * ixgbe_check_phy_link_tnx - Determine link and speed status
972 * @hw: pointer to hardware structure
974 * Reads the VS1 register to determine if link is up and the current speed for
977 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
980 s32 status = IXGBE_SUCCESS;
982 u32 max_time_out = 10;
987 DEBUGFUNC("ixgbe_check_phy_link_tnx");
989 /* Initialize speed and link to default case */
991 *speed = IXGBE_LINK_SPEED_10GB_FULL;
994 * Check current speed and link status of the PHY register.
995 * This is a vendor specific register and may have to
996 * be changed for other copper PHYs.
998 for (time_out = 0; time_out < max_time_out; time_out++) {
1000 status = hw->phy.ops.read_reg(hw,
1001 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1002 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1004 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1005 phy_speed = phy_data &
1006 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1007 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1010 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1011 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1020 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1021 * @hw: pointer to hardware structure
1023 * Restart auto-negotiation and PHY and waits for completion.
1025 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1027 s32 status = IXGBE_SUCCESS;
1028 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1029 bool autoneg = false;
1030 ixgbe_link_speed speed;
1032 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1034 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1036 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1037 /* Set or unset auto-negotiation 10G advertisement */
1038 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1039 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1042 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1043 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1044 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1046 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1047 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1051 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1052 /* Set or unset auto-negotiation 1G advertisement */
1053 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1054 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1057 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1058 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1059 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1061 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1062 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1066 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1067 /* Set or unset auto-negotiation 100M advertisement */
1068 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1069 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1072 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1073 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1074 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1076 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1077 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1081 /* Blocked by MNG FW so don't reset PHY */
1082 if (ixgbe_check_reset_blocked(hw))
1085 /* Restart PHY auto-negotiation. */
1086 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1087 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1089 autoneg_reg |= IXGBE_MII_RESTART;
1091 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1092 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1098 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1099 * @hw: pointer to hardware structure
1100 * @firmware_version: pointer to the PHY Firmware Version
1102 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1103 u16 *firmware_version)
1107 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1109 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1110 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1117 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1118 * @hw: pointer to hardware structure
1119 * @firmware_version: pointer to the PHY Firmware Version
1121 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1122 u16 *firmware_version)
1126 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1128 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1129 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1136 * ixgbe_reset_phy_nl - Performs a PHY reset
1137 * @hw: pointer to hardware structure
1139 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1141 u16 phy_offset, control, eword, edata, block_crc;
1142 bool end_data = false;
1143 u16 list_offset, data_offset;
1145 s32 ret_val = IXGBE_SUCCESS;
1148 DEBUGFUNC("ixgbe_reset_phy_nl");
1150 /* Blocked by MNG FW so bail */
1151 if (ixgbe_check_reset_blocked(hw))
1154 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1155 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1157 /* reset the PHY and poll for completion */
1158 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1159 IXGBE_MDIO_PHY_XS_DEV_TYPE,
1160 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1162 for (i = 0; i < 100; i++) {
1163 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1164 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1165 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1170 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1171 DEBUGOUT("PHY reset did not complete.\n");
1172 ret_val = IXGBE_ERR_PHY;
1176 /* Get init offsets */
1177 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1179 if (ret_val != IXGBE_SUCCESS)
1182 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1186 * Read control word from PHY init contents offset
1188 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1191 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1192 IXGBE_CONTROL_SHIFT_NL;
1193 edata = eword & IXGBE_DATA_MASK_NL;
1195 case IXGBE_DELAY_NL:
1197 DEBUGOUT1("DELAY: %d MS\n", edata);
1201 DEBUGOUT("DATA:\n");
1203 ret_val = hw->eeprom.ops.read(hw, data_offset,
1208 for (i = 0; i < edata; i++) {
1209 ret_val = hw->eeprom.ops.read(hw, data_offset,
1213 hw->phy.ops.write_reg(hw, phy_offset,
1214 IXGBE_TWINAX_DEV, eword);
1215 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1221 case IXGBE_CONTROL_NL:
1223 DEBUGOUT("CONTROL:\n");
1224 if (edata == IXGBE_CONTROL_EOL_NL) {
1227 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1230 DEBUGOUT("Bad control value\n");
1231 ret_val = IXGBE_ERR_PHY;
1236 DEBUGOUT("Bad control type\n");
1237 ret_val = IXGBE_ERR_PHY;
1246 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1247 "eeprom read at offset %d failed", data_offset);
1248 return IXGBE_ERR_PHY;
1252 * ixgbe_identify_module_generic - Identifies module type
1253 * @hw: pointer to hardware structure
1255 * Determines HW type and calls appropriate function.
1257 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1259 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1261 DEBUGFUNC("ixgbe_identify_module_generic");
1263 switch (hw->mac.ops.get_media_type(hw)) {
1264 case ixgbe_media_type_fiber:
1265 status = ixgbe_identify_sfp_module_generic(hw);
1268 case ixgbe_media_type_fiber_qsfp:
1269 status = ixgbe_identify_qsfp_module_generic(hw);
1273 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1274 status = IXGBE_ERR_SFP_NOT_PRESENT;
1282 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1283 * @hw: pointer to hardware structure
1285 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1287 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1289 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1291 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1293 u8 comp_codes_1g = 0;
1294 u8 comp_codes_10g = 0;
1295 u8 oui_bytes[3] = {0, 0, 0};
1298 u16 enforce_sfp = 0;
1300 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1302 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1303 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1304 status = IXGBE_ERR_SFP_NOT_PRESENT;
1308 /* LAN ID is needed for I2C access */
1309 hw->mac.ops.set_lan_id(hw);
1311 status = hw->phy.ops.read_i2c_eeprom(hw,
1312 IXGBE_SFF_IDENTIFIER,
1315 if (status != IXGBE_SUCCESS)
1316 goto err_read_i2c_eeprom;
1318 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1319 hw->phy.type = ixgbe_phy_sfp_unsupported;
1320 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1322 status = hw->phy.ops.read_i2c_eeprom(hw,
1323 IXGBE_SFF_1GBE_COMP_CODES,
1326 if (status != IXGBE_SUCCESS)
1327 goto err_read_i2c_eeprom;
1329 status = hw->phy.ops.read_i2c_eeprom(hw,
1330 IXGBE_SFF_10GBE_COMP_CODES,
1333 if (status != IXGBE_SUCCESS)
1334 goto err_read_i2c_eeprom;
1335 status = hw->phy.ops.read_i2c_eeprom(hw,
1336 IXGBE_SFF_CABLE_TECHNOLOGY,
1339 if (status != IXGBE_SUCCESS)
1340 goto err_read_i2c_eeprom;
1347 * 3 SFP_DA_CORE0 - 82599-specific
1348 * 4 SFP_DA_CORE1 - 82599-specific
1349 * 5 SFP_SR/LR_CORE0 - 82599-specific
1350 * 6 SFP_SR/LR_CORE1 - 82599-specific
1351 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1352 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1353 * 9 SFP_1g_cu_CORE0 - 82599-specific
1354 * 10 SFP_1g_cu_CORE1 - 82599-specific
1355 * 11 SFP_1g_sx_CORE0 - 82599-specific
1356 * 12 SFP_1g_sx_CORE1 - 82599-specific
1358 if (hw->mac.type == ixgbe_mac_82598EB) {
1359 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1360 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1361 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1362 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1363 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1364 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1366 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1368 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1369 if (hw->bus.lan_id == 0)
1371 ixgbe_sfp_type_da_cu_core0;
1374 ixgbe_sfp_type_da_cu_core1;
1375 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1376 hw->phy.ops.read_i2c_eeprom(
1377 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1380 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1381 if (hw->bus.lan_id == 0)
1383 ixgbe_sfp_type_da_act_lmt_core0;
1386 ixgbe_sfp_type_da_act_lmt_core1;
1389 ixgbe_sfp_type_unknown;
1391 } else if (comp_codes_10g &
1392 (IXGBE_SFF_10GBASESR_CAPABLE |
1393 IXGBE_SFF_10GBASELR_CAPABLE)) {
1394 if (hw->bus.lan_id == 0)
1396 ixgbe_sfp_type_srlr_core0;
1399 ixgbe_sfp_type_srlr_core1;
1400 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1401 if (hw->bus.lan_id == 0)
1403 ixgbe_sfp_type_1g_cu_core0;
1406 ixgbe_sfp_type_1g_cu_core1;
1407 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1408 if (hw->bus.lan_id == 0)
1410 ixgbe_sfp_type_1g_sx_core0;
1413 ixgbe_sfp_type_1g_sx_core1;
1414 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1415 if (hw->bus.lan_id == 0)
1417 ixgbe_sfp_type_1g_lx_core0;
1420 ixgbe_sfp_type_1g_lx_core1;
1422 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1426 if (hw->phy.sfp_type != stored_sfp_type)
1427 hw->phy.sfp_setup_needed = true;
1429 /* Determine if the SFP+ PHY is dual speed or not. */
1430 hw->phy.multispeed_fiber = false;
1431 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1432 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1433 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1434 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1435 hw->phy.multispeed_fiber = true;
1437 /* Determine PHY vendor */
1438 if (hw->phy.type != ixgbe_phy_nl) {
1439 hw->phy.id = identifier;
1440 status = hw->phy.ops.read_i2c_eeprom(hw,
1441 IXGBE_SFF_VENDOR_OUI_BYTE0,
1444 if (status != IXGBE_SUCCESS)
1445 goto err_read_i2c_eeprom;
1447 status = hw->phy.ops.read_i2c_eeprom(hw,
1448 IXGBE_SFF_VENDOR_OUI_BYTE1,
1451 if (status != IXGBE_SUCCESS)
1452 goto err_read_i2c_eeprom;
1454 status = hw->phy.ops.read_i2c_eeprom(hw,
1455 IXGBE_SFF_VENDOR_OUI_BYTE2,
1458 if (status != IXGBE_SUCCESS)
1459 goto err_read_i2c_eeprom;
1462 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1463 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1464 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1466 switch (vendor_oui) {
1467 case IXGBE_SFF_VENDOR_OUI_TYCO:
1468 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1470 ixgbe_phy_sfp_passive_tyco;
1472 case IXGBE_SFF_VENDOR_OUI_FTL:
1473 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1474 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1476 hw->phy.type = ixgbe_phy_sfp_ftl;
1478 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1479 hw->phy.type = ixgbe_phy_sfp_avago;
1481 case IXGBE_SFF_VENDOR_OUI_INTEL:
1482 hw->phy.type = ixgbe_phy_sfp_intel;
1485 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1487 ixgbe_phy_sfp_passive_unknown;
1488 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1490 ixgbe_phy_sfp_active_unknown;
1492 hw->phy.type = ixgbe_phy_sfp_unknown;
1497 /* Allow any DA cable vendor */
1498 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1499 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1500 status = IXGBE_SUCCESS;
1504 /* Verify supported 1G SFP modules */
1505 if (comp_codes_10g == 0 &&
1506 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1507 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1508 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1509 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1510 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1511 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1512 hw->phy.type = ixgbe_phy_sfp_unsupported;
1513 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1517 /* Anything else 82598-based is supported */
1518 if (hw->mac.type == ixgbe_mac_82598EB) {
1519 status = IXGBE_SUCCESS;
1523 ixgbe_get_device_caps(hw, &enforce_sfp);
1524 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1525 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1526 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1527 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1528 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1529 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1530 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1531 /* Make sure we're a supported PHY type */
1532 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1533 status = IXGBE_SUCCESS;
1535 if (hw->allow_unsupported_sfp == true) {
1536 EWARN(hw, "WARNING: Intel (R) Network "
1537 "Connections are quality tested "
1538 "using Intel (R) Ethernet Optics."
1539 " Using untested modules is not "
1540 "supported and may cause unstable"
1541 " operation or damage to the "
1542 "module or the adapter. Intel "
1543 "Corporation is not responsible "
1544 "for any harm caused by using "
1545 "untested modules.\n", status);
1546 status = IXGBE_SUCCESS;
1548 DEBUGOUT("SFP+ module not supported\n");
1550 ixgbe_phy_sfp_unsupported;
1551 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1555 status = IXGBE_SUCCESS;
1562 err_read_i2c_eeprom:
1563 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1564 if (hw->phy.type != ixgbe_phy_nl) {
1566 hw->phy.type = ixgbe_phy_unknown;
1568 return IXGBE_ERR_SFP_NOT_PRESENT;
1572 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1573 * @hw: pointer to hardware structure
1575 * Determines physical layer capabilities of the current SFP.
1577 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1579 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1580 u8 comp_codes_10g = 0;
1581 u8 comp_codes_1g = 0;
1583 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1585 hw->phy.ops.identify_sfp(hw);
1586 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1587 return physical_layer;
1589 switch (hw->phy.type) {
1590 case ixgbe_phy_sfp_passive_tyco:
1591 case ixgbe_phy_sfp_passive_unknown:
1592 case ixgbe_phy_qsfp_passive_unknown:
1593 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1595 case ixgbe_phy_sfp_ftl_active:
1596 case ixgbe_phy_sfp_active_unknown:
1597 case ixgbe_phy_qsfp_active_unknown:
1598 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1600 case ixgbe_phy_sfp_avago:
1601 case ixgbe_phy_sfp_ftl:
1602 case ixgbe_phy_sfp_intel:
1603 case ixgbe_phy_sfp_unknown:
1604 hw->phy.ops.read_i2c_eeprom(hw,
1605 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1606 hw->phy.ops.read_i2c_eeprom(hw,
1607 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1608 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1609 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1610 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1611 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1612 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1613 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1614 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1615 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1617 case ixgbe_phy_qsfp_intel:
1618 case ixgbe_phy_qsfp_unknown:
1619 hw->phy.ops.read_i2c_eeprom(hw,
1620 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1621 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1622 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1623 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1624 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1630 return physical_layer;
1634 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1635 * @hw: pointer to hardware structure
1637 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1639 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1641 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1643 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1645 u8 comp_codes_1g = 0;
1646 u8 comp_codes_10g = 0;
1647 u8 oui_bytes[3] = {0, 0, 0};
1648 u16 enforce_sfp = 0;
1650 u8 cable_length = 0;
1652 bool active_cable = false;
1654 DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1656 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1657 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1658 status = IXGBE_ERR_SFP_NOT_PRESENT;
1662 /* LAN ID is needed for I2C access */
1663 hw->mac.ops.set_lan_id(hw);
1665 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1668 if (status != IXGBE_SUCCESS)
1669 goto err_read_i2c_eeprom;
1671 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1672 hw->phy.type = ixgbe_phy_sfp_unsupported;
1673 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1677 hw->phy.id = identifier;
1679 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1682 if (status != IXGBE_SUCCESS)
1683 goto err_read_i2c_eeprom;
1685 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1688 if (status != IXGBE_SUCCESS)
1689 goto err_read_i2c_eeprom;
1691 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1692 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1693 if (hw->bus.lan_id == 0)
1694 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1696 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1697 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1698 IXGBE_SFF_10GBASELR_CAPABLE)) {
1699 if (hw->bus.lan_id == 0)
1700 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1702 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1704 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1705 active_cable = true;
1707 if (!active_cable) {
1708 /* check for active DA cables that pre-date
1710 hw->phy.ops.read_i2c_eeprom(hw,
1711 IXGBE_SFF_QSFP_CONNECTOR,
1714 hw->phy.ops.read_i2c_eeprom(hw,
1715 IXGBE_SFF_QSFP_CABLE_LENGTH,
1718 hw->phy.ops.read_i2c_eeprom(hw,
1719 IXGBE_SFF_QSFP_DEVICE_TECH,
1723 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1724 (cable_length > 0) &&
1725 ((device_tech >> 4) ==
1726 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1727 active_cable = true;
1731 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1732 if (hw->bus.lan_id == 0)
1734 ixgbe_sfp_type_da_act_lmt_core0;
1737 ixgbe_sfp_type_da_act_lmt_core1;
1739 /* unsupported module type */
1740 hw->phy.type = ixgbe_phy_sfp_unsupported;
1741 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1746 if (hw->phy.sfp_type != stored_sfp_type)
1747 hw->phy.sfp_setup_needed = true;
1749 /* Determine if the QSFP+ PHY is dual speed or not. */
1750 hw->phy.multispeed_fiber = false;
1751 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1752 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1753 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1754 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1755 hw->phy.multispeed_fiber = true;
1757 /* Determine PHY vendor for optical modules */
1758 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1759 IXGBE_SFF_10GBASELR_CAPABLE)) {
1760 status = hw->phy.ops.read_i2c_eeprom(hw,
1761 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1764 if (status != IXGBE_SUCCESS)
1765 goto err_read_i2c_eeprom;
1767 status = hw->phy.ops.read_i2c_eeprom(hw,
1768 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1771 if (status != IXGBE_SUCCESS)
1772 goto err_read_i2c_eeprom;
1774 status = hw->phy.ops.read_i2c_eeprom(hw,
1775 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1778 if (status != IXGBE_SUCCESS)
1779 goto err_read_i2c_eeprom;
1782 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1783 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1784 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1786 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1787 hw->phy.type = ixgbe_phy_qsfp_intel;
1789 hw->phy.type = ixgbe_phy_qsfp_unknown;
1791 ixgbe_get_device_caps(hw, &enforce_sfp);
1792 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1793 /* Make sure we're a supported PHY type */
1794 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1795 status = IXGBE_SUCCESS;
1797 if (hw->allow_unsupported_sfp == true) {
1798 EWARN(hw, "WARNING: Intel (R) Network "
1799 "Connections are quality tested "
1800 "using Intel (R) Ethernet Optics."
1801 " Using untested modules is not "
1802 "supported and may cause unstable"
1803 " operation or damage to the "
1804 "module or the adapter. Intel "
1805 "Corporation is not responsible "
1806 "for any harm caused by using "
1807 "untested modules.\n", status);
1808 status = IXGBE_SUCCESS;
1810 DEBUGOUT("QSFP module not supported\n");
1812 ixgbe_phy_sfp_unsupported;
1813 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1817 status = IXGBE_SUCCESS;
1824 err_read_i2c_eeprom:
1825 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1827 hw->phy.type = ixgbe_phy_unknown;
1829 return IXGBE_ERR_SFP_NOT_PRESENT;
1834 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1835 * @hw: pointer to hardware structure
1836 * @list_offset: offset to the SFP ID list
1837 * @data_offset: offset to the SFP data block
1839 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1840 * so it returns the offsets to the phy init sequence block.
1842 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1847 u16 sfp_type = hw->phy.sfp_type;
1849 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1851 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1852 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1854 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1855 return IXGBE_ERR_SFP_NOT_PRESENT;
1857 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1858 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1859 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1862 * Limiting active cables and 1G Phys must be initialized as
1865 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1866 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1867 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1868 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1869 sfp_type = ixgbe_sfp_type_srlr_core0;
1870 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1871 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1872 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1873 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1874 sfp_type = ixgbe_sfp_type_srlr_core1;
1876 /* Read offset to PHY init contents */
1877 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1878 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1879 "eeprom read at offset %d failed",
1880 IXGBE_PHY_INIT_OFFSET_NL);
1881 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1884 if ((!*list_offset) || (*list_offset == 0xFFFF))
1885 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1887 /* Shift offset to first ID word */
1891 * Find the matching SFP ID in the EEPROM
1892 * and program the init sequence
1894 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1897 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1898 if (sfp_id == sfp_type) {
1900 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1902 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1903 DEBUGOUT("SFP+ module not supported\n");
1904 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1909 (*list_offset) += 2;
1910 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1915 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1916 DEBUGOUT("No matching SFP+ module found\n");
1917 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1920 return IXGBE_SUCCESS;
1923 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1924 "eeprom read at offset %d failed", *list_offset);
1925 return IXGBE_ERR_PHY;
1929 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1930 * @hw: pointer to hardware structure
1931 * @byte_offset: EEPROM byte offset to read
1932 * @eeprom_data: value read
1934 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1936 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1939 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1941 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1942 IXGBE_I2C_EEPROM_DEV_ADDR,
1947 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1948 * @hw: pointer to hardware structure
1949 * @byte_offset: byte offset at address 0xA2
1950 * @eeprom_data: value read
1952 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1954 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1957 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1958 IXGBE_I2C_EEPROM_DEV_ADDR2,
1963 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1964 * @hw: pointer to hardware structure
1965 * @byte_offset: EEPROM byte offset to write
1966 * @eeprom_data: value to write
1968 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1970 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1973 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1975 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1976 IXGBE_I2C_EEPROM_DEV_ADDR,
1981 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1982 * @hw: pointer to hardware structure
1983 * @offset: eeprom offset to be read
1984 * @addr: I2C address to be read
1986 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1988 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1989 offset == IXGBE_SFF_IDENTIFIER &&
1990 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1996 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1997 * @hw: pointer to hardware structure
1998 * @byte_offset: byte offset to read
2000 * @lock: true if to take and release semaphore
2002 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2003 * a specified device address.
2005 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2006 u8 dev_addr, u8 *data, bool lock)
2011 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2015 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2017 if (hw->mac.type >= ixgbe_mac_X550)
2019 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2020 max_retry = IXGBE_SFP_DETECT_RETRIES;
2023 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2024 return IXGBE_ERR_SWFW_SYNC;
2026 ixgbe_i2c_start(hw);
2028 /* Device Address and write indication */
2029 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2030 if (status != IXGBE_SUCCESS)
2033 status = ixgbe_get_i2c_ack(hw);
2034 if (status != IXGBE_SUCCESS)
2037 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2038 if (status != IXGBE_SUCCESS)
2041 status = ixgbe_get_i2c_ack(hw);
2042 if (status != IXGBE_SUCCESS)
2045 ixgbe_i2c_start(hw);
2047 /* Device Address and read indication */
2048 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2049 if (status != IXGBE_SUCCESS)
2052 status = ixgbe_get_i2c_ack(hw);
2053 if (status != IXGBE_SUCCESS)
2056 status = ixgbe_clock_in_i2c_byte(hw, data);
2057 if (status != IXGBE_SUCCESS)
2060 status = ixgbe_clock_out_i2c_bit(hw, nack);
2061 if (status != IXGBE_SUCCESS)
2066 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2067 return IXGBE_SUCCESS;
2070 ixgbe_i2c_bus_clear(hw);
2072 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2076 if (retry < max_retry)
2077 DEBUGOUT("I2C byte read error - Retrying.\n");
2079 DEBUGOUT("I2C byte read error.\n");
2081 } while (retry < max_retry);
2087 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2088 * @hw: pointer to hardware structure
2089 * @byte_offset: byte offset to read
2092 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2093 * a specified device address.
2095 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2096 u8 dev_addr, u8 *data)
2098 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2103 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2104 * @hw: pointer to hardware structure
2105 * @byte_offset: byte offset to read
2108 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2109 * a specified device address.
2111 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2112 u8 dev_addr, u8 *data)
2114 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2119 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2120 * @hw: pointer to hardware structure
2121 * @byte_offset: byte offset to write
2122 * @data: value to write
2123 * @lock: true if to take and release semaphore
2125 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2126 * a specified device address.
2128 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2129 u8 dev_addr, u8 data, bool lock)
2134 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2136 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2138 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2140 return IXGBE_ERR_SWFW_SYNC;
2143 ixgbe_i2c_start(hw);
2145 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2146 if (status != IXGBE_SUCCESS)
2149 status = ixgbe_get_i2c_ack(hw);
2150 if (status != IXGBE_SUCCESS)
2153 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2154 if (status != IXGBE_SUCCESS)
2157 status = ixgbe_get_i2c_ack(hw);
2158 if (status != IXGBE_SUCCESS)
2161 status = ixgbe_clock_out_i2c_byte(hw, data);
2162 if (status != IXGBE_SUCCESS)
2165 status = ixgbe_get_i2c_ack(hw);
2166 if (status != IXGBE_SUCCESS)
2171 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2172 return IXGBE_SUCCESS;
2175 ixgbe_i2c_bus_clear(hw);
2177 if (retry < max_retry)
2178 DEBUGOUT("I2C byte write error - Retrying.\n");
2180 DEBUGOUT("I2C byte write error.\n");
2181 } while (retry < max_retry);
2184 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2190 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2191 * @hw: pointer to hardware structure
2192 * @byte_offset: byte offset to write
2193 * @data: value to write
2195 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2196 * a specified device address.
2198 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2199 u8 dev_addr, u8 data)
2201 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2206 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2207 * @hw: pointer to hardware structure
2208 * @byte_offset: byte offset to write
2209 * @data: value to write
2211 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2212 * a specified device address.
2214 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2215 u8 dev_addr, u8 data)
2217 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2222 * ixgbe_i2c_start - Sets I2C start condition
2223 * @hw: pointer to hardware structure
2225 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2226 * Set bit-bang mode on X550 hardware.
2228 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2230 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2232 DEBUGFUNC("ixgbe_i2c_start");
2234 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2236 /* Start condition must begin with data and clock high */
2237 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2238 ixgbe_raise_i2c_clk(hw, &i2cctl);
2240 /* Setup time for start condition (4.7us) */
2241 usec_delay(IXGBE_I2C_T_SU_STA);
2243 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2245 /* Hold time for start condition (4us) */
2246 usec_delay(IXGBE_I2C_T_HD_STA);
2248 ixgbe_lower_i2c_clk(hw, &i2cctl);
2250 /* Minimum low period of clock is 4.7 us */
2251 usec_delay(IXGBE_I2C_T_LOW);
2256 * ixgbe_i2c_stop - Sets I2C stop condition
2257 * @hw: pointer to hardware structure
2259 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2260 * Disables bit-bang mode and negates data output enable on X550
2263 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2265 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2266 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2267 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2268 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2270 DEBUGFUNC("ixgbe_i2c_stop");
2272 /* Stop condition must begin with data low and clock high */
2273 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2274 ixgbe_raise_i2c_clk(hw, &i2cctl);
2276 /* Setup time for stop condition (4us) */
2277 usec_delay(IXGBE_I2C_T_SU_STO);
2279 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2281 /* bus free time between stop and start (4.7us)*/
2282 usec_delay(IXGBE_I2C_T_BUF);
2284 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2285 i2cctl &= ~bb_en_bit;
2286 i2cctl |= data_oe_bit | clk_oe_bit;
2287 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2288 IXGBE_WRITE_FLUSH(hw);
2293 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2294 * @hw: pointer to hardware structure
2295 * @data: data byte to clock in
2297 * Clocks in one byte data via I2C data/clock
2299 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2304 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2307 for (i = 7; i >= 0; i--) {
2308 ixgbe_clock_in_i2c_bit(hw, &bit);
2312 return IXGBE_SUCCESS;
2316 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2317 * @hw: pointer to hardware structure
2318 * @data: data byte clocked out
2320 * Clocks out one byte data via I2C data/clock
2322 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2324 s32 status = IXGBE_SUCCESS;
2329 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2331 for (i = 7; i >= 0; i--) {
2332 bit = (data >> i) & 0x1;
2333 status = ixgbe_clock_out_i2c_bit(hw, bit);
2335 if (status != IXGBE_SUCCESS)
2339 /* Release SDA line (set high) */
2340 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2341 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2342 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2343 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2344 IXGBE_WRITE_FLUSH(hw);
2350 * ixgbe_get_i2c_ack - Polls for I2C ACK
2351 * @hw: pointer to hardware structure
2353 * Clocks in/out one bit via I2C data/clock
2355 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2357 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2358 s32 status = IXGBE_SUCCESS;
2360 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2364 DEBUGFUNC("ixgbe_get_i2c_ack");
2367 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2368 i2cctl |= data_oe_bit;
2369 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2370 IXGBE_WRITE_FLUSH(hw);
2372 ixgbe_raise_i2c_clk(hw, &i2cctl);
2374 /* Minimum high period of clock is 4us */
2375 usec_delay(IXGBE_I2C_T_HIGH);
2377 /* Poll for ACK. Note that ACK in I2C spec is
2378 * transition from 1 to 0 */
2379 for (i = 0; i < timeout; i++) {
2380 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2381 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2389 DEBUGOUT("I2C ack was not received.\n");
2390 status = IXGBE_ERR_I2C;
2393 ixgbe_lower_i2c_clk(hw, &i2cctl);
2395 /* Minimum low period of clock is 4.7 us */
2396 usec_delay(IXGBE_I2C_T_LOW);
2402 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2403 * @hw: pointer to hardware structure
2404 * @data: read data value
2406 * Clocks in one bit via I2C data/clock
2408 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2410 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2411 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2413 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2416 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2417 i2cctl |= data_oe_bit;
2418 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2419 IXGBE_WRITE_FLUSH(hw);
2421 ixgbe_raise_i2c_clk(hw, &i2cctl);
2423 /* Minimum high period of clock is 4us */
2424 usec_delay(IXGBE_I2C_T_HIGH);
2426 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2427 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2429 ixgbe_lower_i2c_clk(hw, &i2cctl);
2431 /* Minimum low period of clock is 4.7 us */
2432 usec_delay(IXGBE_I2C_T_LOW);
2434 return IXGBE_SUCCESS;
2438 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2439 * @hw: pointer to hardware structure
2440 * @data: data value to write
2442 * Clocks out one bit via I2C data/clock
2444 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2447 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2449 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2451 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2452 if (status == IXGBE_SUCCESS) {
2453 ixgbe_raise_i2c_clk(hw, &i2cctl);
2455 /* Minimum high period of clock is 4us */
2456 usec_delay(IXGBE_I2C_T_HIGH);
2458 ixgbe_lower_i2c_clk(hw, &i2cctl);
2460 /* Minimum low period of clock is 4.7 us.
2461 * This also takes care of the data hold time.
2463 usec_delay(IXGBE_I2C_T_LOW);
2465 status = IXGBE_ERR_I2C;
2466 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2467 "I2C data was not set to %X\n", data);
2474 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2475 * @hw: pointer to hardware structure
2476 * @i2cctl: Current value of I2CCTL register
2478 * Raises the I2C clock line '0'->'1'
2479 * Negates the I2C clock output enable on X550 hardware.
2481 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2483 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2485 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2488 DEBUGFUNC("ixgbe_raise_i2c_clk");
2491 *i2cctl |= clk_oe_bit;
2492 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2495 for (i = 0; i < timeout; i++) {
2496 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2498 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2499 IXGBE_WRITE_FLUSH(hw);
2500 /* SCL rise time (1000ns) */
2501 usec_delay(IXGBE_I2C_T_RISE);
2503 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2504 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2510 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2511 * @hw: pointer to hardware structure
2512 * @i2cctl: Current value of I2CCTL register
2514 * Lowers the I2C clock line '1'->'0'
2515 * Asserts the I2C clock output enable on X550 hardware.
2517 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2519 DEBUGFUNC("ixgbe_lower_i2c_clk");
2521 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2522 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2524 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2525 IXGBE_WRITE_FLUSH(hw);
2527 /* SCL fall time (300ns) */
2528 usec_delay(IXGBE_I2C_T_FALL);
2532 * ixgbe_set_i2c_data - Sets the I2C data bit
2533 * @hw: pointer to hardware structure
2534 * @i2cctl: Current value of I2CCTL register
2535 * @data: I2C data value (0 or 1) to set
2537 * Sets the I2C data bit
2538 * Asserts the I2C data output enable on X550 hardware.
2540 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2542 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2543 s32 status = IXGBE_SUCCESS;
2545 DEBUGFUNC("ixgbe_set_i2c_data");
2548 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2550 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2551 *i2cctl &= ~data_oe_bit;
2553 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2554 IXGBE_WRITE_FLUSH(hw);
2556 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2557 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2559 if (!data) /* Can't verify data in this case */
2560 return IXGBE_SUCCESS;
2562 *i2cctl |= data_oe_bit;
2563 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2564 IXGBE_WRITE_FLUSH(hw);
2567 /* Verify data was set correctly */
2568 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2569 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2570 status = IXGBE_ERR_I2C;
2571 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2572 "Error - I2C data was not set to %X.\n",
2580 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2581 * @hw: pointer to hardware structure
2582 * @i2cctl: Current value of I2CCTL register
2584 * Returns the I2C data bit value
2585 * Negates the I2C data output enable on X550 hardware.
2587 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2589 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2592 DEBUGFUNC("ixgbe_get_i2c_data");
2595 *i2cctl |= data_oe_bit;
2596 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2597 IXGBE_WRITE_FLUSH(hw);
2598 usec_delay(IXGBE_I2C_T_FALL);
2601 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2610 * ixgbe_i2c_bus_clear - Clears the I2C bus
2611 * @hw: pointer to hardware structure
2613 * Clears the I2C bus by sending nine clock pulses.
2614 * Used when data line is stuck low.
2616 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2621 DEBUGFUNC("ixgbe_i2c_bus_clear");
2623 ixgbe_i2c_start(hw);
2624 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2626 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2628 for (i = 0; i < 9; i++) {
2629 ixgbe_raise_i2c_clk(hw, &i2cctl);
2631 /* Min high period of clock is 4us */
2632 usec_delay(IXGBE_I2C_T_HIGH);
2634 ixgbe_lower_i2c_clk(hw, &i2cctl);
2636 /* Min low period of clock is 4.7us*/
2637 usec_delay(IXGBE_I2C_T_LOW);
2640 ixgbe_i2c_start(hw);
2642 /* Put the i2c bus back to default state */
2647 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2648 * @hw: pointer to hardware structure
2650 * Checks if the LASI temp alarm status was triggered due to overtemp
2652 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2654 s32 status = IXGBE_SUCCESS;
2657 DEBUGFUNC("ixgbe_tn_check_overtemp");
2659 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2662 /* Check that the LASI temp alarm status was triggered */
2663 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2664 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2666 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2669 status = IXGBE_ERR_OVERTEMP;
2670 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2676 * ixgbe_set_copper_phy_power - Control power for copper phy
2677 * @hw: pointer to hardware structure
2678 * @on: true for on, false for off
2680 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2685 if (!on && ixgbe_mng_present(hw))
2688 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2689 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2695 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2697 if (ixgbe_check_reset_blocked(hw))
2699 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2702 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2703 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,