drivers/net/ixgbe/base/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_api.h"
  35 #include "ixgbe_common.h"
  36 #include "ixgbe_phy.h"
  37
  38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
  39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  50                                           u8 *sff8472_data);
  51
  52 /**
  53  * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
  54  * @hw: pointer to the hardware structure
  55  * @byte: byte to send
  56  *
  57  * Returns an error code on error.
  58  */
  59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
  60 {
  61         s32 status;
  62
  63         status = ixgbe_clock_out_i2c_byte(hw, byte);
  64         if (status)
  65                 return status;
  66         return ixgbe_get_i2c_ack(hw);
  67 }
  68
  69 /**
  70  * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
  71  * @hw: pointer to the hardware structure
  72  * @byte: pointer to a u8 to receive the byte
  73  *
  74  * Returns an error code on error.
  75  */
  76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
  77 {
  78         s32 status;
  79
  80         status = ixgbe_clock_in_i2c_byte(hw, byte);
  81         if (status)
  82                 return status;
  83         /* ACK */
  84         return ixgbe_clock_out_i2c_bit(hw, false);
  85 }
  86
  87 /**
  88  * ixgbe_ones_comp_byte_add - Perform one's complement addition
  89  * @add1 - addend 1
  90  * @add2 - addend 2
  91  *
  92  * Returns one's complement 8-bit sum.
  93  */
  94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
  95 {
  96         u16 sum = add1 + add2;
  97
  98         sum = (sum & 0xFF) + (sum >> 8);
  99         return sum & 0xFF;
 100 }
 101
 102 /**
 103  * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
 104  * @hw: pointer to the hardware structure
 105  * @addr: I2C bus address to read from
 106  * @reg: I2C device register to read from
 107  * @val: pointer to location to receive read value
 108  * @lock: true if to take and release semaphore
 109  *
 110  * Returns an error code on error.
 111  */
 112 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 113                                         u16 *val, bool lock)
 114 {
 115         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 116         int max_retry = 3;
 117         int retry = 0;
 118         u8 csum_byte;
 119         u8 high_bits;
 120         u8 low_bits;
 121         u8 reg_high;
 122         u8 csum;
 123
 124         reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
 125         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 126         csum = ~csum;
 127         do {
 128                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 129                         return IXGBE_ERR_SWFW_SYNC;
 130                 ixgbe_i2c_start(hw);
 131                 /* Device Address and write indication */
 132                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 133                         goto fail;
 134                 /* Write bits 14:8 */
 135                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 136                         goto fail;
 137                 /* Write bits 7:0 */
 138                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 139                         goto fail;
 140                 /* Write csum */
 141                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 142                         goto fail;
 143                 /* Re-start condition */
 144                 ixgbe_i2c_start(hw);
 145                 /* Device Address and read indication */
 146                 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
 147                         goto fail;
 148                 /* Get upper bits */
 149                 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
 150                         goto fail;
 151                 /* Get low bits */
 152                 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
 153                         goto fail;
 154                 /* Get csum */
 155                 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
 156                         goto fail;
 157                 /* NACK */
 158                 if (ixgbe_clock_out_i2c_bit(hw, false))
 159                         goto fail;
 160                 ixgbe_i2c_stop(hw);
 161                 if (lock)
 162                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 163                 *val = (high_bits << 8) | low_bits;
 164                 return 0;
 165
 166 fail:
 167                 ixgbe_i2c_bus_clear(hw);
 168                 if (lock)
 169                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 170                 retry++;
 171                 if (retry < max_retry)
 172                         DEBUGOUT("I2C byte read combined error - Retrying.\n");
 173                 else
 174                         DEBUGOUT("I2C byte read combined error.\n");
 175         } while (retry < max_retry);
 176
 177         return IXGBE_ERR_I2C;
 178 }
 179
 180 /**
 181  * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
 182  * @hw: pointer to the hardware structure
 183  * @addr: I2C bus address to write to
 184  * @reg: I2C device register to write to
 185  * @val: value to write
 186  * @lock: true if to take and release semaphore
 187  *
 188  * Returns an error code on error.
 189  */
 190 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 191                                          u16 val, bool lock)
 192 {
 193         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 194         int max_retry = 1;
 195         int retry = 0;
 196         u8 reg_high;
 197         u8 csum;
 198
 199         reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
 200         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 201         csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
 202         csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
 203         csum = ~csum;
 204         do {
 205                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 206                         return IXGBE_ERR_SWFW_SYNC;
 207                 ixgbe_i2c_start(hw);
 208                 /* Device Address and write indication */
 209                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 210                         goto fail;
 211                 /* Write bits 14:8 */
 212                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 213                         goto fail;
 214                 /* Write bits 7:0 */
 215                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 216                         goto fail;
 217                 /* Write data 15:8 */
 218                 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
 219                         goto fail;
 220                 /* Write data 7:0 */
 221                 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
 222                         goto fail;
 223                 /* Write csum */
 224                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 225                         goto fail;
 226                 ixgbe_i2c_stop(hw);
 227                 if (lock)
 228                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 229                 return 0;
 230
 231 fail:
 232                 ixgbe_i2c_bus_clear(hw);
 233                 if (lock)
 234                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 235                 retry++;
 236                 if (retry < max_retry)
 237                         DEBUGOUT("I2C byte write combined error - Retrying.\n");
 238                 else
 239                         DEBUGOUT("I2C byte write combined error.\n");
 240         } while (retry < max_retry);
 241
 242         return IXGBE_ERR_I2C;
 243 }
 244
 245 /**
 246  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
 247  *  @hw: pointer to the hardware structure
 248  *
 249  *  Initialize the function pointers.
 250  **/
 251 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
 252 {
 253         struct ixgbe_phy_info *phy = &hw->phy;
 254
 255         DEBUGFUNC("ixgbe_init_phy_ops_generic");
 256
 257         /* PHY */
 258         phy->ops.identify = ixgbe_identify_phy_generic;
 259         phy->ops.reset = ixgbe_reset_phy_generic;
 260         phy->ops.read_reg = ixgbe_read_phy_reg_generic;
 261         phy->ops.write_reg = ixgbe_write_phy_reg_generic;
 262         phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
 263         phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
 264         phy->ops.setup_link = ixgbe_setup_phy_link_generic;
 265         phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
 266         phy->ops.check_link = NULL;
 267         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
 268         phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
 269         phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
 270         phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
 271         phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
 272         phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
 273         phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
 274         phy->ops.identify_sfp = ixgbe_identify_module_generic;
 275         phy->sfp_type = ixgbe_sfp_type_unknown;
 276         phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
 277         phy->ops.write_i2c_byte_unlocked =
 278                                 ixgbe_write_i2c_byte_generic_unlocked;
 279         phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
 280         return IXGBE_SUCCESS;
 281 }
 282
 283 /**
 284  * ixgbe_probe_phy - Probe a single address for a PHY
 285  * @hw: pointer to hardware structure
 286  * @phy_addr: PHY address to probe
 287  *
 288  * Returns true if PHY found
 289  */
 290 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
 291 {
 292         u16 ext_ability = 0;
 293
 294         if (!ixgbe_validate_phy_addr(hw, phy_addr))
 295                 return false;
 296
 297         if (ixgbe_get_phy_id(hw))
 298                 return false;
 299
 300         hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
 301
 302         if (hw->phy.type == ixgbe_phy_unknown) {
 303                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
 304                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
 305                 if (ext_ability &
 306                     (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 307                      IXGBE_MDIO_PHY_1000BASET_ABILITY))
 308                         hw->phy.type = ixgbe_phy_cu_unknown;
 309                 else
 310                         hw->phy.type = ixgbe_phy_generic;
 311         }
 312
 313         return true;
 314 }
 315
 316 /**
 317  *  ixgbe_identify_phy_generic - Get physical layer module
 318  *  @hw: pointer to hardware structure
 319  *
 320  *  Determines the physical layer module found on the current adapter.
 321  **/
 322 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 323 {
 324         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 325         u16 phy_addr;
 326
 327         DEBUGFUNC("ixgbe_identify_phy_generic");
 328
 329         if (!hw->phy.phy_semaphore_mask) {
 330                 if (hw->bus.lan_id)
 331                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 332                 else
 333                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 334         }
 335
 336         if (hw->phy.type != ixgbe_phy_unknown)
 337                 return IXGBE_SUCCESS;
 338
 339         if (hw->phy.nw_mng_if_sel) {
 340                 phy_addr = (hw->phy.nw_mng_if_sel &
 341                             IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
 342                            IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
 343                 if (ixgbe_probe_phy(hw, phy_addr))
 344                         return IXGBE_SUCCESS;
 345                 else
 346                         return IXGBE_ERR_PHY_ADDR_INVALID;
 347         }
 348
 349         for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 350                 if (ixgbe_probe_phy(hw, phy_addr)) {
 351                         status = IXGBE_SUCCESS;
 352                         break;
 353                 }
 354         }
 355
 356         /* Certain media types do not have a phy so an address will not
 357          * be found and the code will take this path.  Caller has to
 358          * decide if it is an error or not.
 359          */
 360         if (status != IXGBE_SUCCESS)
 361                 hw->phy.addr = 0;
 362
 363         return status;
 364 }
 365
 366 /**
 367  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 368  * @hw: pointer to the hardware structure
 369  *
 370  * This function checks the MMNGC.MNG_VETO bit to see if there are
 371  * any constraints on link from manageability.  For MAC's that don't
 372  * have this bit just return faluse since the link can not be blocked
 373  * via this method.
 374  **/
 375 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 376 {
 377         u32 mmngc;
 378
 379         DEBUGFUNC("ixgbe_check_reset_blocked");
 380
 381         /* If we don't have this bit, it can't be blocking */
 382         if (hw->mac.type == ixgbe_mac_82598EB)
 383                 return false;
 384
 385         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 386         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 387                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 388                               "MNG_VETO bit detected.\n");
 389                 return true;
 390         }
 391
 392         return false;
 393 }
 394
 395 /**
 396  *  ixgbe_validate_phy_addr - Determines phy address is valid
 397  *  @hw: pointer to hardware structure
 398  *
 399  **/
 400 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 401 {
 402         u16 phy_id = 0;
 403         bool valid = false;
 404
 405         DEBUGFUNC("ixgbe_validate_phy_addr");
 406
 407         hw->phy.addr = phy_addr;
 408         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 409                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 410
 411         if (phy_id != 0xFFFF && phy_id != 0x0)
 412                 valid = true;
 413
 414         return valid;
 415 }
 416
 417 /**
 418  *  ixgbe_get_phy_id - Get the phy type
 419  *  @hw: pointer to hardware structure
 420  *
 421  **/
 422 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 423 {
 424         u32 status;
 425         u16 phy_id_high = 0;
 426         u16 phy_id_low = 0;
 427
 428         DEBUGFUNC("ixgbe_get_phy_id");
 429
 430         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 431                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 432                                       &phy_id_high);
 433
 434         if (status == IXGBE_SUCCESS) {
 435                 hw->phy.id = (u32)(phy_id_high << 16);
 436                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 437                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 438                                               &phy_id_low);
 439                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 440                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 441         }
 442         return status;
 443 }
 444
 445 /**
 446  *  ixgbe_get_phy_type_from_id - Get the phy type
 447  *  @phy_id: PHY ID information
 448  *
 449  **/
 450 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 451 {
 452         enum ixgbe_phy_type phy_type;
 453
 454         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 455
 456         switch (phy_id) {
 457         case TN1010_PHY_ID:
 458                 phy_type = ixgbe_phy_tn;
 459                 break;
 460         case X550_PHY_ID2:
 461         case X550_PHY_ID3:
 462         case X540_PHY_ID:
 463                 phy_type = ixgbe_phy_aq;
 464                 break;
 465         case QT2022_PHY_ID:
 466                 phy_type = ixgbe_phy_qt;
 467                 break;
 468         case ATH_PHY_ID:
 469                 phy_type = ixgbe_phy_nl;
 470                 break;
 471         case X557_PHY_ID:
 472         case X557_PHY_ID2:
 473                 phy_type = ixgbe_phy_x550em_ext_t;
 474                 break;
 475         default:
 476                 phy_type = ixgbe_phy_unknown;
 477                 break;
 478         }
 479         return phy_type;
 480 }
 481
 482 /**
 483  *  ixgbe_reset_phy_generic - Performs a PHY reset
 484  *  @hw: pointer to hardware structure
 485  **/
 486 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 487 {
 488         u32 i;
 489         u16 ctrl = 0;
 490         s32 status = IXGBE_SUCCESS;
 491
 492         DEBUGFUNC("ixgbe_reset_phy_generic");
 493
 494         if (hw->phy.type == ixgbe_phy_unknown)
 495                 status = ixgbe_identify_phy_generic(hw);
 496
 497         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 498                 goto out;
 499
 500         /* Don't reset PHY if it's shut down due to overtemp. */
 501         if (!hw->phy.reset_if_overtemp &&
 502             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 503                 goto out;
 504
 505         /* Blocked by MNG FW so bail */
 506         if (ixgbe_check_reset_blocked(hw))
 507                 goto out;
 508
 509         /*
 510          * Perform soft PHY reset to the PHY_XS.
 511          * This will cause a soft reset to the PHY
 512          */
 513         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 514                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 515                               IXGBE_MDIO_PHY_XS_RESET);
 516
 517         /*
 518          * Poll for reset bit to self-clear indicating reset is complete.
 519          * Some PHYs could take up to 3 seconds to complete and need about
 520          * 1.7 usec delay after the reset is complete.
 521          */
 522         for (i = 0; i < 30; i++) {
 523                 msec_delay(100);
 524                 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
 525                         status = hw->phy.ops.read_reg(hw,
 526                                                   IXGBE_MDIO_TX_VENDOR_ALARMS_3,
 527                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 528                                                   &ctrl);
 529                         if (status != IXGBE_SUCCESS)
 530                                 return status;
 531
 532                         if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
 533                                 usec_delay(2);
 534                                 break;
 535                         }
 536                 } else {
 537                         status = hw->phy.ops.read_reg(hw,
 538                                                      IXGBE_MDIO_PHY_XS_CONTROL,
 539                                                      IXGBE_MDIO_PHY_XS_DEV_TYPE,
 540                                                      &ctrl);
 541                         if (status != IXGBE_SUCCESS)
 542                                 return status;
 543
 544                         if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 545                                 usec_delay(2);
 546                                 break;
 547                         }
 548                 }
 549         }
 550
 551         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 552                 status = IXGBE_ERR_RESET_FAILED;
 553                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 554                              "PHY reset polling failed to complete.\n");
 555         }
 556
 557 out:
 558         return status;
 559 }
 560
 561 /**
 562  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 563  *  the SWFW lock
 564  *  @hw: pointer to hardware structure
 565  *  @reg_addr: 32 bit address of PHY register to read
 566  *  @phy_data: Pointer to read data from PHY register
 567  **/
 568 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 569                        u16 *phy_data)
 570 {
 571         u32 i, data, command;
 572
 573         /* Setup and write the address cycle command */
 574         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 575                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 576                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 577                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 578
 579         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 580
 581         /*
 582          * Check every 10 usec to see if the address cycle completed.
 583          * The MDI Command bit will clear when the operation is
 584          * complete
 585          */
 586         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 587                 usec_delay(10);
 588
 589                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 590                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 591                                 break;
 592         }
 593
 594
 595         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 596                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 597                 return IXGBE_ERR_PHY;
 598         }
 599
 600         /*
 601          * Address cycle complete, setup and write the read
 602          * command
 603          */
 604         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 605                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 606                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 607                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 608
 609         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 610
 611         /*
 612          * Check every 10 usec to see if the address cycle
 613          * completed. The MDI Command bit will clear when the
 614          * operation is complete
 615          */
 616         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 617                 usec_delay(10);
 618
 619                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 620                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 621                         break;
 622         }
 623
 624         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 625                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 626                 return IXGBE_ERR_PHY;
 627         }
 628
 629         /*
 630          * Read operation is complete.  Get the data
 631          * from MSRWD
 632          */
 633         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 634         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 635         *phy_data = (u16)(data);
 636
 637         return IXGBE_SUCCESS;
 638 }
 639
 640 /**
 641  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 642  *  using the SWFW lock - this function is needed in most cases
 643  *  @hw: pointer to hardware structure
 644  *  @reg_addr: 32 bit address of PHY register to read
 645  *  @phy_data: Pointer to read data from PHY register
 646  **/
 647 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 648                                u32 device_type, u16 *phy_data)
 649 {
 650         s32 status;
 651         u32 gssr = hw->phy.phy_semaphore_mask;
 652
 653         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 654
 655         if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
 656                 return IXGBE_ERR_SWFW_SYNC;
 657
 658         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
 659
 660         hw->mac.ops.release_swfw_sync(hw, gssr);
 661
 662         return status;
 663 }
 664
 665 /**
 666  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 667  *  without SWFW lock
 668  *  @hw: pointer to hardware structure
 669  *  @reg_addr: 32 bit PHY register to write
 670  *  @device_type: 5 bit device type
 671  *  @phy_data: Data to write to the PHY register
 672  **/
 673 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 674                                 u32 device_type, u16 phy_data)
 675 {
 676         u32 i, command;
 677
 678         /* Put the data in the MDI single read and write data register*/
 679         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 680
 681         /* Setup and write the address cycle command */
 682         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 683                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 684                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 685                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 686
 687         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 688
 689         /*
 690          * Check every 10 usec to see if the address cycle completed.
 691          * The MDI Command bit will clear when the operation is
 692          * complete
 693          */
 694         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 695                 usec_delay(10);
 696
 697                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 698                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 699                         break;
 700         }
 701
 702         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 703                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 704                 return IXGBE_ERR_PHY;
 705         }
 706
 707         /*
 708          * Address cycle complete, setup and write the write
 709          * command
 710          */
 711         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 712                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 713                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 714                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 715
 716         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 717
 718         /*
 719          * Check every 10 usec to see if the address cycle
 720          * completed. The MDI Command bit will clear when the
 721          * operation is complete
 722          */
 723         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 724                 usec_delay(10);
 725
 726                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 727                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 728                         break;
 729         }
 730
 731         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 732                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 733                 return IXGBE_ERR_PHY;
 734         }
 735
 736         return IXGBE_SUCCESS;
 737 }
 738
 739 /**
 740  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 741  *  using SWFW lock- this function is needed in most cases
 742  *  @hw: pointer to hardware structure
 743  *  @reg_addr: 32 bit PHY register to write
 744  *  @device_type: 5 bit device type
 745  *  @phy_data: Data to write to the PHY register
 746  **/
 747 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 748                                 u32 device_type, u16 phy_data)
 749 {
 750         s32 status;
 751         u32 gssr = hw->phy.phy_semaphore_mask;
 752
 753         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 754
 755         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 756                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
 757                                                  phy_data);
 758                 hw->mac.ops.release_swfw_sync(hw, gssr);
 759         } else {
 760                 status = IXGBE_ERR_SWFW_SYNC;
 761         }
 762
 763         return status;
 764 }
 765
 766 /**
 767  *  ixgbe_setup_phy_link_generic - Set and restart auto-neg
 768  *  @hw: pointer to hardware structure
 769  *
 770  *  Restart auto-negotiation and PHY and waits for completion.
 771  **/
 772 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 773 {
 774         s32 status = IXGBE_SUCCESS;
 775         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 776         bool autoneg = false;
 777         ixgbe_link_speed speed;
 778
 779         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 780
 781         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 782
 783         /* Set or unset auto-negotiation 10G advertisement */
 784         hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 785                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 786                              &autoneg_reg);
 787
 788         autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 789         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
 790             (speed & IXGBE_LINK_SPEED_10GB_FULL))
 791                 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 792
 793         hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 794                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 795                               autoneg_reg);
 796
 797         hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 798                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 799                              &autoneg_reg);
 800
 801         if (hw->mac.type == ixgbe_mac_X550) {
 802                 /* Set or unset auto-negotiation 5G advertisement */
 803                 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
 804                 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
 805                     (speed & IXGBE_LINK_SPEED_5GB_FULL))
 806                         autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
 807
 808                 /* Set or unset auto-negotiation 2.5G advertisement */
 809                 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
 810                 if ((hw->phy.autoneg_advertised &
 811                      IXGBE_LINK_SPEED_2_5GB_FULL) &&
 812                     (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
 813                         autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
 814         }
 815
 816         /* Set or unset auto-negotiation 1G advertisement */
 817         autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 818         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
 819             (speed & IXGBE_LINK_SPEED_1GB_FULL))
 820                 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 821
 822         hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 823                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 824                               autoneg_reg);
 825
 826         /* Set or unset auto-negotiation 100M advertisement */
 827         hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 828                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 829                              &autoneg_reg);
 830
 831         autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 832                          IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 833         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
 834             (speed & IXGBE_LINK_SPEED_100_FULL))
 835                 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 836
 837         hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 838                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 839                               autoneg_reg);
 840
 841         /* Blocked by MNG FW so don't reset PHY */
 842         if (ixgbe_check_reset_blocked(hw))
 843                 return status;
 844
 845         /* Restart PHY auto-negotiation. */
 846         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 847                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 848
 849         autoneg_reg |= IXGBE_MII_RESTART;
 850
 851         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 852                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 853
 854         return status;
 855 }
 856
 857 /**
 858  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 859  *  @hw: pointer to hardware structure
 860  *  @speed: new link speed
 861  **/
 862 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 863                                        ixgbe_link_speed speed,
 864                                        bool autoneg_wait_to_complete)
 865 {
 866         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 867
 868         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 869
 870         /*
 871          * Clear autoneg_advertised and set new values based on input link
 872          * speed.
 873          */
 874         hw->phy.autoneg_advertised = 0;
 875
 876         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 877                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 878
 879         if (speed & IXGBE_LINK_SPEED_5GB_FULL)
 880                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
 881
 882         if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
 883                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
 884
 885         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 886                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 887
 888         if (speed & IXGBE_LINK_SPEED_100_FULL)
 889                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 890
 891         if (speed & IXGBE_LINK_SPEED_10_FULL)
 892                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
 893
 894         /* Setup link based on the new speed settings */
 895         ixgbe_setup_phy_link(hw);
 896
 897         return IXGBE_SUCCESS;
 898 }
 899
 900 /**
 901  * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
 902  * @hw: pointer to hardware structure
 903  *
 904  * Determines the supported link capabilities by reading the PHY auto
 905  * negotiation register.
 906  **/
 907 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
 908 {
 909         s32 status;
 910         u16 speed_ability;
 911
 912         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 913                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 914                                       &speed_ability);
 915         if (status)
 916                 return status;
 917
 918         if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 919                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
 920         if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 921                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
 922         if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 923                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
 924
 925         switch (hw->mac.type) {
 926         case ixgbe_mac_X550:
 927                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
 928                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
 929                 break;
 930         case ixgbe_mac_X550EM_x:
 931         case ixgbe_mac_X550EM_a:
 932                 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
 933                 break;
 934         default:
 935                 break;
 936         }
 937
 938         return status;
 939 }
 940
 941 /**
 942  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 943  *  @hw: pointer to hardware structure
 944  *  @speed: pointer to link speed
 945  *  @autoneg: boolean auto-negotiation value
 946  **/
 947 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 948                                                ixgbe_link_speed *speed,
 949                                                bool *autoneg)
 950 {
 951         s32 status = IXGBE_SUCCESS;
 952
 953         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 954
 955         *autoneg = true;
 956         if (!hw->phy.speeds_supported)
 957                 status = ixgbe_get_copper_speeds_supported(hw);
 958
 959         *speed = hw->phy.speeds_supported;
 960         return status;
 961 }
 962
 963 /**
 964  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 965  *  @hw: pointer to hardware structure
 966  *
 967  *  Reads the VS1 register to determine if link is up and the current speed for
 968  *  the PHY.
 969  **/
 970 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 971                              bool *link_up)
 972 {
 973         s32 status = IXGBE_SUCCESS;
 974         u32 time_out;
 975         u32 max_time_out = 10;
 976         u16 phy_link = 0;
 977         u16 phy_speed = 0;
 978         u16 phy_data = 0;
 979
 980         DEBUGFUNC("ixgbe_check_phy_link_tnx");
 981
 982         /* Initialize speed and link to default case */
 983         *link_up = false;
 984         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 985
 986         /*
 987          * Check current speed and link status of the PHY register.
 988          * This is a vendor specific register and may have to
 989          * be changed for other copper PHYs.
 990          */
 991         for (time_out = 0; time_out < max_time_out; time_out++) {
 992                 usec_delay(10);
 993                 status = hw->phy.ops.read_reg(hw,
 994                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
 995                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 996                                         &phy_data);
 997                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 998                 phy_speed = phy_data &
 999                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1000                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1001                         *link_up = true;
1002                         if (phy_speed ==
1003                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1004                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1005                         break;
1006                 }
1007         }
1008
1009         return status;
1010 }
1011
1012 /**
1013  *      ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1014  *      @hw: pointer to hardware structure
1015  *
1016  *      Restart auto-negotiation and PHY and waits for completion.
1017  **/
1018 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1019 {
1020         s32 status = IXGBE_SUCCESS;
1021         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1022         bool autoneg = false;
1023         ixgbe_link_speed speed;
1024
1025         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1026
1027         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1028
1029         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1030                 /* Set or unset auto-negotiation 10G advertisement */
1031                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1032                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1033                                      &autoneg_reg);
1034
1035                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1036                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1037                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1038
1039                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1040                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1041                                       autoneg_reg);
1042         }
1043
1044         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1045                 /* Set or unset auto-negotiation 1G advertisement */
1046                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1047                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1048                                      &autoneg_reg);
1049
1050                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1051                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1052                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1053
1054                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1055                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1056                                       autoneg_reg);
1057         }
1058
1059         if (speed & IXGBE_LINK_SPEED_100_FULL) {
1060                 /* Set or unset auto-negotiation 100M advertisement */
1061                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1062                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1063                                      &autoneg_reg);
1064
1065                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1066                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1067                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1068
1069                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1070                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1071                                       autoneg_reg);
1072         }
1073
1074         /* Blocked by MNG FW so don't reset PHY */
1075         if (ixgbe_check_reset_blocked(hw))
1076                 return status;
1077
1078         /* Restart PHY auto-negotiation. */
1079         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1080                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1081
1082         autoneg_reg |= IXGBE_MII_RESTART;
1083
1084         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1085                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1086
1087         return status;
1088 }
1089
1090 /**
1091  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1092  *  @hw: pointer to hardware structure
1093  *  @firmware_version: pointer to the PHY Firmware Version
1094  **/
1095 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1096                                        u16 *firmware_version)
1097 {
1098         s32 status;
1099
1100         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1101
1102         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1103                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1104                                       firmware_version);
1105
1106         return status;
1107 }
1108
1109 /**
1110  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1111  *  @hw: pointer to hardware structure
1112  *  @firmware_version: pointer to the PHY Firmware Version
1113  **/
1114 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1115                                            u16 *firmware_version)
1116 {
1117         s32 status;
1118
1119         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1120
1121         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1122                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1123                                       firmware_version);
1124
1125         return status;
1126 }
1127
1128 /**
1129  *  ixgbe_reset_phy_nl - Performs a PHY reset
1130  *  @hw: pointer to hardware structure
1131  **/
1132 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1133 {
1134         u16 phy_offset, control, eword, edata, block_crc;
1135         bool end_data = false;
1136         u16 list_offset, data_offset;
1137         u16 phy_data = 0;
1138         s32 ret_val = IXGBE_SUCCESS;
1139         u32 i;
1140
1141         DEBUGFUNC("ixgbe_reset_phy_nl");
1142
1143         /* Blocked by MNG FW so bail */
1144         if (ixgbe_check_reset_blocked(hw))
1145                 goto out;
1146
1147         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1148                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1149
1150         /* reset the PHY and poll for completion */
1151         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1152                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
1153                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1154
1155         for (i = 0; i < 100; i++) {
1156                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1157                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1158                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1159                         break;
1160                 msec_delay(10);
1161         }
1162
1163         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1164                 DEBUGOUT("PHY reset did not complete.\n");
1165                 ret_val = IXGBE_ERR_PHY;
1166                 goto out;
1167         }
1168
1169         /* Get init offsets */
1170         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1171                                                       &data_offset);
1172         if (ret_val != IXGBE_SUCCESS)
1173                 goto out;
1174
1175         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1176         data_offset++;
1177         while (!end_data) {
1178                 /*
1179                  * Read control word from PHY init contents offset
1180                  */
1181                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1182                 if (ret_val)
1183                         goto err_eeprom;
1184                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1185                            IXGBE_CONTROL_SHIFT_NL;
1186                 edata = eword & IXGBE_DATA_MASK_NL;
1187                 switch (control) {
1188                 case IXGBE_DELAY_NL:
1189                         data_offset++;
1190                         DEBUGOUT1("DELAY: %d MS\n", edata);
1191                         msec_delay(edata);
1192                         break;
1193                 case IXGBE_DATA_NL:
1194                         DEBUGOUT("DATA:\n");
1195                         data_offset++;
1196                         ret_val = hw->eeprom.ops.read(hw, data_offset,
1197                                                       &phy_offset);
1198                         if (ret_val)
1199                                 goto err_eeprom;
1200                         data_offset++;
1201                         for (i = 0; i < edata; i++) {
1202                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
1203                                                               &eword);
1204                                 if (ret_val)
1205                                         goto err_eeprom;
1206                                 hw->phy.ops.write_reg(hw, phy_offset,
1207                                                       IXGBE_TWINAX_DEV, eword);
1208                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1209                                           phy_offset);
1210                                 data_offset++;
1211                                 phy_offset++;
1212                         }
1213                         break;
1214                 case IXGBE_CONTROL_NL:
1215                         data_offset++;
1216                         DEBUGOUT("CONTROL:\n");
1217                         if (edata == IXGBE_CONTROL_EOL_NL) {
1218                                 DEBUGOUT("EOL\n");
1219                                 end_data = true;
1220                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
1221                                 DEBUGOUT("SOL\n");
1222                         } else {
1223                                 DEBUGOUT("Bad control value\n");
1224                                 ret_val = IXGBE_ERR_PHY;
1225                                 goto out;
1226                         }
1227                         break;
1228                 default:
1229                         DEBUGOUT("Bad control type\n");
1230                         ret_val = IXGBE_ERR_PHY;
1231                         goto out;
1232                 }
1233         }
1234
1235 out:
1236         return ret_val;
1237
1238 err_eeprom:
1239         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1240                       "eeprom read at offset %d failed", data_offset);
1241         return IXGBE_ERR_PHY;
1242 }
1243
1244 /**
1245  *  ixgbe_identify_module_generic - Identifies module type
1246  *  @hw: pointer to hardware structure
1247  *
1248  *  Determines HW type and calls appropriate function.
1249  **/
1250 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1251 {
1252         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1253
1254         DEBUGFUNC("ixgbe_identify_module_generic");
1255
1256         switch (hw->mac.ops.get_media_type(hw)) {
1257         case ixgbe_media_type_fiber:
1258                 status = ixgbe_identify_sfp_module_generic(hw);
1259                 break;
1260
1261         case ixgbe_media_type_fiber_qsfp:
1262                 status = ixgbe_identify_qsfp_module_generic(hw);
1263                 break;
1264
1265         default:
1266                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1267                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1268                 break;
1269         }
1270
1271         return status;
1272 }
1273
1274 /**
1275  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1276  *  @hw: pointer to hardware structure
1277  *
1278  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1279  **/
1280 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1281 {
1282         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1283         u32 vendor_oui = 0;
1284         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1285         u8 identifier = 0;
1286         u8 comp_codes_1g = 0;
1287         u8 comp_codes_10g = 0;
1288         u8 oui_bytes[3] = {0, 0, 0};
1289         u8 cable_tech = 0;
1290         u8 cable_spec = 0;
1291         u16 enforce_sfp = 0;
1292
1293         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1294
1295         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1296                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1297                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1298                 goto out;
1299         }
1300
1301         /* LAN ID is needed for I2C access */
1302         hw->mac.ops.set_lan_id(hw);
1303
1304         status = hw->phy.ops.read_i2c_eeprom(hw,
1305                                              IXGBE_SFF_IDENTIFIER,
1306                                              &identifier);
1307
1308         if (status != IXGBE_SUCCESS)
1309                 goto err_read_i2c_eeprom;
1310
1311         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1312                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1313                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1314         } else {
1315                 status = hw->phy.ops.read_i2c_eeprom(hw,
1316                                                      IXGBE_SFF_1GBE_COMP_CODES,
1317                                                      &comp_codes_1g);
1318
1319                 if (status != IXGBE_SUCCESS)
1320                         goto err_read_i2c_eeprom;
1321
1322                 status = hw->phy.ops.read_i2c_eeprom(hw,
1323                                                      IXGBE_SFF_10GBE_COMP_CODES,
1324                                                      &comp_codes_10g);
1325
1326                 if (status != IXGBE_SUCCESS)
1327                         goto err_read_i2c_eeprom;
1328                 status = hw->phy.ops.read_i2c_eeprom(hw,
1329                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1330                                                      &cable_tech);
1331
1332                 if (status != IXGBE_SUCCESS)
1333                         goto err_read_i2c_eeprom;
1334
1335                  /* ID Module
1336                   * =========
1337                   * 0   SFP_DA_CU
1338                   * 1   SFP_SR
1339                   * 2   SFP_LR
1340                   * 3   SFP_DA_CORE0 - 82599-specific
1341                   * 4   SFP_DA_CORE1 - 82599-specific
1342                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1343                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1344                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1345                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1346                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1347                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1348                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1349                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1350                   */
1351                 if (hw->mac.type == ixgbe_mac_82598EB) {
1352                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1353                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1354                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1355                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1356                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1357                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1358                         else
1359                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1360                 } else {
1361                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1362                                 if (hw->bus.lan_id == 0)
1363                                         hw->phy.sfp_type =
1364                                                      ixgbe_sfp_type_da_cu_core0;
1365                                 else
1366                                         hw->phy.sfp_type =
1367                                                      ixgbe_sfp_type_da_cu_core1;
1368                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1369                                 hw->phy.ops.read_i2c_eeprom(
1370                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1371                                                 &cable_spec);
1372                                 if (cable_spec &
1373                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1374                                         if (hw->bus.lan_id == 0)
1375                                                 hw->phy.sfp_type =
1376                                                 ixgbe_sfp_type_da_act_lmt_core0;
1377                                         else
1378                                                 hw->phy.sfp_type =
1379                                                 ixgbe_sfp_type_da_act_lmt_core1;
1380                                 } else {
1381                                         hw->phy.sfp_type =
1382                                                         ixgbe_sfp_type_unknown;
1383                                 }
1384                         } else if (comp_codes_10g &
1385                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1386                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1387                                 if (hw->bus.lan_id == 0)
1388                                         hw->phy.sfp_type =
1389                                                       ixgbe_sfp_type_srlr_core0;
1390                                 else
1391                                         hw->phy.sfp_type =
1392                                                       ixgbe_sfp_type_srlr_core1;
1393                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1394                                 if (hw->bus.lan_id == 0)
1395                                         hw->phy.sfp_type =
1396                                                 ixgbe_sfp_type_1g_cu_core0;
1397                                 else
1398                                         hw->phy.sfp_type =
1399                                                 ixgbe_sfp_type_1g_cu_core1;
1400                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1401                                 if (hw->bus.lan_id == 0)
1402                                         hw->phy.sfp_type =
1403                                                 ixgbe_sfp_type_1g_sx_core0;
1404                                 else
1405                                         hw->phy.sfp_type =
1406                                                 ixgbe_sfp_type_1g_sx_core1;
1407                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1408                                 if (hw->bus.lan_id == 0)
1409                                         hw->phy.sfp_type =
1410                                                 ixgbe_sfp_type_1g_lx_core0;
1411                                 else
1412                                         hw->phy.sfp_type =
1413                                                 ixgbe_sfp_type_1g_lx_core1;
1414                         } else {
1415                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1416                         }
1417                 }
1418
1419                 if (hw->phy.sfp_type != stored_sfp_type)
1420                         hw->phy.sfp_setup_needed = true;
1421
1422                 /* Determine if the SFP+ PHY is dual speed or not. */
1423                 hw->phy.multispeed_fiber = false;
1424                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1425                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1426                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1427                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1428                         hw->phy.multispeed_fiber = true;
1429
1430                 /* Determine PHY vendor */
1431                 if (hw->phy.type != ixgbe_phy_nl) {
1432                         hw->phy.id = identifier;
1433                         status = hw->phy.ops.read_i2c_eeprom(hw,
1434                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1435                                                     &oui_bytes[0]);
1436
1437                         if (status != IXGBE_SUCCESS)
1438                                 goto err_read_i2c_eeprom;
1439
1440                         status = hw->phy.ops.read_i2c_eeprom(hw,
1441                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1442                                                     &oui_bytes[1]);
1443
1444                         if (status != IXGBE_SUCCESS)
1445                                 goto err_read_i2c_eeprom;
1446
1447                         status = hw->phy.ops.read_i2c_eeprom(hw,
1448                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1449                                                     &oui_bytes[2]);
1450
1451                         if (status != IXGBE_SUCCESS)
1452                                 goto err_read_i2c_eeprom;
1453
1454                         vendor_oui =
1455                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1456                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1457                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1458
1459                         switch (vendor_oui) {
1460                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1461                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1462                                         hw->phy.type =
1463                                                     ixgbe_phy_sfp_passive_tyco;
1464                                 break;
1465                         case IXGBE_SFF_VENDOR_OUI_FTL:
1466                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1467                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1468                                 else
1469                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1470                                 break;
1471                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1472                                 hw->phy.type = ixgbe_phy_sfp_avago;
1473                                 break;
1474                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1475                                 hw->phy.type = ixgbe_phy_sfp_intel;
1476                                 break;
1477                         default:
1478                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1479                                         hw->phy.type =
1480                                                  ixgbe_phy_sfp_passive_unknown;
1481                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1482                                         hw->phy.type =
1483                                                 ixgbe_phy_sfp_active_unknown;
1484                                 else
1485                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1486                                 break;
1487                         }
1488                 }
1489
1490                 /* Allow any DA cable vendor */
1491                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1492                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1493                         status = IXGBE_SUCCESS;
1494                         goto out;
1495                 }
1496
1497                 /* Verify supported 1G SFP modules */
1498                 if (comp_codes_10g == 0 &&
1499                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1500                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1501                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1502                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1503                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1504                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1505                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1506                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1507                         goto out;
1508                 }
1509
1510                 /* Anything else 82598-based is supported */
1511                 if (hw->mac.type == ixgbe_mac_82598EB) {
1512                         status = IXGBE_SUCCESS;
1513                         goto out;
1514                 }
1515
1516                 ixgbe_get_device_caps(hw, &enforce_sfp);
1517                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1518                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1519                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1520                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1521                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1522                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1523                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1524                         /* Make sure we're a supported PHY type */
1525                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1526                                 status = IXGBE_SUCCESS;
1527                         } else {
1528                                 if (hw->allow_unsupported_sfp == true) {
1529                                         EWARN(hw, "WARNING: Intel (R) Network "
1530                                               "Connections are quality tested "
1531                                               "using Intel (R) Ethernet Optics."
1532                                               " Using untested modules is not "
1533                                               "supported and may cause unstable"
1534                                               " operation or damage to the "
1535                                               "module or the adapter. Intel "
1536                                               "Corporation is not responsible "
1537                                               "for any harm caused by using "
1538                                               "untested modules.\n", status);
1539                                         status = IXGBE_SUCCESS;
1540                                 } else {
1541                                         DEBUGOUT("SFP+ module not supported\n");
1542                                         hw->phy.type =
1543                                                 ixgbe_phy_sfp_unsupported;
1544                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1545                                 }
1546                         }
1547                 } else {
1548                         status = IXGBE_SUCCESS;
1549                 }
1550         }
1551
1552 out:
1553         return status;
1554
1555 err_read_i2c_eeprom:
1556         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1557         if (hw->phy.type != ixgbe_phy_nl) {
1558                 hw->phy.id = 0;
1559                 hw->phy.type = ixgbe_phy_unknown;
1560         }
1561         return IXGBE_ERR_SFP_NOT_PRESENT;
1562 }
1563
1564 /**
1565  *  ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1566  *  @hw: pointer to hardware structure
1567  *
1568  *  Determines physical layer capabilities of the current SFP.
1569  */
1570 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1571 {
1572         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1573         u8 comp_codes_10g = 0;
1574         u8 comp_codes_1g = 0;
1575
1576         DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1577
1578         hw->phy.ops.identify_sfp(hw);
1579         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1580                 return physical_layer;
1581
1582         switch (hw->phy.type) {
1583         case ixgbe_phy_sfp_passive_tyco:
1584         case ixgbe_phy_sfp_passive_unknown:
1585         case ixgbe_phy_qsfp_passive_unknown:
1586                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1587                 break;
1588         case ixgbe_phy_sfp_ftl_active:
1589         case ixgbe_phy_sfp_active_unknown:
1590         case ixgbe_phy_qsfp_active_unknown:
1591                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1592                 break;
1593         case ixgbe_phy_sfp_avago:
1594         case ixgbe_phy_sfp_ftl:
1595         case ixgbe_phy_sfp_intel:
1596         case ixgbe_phy_sfp_unknown:
1597                 hw->phy.ops.read_i2c_eeprom(hw,
1598                       IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1599                 hw->phy.ops.read_i2c_eeprom(hw,
1600                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1601                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1602                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1603                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1604                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1605                 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1606                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1607                 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1608                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1609                 break;
1610         case ixgbe_phy_qsfp_intel:
1611         case ixgbe_phy_qsfp_unknown:
1612                 hw->phy.ops.read_i2c_eeprom(hw,
1613                       IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1614                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1615                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1616                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1617                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1618                 break;
1619         default:
1620                 break;
1621         }
1622
1623         return physical_layer;
1624 }
1625
1626 /**
1627  *  ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1628  *  @hw: pointer to hardware structure
1629  *
1630  *  Searches for and identifies the QSFP module and assigns appropriate PHY type
1631  **/
1632 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1633 {
1634         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1635         u32 vendor_oui = 0;
1636         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1637         u8 identifier = 0;
1638         u8 comp_codes_1g = 0;
1639         u8 comp_codes_10g = 0;
1640         u8 oui_bytes[3] = {0, 0, 0};
1641         u16 enforce_sfp = 0;
1642         u8 connector = 0;
1643         u8 cable_length = 0;
1644         u8 device_tech = 0;
1645         bool active_cable = false;
1646
1647         DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1648
1649         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1650                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1651                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1652                 goto out;
1653         }
1654
1655         /* LAN ID is needed for I2C access */
1656         hw->mac.ops.set_lan_id(hw);
1657
1658         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1659                                              &identifier);
1660
1661         if (status != IXGBE_SUCCESS)
1662                 goto err_read_i2c_eeprom;
1663
1664         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1665                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1666                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1667                 goto out;
1668         }
1669
1670         hw->phy.id = identifier;
1671
1672         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1673                                              &comp_codes_10g);
1674
1675         if (status != IXGBE_SUCCESS)
1676                 goto err_read_i2c_eeprom;
1677
1678         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1679                                              &comp_codes_1g);
1680
1681         if (status != IXGBE_SUCCESS)
1682                 goto err_read_i2c_eeprom;
1683
1684         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1685                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1686                 if (hw->bus.lan_id == 0)
1687                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1688                 else
1689                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1690         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1691                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1692                 if (hw->bus.lan_id == 0)
1693                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1694                 else
1695                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1696         } else {
1697                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1698                         active_cable = true;
1699
1700                 if (!active_cable) {
1701                         /* check for active DA cables that pre-date
1702                          * SFF-8436 v3.6 */
1703                         hw->phy.ops.read_i2c_eeprom(hw,
1704                                         IXGBE_SFF_QSFP_CONNECTOR,
1705                                         &connector);
1706
1707                         hw->phy.ops.read_i2c_eeprom(hw,
1708                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1709                                         &cable_length);
1710
1711                         hw->phy.ops.read_i2c_eeprom(hw,
1712                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1713                                         &device_tech);
1714
1715                         if ((connector ==
1716                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1717                             (cable_length > 0) &&
1718                             ((device_tech >> 4) ==
1719                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1720                                 active_cable = true;
1721                 }
1722
1723                 if (active_cable) {
1724                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1725                         if (hw->bus.lan_id == 0)
1726                                 hw->phy.sfp_type =
1727                                                 ixgbe_sfp_type_da_act_lmt_core0;
1728                         else
1729                                 hw->phy.sfp_type =
1730                                                 ixgbe_sfp_type_da_act_lmt_core1;
1731                 } else {
1732                         /* unsupported module type */
1733                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1734                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1735                         goto out;
1736                 }
1737         }
1738
1739         if (hw->phy.sfp_type != stored_sfp_type)
1740                 hw->phy.sfp_setup_needed = true;
1741
1742         /* Determine if the QSFP+ PHY is dual speed or not. */
1743         hw->phy.multispeed_fiber = false;
1744         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1745            (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1746            ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1747            (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1748                 hw->phy.multispeed_fiber = true;
1749
1750         /* Determine PHY vendor for optical modules */
1751         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1752                               IXGBE_SFF_10GBASELR_CAPABLE))  {
1753                 status = hw->phy.ops.read_i2c_eeprom(hw,
1754                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1755                                             &oui_bytes[0]);
1756
1757                 if (status != IXGBE_SUCCESS)
1758                         goto err_read_i2c_eeprom;
1759
1760                 status = hw->phy.ops.read_i2c_eeprom(hw,
1761                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1762                                             &oui_bytes[1]);
1763
1764                 if (status != IXGBE_SUCCESS)
1765                         goto err_read_i2c_eeprom;
1766
1767                 status = hw->phy.ops.read_i2c_eeprom(hw,
1768                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1769                                             &oui_bytes[2]);
1770
1771                 if (status != IXGBE_SUCCESS)
1772                         goto err_read_i2c_eeprom;
1773
1774                 vendor_oui =
1775                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1776                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1777                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1778
1779                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1780                         hw->phy.type = ixgbe_phy_qsfp_intel;
1781                 else
1782                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1783
1784                 ixgbe_get_device_caps(hw, &enforce_sfp);
1785                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1786                         /* Make sure we're a supported PHY type */
1787                         if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1788                                 status = IXGBE_SUCCESS;
1789                         } else {
1790                                 if (hw->allow_unsupported_sfp == true) {
1791                                         EWARN(hw, "WARNING: Intel (R) Network "
1792                                               "Connections are quality tested "
1793                                               "using Intel (R) Ethernet Optics."
1794                                               " Using untested modules is not "
1795                                               "supported and may cause unstable"
1796                                               " operation or damage to the "
1797                                               "module or the adapter. Intel "
1798                                               "Corporation is not responsible "
1799                                               "for any harm caused by using "
1800                                               "untested modules.\n", status);
1801                                         status = IXGBE_SUCCESS;
1802                                 } else {
1803                                         DEBUGOUT("QSFP module not supported\n");
1804                                         hw->phy.type =
1805                                                 ixgbe_phy_sfp_unsupported;
1806                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1807                                 }
1808                         }
1809                 } else {
1810                         status = IXGBE_SUCCESS;
1811                 }
1812         }
1813
1814 out:
1815         return status;
1816
1817 err_read_i2c_eeprom:
1818         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1819         hw->phy.id = 0;
1820         hw->phy.type = ixgbe_phy_unknown;
1821
1822         return IXGBE_ERR_SFP_NOT_PRESENT;
1823 }
1824
1825
1826 /**
1827  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1828  *  @hw: pointer to hardware structure
1829  *  @list_offset: offset to the SFP ID list
1830  *  @data_offset: offset to the SFP data block
1831  *
1832  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1833  *  so it returns the offsets to the phy init sequence block.
1834  **/
1835 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1836                                         u16 *list_offset,
1837                                         u16 *data_offset)
1838 {
1839         u16 sfp_id;
1840         u16 sfp_type = hw->phy.sfp_type;
1841
1842         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1843
1844         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1845                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1846
1847         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1848                 return IXGBE_ERR_SFP_NOT_PRESENT;
1849
1850         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1851             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1852                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1853
1854         /*
1855          * Limiting active cables and 1G Phys must be initialized as
1856          * SR modules
1857          */
1858         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1859             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1860             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1861             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1862                 sfp_type = ixgbe_sfp_type_srlr_core0;
1863         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1864                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1865                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1866                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1867                 sfp_type = ixgbe_sfp_type_srlr_core1;
1868
1869         /* Read offset to PHY init contents */
1870         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1871                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1872                               "eeprom read at offset %d failed",
1873                               IXGBE_PHY_INIT_OFFSET_NL);
1874                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1875         }
1876
1877         if ((!*list_offset) || (*list_offset == 0xFFFF))
1878                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1879
1880         /* Shift offset to first ID word */
1881         (*list_offset)++;
1882
1883         /*
1884          * Find the matching SFP ID in the EEPROM
1885          * and program the init sequence
1886          */
1887         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1888                 goto err_phy;
1889
1890         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1891                 if (sfp_id == sfp_type) {
1892                         (*list_offset)++;
1893                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1894                                 goto err_phy;
1895                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1896                                 DEBUGOUT("SFP+ module not supported\n");
1897                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1898                         } else {
1899                                 break;
1900                         }
1901                 } else {
1902                         (*list_offset) += 2;
1903                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1904                                 goto err_phy;
1905                 }
1906         }
1907
1908         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1909                 DEBUGOUT("No matching SFP+ module found\n");
1910                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1911         }
1912
1913         return IXGBE_SUCCESS;
1914
1915 err_phy:
1916         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1917                       "eeprom read at offset %d failed", *list_offset);
1918         return IXGBE_ERR_PHY;
1919 }
1920
1921 /**
1922  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1923  *  @hw: pointer to hardware structure
1924  *  @byte_offset: EEPROM byte offset to read
1925  *  @eeprom_data: value read
1926  *
1927  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1928  **/
1929 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1930                                   u8 *eeprom_data)
1931 {
1932         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1933
1934         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1935                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1936                                          eeprom_data);
1937 }
1938
1939 /**
1940  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1941  *  @hw: pointer to hardware structure
1942  *  @byte_offset: byte offset at address 0xA2
1943  *  @eeprom_data: value read
1944  *
1945  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1946  **/
1947 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1948                                           u8 *sff8472_data)
1949 {
1950         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1951                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1952                                          sff8472_data);
1953 }
1954
1955 /**
1956  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1957  *  @hw: pointer to hardware structure
1958  *  @byte_offset: EEPROM byte offset to write
1959  *  @eeprom_data: value to write
1960  *
1961  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1962  **/
1963 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1964                                    u8 eeprom_data)
1965 {
1966         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1967
1968         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1969                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1970                                           eeprom_data);
1971 }
1972
1973 /**
1974  * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1975  * @hw: pointer to hardware structure
1976  * @offset: eeprom offset to be read
1977  * @addr: I2C address to be read
1978  */
1979 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1980 {
1981         if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1982             offset == IXGBE_SFF_IDENTIFIER &&
1983             hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1984                 return true;
1985         return false;
1986 }
1987
1988 /**
1989  *  ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1990  *  @hw: pointer to hardware structure
1991  *  @byte_offset: byte offset to read
1992  *  @data: value read
1993  *  @lock: true if to take and release semaphore
1994  *
1995  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1996  *  a specified device address.
1997  **/
1998 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1999                                            u8 dev_addr, u8 *data, bool lock)
2000 {
2001         s32 status;
2002         u32 max_retry = 10;
2003         u32 retry = 0;
2004         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2005         bool nack = 1;
2006         *data = 0;
2007
2008         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2009
2010         if (hw->mac.type >= ixgbe_mac_X550)
2011                 max_retry = 3;
2012         if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2013                 max_retry = IXGBE_SFP_DETECT_RETRIES;
2014
2015         do {
2016                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2017                         return IXGBE_ERR_SWFW_SYNC;
2018
2019                 ixgbe_i2c_start(hw);
2020
2021                 /* Device Address and write indication */
2022                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2023                 if (status != IXGBE_SUCCESS)
2024                         goto fail;
2025
2026                 status = ixgbe_get_i2c_ack(hw);
2027                 if (status != IXGBE_SUCCESS)
2028                         goto fail;
2029
2030                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2031                 if (status != IXGBE_SUCCESS)
2032                         goto fail;
2033
2034                 status = ixgbe_get_i2c_ack(hw);
2035                 if (status != IXGBE_SUCCESS)
2036                         goto fail;
2037
2038                 ixgbe_i2c_start(hw);
2039
2040                 /* Device Address and read indication */
2041                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2042                 if (status != IXGBE_SUCCESS)
2043                         goto fail;
2044
2045                 status = ixgbe_get_i2c_ack(hw);
2046                 if (status != IXGBE_SUCCESS)
2047                         goto fail;
2048
2049                 status = ixgbe_clock_in_i2c_byte(hw, data);
2050                 if (status != IXGBE_SUCCESS)
2051                         goto fail;
2052
2053                 status = ixgbe_clock_out_i2c_bit(hw, nack);
2054                 if (status != IXGBE_SUCCESS)
2055                         goto fail;
2056
2057                 ixgbe_i2c_stop(hw);
2058                 if (lock)
2059                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2060                 return IXGBE_SUCCESS;
2061
2062 fail:
2063                 ixgbe_i2c_bus_clear(hw);
2064                 if (lock) {
2065                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2066                         msec_delay(100);
2067                 }
2068                 retry++;
2069                 if (retry < max_retry)
2070                         DEBUGOUT("I2C byte read error - Retrying.\n");
2071                 else
2072                         DEBUGOUT("I2C byte read error.\n");
2073
2074         } while (retry < max_retry);
2075
2076         return status;
2077 }
2078
2079 /**
2080  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2081  *  @hw: pointer to hardware structure
2082  *  @byte_offset: byte offset to read
2083  *  @data: value read
2084  *
2085  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2086  *  a specified device address.
2087  **/
2088 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2089                                 u8 dev_addr, u8 *data)
2090 {
2091         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2092                                                data, true);
2093 }
2094
2095 /**
2096  *  ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2097  *  @hw: pointer to hardware structure
2098  *  @byte_offset: byte offset to read
2099  *  @data: value read
2100  *
2101  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2102  *  a specified device address.
2103  **/
2104 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2105                                          u8 dev_addr, u8 *data)
2106 {
2107         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2108                                                data, false);
2109 }
2110
2111 /**
2112  *  ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2113  *  @hw: pointer to hardware structure
2114  *  @byte_offset: byte offset to write
2115  *  @data: value to write
2116  *  @lock: true if to take and release semaphore
2117  *
2118  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2119  *  a specified device address.
2120  **/
2121 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2122                                             u8 dev_addr, u8 data, bool lock)
2123 {
2124         s32 status;
2125         u32 max_retry = 1;
2126         u32 retry = 0;
2127         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2128
2129         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2130
2131         if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2132             IXGBE_SUCCESS)
2133                 return IXGBE_ERR_SWFW_SYNC;
2134
2135         do {
2136                 ixgbe_i2c_start(hw);
2137
2138                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2139                 if (status != IXGBE_SUCCESS)
2140                         goto fail;
2141
2142                 status = ixgbe_get_i2c_ack(hw);
2143                 if (status != IXGBE_SUCCESS)
2144                         goto fail;
2145
2146                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2147                 if (status != IXGBE_SUCCESS)
2148                         goto fail;
2149
2150                 status = ixgbe_get_i2c_ack(hw);
2151                 if (status != IXGBE_SUCCESS)
2152                         goto fail;
2153
2154                 status = ixgbe_clock_out_i2c_byte(hw, data);
2155                 if (status != IXGBE_SUCCESS)
2156                         goto fail;
2157
2158                 status = ixgbe_get_i2c_ack(hw);
2159                 if (status != IXGBE_SUCCESS)
2160                         goto fail;
2161
2162                 ixgbe_i2c_stop(hw);
2163                 if (lock)
2164                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2165                 return IXGBE_SUCCESS;
2166
2167 fail:
2168                 ixgbe_i2c_bus_clear(hw);
2169                 retry++;
2170                 if (retry < max_retry)
2171                         DEBUGOUT("I2C byte write error - Retrying.\n");
2172                 else
2173                         DEBUGOUT("I2C byte write error.\n");
2174         } while (retry < max_retry);
2175
2176         if (lock)
2177                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2178
2179         return status;
2180 }
2181
2182 /**
2183  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2184  *  @hw: pointer to hardware structure
2185  *  @byte_offset: byte offset to write
2186  *  @data: value to write
2187  *
2188  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2189  *  a specified device address.
2190  **/
2191 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2192                                  u8 dev_addr, u8 data)
2193 {
2194         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2195                                                 data, true);
2196 }
2197
2198 /**
2199  *  ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2200  *  @hw: pointer to hardware structure
2201  *  @byte_offset: byte offset to write
2202  *  @data: value to write
2203  *
2204  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2205  *  a specified device address.
2206  **/
2207 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2208                                           u8 dev_addr, u8 data)
2209 {
2210         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2211                                                 data, false);
2212 }
2213
2214 /**
2215  *  ixgbe_i2c_start - Sets I2C start condition
2216  *  @hw: pointer to hardware structure
2217  *
2218  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
2219  *  Set bit-bang mode on X550 hardware.
2220  **/
2221 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2222 {
2223         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2224
2225         DEBUGFUNC("ixgbe_i2c_start");
2226
2227         i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2228
2229         /* Start condition must begin with data and clock high */
2230         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2231         ixgbe_raise_i2c_clk(hw, &i2cctl);
2232
2233         /* Setup time for start condition (4.7us) */
2234         usec_delay(IXGBE_I2C_T_SU_STA);
2235
2236         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2237
2238         /* Hold time for start condition (4us) */
2239         usec_delay(IXGBE_I2C_T_HD_STA);
2240
2241         ixgbe_lower_i2c_clk(hw, &i2cctl);
2242
2243         /* Minimum low period of clock is 4.7 us */
2244         usec_delay(IXGBE_I2C_T_LOW);
2245
2246 }
2247
2248 /**
2249  *  ixgbe_i2c_stop - Sets I2C stop condition
2250  *  @hw: pointer to hardware structure
2251  *
2252  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
2253  *  Disables bit-bang mode and negates data output enable on X550
2254  *  hardware.
2255  **/
2256 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2257 {
2258         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2259         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2260         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2261         u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2262
2263         DEBUGFUNC("ixgbe_i2c_stop");
2264
2265         /* Stop condition must begin with data low and clock high */
2266         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2267         ixgbe_raise_i2c_clk(hw, &i2cctl);
2268
2269         /* Setup time for stop condition (4us) */
2270         usec_delay(IXGBE_I2C_T_SU_STO);
2271
2272         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2273
2274         /* bus free time between stop and start (4.7us)*/
2275         usec_delay(IXGBE_I2C_T_BUF);
2276
2277         if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2278                 i2cctl &= ~bb_en_bit;
2279                 i2cctl |= data_oe_bit | clk_oe_bit;
2280                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2281                 IXGBE_WRITE_FLUSH(hw);
2282         }
2283 }
2284
2285 /**
2286  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2287  *  @hw: pointer to hardware structure
2288  *  @data: data byte to clock in
2289  *
2290  *  Clocks in one byte data via I2C data/clock
2291  **/
2292 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2293 {
2294         s32 i;
2295         bool bit = 0;
2296
2297         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2298
2299         *data = 0;
2300         for (i = 7; i >= 0; i--) {
2301                 ixgbe_clock_in_i2c_bit(hw, &bit);
2302                 *data |= bit << i;
2303         }
2304
2305         return IXGBE_SUCCESS;
2306 }
2307
2308 /**
2309  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2310  *  @hw: pointer to hardware structure
2311  *  @data: data byte clocked out
2312  *
2313  *  Clocks out one byte data via I2C data/clock
2314  **/
2315 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2316 {
2317         s32 status = IXGBE_SUCCESS;
2318         s32 i;
2319         u32 i2cctl;
2320         bool bit;
2321
2322         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2323
2324         for (i = 7; i >= 0; i--) {
2325                 bit = (data >> i) & 0x1;
2326                 status = ixgbe_clock_out_i2c_bit(hw, bit);
2327
2328                 if (status != IXGBE_SUCCESS)
2329                         break;
2330         }
2331
2332         /* Release SDA line (set high) */
2333         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2334         i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2335         i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2336         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2337         IXGBE_WRITE_FLUSH(hw);
2338
2339         return status;
2340 }
2341
2342 /**
2343  *  ixgbe_get_i2c_ack - Polls for I2C ACK
2344  *  @hw: pointer to hardware structure
2345  *
2346  *  Clocks in/out one bit via I2C data/clock
2347  **/
2348 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2349 {
2350         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2351         s32 status = IXGBE_SUCCESS;
2352         u32 i = 0;
2353         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2354         u32 timeout = 10;
2355         bool ack = 1;
2356
2357         DEBUGFUNC("ixgbe_get_i2c_ack");
2358
2359         if (data_oe_bit) {
2360                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2361                 i2cctl |= data_oe_bit;
2362                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2363                 IXGBE_WRITE_FLUSH(hw);
2364         }
2365         ixgbe_raise_i2c_clk(hw, &i2cctl);
2366
2367         /* Minimum high period of clock is 4us */
2368         usec_delay(IXGBE_I2C_T_HIGH);
2369
2370         /* Poll for ACK.  Note that ACK in I2C spec is
2371          * transition from 1 to 0 */
2372         for (i = 0; i < timeout; i++) {
2373                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2374                 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2375
2376                 usec_delay(1);
2377                 if (!ack)
2378                         break;
2379         }
2380
2381         if (ack) {
2382                 DEBUGOUT("I2C ack was not received.\n");
2383                 status = IXGBE_ERR_I2C;
2384         }
2385
2386         ixgbe_lower_i2c_clk(hw, &i2cctl);
2387
2388         /* Minimum low period of clock is 4.7 us */
2389         usec_delay(IXGBE_I2C_T_LOW);
2390
2391         return status;
2392 }
2393
2394 /**
2395  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2396  *  @hw: pointer to hardware structure
2397  *  @data: read data value
2398  *
2399  *  Clocks in one bit via I2C data/clock
2400  **/
2401 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2402 {
2403         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2404         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2405
2406         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2407
2408         if (data_oe_bit) {
2409                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2410                 i2cctl |= data_oe_bit;
2411                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2412                 IXGBE_WRITE_FLUSH(hw);
2413         }
2414         ixgbe_raise_i2c_clk(hw, &i2cctl);
2415
2416         /* Minimum high period of clock is 4us */
2417         usec_delay(IXGBE_I2C_T_HIGH);
2418
2419         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2420         *data = ixgbe_get_i2c_data(hw, &i2cctl);
2421
2422         ixgbe_lower_i2c_clk(hw, &i2cctl);
2423
2424         /* Minimum low period of clock is 4.7 us */
2425         usec_delay(IXGBE_I2C_T_LOW);
2426
2427         return IXGBE_SUCCESS;
2428 }
2429
2430 /**
2431  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2432  *  @hw: pointer to hardware structure
2433  *  @data: data value to write
2434  *
2435  *  Clocks out one bit via I2C data/clock
2436  **/
2437 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2438 {
2439         s32 status;
2440         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2441
2442         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2443
2444         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2445         if (status == IXGBE_SUCCESS) {
2446                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2447
2448                 /* Minimum high period of clock is 4us */
2449                 usec_delay(IXGBE_I2C_T_HIGH);
2450
2451                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2452
2453                 /* Minimum low period of clock is 4.7 us.
2454                  * This also takes care of the data hold time.
2455                  */
2456                 usec_delay(IXGBE_I2C_T_LOW);
2457         } else {
2458                 status = IXGBE_ERR_I2C;
2459                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2460                              "I2C data was not set to %X\n", data);
2461         }
2462
2463         return status;
2464 }
2465
2466 /**
2467  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2468  *  @hw: pointer to hardware structure
2469  *  @i2cctl: Current value of I2CCTL register
2470  *
2471  *  Raises the I2C clock line '0'->'1'
2472  *  Negates the I2C clock output enable on X550 hardware.
2473  **/
2474 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2475 {
2476         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2477         u32 i = 0;
2478         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2479         u32 i2cctl_r = 0;
2480
2481         DEBUGFUNC("ixgbe_raise_i2c_clk");
2482
2483         if (clk_oe_bit) {
2484                 *i2cctl |= clk_oe_bit;
2485                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2486         }
2487
2488         for (i = 0; i < timeout; i++) {
2489                 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2490
2491                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2492                 IXGBE_WRITE_FLUSH(hw);
2493                 /* SCL rise time (1000ns) */
2494                 usec_delay(IXGBE_I2C_T_RISE);
2495
2496                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2497                 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2498                         break;
2499         }
2500 }
2501
2502 /**
2503  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2504  *  @hw: pointer to hardware structure
2505  *  @i2cctl: Current value of I2CCTL register
2506  *
2507  *  Lowers the I2C clock line '1'->'0'
2508  *  Asserts the I2C clock output enable on X550 hardware.
2509  **/
2510 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2511 {
2512         DEBUGFUNC("ixgbe_lower_i2c_clk");
2513
2514         *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2515         *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2516
2517         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2518         IXGBE_WRITE_FLUSH(hw);
2519
2520         /* SCL fall time (300ns) */
2521         usec_delay(IXGBE_I2C_T_FALL);
2522 }
2523
2524 /**
2525  *  ixgbe_set_i2c_data - Sets the I2C data bit
2526  *  @hw: pointer to hardware structure
2527  *  @i2cctl: Current value of I2CCTL register
2528  *  @data: I2C data value (0 or 1) to set
2529  *
2530  *  Sets the I2C data bit
2531  *  Asserts the I2C data output enable on X550 hardware.
2532  **/
2533 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2534 {
2535         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2536         s32 status = IXGBE_SUCCESS;
2537
2538         DEBUGFUNC("ixgbe_set_i2c_data");
2539
2540         if (data)
2541                 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2542         else
2543                 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2544         *i2cctl &= ~data_oe_bit;
2545
2546         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2547         IXGBE_WRITE_FLUSH(hw);
2548
2549         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2550         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2551
2552         if (!data)      /* Can't verify data in this case */
2553                 return IXGBE_SUCCESS;
2554         if (data_oe_bit) {
2555                 *i2cctl |= data_oe_bit;
2556                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2557                 IXGBE_WRITE_FLUSH(hw);
2558         }
2559
2560         /* Verify data was set correctly */
2561         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2562         if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2563                 status = IXGBE_ERR_I2C;
2564                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2565                              "Error - I2C data was not set to %X.\n",
2566                              data);
2567         }
2568
2569         return status;
2570 }
2571
2572 /**
2573  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2574  *  @hw: pointer to hardware structure
2575  *  @i2cctl: Current value of I2CCTL register
2576  *
2577  *  Returns the I2C data bit value
2578  *  Negates the I2C data output enable on X550 hardware.
2579  **/
2580 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2581 {
2582         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2583         bool data;
2584
2585         DEBUGFUNC("ixgbe_get_i2c_data");
2586
2587         if (data_oe_bit) {
2588                 *i2cctl |= data_oe_bit;
2589                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2590                 IXGBE_WRITE_FLUSH(hw);
2591                 usec_delay(IXGBE_I2C_T_FALL);
2592         }
2593
2594         if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2595                 data = 1;
2596         else
2597                 data = 0;
2598
2599         return data;
2600 }
2601
2602 /**
2603  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2604  *  @hw: pointer to hardware structure
2605  *
2606  *  Clears the I2C bus by sending nine clock pulses.
2607  *  Used when data line is stuck low.
2608  **/
2609 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2610 {
2611         u32 i2cctl;
2612         u32 i;
2613
2614         DEBUGFUNC("ixgbe_i2c_bus_clear");
2615
2616         ixgbe_i2c_start(hw);
2617         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2618
2619         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2620
2621         for (i = 0; i < 9; i++) {
2622                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2623
2624                 /* Min high period of clock is 4us */
2625                 usec_delay(IXGBE_I2C_T_HIGH);
2626
2627                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2628
2629                 /* Min low period of clock is 4.7us*/
2630                 usec_delay(IXGBE_I2C_T_LOW);
2631         }
2632
2633         ixgbe_i2c_start(hw);
2634
2635         /* Put the i2c bus back to default state */
2636         ixgbe_i2c_stop(hw);
2637 }
2638
2639 /**
2640  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2641  *  @hw: pointer to hardware structure
2642  *
2643  *  Checks if the LASI temp alarm status was triggered due to overtemp
2644  **/
2645 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2646 {
2647         s32 status = IXGBE_SUCCESS;
2648         u16 phy_data = 0;
2649
2650         DEBUGFUNC("ixgbe_tn_check_overtemp");
2651
2652         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2653                 goto out;
2654
2655         /* Check that the LASI temp alarm status was triggered */
2656         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2657                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2658
2659         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2660                 goto out;
2661
2662         status = IXGBE_ERR_OVERTEMP;
2663         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2664 out:
2665         return status;
2666 }
2667
2668 /**
2669  * ixgbe_set_copper_phy_power - Control power for copper phy
2670  * @hw: pointer to hardware structure
2671  * @on: true for on, false for off
2672  */
2673 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2674 {
2675         u32 status;
2676         u16 reg;
2677
2678         if (!on && ixgbe_mng_present(hw))
2679                 return 0;
2680
2681         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2682                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2683                                       &reg);
2684         if (status)
2685                 return status;
2686
2687         if (on) {
2688                 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2689         } else {
2690                 if (ixgbe_check_reset_blocked(hw))
2691                         return 0;
2692                 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2693         }
2694
2695         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2696                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2697                                        reg);
2698         return status;
2699 }