1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
6 #include "ixgbe_common.h"
9 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
10 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
11 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
12 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
13 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
14 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
15 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
16 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
17 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
18 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
19 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
20 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
24 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
25 * @hw: pointer to the hardware structure
28 * Returns an error code on error.
30 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
34 status = ixgbe_clock_out_i2c_byte(hw, byte);
37 return ixgbe_get_i2c_ack(hw);
41 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
42 * @hw: pointer to the hardware structure
43 * @byte: pointer to a u8 to receive the byte
45 * Returns an error code on error.
47 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
51 status = ixgbe_clock_in_i2c_byte(hw, byte);
55 return ixgbe_clock_out_i2c_bit(hw, false);
59 * ixgbe_ones_comp_byte_add - Perform one's complement addition
63 * Returns one's complement 8-bit sum.
65 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
67 u16 sum = add1 + add2;
69 sum = (sum & 0xFF) + (sum >> 8);
74 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
75 * @hw: pointer to the hardware structure
76 * @addr: I2C bus address to read from
77 * @reg: I2C device register to read from
78 * @val: pointer to location to receive read value
79 * @lock: true if to take and release semaphore
81 * Returns an error code on error.
83 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
86 u32 swfw_mask = hw->phy.phy_semaphore_mask;
95 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
96 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
99 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
100 return IXGBE_ERR_SWFW_SYNC;
102 /* Device Address and write indication */
103 if (ixgbe_out_i2c_byte_ack(hw, addr))
105 /* Write bits 14:8 */
106 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
109 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
112 if (ixgbe_out_i2c_byte_ack(hw, csum))
114 /* Re-start condition */
116 /* Device Address and read indication */
117 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
120 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
123 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
126 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
129 if (ixgbe_clock_out_i2c_bit(hw, false))
133 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
134 *val = (high_bits << 8) | low_bits;
138 ixgbe_i2c_bus_clear(hw);
140 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
141 if (retry < max_retry)
142 DEBUGOUT("I2C byte read combined error - Retrying.\n");
144 DEBUGOUT("I2C byte read combined error.\n");
146 } while (retry <= max_retry);
148 return IXGBE_ERR_I2C;
152 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
153 * @hw: pointer to the hardware structure
154 * @addr: I2C bus address to write to
155 * @reg: I2C device register to write to
156 * @val: value to write
157 * @lock: true if to take and release semaphore
159 * Returns an error code on error.
161 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
164 u32 swfw_mask = hw->phy.phy_semaphore_mask;
170 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
171 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
172 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
173 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
176 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
177 return IXGBE_ERR_SWFW_SYNC;
179 /* Device Address and write indication */
180 if (ixgbe_out_i2c_byte_ack(hw, addr))
182 /* Write bits 14:8 */
183 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
186 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
188 /* Write data 15:8 */
189 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
192 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
195 if (ixgbe_out_i2c_byte_ack(hw, csum))
199 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
203 ixgbe_i2c_bus_clear(hw);
205 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
206 if (retry < max_retry)
207 DEBUGOUT("I2C byte write combined error - Retrying.\n");
209 DEBUGOUT("I2C byte write combined error.\n");
211 } while (retry <= max_retry);
213 return IXGBE_ERR_I2C;
217 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
218 * @hw: pointer to the hardware structure
220 * Initialize the function pointers.
222 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
224 struct ixgbe_phy_info *phy = &hw->phy;
226 DEBUGFUNC("ixgbe_init_phy_ops_generic");
229 phy->ops.identify = ixgbe_identify_phy_generic;
230 phy->ops.reset = ixgbe_reset_phy_generic;
231 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
232 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
233 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
234 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
235 phy->ops.setup_link = ixgbe_setup_phy_link_generic;
236 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
237 phy->ops.check_link = NULL;
238 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
239 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
240 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
241 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
242 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
243 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
244 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
245 phy->ops.identify_sfp = ixgbe_identify_module_generic;
246 phy->sfp_type = ixgbe_sfp_type_unknown;
247 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
248 phy->ops.write_i2c_byte_unlocked =
249 ixgbe_write_i2c_byte_generic_unlocked;
250 phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
251 return IXGBE_SUCCESS;
255 * ixgbe_probe_phy - Probe a single address for a PHY
256 * @hw: pointer to hardware structure
257 * @phy_addr: PHY address to probe
259 * Returns true if PHY found
261 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
265 if (!ixgbe_validate_phy_addr(hw, phy_addr)) {
266 DEBUGOUT1("Unable to validate PHY address 0x%04X\n",
271 if (ixgbe_get_phy_id(hw))
274 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
276 if (hw->phy.type == ixgbe_phy_unknown) {
277 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
278 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
280 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
281 IXGBE_MDIO_PHY_1000BASET_ABILITY))
282 hw->phy.type = ixgbe_phy_cu_unknown;
284 hw->phy.type = ixgbe_phy_generic;
291 * ixgbe_identify_phy_generic - Get physical layer module
292 * @hw: pointer to hardware structure
294 * Determines the physical layer module found on the current adapter.
296 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
298 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
301 DEBUGFUNC("ixgbe_identify_phy_generic");
303 if (!hw->phy.phy_semaphore_mask) {
305 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
307 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
310 if (hw->phy.type != ixgbe_phy_unknown)
311 return IXGBE_SUCCESS;
313 if (hw->phy.nw_mng_if_sel) {
314 phy_addr = (hw->phy.nw_mng_if_sel &
315 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
316 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
317 if (ixgbe_probe_phy(hw, phy_addr))
318 return IXGBE_SUCCESS;
320 return IXGBE_ERR_PHY_ADDR_INVALID;
323 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
324 if (ixgbe_probe_phy(hw, phy_addr)) {
325 status = IXGBE_SUCCESS;
330 /* Certain media types do not have a phy so an address will not
331 * be found and the code will take this path. Caller has to
332 * decide if it is an error or not.
334 if (status != IXGBE_SUCCESS)
341 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
342 * @hw: pointer to the hardware structure
344 * This function checks the MMNGC.MNG_VETO bit to see if there are
345 * any constraints on link from manageability. For MAC's that don't
346 * have this bit just return faluse since the link can not be blocked
349 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
353 DEBUGFUNC("ixgbe_check_reset_blocked");
355 /* If we don't have this bit, it can't be blocking */
356 if (hw->mac.type == ixgbe_mac_82598EB)
359 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
360 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
361 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
362 "MNG_VETO bit detected.\n");
370 * ixgbe_validate_phy_addr - Determines phy address is valid
371 * @hw: pointer to hardware structure
372 * @phy_addr: PHY address
375 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
380 DEBUGFUNC("ixgbe_validate_phy_addr");
382 hw->phy.addr = phy_addr;
383 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
384 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
386 if (phy_id != 0xFFFF && phy_id != 0x0)
389 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id);
395 * ixgbe_get_phy_id - Get the phy type
396 * @hw: pointer to hardware structure
399 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
405 DEBUGFUNC("ixgbe_get_phy_id");
407 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
408 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
411 if (status == IXGBE_SUCCESS) {
412 hw->phy.id = (u32)(phy_id_high << 16);
413 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
414 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
416 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
417 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
419 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
420 phy_id_high, phy_id_low);
426 * ixgbe_get_phy_type_from_id - Get the phy type
427 * @phy_id: PHY ID information
430 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
432 enum ixgbe_phy_type phy_type;
434 DEBUGFUNC("ixgbe_get_phy_type_from_id");
438 phy_type = ixgbe_phy_tn;
443 phy_type = ixgbe_phy_aq;
446 phy_type = ixgbe_phy_qt;
449 phy_type = ixgbe_phy_nl;
453 phy_type = ixgbe_phy_x550em_ext_t;
455 case IXGBE_M88E1500_E_PHY_ID:
456 case IXGBE_M88E1543_E_PHY_ID:
457 phy_type = ixgbe_phy_ext_1g_t;
460 phy_type = ixgbe_phy_unknown;
467 * ixgbe_reset_phy_generic - Performs a PHY reset
468 * @hw: pointer to hardware structure
470 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
474 s32 status = IXGBE_SUCCESS;
476 DEBUGFUNC("ixgbe_reset_phy_generic");
478 if (hw->phy.type == ixgbe_phy_unknown)
479 status = ixgbe_identify_phy_generic(hw);
481 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
484 /* Don't reset PHY if it's shut down due to overtemp. */
485 if (!hw->phy.reset_if_overtemp &&
486 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
489 /* Blocked by MNG FW so bail */
490 if (ixgbe_check_reset_blocked(hw))
494 * Perform soft PHY reset to the PHY_XS.
495 * This will cause a soft reset to the PHY
497 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
498 IXGBE_MDIO_PHY_XS_DEV_TYPE,
499 IXGBE_MDIO_PHY_XS_RESET);
502 * Poll for reset bit to self-clear indicating reset is complete.
503 * Some PHYs could take up to 3 seconds to complete and need about
504 * 1.7 usec delay after the reset is complete.
506 for (i = 0; i < 30; i++) {
508 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
509 status = hw->phy.ops.read_reg(hw,
510 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
511 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
513 if (status != IXGBE_SUCCESS)
516 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
521 status = hw->phy.ops.read_reg(hw,
522 IXGBE_MDIO_PHY_XS_CONTROL,
523 IXGBE_MDIO_PHY_XS_DEV_TYPE,
525 if (status != IXGBE_SUCCESS)
528 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
535 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
536 status = IXGBE_ERR_RESET_FAILED;
537 ERROR_REPORT1(IXGBE_ERROR_POLLING,
538 "PHY reset polling failed to complete.\n");
546 * ixgbe_restart_auto_neg - Restart auto negotiation on the PHY
547 * @hw: pointer to hardware structure
549 void ixgbe_restart_auto_neg(struct ixgbe_hw *hw)
553 /* Check if PHY reset is blocked by MNG FW */
554 if (ixgbe_check_reset_blocked(hw))
557 /* Restart PHY auto-negotiation. */
558 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
559 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
560 autoneg_reg |= IXGBE_MII_RESTART;
561 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
562 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
566 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
568 * @hw: pointer to hardware structure
569 * @reg_addr: 32 bit address of PHY register to read
570 * @device_type: 5 bit device type
571 * @phy_data: Pointer to read data from PHY register
573 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
576 u32 i, data, command;
578 /* Setup and write the address cycle command */
579 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
580 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
581 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
582 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
584 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
587 * Check every 10 usec to see if the address cycle completed.
588 * The MDI Command bit will clear when the operation is
591 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
594 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
595 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
600 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
601 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
602 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n");
603 return IXGBE_ERR_PHY;
607 * Address cycle complete, setup and write the read
610 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
611 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
612 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
613 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
615 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
618 * Check every 10 usec to see if the address cycle
619 * completed. The MDI Command bit will clear when the
620 * operation is complete
622 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
625 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
626 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
630 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
631 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
632 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n");
633 return IXGBE_ERR_PHY;
637 * Read operation is complete. Get the data
640 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
641 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
642 *phy_data = (u16)(data);
644 return IXGBE_SUCCESS;
648 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
649 * using the SWFW lock - this function is needed in most cases
650 * @hw: pointer to hardware structure
651 * @reg_addr: 32 bit address of PHY register to read
652 * @device_type: 5 bit device type
653 * @phy_data: Pointer to read data from PHY register
655 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
656 u32 device_type, u16 *phy_data)
659 u32 gssr = hw->phy.phy_semaphore_mask;
661 DEBUGFUNC("ixgbe_read_phy_reg_generic");
663 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
664 return IXGBE_ERR_SWFW_SYNC;
666 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
668 hw->mac.ops.release_swfw_sync(hw, gssr);
674 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
676 * @hw: pointer to hardware structure
677 * @reg_addr: 32 bit PHY register to write
678 * @device_type: 5 bit device type
679 * @phy_data: Data to write to the PHY register
681 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
682 u32 device_type, u16 phy_data)
686 /* Put the data in the MDI single read and write data register*/
687 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
689 /* Setup and write the address cycle command */
690 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
691 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
692 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
693 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
695 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
698 * Check every 10 usec to see if the address cycle completed.
699 * The MDI Command bit will clear when the operation is
702 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
705 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
706 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
710 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
711 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
712 return IXGBE_ERR_PHY;
716 * Address cycle complete, setup and write the write
719 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
720 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
721 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
722 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
724 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
727 * Check every 10 usec to see if the address cycle
728 * completed. The MDI Command bit will clear when the
729 * operation is complete
731 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
734 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
735 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
739 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
740 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
741 return IXGBE_ERR_PHY;
744 return IXGBE_SUCCESS;
748 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
749 * using SWFW lock- this function is needed in most cases
750 * @hw: pointer to hardware structure
751 * @reg_addr: 32 bit PHY register to write
752 * @device_type: 5 bit device type
753 * @phy_data: Data to write to the PHY register
755 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
756 u32 device_type, u16 phy_data)
759 u32 gssr = hw->phy.phy_semaphore_mask;
761 DEBUGFUNC("ixgbe_write_phy_reg_generic");
763 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
764 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
766 hw->mac.ops.release_swfw_sync(hw, gssr);
768 status = IXGBE_ERR_SWFW_SYNC;
775 * ixgbe_setup_phy_link_generic - Set and restart auto-neg
776 * @hw: pointer to hardware structure
778 * Restart auto-negotiation and PHY and waits for completion.
780 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
782 s32 status = IXGBE_SUCCESS;
783 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
784 bool autoneg = false;
785 ixgbe_link_speed speed;
787 DEBUGFUNC("ixgbe_setup_phy_link_generic");
789 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
791 /* Set or unset auto-negotiation 10G advertisement */
792 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
793 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
796 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
797 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
798 (speed & IXGBE_LINK_SPEED_10GB_FULL))
799 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
801 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
802 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
805 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
806 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
809 if (hw->mac.type == ixgbe_mac_X550) {
810 /* Set or unset auto-negotiation 5G advertisement */
811 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
812 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
813 (speed & IXGBE_LINK_SPEED_5GB_FULL))
814 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
816 /* Set or unset auto-negotiation 2.5G advertisement */
817 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
818 if ((hw->phy.autoneg_advertised &
819 IXGBE_LINK_SPEED_2_5GB_FULL) &&
820 (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
821 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
824 /* Set or unset auto-negotiation 1G advertisement */
825 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
826 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
827 (speed & IXGBE_LINK_SPEED_1GB_FULL))
828 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
830 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
831 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
834 /* Set or unset auto-negotiation 100M advertisement */
835 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
836 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
839 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
840 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
841 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
842 (speed & IXGBE_LINK_SPEED_100_FULL))
843 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
845 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
846 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
849 ixgbe_restart_auto_neg(hw);
854 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
855 * @hw: pointer to hardware structure
856 * @speed: new link speed
857 * @autoneg_wait_to_complete: unused
859 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
860 ixgbe_link_speed speed,
861 bool autoneg_wait_to_complete)
863 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
865 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
868 * Clear autoneg_advertised and set new values based on input link
871 hw->phy.autoneg_advertised = 0;
873 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
874 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
876 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
877 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
879 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
880 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
882 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
883 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
885 if (speed & IXGBE_LINK_SPEED_100_FULL)
886 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
888 if (speed & IXGBE_LINK_SPEED_10_FULL)
889 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
891 /* Setup link based on the new speed settings */
892 ixgbe_setup_phy_link(hw);
894 return IXGBE_SUCCESS;
898 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
899 * @hw: pointer to hardware structure
901 * Determines the supported link capabilities by reading the PHY auto
902 * negotiation register.
904 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
909 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
910 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
915 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
916 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
917 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
918 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
919 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
920 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
922 switch (hw->mac.type) {
924 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
925 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
927 case ixgbe_mac_X550EM_x:
928 case ixgbe_mac_X550EM_a:
929 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
939 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
940 * @hw: pointer to hardware structure
941 * @speed: pointer to link speed
942 * @autoneg: boolean auto-negotiation value
944 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
945 ixgbe_link_speed *speed,
948 s32 status = IXGBE_SUCCESS;
950 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
953 if (!hw->phy.speeds_supported)
954 status = ixgbe_get_copper_speeds_supported(hw);
956 *speed = hw->phy.speeds_supported;
961 * ixgbe_check_phy_link_tnx - Determine link and speed status
962 * @hw: pointer to hardware structure
963 * @speed: current link speed
964 * @link_up: true is link is up, false otherwise
966 * Reads the VS1 register to determine if link is up and the current speed for
969 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
972 s32 status = IXGBE_SUCCESS;
974 u32 max_time_out = 10;
979 DEBUGFUNC("ixgbe_check_phy_link_tnx");
981 /* Initialize speed and link to default case */
983 *speed = IXGBE_LINK_SPEED_10GB_FULL;
986 * Check current speed and link status of the PHY register.
987 * This is a vendor specific register and may have to
988 * be changed for other copper PHYs.
990 for (time_out = 0; time_out < max_time_out; time_out++) {
992 status = hw->phy.ops.read_reg(hw,
993 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
994 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
996 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
997 phy_speed = phy_data &
998 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
999 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1002 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1003 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1012 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1013 * @hw: pointer to hardware structure
1015 * Restart auto-negotiation and PHY and waits for completion.
1017 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1019 s32 status = IXGBE_SUCCESS;
1020 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1021 bool autoneg = false;
1022 ixgbe_link_speed speed;
1024 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1026 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1028 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1029 /* Set or unset auto-negotiation 10G advertisement */
1030 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1031 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1034 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1035 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1036 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1038 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1039 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1043 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1044 /* Set or unset auto-negotiation 1G advertisement */
1045 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1046 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1049 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1050 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1051 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1053 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1054 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1058 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1059 /* Set or unset auto-negotiation 100M advertisement */
1060 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1061 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1064 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1065 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1066 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1068 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1069 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1073 ixgbe_restart_auto_neg(hw);
1078 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1079 * @hw: pointer to hardware structure
1080 * @firmware_version: pointer to the PHY Firmware Version
1082 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1083 u16 *firmware_version)
1087 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1089 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1090 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1097 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1098 * @hw: pointer to hardware structure
1099 * @firmware_version: pointer to the PHY Firmware Version
1101 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1102 u16 *firmware_version)
1106 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1108 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1109 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1116 * ixgbe_reset_phy_nl - Performs a PHY reset
1117 * @hw: pointer to hardware structure
1119 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1121 u16 phy_offset, control, eword, edata, block_crc;
1122 bool end_data = false;
1123 u16 list_offset, data_offset;
1125 s32 ret_val = IXGBE_SUCCESS;
1128 DEBUGFUNC("ixgbe_reset_phy_nl");
1130 /* Blocked by MNG FW so bail */
1131 if (ixgbe_check_reset_blocked(hw))
1134 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1135 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1137 /* reset the PHY and poll for completion */
1138 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1139 IXGBE_MDIO_PHY_XS_DEV_TYPE,
1140 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1142 for (i = 0; i < 100; i++) {
1143 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1144 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1145 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1150 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1151 DEBUGOUT("PHY reset did not complete.\n");
1152 ret_val = IXGBE_ERR_PHY;
1156 /* Get init offsets */
1157 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1159 if (ret_val != IXGBE_SUCCESS)
1162 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1166 * Read control word from PHY init contents offset
1168 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1171 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1172 IXGBE_CONTROL_SHIFT_NL;
1173 edata = eword & IXGBE_DATA_MASK_NL;
1175 case IXGBE_DELAY_NL:
1177 DEBUGOUT1("DELAY: %d MS\n", edata);
1181 DEBUGOUT("DATA:\n");
1183 ret_val = hw->eeprom.ops.read(hw, data_offset,
1188 for (i = 0; i < edata; i++) {
1189 ret_val = hw->eeprom.ops.read(hw, data_offset,
1193 hw->phy.ops.write_reg(hw, phy_offset,
1194 IXGBE_TWINAX_DEV, eword);
1195 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1201 case IXGBE_CONTROL_NL:
1203 DEBUGOUT("CONTROL:\n");
1204 if (edata == IXGBE_CONTROL_EOL_NL) {
1207 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1210 DEBUGOUT("Bad control value\n");
1211 ret_val = IXGBE_ERR_PHY;
1216 DEBUGOUT("Bad control type\n");
1217 ret_val = IXGBE_ERR_PHY;
1226 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1227 "eeprom read at offset %d failed", data_offset);
1228 return IXGBE_ERR_PHY;
1232 * ixgbe_identify_module_generic - Identifies module type
1233 * @hw: pointer to hardware structure
1235 * Determines HW type and calls appropriate function.
1237 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1239 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1241 DEBUGFUNC("ixgbe_identify_module_generic");
1243 switch (hw->mac.ops.get_media_type(hw)) {
1244 case ixgbe_media_type_fiber:
1245 status = ixgbe_identify_sfp_module_generic(hw);
1248 case ixgbe_media_type_fiber_qsfp:
1249 status = ixgbe_identify_qsfp_module_generic(hw);
1253 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1254 status = IXGBE_ERR_SFP_NOT_PRESENT;
1262 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1263 * @hw: pointer to hardware structure
1265 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1267 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1269 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1271 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1273 u8 comp_codes_1g = 0;
1274 u8 comp_codes_10g = 0;
1275 u8 oui_bytes[3] = {0, 0, 0};
1278 u16 enforce_sfp = 0;
1280 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1282 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1283 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1284 status = IXGBE_ERR_SFP_NOT_PRESENT;
1288 /* LAN ID is needed for I2C access */
1289 hw->mac.ops.set_lan_id(hw);
1291 status = hw->phy.ops.read_i2c_eeprom(hw,
1292 IXGBE_SFF_IDENTIFIER,
1295 if (status != IXGBE_SUCCESS)
1296 goto err_read_i2c_eeprom;
1298 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1299 hw->phy.type = ixgbe_phy_sfp_unsupported;
1300 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1302 status = hw->phy.ops.read_i2c_eeprom(hw,
1303 IXGBE_SFF_1GBE_COMP_CODES,
1306 if (status != IXGBE_SUCCESS)
1307 goto err_read_i2c_eeprom;
1309 status = hw->phy.ops.read_i2c_eeprom(hw,
1310 IXGBE_SFF_10GBE_COMP_CODES,
1313 if (status != IXGBE_SUCCESS)
1314 goto err_read_i2c_eeprom;
1315 status = hw->phy.ops.read_i2c_eeprom(hw,
1316 IXGBE_SFF_CABLE_TECHNOLOGY,
1319 if (status != IXGBE_SUCCESS)
1320 goto err_read_i2c_eeprom;
1327 * 3 SFP_DA_CORE0 - 82599-specific
1328 * 4 SFP_DA_CORE1 - 82599-specific
1329 * 5 SFP_SR/LR_CORE0 - 82599-specific
1330 * 6 SFP_SR/LR_CORE1 - 82599-specific
1331 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1332 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1333 * 9 SFP_1g_cu_CORE0 - 82599-specific
1334 * 10 SFP_1g_cu_CORE1 - 82599-specific
1335 * 11 SFP_1g_sx_CORE0 - 82599-specific
1336 * 12 SFP_1g_sx_CORE1 - 82599-specific
1338 if (hw->mac.type == ixgbe_mac_82598EB) {
1339 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1340 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1341 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1342 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1343 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1344 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1346 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1348 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1349 if (hw->bus.lan_id == 0)
1351 ixgbe_sfp_type_da_cu_core0;
1354 ixgbe_sfp_type_da_cu_core1;
1355 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1356 hw->phy.ops.read_i2c_eeprom(
1357 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1360 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1361 if (hw->bus.lan_id == 0)
1363 ixgbe_sfp_type_da_act_lmt_core0;
1366 ixgbe_sfp_type_da_act_lmt_core1;
1369 ixgbe_sfp_type_unknown;
1371 } else if (comp_codes_10g &
1372 (IXGBE_SFF_10GBASESR_CAPABLE |
1373 IXGBE_SFF_10GBASELR_CAPABLE)) {
1374 if (hw->bus.lan_id == 0)
1376 ixgbe_sfp_type_srlr_core0;
1379 ixgbe_sfp_type_srlr_core1;
1380 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1381 if (hw->bus.lan_id == 0)
1383 ixgbe_sfp_type_1g_cu_core0;
1386 ixgbe_sfp_type_1g_cu_core1;
1387 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1388 if (hw->bus.lan_id == 0)
1390 ixgbe_sfp_type_1g_sx_core0;
1393 ixgbe_sfp_type_1g_sx_core1;
1394 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1395 if (hw->bus.lan_id == 0)
1397 ixgbe_sfp_type_1g_lx_core0;
1400 ixgbe_sfp_type_1g_lx_core1;
1401 } else if (comp_codes_1g & IXGBE_SFF_1GBASELHA_CAPABLE) {
1402 if (hw->bus.lan_id == 0)
1404 ixgbe_sfp_type_1g_lha_core0;
1407 ixgbe_sfp_type_1g_lha_core1;
1409 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1413 if (hw->phy.sfp_type != stored_sfp_type)
1414 hw->phy.sfp_setup_needed = true;
1416 /* Determine if the SFP+ PHY is dual speed or not. */
1417 hw->phy.multispeed_fiber = false;
1418 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1419 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1420 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1421 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1422 hw->phy.multispeed_fiber = true;
1424 /* Determine PHY vendor */
1425 if (hw->phy.type != ixgbe_phy_nl) {
1426 hw->phy.id = identifier;
1427 status = hw->phy.ops.read_i2c_eeprom(hw,
1428 IXGBE_SFF_VENDOR_OUI_BYTE0,
1431 if (status != IXGBE_SUCCESS)
1432 goto err_read_i2c_eeprom;
1434 status = hw->phy.ops.read_i2c_eeprom(hw,
1435 IXGBE_SFF_VENDOR_OUI_BYTE1,
1438 if (status != IXGBE_SUCCESS)
1439 goto err_read_i2c_eeprom;
1441 status = hw->phy.ops.read_i2c_eeprom(hw,
1442 IXGBE_SFF_VENDOR_OUI_BYTE2,
1445 if (status != IXGBE_SUCCESS)
1446 goto err_read_i2c_eeprom;
1449 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1450 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1451 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1453 switch (vendor_oui) {
1454 case IXGBE_SFF_VENDOR_OUI_TYCO:
1455 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1457 ixgbe_phy_sfp_passive_tyco;
1459 case IXGBE_SFF_VENDOR_OUI_FTL:
1460 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1461 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1463 hw->phy.type = ixgbe_phy_sfp_ftl;
1465 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1466 hw->phy.type = ixgbe_phy_sfp_avago;
1468 case IXGBE_SFF_VENDOR_OUI_INTEL:
1469 hw->phy.type = ixgbe_phy_sfp_intel;
1472 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1474 ixgbe_phy_sfp_passive_unknown;
1475 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1477 ixgbe_phy_sfp_active_unknown;
1479 hw->phy.type = ixgbe_phy_sfp_unknown;
1484 /* Allow any DA cable vendor */
1485 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1486 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1487 status = IXGBE_SUCCESS;
1491 /* Verify supported 1G SFP modules */
1492 if (comp_codes_10g == 0 &&
1493 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1494 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1495 hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core0 ||
1496 hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core1 ||
1497 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1498 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1499 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1500 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1501 hw->phy.type = ixgbe_phy_sfp_unsupported;
1502 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1506 /* Anything else 82598-based is supported */
1507 if (hw->mac.type == ixgbe_mac_82598EB) {
1508 status = IXGBE_SUCCESS;
1512 ixgbe_get_device_caps(hw, &enforce_sfp);
1513 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1514 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1515 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1516 hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core0 ||
1517 hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core1 ||
1518 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1519 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1520 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1521 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1522 /* Make sure we're a supported PHY type */
1523 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1524 status = IXGBE_SUCCESS;
1526 if (hw->allow_unsupported_sfp == true) {
1528 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. "
1529 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1530 "Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1531 status = IXGBE_SUCCESS;
1533 DEBUGOUT("SFP+ module not supported\n");
1535 ixgbe_phy_sfp_unsupported;
1536 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1540 status = IXGBE_SUCCESS;
1547 err_read_i2c_eeprom:
1548 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1549 if (hw->phy.type != ixgbe_phy_nl) {
1551 hw->phy.type = ixgbe_phy_unknown;
1553 return IXGBE_ERR_SFP_NOT_PRESENT;
1557 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1558 * @hw: pointer to hardware structure
1560 * Determines physical layer capabilities of the current SFP.
1562 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1564 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1565 u8 comp_codes_10g = 0;
1566 u8 comp_codes_1g = 0;
1568 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1570 hw->phy.ops.identify_sfp(hw);
1571 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1572 return physical_layer;
1574 switch (hw->phy.type) {
1575 case ixgbe_phy_sfp_passive_tyco:
1576 case ixgbe_phy_sfp_passive_unknown:
1577 case ixgbe_phy_qsfp_passive_unknown:
1578 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1580 case ixgbe_phy_sfp_ftl_active:
1581 case ixgbe_phy_sfp_active_unknown:
1582 case ixgbe_phy_qsfp_active_unknown:
1583 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1585 case ixgbe_phy_sfp_avago:
1586 case ixgbe_phy_sfp_ftl:
1587 case ixgbe_phy_sfp_intel:
1588 case ixgbe_phy_sfp_unknown:
1589 hw->phy.ops.read_i2c_eeprom(hw,
1590 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1591 hw->phy.ops.read_i2c_eeprom(hw,
1592 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1593 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1594 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1595 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1596 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1597 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1598 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1599 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1600 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1602 case ixgbe_phy_qsfp_intel:
1603 case ixgbe_phy_qsfp_unknown:
1604 hw->phy.ops.read_i2c_eeprom(hw,
1605 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1606 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1607 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1608 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1609 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1615 return physical_layer;
1619 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1620 * @hw: pointer to hardware structure
1622 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1624 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1626 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1628 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1630 u8 comp_codes_1g = 0;
1631 u8 comp_codes_10g = 0;
1632 u8 oui_bytes[3] = {0, 0, 0};
1633 u16 enforce_sfp = 0;
1635 u8 cable_length = 0;
1637 bool active_cable = false;
1639 DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1641 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1642 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1643 status = IXGBE_ERR_SFP_NOT_PRESENT;
1647 /* LAN ID is needed for I2C access */
1648 hw->mac.ops.set_lan_id(hw);
1650 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1653 if (status != IXGBE_SUCCESS)
1654 goto err_read_i2c_eeprom;
1656 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1657 hw->phy.type = ixgbe_phy_sfp_unsupported;
1658 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1662 hw->phy.id = identifier;
1664 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1667 if (status != IXGBE_SUCCESS)
1668 goto err_read_i2c_eeprom;
1670 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1673 if (status != IXGBE_SUCCESS)
1674 goto err_read_i2c_eeprom;
1676 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1677 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1678 if (hw->bus.lan_id == 0)
1679 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1681 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1682 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1683 IXGBE_SFF_10GBASELR_CAPABLE)) {
1684 if (hw->bus.lan_id == 0)
1685 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1687 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1689 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1690 active_cable = true;
1692 if (!active_cable) {
1693 /* check for active DA cables that pre-date
1695 hw->phy.ops.read_i2c_eeprom(hw,
1696 IXGBE_SFF_QSFP_CONNECTOR,
1699 hw->phy.ops.read_i2c_eeprom(hw,
1700 IXGBE_SFF_QSFP_CABLE_LENGTH,
1703 hw->phy.ops.read_i2c_eeprom(hw,
1704 IXGBE_SFF_QSFP_DEVICE_TECH,
1708 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1709 (cable_length > 0) &&
1710 ((device_tech >> 4) ==
1711 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1712 active_cable = true;
1716 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1717 if (hw->bus.lan_id == 0)
1719 ixgbe_sfp_type_da_act_lmt_core0;
1722 ixgbe_sfp_type_da_act_lmt_core1;
1724 /* unsupported module type */
1725 hw->phy.type = ixgbe_phy_sfp_unsupported;
1726 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1731 if (hw->phy.sfp_type != stored_sfp_type)
1732 hw->phy.sfp_setup_needed = true;
1734 /* Determine if the QSFP+ PHY is dual speed or not. */
1735 hw->phy.multispeed_fiber = false;
1736 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1737 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1738 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1739 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1740 hw->phy.multispeed_fiber = true;
1742 /* Determine PHY vendor for optical modules */
1743 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1744 IXGBE_SFF_10GBASELR_CAPABLE)) {
1745 status = hw->phy.ops.read_i2c_eeprom(hw,
1746 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1749 if (status != IXGBE_SUCCESS)
1750 goto err_read_i2c_eeprom;
1752 status = hw->phy.ops.read_i2c_eeprom(hw,
1753 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1756 if (status != IXGBE_SUCCESS)
1757 goto err_read_i2c_eeprom;
1759 status = hw->phy.ops.read_i2c_eeprom(hw,
1760 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1763 if (status != IXGBE_SUCCESS)
1764 goto err_read_i2c_eeprom;
1767 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1768 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1769 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1771 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1772 hw->phy.type = ixgbe_phy_qsfp_intel;
1774 hw->phy.type = ixgbe_phy_qsfp_unknown;
1776 ixgbe_get_device_caps(hw, &enforce_sfp);
1777 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1778 /* Make sure we're a supported PHY type */
1779 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1780 status = IXGBE_SUCCESS;
1782 if (hw->allow_unsupported_sfp == true) {
1784 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. "
1785 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1786 "Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1787 status = IXGBE_SUCCESS;
1789 DEBUGOUT("QSFP module not supported\n");
1791 ixgbe_phy_sfp_unsupported;
1792 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1796 status = IXGBE_SUCCESS;
1803 err_read_i2c_eeprom:
1804 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1806 hw->phy.type = ixgbe_phy_unknown;
1808 return IXGBE_ERR_SFP_NOT_PRESENT;
1812 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1813 * @hw: pointer to hardware structure
1814 * @list_offset: offset to the SFP ID list
1815 * @data_offset: offset to the SFP data block
1817 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1818 * so it returns the offsets to the phy init sequence block.
1820 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1825 u16 sfp_type = hw->phy.sfp_type;
1827 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1829 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1830 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1832 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1833 return IXGBE_ERR_SFP_NOT_PRESENT;
1835 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1836 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1837 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1840 * Limiting active cables and 1G Phys must be initialized as
1843 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1844 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1845 sfp_type == ixgbe_sfp_type_1g_lha_core0 ||
1846 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1847 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1848 sfp_type = ixgbe_sfp_type_srlr_core0;
1849 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1850 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1851 sfp_type == ixgbe_sfp_type_1g_lha_core1 ||
1852 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1853 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1854 sfp_type = ixgbe_sfp_type_srlr_core1;
1856 /* Read offset to PHY init contents */
1857 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1858 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1859 "eeprom read at offset %d failed",
1860 IXGBE_PHY_INIT_OFFSET_NL);
1861 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1864 if ((!*list_offset) || (*list_offset == 0xFFFF))
1865 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1867 /* Shift offset to first ID word */
1871 * Find the matching SFP ID in the EEPROM
1872 * and program the init sequence
1874 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1877 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1878 if (sfp_id == sfp_type) {
1880 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1882 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1883 DEBUGOUT("SFP+ module not supported\n");
1884 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1889 (*list_offset) += 2;
1890 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1895 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1896 DEBUGOUT("No matching SFP+ module found\n");
1897 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1900 return IXGBE_SUCCESS;
1903 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1904 "eeprom read at offset %d failed", *list_offset);
1905 return IXGBE_ERR_PHY;
1909 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1910 * @hw: pointer to hardware structure
1911 * @byte_offset: EEPROM byte offset to read
1912 * @eeprom_data: value read
1914 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1916 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1919 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1921 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1922 IXGBE_I2C_EEPROM_DEV_ADDR,
1927 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1928 * @hw: pointer to hardware structure
1929 * @byte_offset: byte offset at address 0xA2
1930 * @sff8472_data: value read
1932 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1934 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1937 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1938 IXGBE_I2C_EEPROM_DEV_ADDR2,
1943 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1944 * @hw: pointer to hardware structure
1945 * @byte_offset: EEPROM byte offset to write
1946 * @eeprom_data: value to write
1948 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1950 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1953 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1955 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1956 IXGBE_I2C_EEPROM_DEV_ADDR,
1961 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1962 * @hw: pointer to hardware structure
1963 * @offset: eeprom offset to be read
1964 * @addr: I2C address to be read
1966 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1968 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1969 offset == IXGBE_SFF_IDENTIFIER &&
1970 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1976 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1977 * @hw: pointer to hardware structure
1978 * @byte_offset: byte offset to read
1979 * @dev_addr: address to read from
1981 * @lock: true if to take and release semaphore
1983 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1984 * a specified device address.
1986 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1987 u8 dev_addr, u8 *data, bool lock)
1992 u32 swfw_mask = hw->phy.phy_semaphore_mask;
1996 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1998 if (hw->mac.type >= ixgbe_mac_X550)
2000 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2001 max_retry = IXGBE_SFP_DETECT_RETRIES;
2004 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2005 return IXGBE_ERR_SWFW_SYNC;
2007 ixgbe_i2c_start(hw);
2009 /* Device Address and write indication */
2010 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2011 if (status != IXGBE_SUCCESS)
2014 status = ixgbe_get_i2c_ack(hw);
2015 if (status != IXGBE_SUCCESS)
2018 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2019 if (status != IXGBE_SUCCESS)
2022 status = ixgbe_get_i2c_ack(hw);
2023 if (status != IXGBE_SUCCESS)
2026 ixgbe_i2c_start(hw);
2028 /* Device Address and read indication */
2029 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2030 if (status != IXGBE_SUCCESS)
2033 status = ixgbe_get_i2c_ack(hw);
2034 if (status != IXGBE_SUCCESS)
2037 status = ixgbe_clock_in_i2c_byte(hw, data);
2038 if (status != IXGBE_SUCCESS)
2041 status = ixgbe_clock_out_i2c_bit(hw, nack);
2042 if (status != IXGBE_SUCCESS)
2047 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2048 return IXGBE_SUCCESS;
2051 ixgbe_i2c_bus_clear(hw);
2053 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2056 if (retry < max_retry)
2057 DEBUGOUT("I2C byte read error - Retrying.\n");
2059 DEBUGOUT("I2C byte read error.\n");
2061 } while (retry <= max_retry);
2067 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2068 * @hw: pointer to hardware structure
2069 * @byte_offset: byte offset to read
2070 * @dev_addr: address to read from
2073 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2074 * a specified device address.
2076 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2077 u8 dev_addr, u8 *data)
2079 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2084 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2085 * @hw: pointer to hardware structure
2086 * @byte_offset: byte offset to read
2087 * @dev_addr: address to read from
2090 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2091 * a specified device address.
2093 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2094 u8 dev_addr, u8 *data)
2096 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2101 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2102 * @hw: pointer to hardware structure
2103 * @byte_offset: byte offset to write
2104 * @dev_addr: address to write to
2105 * @data: value to write
2106 * @lock: true if to take and release semaphore
2108 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2109 * a specified device address.
2111 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2112 u8 dev_addr, u8 data, bool lock)
2117 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2119 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2121 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2123 return IXGBE_ERR_SWFW_SYNC;
2126 ixgbe_i2c_start(hw);
2128 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2129 if (status != IXGBE_SUCCESS)
2132 status = ixgbe_get_i2c_ack(hw);
2133 if (status != IXGBE_SUCCESS)
2136 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2137 if (status != IXGBE_SUCCESS)
2140 status = ixgbe_get_i2c_ack(hw);
2141 if (status != IXGBE_SUCCESS)
2144 status = ixgbe_clock_out_i2c_byte(hw, data);
2145 if (status != IXGBE_SUCCESS)
2148 status = ixgbe_get_i2c_ack(hw);
2149 if (status != IXGBE_SUCCESS)
2154 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2155 return IXGBE_SUCCESS;
2158 ixgbe_i2c_bus_clear(hw);
2159 if (retry < max_retry)
2160 DEBUGOUT("I2C byte write error - Retrying.\n");
2162 DEBUGOUT("I2C byte write error.\n");
2164 } while (retry <= max_retry);
2167 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2173 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2174 * @hw: pointer to hardware structure
2175 * @byte_offset: byte offset to write
2176 * @dev_addr: address to write to
2177 * @data: value to write
2179 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2180 * a specified device address.
2182 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2183 u8 dev_addr, u8 data)
2185 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2190 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2191 * @hw: pointer to hardware structure
2192 * @byte_offset: byte offset to write
2193 * @dev_addr: address to write to
2194 * @data: value to write
2196 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2197 * a specified device address.
2199 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2200 u8 dev_addr, u8 data)
2202 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2207 * ixgbe_i2c_start - Sets I2C start condition
2208 * @hw: pointer to hardware structure
2210 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2211 * Set bit-bang mode on X550 hardware.
2213 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2215 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2217 DEBUGFUNC("ixgbe_i2c_start");
2219 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2221 /* Start condition must begin with data and clock high */
2222 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2223 ixgbe_raise_i2c_clk(hw, &i2cctl);
2225 /* Setup time for start condition (4.7us) */
2226 usec_delay(IXGBE_I2C_T_SU_STA);
2228 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2230 /* Hold time for start condition (4us) */
2231 usec_delay(IXGBE_I2C_T_HD_STA);
2233 ixgbe_lower_i2c_clk(hw, &i2cctl);
2235 /* Minimum low period of clock is 4.7 us */
2236 usec_delay(IXGBE_I2C_T_LOW);
2241 * ixgbe_i2c_stop - Sets I2C stop condition
2242 * @hw: pointer to hardware structure
2244 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2245 * Disables bit-bang mode and negates data output enable on X550
2248 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2250 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2251 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2252 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2253 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2255 DEBUGFUNC("ixgbe_i2c_stop");
2257 /* Stop condition must begin with data low and clock high */
2258 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2259 ixgbe_raise_i2c_clk(hw, &i2cctl);
2261 /* Setup time for stop condition (4us) */
2262 usec_delay(IXGBE_I2C_T_SU_STO);
2264 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2266 /* bus free time between stop and start (4.7us)*/
2267 usec_delay(IXGBE_I2C_T_BUF);
2269 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2270 i2cctl &= ~bb_en_bit;
2271 i2cctl |= data_oe_bit | clk_oe_bit;
2272 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2273 IXGBE_WRITE_FLUSH(hw);
2278 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2279 * @hw: pointer to hardware structure
2280 * @data: data byte to clock in
2282 * Clocks in one byte data via I2C data/clock
2284 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2289 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2292 for (i = 7; i >= 0; i--) {
2293 ixgbe_clock_in_i2c_bit(hw, &bit);
2297 return IXGBE_SUCCESS;
2301 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2302 * @hw: pointer to hardware structure
2303 * @data: data byte clocked out
2305 * Clocks out one byte data via I2C data/clock
2307 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2309 s32 status = IXGBE_SUCCESS;
2314 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2316 for (i = 7; i >= 0; i--) {
2317 bit = (data >> i) & 0x1;
2318 status = ixgbe_clock_out_i2c_bit(hw, bit);
2320 if (status != IXGBE_SUCCESS)
2324 /* Release SDA line (set high) */
2325 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2326 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2327 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2328 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2329 IXGBE_WRITE_FLUSH(hw);
2335 * ixgbe_get_i2c_ack - Polls for I2C ACK
2336 * @hw: pointer to hardware structure
2338 * Clocks in/out one bit via I2C data/clock
2340 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2342 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2343 s32 status = IXGBE_SUCCESS;
2345 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2349 DEBUGFUNC("ixgbe_get_i2c_ack");
2352 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2353 i2cctl |= data_oe_bit;
2354 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2355 IXGBE_WRITE_FLUSH(hw);
2357 ixgbe_raise_i2c_clk(hw, &i2cctl);
2359 /* Minimum high period of clock is 4us */
2360 usec_delay(IXGBE_I2C_T_HIGH);
2362 /* Poll for ACK. Note that ACK in I2C spec is
2363 * transition from 1 to 0 */
2364 for (i = 0; i < timeout; i++) {
2365 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2366 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2374 DEBUGOUT("I2C ack was not received.\n");
2375 status = IXGBE_ERR_I2C;
2378 ixgbe_lower_i2c_clk(hw, &i2cctl);
2380 /* Minimum low period of clock is 4.7 us */
2381 usec_delay(IXGBE_I2C_T_LOW);
2387 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2388 * @hw: pointer to hardware structure
2389 * @data: read data value
2391 * Clocks in one bit via I2C data/clock
2393 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2395 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2396 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2398 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2401 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2402 i2cctl |= data_oe_bit;
2403 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2404 IXGBE_WRITE_FLUSH(hw);
2406 ixgbe_raise_i2c_clk(hw, &i2cctl);
2408 /* Minimum high period of clock is 4us */
2409 usec_delay(IXGBE_I2C_T_HIGH);
2411 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2412 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2414 ixgbe_lower_i2c_clk(hw, &i2cctl);
2416 /* Minimum low period of clock is 4.7 us */
2417 usec_delay(IXGBE_I2C_T_LOW);
2419 return IXGBE_SUCCESS;
2423 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2424 * @hw: pointer to hardware structure
2425 * @data: data value to write
2427 * Clocks out one bit via I2C data/clock
2429 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2432 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2434 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2436 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2437 if (status == IXGBE_SUCCESS) {
2438 ixgbe_raise_i2c_clk(hw, &i2cctl);
2440 /* Minimum high period of clock is 4us */
2441 usec_delay(IXGBE_I2C_T_HIGH);
2443 ixgbe_lower_i2c_clk(hw, &i2cctl);
2445 /* Minimum low period of clock is 4.7 us.
2446 * This also takes care of the data hold time.
2448 usec_delay(IXGBE_I2C_T_LOW);
2450 status = IXGBE_ERR_I2C;
2451 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2452 "I2C data was not set to %X\n", data);
2459 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2460 * @hw: pointer to hardware structure
2461 * @i2cctl: Current value of I2CCTL register
2463 * Raises the I2C clock line '0'->'1'
2464 * Negates the I2C clock output enable on X550 hardware.
2466 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2468 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2470 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2473 DEBUGFUNC("ixgbe_raise_i2c_clk");
2476 *i2cctl |= clk_oe_bit;
2477 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2480 for (i = 0; i < timeout; i++) {
2481 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2483 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2484 IXGBE_WRITE_FLUSH(hw);
2485 /* SCL rise time (1000ns) */
2486 usec_delay(IXGBE_I2C_T_RISE);
2488 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2489 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2495 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2496 * @hw: pointer to hardware structure
2497 * @i2cctl: Current value of I2CCTL register
2499 * Lowers the I2C clock line '1'->'0'
2500 * Asserts the I2C clock output enable on X550 hardware.
2502 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2504 DEBUGFUNC("ixgbe_lower_i2c_clk");
2506 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2507 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2509 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2510 IXGBE_WRITE_FLUSH(hw);
2512 /* SCL fall time (300ns) */
2513 usec_delay(IXGBE_I2C_T_FALL);
2517 * ixgbe_set_i2c_data - Sets the I2C data bit
2518 * @hw: pointer to hardware structure
2519 * @i2cctl: Current value of I2CCTL register
2520 * @data: I2C data value (0 or 1) to set
2522 * Sets the I2C data bit
2523 * Asserts the I2C data output enable on X550 hardware.
2525 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2527 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2528 s32 status = IXGBE_SUCCESS;
2530 DEBUGFUNC("ixgbe_set_i2c_data");
2533 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2535 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2536 *i2cctl &= ~data_oe_bit;
2538 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2539 IXGBE_WRITE_FLUSH(hw);
2541 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2542 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2544 if (!data) /* Can't verify data in this case */
2545 return IXGBE_SUCCESS;
2547 *i2cctl |= data_oe_bit;
2548 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2549 IXGBE_WRITE_FLUSH(hw);
2552 /* Verify data was set correctly */
2553 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2554 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2555 status = IXGBE_ERR_I2C;
2556 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2557 "Error - I2C data was not set to %X.\n",
2565 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2566 * @hw: pointer to hardware structure
2567 * @i2cctl: Current value of I2CCTL register
2569 * Returns the I2C data bit value
2570 * Negates the I2C data output enable on X550 hardware.
2572 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2574 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2577 DEBUGFUNC("ixgbe_get_i2c_data");
2580 *i2cctl |= data_oe_bit;
2581 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2582 IXGBE_WRITE_FLUSH(hw);
2583 usec_delay(IXGBE_I2C_T_FALL);
2586 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2595 * ixgbe_i2c_bus_clear - Clears the I2C bus
2596 * @hw: pointer to hardware structure
2598 * Clears the I2C bus by sending nine clock pulses.
2599 * Used when data line is stuck low.
2601 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2606 DEBUGFUNC("ixgbe_i2c_bus_clear");
2608 ixgbe_i2c_start(hw);
2609 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2611 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2613 for (i = 0; i < 9; i++) {
2614 ixgbe_raise_i2c_clk(hw, &i2cctl);
2616 /* Min high period of clock is 4us */
2617 usec_delay(IXGBE_I2C_T_HIGH);
2619 ixgbe_lower_i2c_clk(hw, &i2cctl);
2621 /* Min low period of clock is 4.7us*/
2622 usec_delay(IXGBE_I2C_T_LOW);
2625 ixgbe_i2c_start(hw);
2627 /* Put the i2c bus back to default state */
2632 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2633 * @hw: pointer to hardware structure
2635 * Checks if the LASI temp alarm status was triggered due to overtemp
2637 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2639 s32 status = IXGBE_SUCCESS;
2642 DEBUGFUNC("ixgbe_tn_check_overtemp");
2644 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2647 /* Check that the LASI temp alarm status was triggered */
2648 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2649 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2651 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2654 status = IXGBE_ERR_OVERTEMP;
2655 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2661 * ixgbe_set_copper_phy_power - Control power for copper phy
2662 * @hw: pointer to hardware structure
2663 * @on: true for on, false for off
2665 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2670 if (!on && ixgbe_mng_present(hw))
2673 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2674 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2680 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2682 if (ixgbe_check_reset_blocked(hw))
2684 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2687 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2688 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,