drivers/net/ixgbe/base/ixgbe_phy.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2018
   3  */
   4
   5 #include "ixgbe_api.h"
   6 #include "ixgbe_common.h"
   7 #include "ixgbe_phy.h"
   8
   9 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
  10 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  11 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  12 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  13 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  14 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  15 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  16 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  17 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  18 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  19 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  20 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  21                                           u8 *sff8472_data);
  22
  23 /**
  24  * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
  25  * @hw: pointer to the hardware structure
  26  * @byte: byte to send
  27  *
  28  * Returns an error code on error.
  29  */
  30 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
  31 {
  32         s32 status;
  33
  34         status = ixgbe_clock_out_i2c_byte(hw, byte);
  35         if (status)
  36                 return status;
  37         return ixgbe_get_i2c_ack(hw);
  38 }
  39
  40 /**
  41  * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
  42  * @hw: pointer to the hardware structure
  43  * @byte: pointer to a u8 to receive the byte
  44  *
  45  * Returns an error code on error.
  46  */
  47 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
  48 {
  49         s32 status;
  50
  51         status = ixgbe_clock_in_i2c_byte(hw, byte);
  52         if (status)
  53                 return status;
  54         /* ACK */
  55         return ixgbe_clock_out_i2c_bit(hw, false);
  56 }
  57
  58 /**
  59  * ixgbe_ones_comp_byte_add - Perform one's complement addition
  60  * @add1: addend 1
  61  * @add2: addend 2
  62  *
  63  * Returns one's complement 8-bit sum.
  64  */
  65 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
  66 {
  67         u16 sum = add1 + add2;
  68
  69         sum = (sum & 0xFF) + (sum >> 8);
  70         return sum & 0xFF;
  71 }
  72
  73 /**
  74  * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
  75  * @hw: pointer to the hardware structure
  76  * @addr: I2C bus address to read from
  77  * @reg: I2C device register to read from
  78  * @val: pointer to location to receive read value
  79  * @lock: true if to take and release semaphore
  80  *
  81  * Returns an error code on error.
  82  */
  83 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
  84                                         u16 *val, bool lock)
  85 {
  86         u32 swfw_mask = hw->phy.phy_semaphore_mask;
  87         int max_retry = 3;
  88         int retry = 0;
  89         u8 csum_byte;
  90         u8 high_bits;
  91         u8 low_bits;
  92         u8 reg_high;
  93         u8 csum;
  94
  95         reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
  96         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
  97         csum = ~csum;
  98         do {
  99                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 100                         return IXGBE_ERR_SWFW_SYNC;
 101                 ixgbe_i2c_start(hw);
 102                 /* Device Address and write indication */
 103                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 104                         goto fail;
 105                 /* Write bits 14:8 */
 106                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 107                         goto fail;
 108                 /* Write bits 7:0 */
 109                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 110                         goto fail;
 111                 /* Write csum */
 112                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 113                         goto fail;
 114                 /* Re-start condition */
 115                 ixgbe_i2c_start(hw);
 116                 /* Device Address and read indication */
 117                 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
 118                         goto fail;
 119                 /* Get upper bits */
 120                 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
 121                         goto fail;
 122                 /* Get low bits */
 123                 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
 124                         goto fail;
 125                 /* Get csum */
 126                 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
 127                         goto fail;
 128                 /* NACK */
 129                 if (ixgbe_clock_out_i2c_bit(hw, false))
 130                         goto fail;
 131                 ixgbe_i2c_stop(hw);
 132                 if (lock)
 133                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 134                 *val = (high_bits << 8) | low_bits;
 135                 return 0;
 136
 137 fail:
 138                 ixgbe_i2c_bus_clear(hw);
 139                 if (lock)
 140                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 141                 retry++;
 142                 if (retry < max_retry)
 143                         DEBUGOUT("I2C byte read combined error - Retrying.\n");
 144                 else
 145                         DEBUGOUT("I2C byte read combined error.\n");
 146         } while (retry < max_retry);
 147
 148         return IXGBE_ERR_I2C;
 149 }
 150
 151 /**
 152  * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
 153  * @hw: pointer to the hardware structure
 154  * @addr: I2C bus address to write to
 155  * @reg: I2C device register to write to
 156  * @val: value to write
 157  * @lock: true if to take and release semaphore
 158  *
 159  * Returns an error code on error.
 160  */
 161 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 162                                          u16 val, bool lock)
 163 {
 164         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 165         int max_retry = 1;
 166         int retry = 0;
 167         u8 reg_high;
 168         u8 csum;
 169
 170         reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
 171         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 172         csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
 173         csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
 174         csum = ~csum;
 175         do {
 176                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 177                         return IXGBE_ERR_SWFW_SYNC;
 178                 ixgbe_i2c_start(hw);
 179                 /* Device Address and write indication */
 180                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 181                         goto fail;
 182                 /* Write bits 14:8 */
 183                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 184                         goto fail;
 185                 /* Write bits 7:0 */
 186                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 187                         goto fail;
 188                 /* Write data 15:8 */
 189                 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
 190                         goto fail;
 191                 /* Write data 7:0 */
 192                 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
 193                         goto fail;
 194                 /* Write csum */
 195                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 196                         goto fail;
 197                 ixgbe_i2c_stop(hw);
 198                 if (lock)
 199                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 200                 return 0;
 201
 202 fail:
 203                 ixgbe_i2c_bus_clear(hw);
 204                 if (lock)
 205                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 206                 retry++;
 207                 if (retry < max_retry)
 208                         DEBUGOUT("I2C byte write combined error - Retrying.\n");
 209                 else
 210                         DEBUGOUT("I2C byte write combined error.\n");
 211         } while (retry < max_retry);
 212
 213         return IXGBE_ERR_I2C;
 214 }
 215
 216 /**
 217  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
 218  *  @hw: pointer to the hardware structure
 219  *
 220  *  Initialize the function pointers.
 221  **/
 222 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
 223 {
 224         struct ixgbe_phy_info *phy = &hw->phy;
 225
 226         DEBUGFUNC("ixgbe_init_phy_ops_generic");
 227
 228         /* PHY */
 229         phy->ops.identify = ixgbe_identify_phy_generic;
 230         phy->ops.reset = ixgbe_reset_phy_generic;
 231         phy->ops.read_reg = ixgbe_read_phy_reg_generic;
 232         phy->ops.write_reg = ixgbe_write_phy_reg_generic;
 233         phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
 234         phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
 235         phy->ops.setup_link = ixgbe_setup_phy_link_generic;
 236         phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
 237         phy->ops.check_link = NULL;
 238         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
 239         phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
 240         phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
 241         phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
 242         phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
 243         phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
 244         phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
 245         phy->ops.identify_sfp = ixgbe_identify_module_generic;
 246         phy->sfp_type = ixgbe_sfp_type_unknown;
 247         phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
 248         phy->ops.write_i2c_byte_unlocked =
 249                                 ixgbe_write_i2c_byte_generic_unlocked;
 250         phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
 251         return IXGBE_SUCCESS;
 252 }
 253
 254 /**
 255  * ixgbe_probe_phy - Probe a single address for a PHY
 256  * @hw: pointer to hardware structure
 257  * @phy_addr: PHY address to probe
 258  *
 259  * Returns true if PHY found
 260  */
 261 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
 262 {
 263         u16 ext_ability = 0;
 264
 265         if (!ixgbe_validate_phy_addr(hw, phy_addr)) {
 266                 DEBUGOUT1("Unable to validate PHY address 0x%04X\n",
 267                         phy_addr);
 268                 return false;
 269         }
 270
 271         if (ixgbe_get_phy_id(hw))
 272                 return false;
 273
 274         hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
 275
 276         if (hw->phy.type == ixgbe_phy_unknown) {
 277                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
 278                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
 279                 if (ext_ability &
 280                     (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 281                      IXGBE_MDIO_PHY_1000BASET_ABILITY))
 282                         hw->phy.type = ixgbe_phy_cu_unknown;
 283                 else
 284                         hw->phy.type = ixgbe_phy_generic;
 285         }
 286
 287         return true;
 288 }
 289
 290 /**
 291  *  ixgbe_identify_phy_generic - Get physical layer module
 292  *  @hw: pointer to hardware structure
 293  *
 294  *  Determines the physical layer module found on the current adapter.
 295  **/
 296 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 297 {
 298         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 299         u16 phy_addr;
 300
 301         DEBUGFUNC("ixgbe_identify_phy_generic");
 302
 303         if (!hw->phy.phy_semaphore_mask) {
 304                 if (hw->bus.lan_id)
 305                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 306                 else
 307                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 308         }
 309
 310         if (hw->phy.type != ixgbe_phy_unknown)
 311                 return IXGBE_SUCCESS;
 312
 313         if (hw->phy.nw_mng_if_sel) {
 314                 phy_addr = (hw->phy.nw_mng_if_sel &
 315                             IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
 316                            IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
 317                 if (ixgbe_probe_phy(hw, phy_addr))
 318                         return IXGBE_SUCCESS;
 319                 else
 320                         return IXGBE_ERR_PHY_ADDR_INVALID;
 321         }
 322
 323         for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 324                 if (ixgbe_probe_phy(hw, phy_addr)) {
 325                         status = IXGBE_SUCCESS;
 326                         break;
 327                 }
 328         }
 329
 330         /* Certain media types do not have a phy so an address will not
 331          * be found and the code will take this path.  Caller has to
 332          * decide if it is an error or not.
 333          */
 334         if (status != IXGBE_SUCCESS)
 335                 hw->phy.addr = 0;
 336
 337         return status;
 338 }
 339
 340 /**
 341  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 342  * @hw: pointer to the hardware structure
 343  *
 344  * This function checks the MMNGC.MNG_VETO bit to see if there are
 345  * any constraints on link from manageability.  For MAC's that don't
 346  * have this bit just return faluse since the link can not be blocked
 347  * via this method.
 348  **/
 349 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 350 {
 351         u32 mmngc;
 352
 353         DEBUGFUNC("ixgbe_check_reset_blocked");
 354
 355         /* If we don't have this bit, it can't be blocking */
 356         if (hw->mac.type == ixgbe_mac_82598EB)
 357                 return false;
 358
 359         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 360         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 361                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 362                               "MNG_VETO bit detected.\n");
 363                 return true;
 364         }
 365
 366         return false;
 367 }
 368
 369 /**
 370  *  ixgbe_validate_phy_addr - Determines phy address is valid
 371  *  @hw: pointer to hardware structure
 372  *  @phy_addr: PHY address
 373  *
 374  **/
 375 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 376 {
 377         u16 phy_id = 0;
 378         bool valid = false;
 379
 380         DEBUGFUNC("ixgbe_validate_phy_addr");
 381
 382         hw->phy.addr = phy_addr;
 383         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 384                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 385
 386         if (phy_id != 0xFFFF && phy_id != 0x0)
 387                 valid = true;
 388
 389         DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id);
 390
 391         return valid;
 392 }
 393
 394 /**
 395  *  ixgbe_get_phy_id - Get the phy type
 396  *  @hw: pointer to hardware structure
 397  *
 398  **/
 399 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 400 {
 401         u32 status;
 402         u16 phy_id_high = 0;
 403         u16 phy_id_low = 0;
 404
 405         DEBUGFUNC("ixgbe_get_phy_id");
 406
 407         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 408                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 409                                       &phy_id_high);
 410
 411         if (status == IXGBE_SUCCESS) {
 412                 hw->phy.id = (u32)(phy_id_high << 16);
 413                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 414                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 415                                               &phy_id_low);
 416                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 417                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 418         }
 419         DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
 420                   phy_id_high, phy_id_low);
 421
 422         return status;
 423 }
 424
 425 /**
 426  *  ixgbe_get_phy_type_from_id - Get the phy type
 427  *  @phy_id: PHY ID information
 428  *
 429  **/
 430 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 431 {
 432         enum ixgbe_phy_type phy_type;
 433
 434         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 435
 436         switch (phy_id) {
 437         case TN1010_PHY_ID:
 438                 phy_type = ixgbe_phy_tn;
 439                 break;
 440         case X550_PHY_ID2:
 441         case X550_PHY_ID3:
 442         case X540_PHY_ID:
 443                 phy_type = ixgbe_phy_aq;
 444                 break;
 445         case QT2022_PHY_ID:
 446                 phy_type = ixgbe_phy_qt;
 447                 break;
 448         case ATH_PHY_ID:
 449                 phy_type = ixgbe_phy_nl;
 450                 break;
 451         case X557_PHY_ID:
 452         case X557_PHY_ID2:
 453                 phy_type = ixgbe_phy_x550em_ext_t;
 454                 break;
 455         case IXGBE_M88E1500_E_PHY_ID:
 456         case IXGBE_M88E1543_E_PHY_ID:
 457                 phy_type = ixgbe_phy_ext_1g_t;
 458                 break;
 459         default:
 460                 phy_type = ixgbe_phy_unknown;
 461                 break;
 462         }
 463         return phy_type;
 464 }
 465
 466 /**
 467  *  ixgbe_reset_phy_generic - Performs a PHY reset
 468  *  @hw: pointer to hardware structure
 469  **/
 470 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 471 {
 472         u32 i;
 473         u16 ctrl = 0;
 474         s32 status = IXGBE_SUCCESS;
 475
 476         DEBUGFUNC("ixgbe_reset_phy_generic");
 477
 478         if (hw->phy.type == ixgbe_phy_unknown)
 479                 status = ixgbe_identify_phy_generic(hw);
 480
 481         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 482                 goto out;
 483
 484         /* Don't reset PHY if it's shut down due to overtemp. */
 485         if (!hw->phy.reset_if_overtemp &&
 486             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 487                 goto out;
 488
 489         /* Blocked by MNG FW so bail */
 490         if (ixgbe_check_reset_blocked(hw))
 491                 goto out;
 492
 493         /*
 494          * Perform soft PHY reset to the PHY_XS.
 495          * This will cause a soft reset to the PHY
 496          */
 497         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 498                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 499                               IXGBE_MDIO_PHY_XS_RESET);
 500
 501         /*
 502          * Poll for reset bit to self-clear indicating reset is complete.
 503          * Some PHYs could take up to 3 seconds to complete and need about
 504          * 1.7 usec delay after the reset is complete.
 505          */
 506         for (i = 0; i < 30; i++) {
 507                 msec_delay(100);
 508                 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
 509                         status = hw->phy.ops.read_reg(hw,
 510                                                   IXGBE_MDIO_TX_VENDOR_ALARMS_3,
 511                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 512                                                   &ctrl);
 513                         if (status != IXGBE_SUCCESS)
 514                                 return status;
 515
 516                         if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
 517                                 usec_delay(2);
 518                                 break;
 519                         }
 520                 } else {
 521                         status = hw->phy.ops.read_reg(hw,
 522                                                      IXGBE_MDIO_PHY_XS_CONTROL,
 523                                                      IXGBE_MDIO_PHY_XS_DEV_TYPE,
 524                                                      &ctrl);
 525                         if (status != IXGBE_SUCCESS)
 526                                 return status;
 527
 528                         if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 529                                 usec_delay(2);
 530                                 break;
 531                         }
 532                 }
 533         }
 534
 535         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 536                 status = IXGBE_ERR_RESET_FAILED;
 537                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 538                              "PHY reset polling failed to complete.\n");
 539         }
 540
 541 out:
 542         return status;
 543 }
 544
 545 /**
 546  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 547  *  the SWFW lock
 548  *  @hw: pointer to hardware structure
 549  *  @reg_addr: 32 bit address of PHY register to read
 550  *  @device_type: 5 bit device type
 551  *  @phy_data: Pointer to read data from PHY register
 552  **/
 553 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 554                            u16 *phy_data)
 555 {
 556         u32 i, data, command;
 557
 558         /* Setup and write the address cycle command */
 559         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 560                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 561                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 562                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 563
 564         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 565
 566         /*
 567          * Check every 10 usec to see if the address cycle completed.
 568          * The MDI Command bit will clear when the operation is
 569          * complete
 570          */
 571         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 572                 usec_delay(10);
 573
 574                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 575                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 576                         break;
 577         }
 578
 579
 580         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 581                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 582                 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n");
 583                 return IXGBE_ERR_PHY;
 584         }
 585
 586         /*
 587          * Address cycle complete, setup and write the read
 588          * command
 589          */
 590         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 591                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 592                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 593                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 594
 595         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 596
 597         /*
 598          * Check every 10 usec to see if the address cycle
 599          * completed. The MDI Command bit will clear when the
 600          * operation is complete
 601          */
 602         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 603                 usec_delay(10);
 604
 605                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 606                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 607                         break;
 608         }
 609
 610         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 611                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 612                 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n");
 613                 return IXGBE_ERR_PHY;
 614         }
 615
 616         /*
 617          * Read operation is complete.  Get the data
 618          * from MSRWD
 619          */
 620         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 621         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 622         *phy_data = (u16)(data);
 623
 624         return IXGBE_SUCCESS;
 625 }
 626
 627 /**
 628  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 629  *  using the SWFW lock - this function is needed in most cases
 630  *  @hw: pointer to hardware structure
 631  *  @reg_addr: 32 bit address of PHY register to read
 632  *  @device_type: 5 bit device type
 633  *  @phy_data: Pointer to read data from PHY register
 634  **/
 635 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 636                                u32 device_type, u16 *phy_data)
 637 {
 638         s32 status;
 639         u32 gssr = hw->phy.phy_semaphore_mask;
 640
 641         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 642
 643         if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
 644                 return IXGBE_ERR_SWFW_SYNC;
 645
 646         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
 647
 648         hw->mac.ops.release_swfw_sync(hw, gssr);
 649
 650         return status;
 651 }
 652
 653 /**
 654  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 655  *  without SWFW lock
 656  *  @hw: pointer to hardware structure
 657  *  @reg_addr: 32 bit PHY register to write
 658  *  @device_type: 5 bit device type
 659  *  @phy_data: Data to write to the PHY register
 660  **/
 661 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 662                                 u32 device_type, u16 phy_data)
 663 {
 664         u32 i, command;
 665
 666         /* Put the data in the MDI single read and write data register*/
 667         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 668
 669         /* Setup and write the address cycle command */
 670         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 671                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 672                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 673                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 674
 675         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 676
 677         /*
 678          * Check every 10 usec to see if the address cycle completed.
 679          * The MDI Command bit will clear when the operation is
 680          * complete
 681          */
 682         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 683                 usec_delay(10);
 684
 685                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 686                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 687                         break;
 688         }
 689
 690         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 691                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 692                 return IXGBE_ERR_PHY;
 693         }
 694
 695         /*
 696          * Address cycle complete, setup and write the write
 697          * command
 698          */
 699         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 700                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 701                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 702                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 703
 704         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 705
 706         /*
 707          * Check every 10 usec to see if the address cycle
 708          * completed. The MDI Command bit will clear when the
 709          * operation is complete
 710          */
 711         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 712                 usec_delay(10);
 713
 714                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 715                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 716                         break;
 717         }
 718
 719         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 720                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 721                 return IXGBE_ERR_PHY;
 722         }
 723
 724         return IXGBE_SUCCESS;
 725 }
 726
 727 /**
 728  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 729  *  using SWFW lock- this function is needed in most cases
 730  *  @hw: pointer to hardware structure
 731  *  @reg_addr: 32 bit PHY register to write
 732  *  @device_type: 5 bit device type
 733  *  @phy_data: Data to write to the PHY register
 734  **/
 735 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 736                                 u32 device_type, u16 phy_data)
 737 {
 738         s32 status;
 739         u32 gssr = hw->phy.phy_semaphore_mask;
 740
 741         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 742
 743         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 744                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
 745                                                  phy_data);
 746                 hw->mac.ops.release_swfw_sync(hw, gssr);
 747         } else {
 748                 status = IXGBE_ERR_SWFW_SYNC;
 749         }
 750
 751         return status;
 752 }
 753
 754 /**
 755  *  ixgbe_setup_phy_link_generic - Set and restart auto-neg
 756  *  @hw: pointer to hardware structure
 757  *
 758  *  Restart auto-negotiation and PHY and waits for completion.
 759  **/
 760 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 761 {
 762         s32 status = IXGBE_SUCCESS;
 763         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 764         bool autoneg = false;
 765         ixgbe_link_speed speed;
 766
 767         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 768
 769         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 770
 771         /* Set or unset auto-negotiation 10G advertisement */
 772         hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 773                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 774                              &autoneg_reg);
 775
 776         autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 777         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
 778             (speed & IXGBE_LINK_SPEED_10GB_FULL))
 779                 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 780
 781         hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 782                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 783                               autoneg_reg);
 784
 785         hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 786                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 787                              &autoneg_reg);
 788
 789         if (hw->mac.type == ixgbe_mac_X550) {
 790                 /* Set or unset auto-negotiation 5G advertisement */
 791                 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
 792                 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
 793                     (speed & IXGBE_LINK_SPEED_5GB_FULL))
 794                         autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
 795
 796                 /* Set or unset auto-negotiation 2.5G advertisement */
 797                 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
 798                 if ((hw->phy.autoneg_advertised &
 799                      IXGBE_LINK_SPEED_2_5GB_FULL) &&
 800                     (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
 801                         autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
 802         }
 803
 804         /* Set or unset auto-negotiation 1G advertisement */
 805         autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 806         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
 807             (speed & IXGBE_LINK_SPEED_1GB_FULL))
 808                 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 809
 810         hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 811                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 812                               autoneg_reg);
 813
 814         /* Set or unset auto-negotiation 100M advertisement */
 815         hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 816                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 817                              &autoneg_reg);
 818
 819         autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 820                          IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 821         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
 822             (speed & IXGBE_LINK_SPEED_100_FULL))
 823                 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 824
 825         hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 826                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 827                               autoneg_reg);
 828
 829         /* Blocked by MNG FW so don't reset PHY */
 830         if (ixgbe_check_reset_blocked(hw))
 831                 return status;
 832
 833         /* Restart PHY auto-negotiation. */
 834         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 835                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 836
 837         autoneg_reg |= IXGBE_MII_RESTART;
 838
 839         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 840                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 841
 842         return status;
 843 }
 844
 845 /**
 846  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 847  *  @hw: pointer to hardware structure
 848  *  @speed: new link speed
 849  *  @autoneg_wait_to_complete: unused
 850  **/
 851 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 852                                        ixgbe_link_speed speed,
 853                                        bool autoneg_wait_to_complete)
 854 {
 855         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 856
 857         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 858
 859         /*
 860          * Clear autoneg_advertised and set new values based on input link
 861          * speed.
 862          */
 863         hw->phy.autoneg_advertised = 0;
 864
 865         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 866                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 867
 868         if (speed & IXGBE_LINK_SPEED_5GB_FULL)
 869                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
 870
 871         if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
 872                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
 873
 874         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 875                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 876
 877         if (speed & IXGBE_LINK_SPEED_100_FULL)
 878                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 879
 880         if (speed & IXGBE_LINK_SPEED_10_FULL)
 881                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
 882
 883         /* Setup link based on the new speed settings */
 884         ixgbe_setup_phy_link(hw);
 885
 886         return IXGBE_SUCCESS;
 887 }
 888
 889 /**
 890  * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
 891  * @hw: pointer to hardware structure
 892  *
 893  * Determines the supported link capabilities by reading the PHY auto
 894  * negotiation register.
 895  **/
 896 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
 897 {
 898         s32 status;
 899         u16 speed_ability;
 900
 901         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 902                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 903                                       &speed_ability);
 904         if (status)
 905                 return status;
 906
 907         if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 908                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
 909         if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 910                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
 911         if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 912                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
 913
 914         switch (hw->mac.type) {
 915         case ixgbe_mac_X550:
 916                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
 917                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
 918                 break;
 919         case ixgbe_mac_X550EM_x:
 920         case ixgbe_mac_X550EM_a:
 921                 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
 922                 break;
 923         default:
 924                 break;
 925         }
 926
 927         return status;
 928 }
 929
 930 /**
 931  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 932  *  @hw: pointer to hardware structure
 933  *  @speed: pointer to link speed
 934  *  @autoneg: boolean auto-negotiation value
 935  **/
 936 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 937                                                ixgbe_link_speed *speed,
 938                                                bool *autoneg)
 939 {
 940         s32 status = IXGBE_SUCCESS;
 941
 942         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 943
 944         *autoneg = true;
 945         if (!hw->phy.speeds_supported)
 946                 status = ixgbe_get_copper_speeds_supported(hw);
 947
 948         *speed = hw->phy.speeds_supported;
 949         return status;
 950 }
 951
 952 /**
 953  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 954  *  @hw: pointer to hardware structure
 955  *  @speed: current link speed
 956  *  @link_up: true is link is up, false otherwise
 957  *
 958  *  Reads the VS1 register to determine if link is up and the current speed for
 959  *  the PHY.
 960  **/
 961 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 962                              bool *link_up)
 963 {
 964         s32 status = IXGBE_SUCCESS;
 965         u32 time_out;
 966         u32 max_time_out = 10;
 967         u16 phy_link = 0;
 968         u16 phy_speed = 0;
 969         u16 phy_data = 0;
 970
 971         DEBUGFUNC("ixgbe_check_phy_link_tnx");
 972
 973         /* Initialize speed and link to default case */
 974         *link_up = false;
 975         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 976
 977         /*
 978          * Check current speed and link status of the PHY register.
 979          * This is a vendor specific register and may have to
 980          * be changed for other copper PHYs.
 981          */
 982         for (time_out = 0; time_out < max_time_out; time_out++) {
 983                 usec_delay(10);
 984                 status = hw->phy.ops.read_reg(hw,
 985                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
 986                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 987                                         &phy_data);
 988                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 989                 phy_speed = phy_data &
 990                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 991                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 992                         *link_up = true;
 993                         if (phy_speed ==
 994                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 995                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 996                         break;
 997                 }
 998         }
 999
1000         return status;
1001 }
1002
1003 /**
1004  *      ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1005  *      @hw: pointer to hardware structure
1006  *
1007  *      Restart auto-negotiation and PHY and waits for completion.
1008  **/
1009 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1010 {
1011         s32 status = IXGBE_SUCCESS;
1012         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1013         bool autoneg = false;
1014         ixgbe_link_speed speed;
1015
1016         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1017
1018         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1019
1020         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1021                 /* Set or unset auto-negotiation 10G advertisement */
1022                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1023                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1024                                      &autoneg_reg);
1025
1026                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1027                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1028                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1029
1030                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1031                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1032                                       autoneg_reg);
1033         }
1034
1035         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1036                 /* Set or unset auto-negotiation 1G advertisement */
1037                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1038                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1039                                      &autoneg_reg);
1040
1041                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1042                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1043                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1044
1045                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1046                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1047                                       autoneg_reg);
1048         }
1049
1050         if (speed & IXGBE_LINK_SPEED_100_FULL) {
1051                 /* Set or unset auto-negotiation 100M advertisement */
1052                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1053                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1054                                      &autoneg_reg);
1055
1056                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1057                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1058                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1059
1060                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1061                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1062                                       autoneg_reg);
1063         }
1064
1065         /* Blocked by MNG FW so don't reset PHY */
1066         if (ixgbe_check_reset_blocked(hw))
1067                 return status;
1068
1069         /* Restart PHY auto-negotiation. */
1070         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1071                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1072
1073         autoneg_reg |= IXGBE_MII_RESTART;
1074
1075         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1076                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1077
1078         return status;
1079 }
1080
1081 /**
1082  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1083  *  @hw: pointer to hardware structure
1084  *  @firmware_version: pointer to the PHY Firmware Version
1085  **/
1086 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1087                                        u16 *firmware_version)
1088 {
1089         s32 status;
1090
1091         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1092
1093         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1094                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1095                                       firmware_version);
1096
1097         return status;
1098 }
1099
1100 /**
1101  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1102  *  @hw: pointer to hardware structure
1103  *  @firmware_version: pointer to the PHY Firmware Version
1104  **/
1105 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1106                                            u16 *firmware_version)
1107 {
1108         s32 status;
1109
1110         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1111
1112         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1113                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1114                                       firmware_version);
1115
1116         return status;
1117 }
1118
1119 /**
1120  *  ixgbe_reset_phy_nl - Performs a PHY reset
1121  *  @hw: pointer to hardware structure
1122  **/
1123 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1124 {
1125         u16 phy_offset, control, eword, edata, block_crc;
1126         bool end_data = false;
1127         u16 list_offset, data_offset;
1128         u16 phy_data = 0;
1129         s32 ret_val = IXGBE_SUCCESS;
1130         u32 i;
1131
1132         DEBUGFUNC("ixgbe_reset_phy_nl");
1133
1134         /* Blocked by MNG FW so bail */
1135         if (ixgbe_check_reset_blocked(hw))
1136                 goto out;
1137
1138         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1139                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1140
1141         /* reset the PHY and poll for completion */
1142         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1143                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
1144                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1145
1146         for (i = 0; i < 100; i++) {
1147                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1148                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1149                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1150                         break;
1151                 msec_delay(10);
1152         }
1153
1154         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1155                 DEBUGOUT("PHY reset did not complete.\n");
1156                 ret_val = IXGBE_ERR_PHY;
1157                 goto out;
1158         }
1159
1160         /* Get init offsets */
1161         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1162                                                       &data_offset);
1163         if (ret_val != IXGBE_SUCCESS)
1164                 goto out;
1165
1166         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1167         data_offset++;
1168         while (!end_data) {
1169                 /*
1170                  * Read control word from PHY init contents offset
1171                  */
1172                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1173                 if (ret_val)
1174                         goto err_eeprom;
1175                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1176                            IXGBE_CONTROL_SHIFT_NL;
1177                 edata = eword & IXGBE_DATA_MASK_NL;
1178                 switch (control) {
1179                 case IXGBE_DELAY_NL:
1180                         data_offset++;
1181                         DEBUGOUT1("DELAY: %d MS\n", edata);
1182                         msec_delay(edata);
1183                         break;
1184                 case IXGBE_DATA_NL:
1185                         DEBUGOUT("DATA:\n");
1186                         data_offset++;
1187                         ret_val = hw->eeprom.ops.read(hw, data_offset,
1188                                                       &phy_offset);
1189                         if (ret_val)
1190                                 goto err_eeprom;
1191                         data_offset++;
1192                         for (i = 0; i < edata; i++) {
1193                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
1194                                                               &eword);
1195                                 if (ret_val)
1196                                         goto err_eeprom;
1197                                 hw->phy.ops.write_reg(hw, phy_offset,
1198                                                       IXGBE_TWINAX_DEV, eword);
1199                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1200                                           phy_offset);
1201                                 data_offset++;
1202                                 phy_offset++;
1203                         }
1204                         break;
1205                 case IXGBE_CONTROL_NL:
1206                         data_offset++;
1207                         DEBUGOUT("CONTROL:\n");
1208                         if (edata == IXGBE_CONTROL_EOL_NL) {
1209                                 DEBUGOUT("EOL\n");
1210                                 end_data = true;
1211                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
1212                                 DEBUGOUT("SOL\n");
1213                         } else {
1214                                 DEBUGOUT("Bad control value\n");
1215                                 ret_val = IXGBE_ERR_PHY;
1216                                 goto out;
1217                         }
1218                         break;
1219                 default:
1220                         DEBUGOUT("Bad control type\n");
1221                         ret_val = IXGBE_ERR_PHY;
1222                         goto out;
1223                 }
1224         }
1225
1226 out:
1227         return ret_val;
1228
1229 err_eeprom:
1230         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1231                       "eeprom read at offset %d failed", data_offset);
1232         return IXGBE_ERR_PHY;
1233 }
1234
1235 /**
1236  *  ixgbe_identify_module_generic - Identifies module type
1237  *  @hw: pointer to hardware structure
1238  *
1239  *  Determines HW type and calls appropriate function.
1240  **/
1241 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1242 {
1243         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1244
1245         DEBUGFUNC("ixgbe_identify_module_generic");
1246
1247         switch (hw->mac.ops.get_media_type(hw)) {
1248         case ixgbe_media_type_fiber:
1249                 status = ixgbe_identify_sfp_module_generic(hw);
1250                 break;
1251
1252         case ixgbe_media_type_fiber_qsfp:
1253                 status = ixgbe_identify_qsfp_module_generic(hw);
1254                 break;
1255
1256         default:
1257                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1258                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1259                 break;
1260         }
1261
1262         return status;
1263 }
1264
1265 /**
1266  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1267  *  @hw: pointer to hardware structure
1268  *
1269  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1270  **/
1271 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1272 {
1273         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1274         u32 vendor_oui = 0;
1275         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1276         u8 identifier = 0;
1277         u8 comp_codes_1g = 0;
1278         u8 comp_codes_10g = 0;
1279         u8 oui_bytes[3] = {0, 0, 0};
1280         u8 cable_tech = 0;
1281         u8 cable_spec = 0;
1282         u16 enforce_sfp = 0;
1283
1284         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1285
1286         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1287                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1288                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1289                 goto out;
1290         }
1291
1292         /* LAN ID is needed for I2C access */
1293         hw->mac.ops.set_lan_id(hw);
1294
1295         status = hw->phy.ops.read_i2c_eeprom(hw,
1296                                              IXGBE_SFF_IDENTIFIER,
1297                                              &identifier);
1298
1299         if (status != IXGBE_SUCCESS)
1300                 goto err_read_i2c_eeprom;
1301
1302         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1303                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1304                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1305         } else {
1306                 status = hw->phy.ops.read_i2c_eeprom(hw,
1307                                                      IXGBE_SFF_1GBE_COMP_CODES,
1308                                                      &comp_codes_1g);
1309
1310                 if (status != IXGBE_SUCCESS)
1311                         goto err_read_i2c_eeprom;
1312
1313                 status = hw->phy.ops.read_i2c_eeprom(hw,
1314                                                      IXGBE_SFF_10GBE_COMP_CODES,
1315                                                      &comp_codes_10g);
1316
1317                 if (status != IXGBE_SUCCESS)
1318                         goto err_read_i2c_eeprom;
1319                 status = hw->phy.ops.read_i2c_eeprom(hw,
1320                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1321                                                      &cable_tech);
1322
1323                 if (status != IXGBE_SUCCESS)
1324                         goto err_read_i2c_eeprom;
1325
1326                  /* ID Module
1327                   * =========
1328                   * 0   SFP_DA_CU
1329                   * 1   SFP_SR
1330                   * 2   SFP_LR
1331                   * 3   SFP_DA_CORE0 - 82599-specific
1332                   * 4   SFP_DA_CORE1 - 82599-specific
1333                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1334                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1335                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1336                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1337                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1338                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1339                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1340                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1341                   */
1342                 if (hw->mac.type == ixgbe_mac_82598EB) {
1343                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1344                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1345                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1346                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1347                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1348                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1349                         else
1350                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1351                 } else {
1352                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1353                                 if (hw->bus.lan_id == 0)
1354                                         hw->phy.sfp_type =
1355                                                      ixgbe_sfp_type_da_cu_core0;
1356                                 else
1357                                         hw->phy.sfp_type =
1358                                                      ixgbe_sfp_type_da_cu_core1;
1359                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1360                                 hw->phy.ops.read_i2c_eeprom(
1361                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1362                                                 &cable_spec);
1363                                 if (cable_spec &
1364                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1365                                         if (hw->bus.lan_id == 0)
1366                                                 hw->phy.sfp_type =
1367                                                 ixgbe_sfp_type_da_act_lmt_core0;
1368                                         else
1369                                                 hw->phy.sfp_type =
1370                                                 ixgbe_sfp_type_da_act_lmt_core1;
1371                                 } else {
1372                                         hw->phy.sfp_type =
1373                                                         ixgbe_sfp_type_unknown;
1374                                 }
1375                         } else if (comp_codes_10g &
1376                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1377                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1378                                 if (hw->bus.lan_id == 0)
1379                                         hw->phy.sfp_type =
1380                                                       ixgbe_sfp_type_srlr_core0;
1381                                 else
1382                                         hw->phy.sfp_type =
1383                                                       ixgbe_sfp_type_srlr_core1;
1384                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1385                                 if (hw->bus.lan_id == 0)
1386                                         hw->phy.sfp_type =
1387                                                 ixgbe_sfp_type_1g_cu_core0;
1388                                 else
1389                                         hw->phy.sfp_type =
1390                                                 ixgbe_sfp_type_1g_cu_core1;
1391                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1392                                 if (hw->bus.lan_id == 0)
1393                                         hw->phy.sfp_type =
1394                                                 ixgbe_sfp_type_1g_sx_core0;
1395                                 else
1396                                         hw->phy.sfp_type =
1397                                                 ixgbe_sfp_type_1g_sx_core1;
1398                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1399                                 if (hw->bus.lan_id == 0)
1400                                         hw->phy.sfp_type =
1401                                                 ixgbe_sfp_type_1g_lx_core0;
1402                                 else
1403                                         hw->phy.sfp_type =
1404                                                 ixgbe_sfp_type_1g_lx_core1;
1405                         } else {
1406                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1407                         }
1408                 }
1409
1410                 if (hw->phy.sfp_type != stored_sfp_type)
1411                         hw->phy.sfp_setup_needed = true;
1412
1413                 /* Determine if the SFP+ PHY is dual speed or not. */
1414                 hw->phy.multispeed_fiber = false;
1415                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1416                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1417                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1418                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1419                         hw->phy.multispeed_fiber = true;
1420
1421                 /* Determine PHY vendor */
1422                 if (hw->phy.type != ixgbe_phy_nl) {
1423                         hw->phy.id = identifier;
1424                         status = hw->phy.ops.read_i2c_eeprom(hw,
1425                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1426                                                     &oui_bytes[0]);
1427
1428                         if (status != IXGBE_SUCCESS)
1429                                 goto err_read_i2c_eeprom;
1430
1431                         status = hw->phy.ops.read_i2c_eeprom(hw,
1432                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1433                                                     &oui_bytes[1]);
1434
1435                         if (status != IXGBE_SUCCESS)
1436                                 goto err_read_i2c_eeprom;
1437
1438                         status = hw->phy.ops.read_i2c_eeprom(hw,
1439                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1440                                                     &oui_bytes[2]);
1441
1442                         if (status != IXGBE_SUCCESS)
1443                                 goto err_read_i2c_eeprom;
1444
1445                         vendor_oui =
1446                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1447                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1448                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1449
1450                         switch (vendor_oui) {
1451                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1452                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1453                                         hw->phy.type =
1454                                                     ixgbe_phy_sfp_passive_tyco;
1455                                 break;
1456                         case IXGBE_SFF_VENDOR_OUI_FTL:
1457                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1458                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1459                                 else
1460                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1461                                 break;
1462                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1463                                 hw->phy.type = ixgbe_phy_sfp_avago;
1464                                 break;
1465                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1466                                 hw->phy.type = ixgbe_phy_sfp_intel;
1467                                 break;
1468                         default:
1469                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1470                                         hw->phy.type =
1471                                                  ixgbe_phy_sfp_passive_unknown;
1472                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1473                                         hw->phy.type =
1474                                                 ixgbe_phy_sfp_active_unknown;
1475                                 else
1476                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1477                                 break;
1478                         }
1479                 }
1480
1481                 /* Allow any DA cable vendor */
1482                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1483                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1484                         status = IXGBE_SUCCESS;
1485                         goto out;
1486                 }
1487
1488                 /* Verify supported 1G SFP modules */
1489                 if (comp_codes_10g == 0 &&
1490                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1491                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1492                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1493                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1494                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1495                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1496                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1497                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1498                         goto out;
1499                 }
1500
1501                 /* Anything else 82598-based is supported */
1502                 if (hw->mac.type == ixgbe_mac_82598EB) {
1503                         status = IXGBE_SUCCESS;
1504                         goto out;
1505                 }
1506
1507                 ixgbe_get_device_caps(hw, &enforce_sfp);
1508                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1509                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1510                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1511                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1512                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1513                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1514                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1515                         /* Make sure we're a supported PHY type */
1516                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1517                                 status = IXGBE_SUCCESS;
1518                         } else {
1519                                 if (hw->allow_unsupported_sfp == true) {
1520                                         EWARN(hw,
1521                                                 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. "
1522                                                 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1523                                                 "Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1524                                         status = IXGBE_SUCCESS;
1525                                 } else {
1526                                         DEBUGOUT("SFP+ module not supported\n");
1527                                         hw->phy.type =
1528                                                 ixgbe_phy_sfp_unsupported;
1529                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1530                                 }
1531                         }
1532                 } else {
1533                         status = IXGBE_SUCCESS;
1534                 }
1535         }
1536
1537 out:
1538         return status;
1539
1540 err_read_i2c_eeprom:
1541         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1542         if (hw->phy.type != ixgbe_phy_nl) {
1543                 hw->phy.id = 0;
1544                 hw->phy.type = ixgbe_phy_unknown;
1545         }
1546         return IXGBE_ERR_SFP_NOT_PRESENT;
1547 }
1548
1549 /**
1550  *  ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1551  *  @hw: pointer to hardware structure
1552  *
1553  *  Determines physical layer capabilities of the current SFP.
1554  */
1555 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1556 {
1557         u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1558         u8 comp_codes_10g = 0;
1559         u8 comp_codes_1g = 0;
1560
1561         DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1562
1563         hw->phy.ops.identify_sfp(hw);
1564         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1565                 return physical_layer;
1566
1567         switch (hw->phy.type) {
1568         case ixgbe_phy_sfp_passive_tyco:
1569         case ixgbe_phy_sfp_passive_unknown:
1570         case ixgbe_phy_qsfp_passive_unknown:
1571                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1572                 break;
1573         case ixgbe_phy_sfp_ftl_active:
1574         case ixgbe_phy_sfp_active_unknown:
1575         case ixgbe_phy_qsfp_active_unknown:
1576                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1577                 break;
1578         case ixgbe_phy_sfp_avago:
1579         case ixgbe_phy_sfp_ftl:
1580         case ixgbe_phy_sfp_intel:
1581         case ixgbe_phy_sfp_unknown:
1582                 hw->phy.ops.read_i2c_eeprom(hw,
1583                       IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1584                 hw->phy.ops.read_i2c_eeprom(hw,
1585                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1586                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1587                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1588                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1589                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1590                 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1591                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1592                 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1593                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1594                 break;
1595         case ixgbe_phy_qsfp_intel:
1596         case ixgbe_phy_qsfp_unknown:
1597                 hw->phy.ops.read_i2c_eeprom(hw,
1598                       IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1599                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1600                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1601                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1602                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1603                 break;
1604         default:
1605                 break;
1606         }
1607
1608         return physical_layer;
1609 }
1610
1611 /**
1612  *  ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1613  *  @hw: pointer to hardware structure
1614  *
1615  *  Searches for and identifies the QSFP module and assigns appropriate PHY type
1616  **/
1617 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1618 {
1619         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1620         u32 vendor_oui = 0;
1621         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1622         u8 identifier = 0;
1623         u8 comp_codes_1g = 0;
1624         u8 comp_codes_10g = 0;
1625         u8 oui_bytes[3] = {0, 0, 0};
1626         u16 enforce_sfp = 0;
1627         u8 connector = 0;
1628         u8 cable_length = 0;
1629         u8 device_tech = 0;
1630         bool active_cable = false;
1631
1632         DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1633
1634         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1635                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1636                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1637                 goto out;
1638         }
1639
1640         /* LAN ID is needed for I2C access */
1641         hw->mac.ops.set_lan_id(hw);
1642
1643         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1644                                              &identifier);
1645
1646         if (status != IXGBE_SUCCESS)
1647                 goto err_read_i2c_eeprom;
1648
1649         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1650                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1651                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1652                 goto out;
1653         }
1654
1655         hw->phy.id = identifier;
1656
1657         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1658                                              &comp_codes_10g);
1659
1660         if (status != IXGBE_SUCCESS)
1661                 goto err_read_i2c_eeprom;
1662
1663         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1664                                              &comp_codes_1g);
1665
1666         if (status != IXGBE_SUCCESS)
1667                 goto err_read_i2c_eeprom;
1668
1669         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1670                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1671                 if (hw->bus.lan_id == 0)
1672                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1673                 else
1674                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1675         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1676                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1677                 if (hw->bus.lan_id == 0)
1678                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1679                 else
1680                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1681         } else {
1682                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1683                         active_cable = true;
1684
1685                 if (!active_cable) {
1686                         /* check for active DA cables that pre-date
1687                          * SFF-8436 v3.6 */
1688                         hw->phy.ops.read_i2c_eeprom(hw,
1689                                         IXGBE_SFF_QSFP_CONNECTOR,
1690                                         &connector);
1691
1692                         hw->phy.ops.read_i2c_eeprom(hw,
1693                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1694                                         &cable_length);
1695
1696                         hw->phy.ops.read_i2c_eeprom(hw,
1697                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1698                                         &device_tech);
1699
1700                         if ((connector ==
1701                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1702                             (cable_length > 0) &&
1703                             ((device_tech >> 4) ==
1704                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1705                                 active_cable = true;
1706                 }
1707
1708                 if (active_cable) {
1709                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1710                         if (hw->bus.lan_id == 0)
1711                                 hw->phy.sfp_type =
1712                                                 ixgbe_sfp_type_da_act_lmt_core0;
1713                         else
1714                                 hw->phy.sfp_type =
1715                                                 ixgbe_sfp_type_da_act_lmt_core1;
1716                 } else {
1717                         /* unsupported module type */
1718                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1719                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1720                         goto out;
1721                 }
1722         }
1723
1724         if (hw->phy.sfp_type != stored_sfp_type)
1725                 hw->phy.sfp_setup_needed = true;
1726
1727         /* Determine if the QSFP+ PHY is dual speed or not. */
1728         hw->phy.multispeed_fiber = false;
1729         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1730            (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1731            ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1732            (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1733                 hw->phy.multispeed_fiber = true;
1734
1735         /* Determine PHY vendor for optical modules */
1736         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1737                               IXGBE_SFF_10GBASELR_CAPABLE))  {
1738                 status = hw->phy.ops.read_i2c_eeprom(hw,
1739                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1740                                             &oui_bytes[0]);
1741
1742                 if (status != IXGBE_SUCCESS)
1743                         goto err_read_i2c_eeprom;
1744
1745                 status = hw->phy.ops.read_i2c_eeprom(hw,
1746                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1747                                             &oui_bytes[1]);
1748
1749                 if (status != IXGBE_SUCCESS)
1750                         goto err_read_i2c_eeprom;
1751
1752                 status = hw->phy.ops.read_i2c_eeprom(hw,
1753                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1754                                             &oui_bytes[2]);
1755
1756                 if (status != IXGBE_SUCCESS)
1757                         goto err_read_i2c_eeprom;
1758
1759                 vendor_oui =
1760                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1761                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1762                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1763
1764                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1765                         hw->phy.type = ixgbe_phy_qsfp_intel;
1766                 else
1767                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1768
1769                 ixgbe_get_device_caps(hw, &enforce_sfp);
1770                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1771                         /* Make sure we're a supported PHY type */
1772                         if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1773                                 status = IXGBE_SUCCESS;
1774                         } else {
1775                                 if (hw->allow_unsupported_sfp == true) {
1776                                         EWARN(hw,
1777                                                 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. "
1778                                                 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1779                                                 "Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1780                                         status = IXGBE_SUCCESS;
1781                                 } else {
1782                                         DEBUGOUT("QSFP module not supported\n");
1783                                         hw->phy.type =
1784                                                 ixgbe_phy_sfp_unsupported;
1785                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1786                                 }
1787                         }
1788                 } else {
1789                         status = IXGBE_SUCCESS;
1790                 }
1791         }
1792
1793 out:
1794         return status;
1795
1796 err_read_i2c_eeprom:
1797         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1798         hw->phy.id = 0;
1799         hw->phy.type = ixgbe_phy_unknown;
1800
1801         return IXGBE_ERR_SFP_NOT_PRESENT;
1802 }
1803
1804 /**
1805  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1806  *  @hw: pointer to hardware structure
1807  *  @list_offset: offset to the SFP ID list
1808  *  @data_offset: offset to the SFP data block
1809  *
1810  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1811  *  so it returns the offsets to the phy init sequence block.
1812  **/
1813 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1814                                         u16 *list_offset,
1815                                         u16 *data_offset)
1816 {
1817         u16 sfp_id;
1818         u16 sfp_type = hw->phy.sfp_type;
1819
1820         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1821
1822         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1823                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1824
1825         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1826                 return IXGBE_ERR_SFP_NOT_PRESENT;
1827
1828         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1829             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1830                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1831
1832         /*
1833          * Limiting active cables and 1G Phys must be initialized as
1834          * SR modules
1835          */
1836         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1837             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1838             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1839             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1840                 sfp_type = ixgbe_sfp_type_srlr_core0;
1841         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1842                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1843                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1844                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1845                 sfp_type = ixgbe_sfp_type_srlr_core1;
1846
1847         /* Read offset to PHY init contents */
1848         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1849                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1850                               "eeprom read at offset %d failed",
1851                               IXGBE_PHY_INIT_OFFSET_NL);
1852                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1853         }
1854
1855         if ((!*list_offset) || (*list_offset == 0xFFFF))
1856                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1857
1858         /* Shift offset to first ID word */
1859         (*list_offset)++;
1860
1861         /*
1862          * Find the matching SFP ID in the EEPROM
1863          * and program the init sequence
1864          */
1865         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1866                 goto err_phy;
1867
1868         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1869                 if (sfp_id == sfp_type) {
1870                         (*list_offset)++;
1871                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1872                                 goto err_phy;
1873                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1874                                 DEBUGOUT("SFP+ module not supported\n");
1875                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1876                         } else {
1877                                 break;
1878                         }
1879                 } else {
1880                         (*list_offset) += 2;
1881                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1882                                 goto err_phy;
1883                 }
1884         }
1885
1886         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1887                 DEBUGOUT("No matching SFP+ module found\n");
1888                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1889         }
1890
1891         return IXGBE_SUCCESS;
1892
1893 err_phy:
1894         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1895                       "eeprom read at offset %d failed", *list_offset);
1896         return IXGBE_ERR_PHY;
1897 }
1898
1899 /**
1900  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1901  *  @hw: pointer to hardware structure
1902  *  @byte_offset: EEPROM byte offset to read
1903  *  @eeprom_data: value read
1904  *
1905  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1906  **/
1907 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1908                                   u8 *eeprom_data)
1909 {
1910         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1911
1912         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1913                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1914                                          eeprom_data);
1915 }
1916
1917 /**
1918  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1919  *  @hw: pointer to hardware structure
1920  *  @byte_offset: byte offset at address 0xA2
1921  *  @sff8472_data: value read
1922  *
1923  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1924  **/
1925 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1926                                           u8 *sff8472_data)
1927 {
1928         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1929                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1930                                          sff8472_data);
1931 }
1932
1933 /**
1934  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1935  *  @hw: pointer to hardware structure
1936  *  @byte_offset: EEPROM byte offset to write
1937  *  @eeprom_data: value to write
1938  *
1939  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1940  **/
1941 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1942                                    u8 eeprom_data)
1943 {
1944         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1945
1946         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1947                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1948                                           eeprom_data);
1949 }
1950
1951 /**
1952  * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1953  * @hw: pointer to hardware structure
1954  * @offset: eeprom offset to be read
1955  * @addr: I2C address to be read
1956  */
1957 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1958 {
1959         if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1960             offset == IXGBE_SFF_IDENTIFIER &&
1961             hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1962                 return true;
1963         return false;
1964 }
1965
1966 /**
1967  *  ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1968  *  @hw: pointer to hardware structure
1969  *  @byte_offset: byte offset to read
1970  *  @dev_addr: address to read from
1971  *  @data: value read
1972  *  @lock: true if to take and release semaphore
1973  *
1974  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1975  *  a specified device address.
1976  **/
1977 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1978                                            u8 dev_addr, u8 *data, bool lock)
1979 {
1980         s32 status;
1981         u32 max_retry = 10;
1982         u32 retry = 0;
1983         u32 swfw_mask = hw->phy.phy_semaphore_mask;
1984         bool nack = 1;
1985         *data = 0;
1986
1987         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1988
1989         if (hw->mac.type >= ixgbe_mac_X550)
1990                 max_retry = 3;
1991         if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
1992                 max_retry = IXGBE_SFP_DETECT_RETRIES;
1993
1994         do {
1995                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1996                         return IXGBE_ERR_SWFW_SYNC;
1997
1998                 ixgbe_i2c_start(hw);
1999
2000                 /* Device Address and write indication */
2001                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2002                 if (status != IXGBE_SUCCESS)
2003                         goto fail;
2004
2005                 status = ixgbe_get_i2c_ack(hw);
2006                 if (status != IXGBE_SUCCESS)
2007                         goto fail;
2008
2009                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2010                 if (status != IXGBE_SUCCESS)
2011                         goto fail;
2012
2013                 status = ixgbe_get_i2c_ack(hw);
2014                 if (status != IXGBE_SUCCESS)
2015                         goto fail;
2016
2017                 ixgbe_i2c_start(hw);
2018
2019                 /* Device Address and read indication */
2020                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2021                 if (status != IXGBE_SUCCESS)
2022                         goto fail;
2023
2024                 status = ixgbe_get_i2c_ack(hw);
2025                 if (status != IXGBE_SUCCESS)
2026                         goto fail;
2027
2028                 status = ixgbe_clock_in_i2c_byte(hw, data);
2029                 if (status != IXGBE_SUCCESS)
2030                         goto fail;
2031
2032                 status = ixgbe_clock_out_i2c_bit(hw, nack);
2033                 if (status != IXGBE_SUCCESS)
2034                         goto fail;
2035
2036                 ixgbe_i2c_stop(hw);
2037                 if (lock)
2038                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2039                 return IXGBE_SUCCESS;
2040
2041 fail:
2042                 ixgbe_i2c_bus_clear(hw);
2043                 if (lock) {
2044                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2045                         msec_delay(100);
2046                 }
2047                 retry++;
2048                 if (retry < max_retry)
2049                         DEBUGOUT("I2C byte read error - Retrying.\n");
2050                 else
2051                         DEBUGOUT("I2C byte read error.\n");
2052
2053         } while (retry < max_retry);
2054
2055         return status;
2056 }
2057
2058 /**
2059  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2060  *  @hw: pointer to hardware structure
2061  *  @byte_offset: byte offset to read
2062  *  @dev_addr: address to read from
2063  *  @data: value read
2064  *
2065  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2066  *  a specified device address.
2067  **/
2068 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2069                                 u8 dev_addr, u8 *data)
2070 {
2071         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2072                                                data, true);
2073 }
2074
2075 /**
2076  *  ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2077  *  @hw: pointer to hardware structure
2078  *  @byte_offset: byte offset to read
2079  *  @dev_addr: address to read from
2080  *  @data: value read
2081  *
2082  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2083  *  a specified device address.
2084  **/
2085 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2086                                          u8 dev_addr, u8 *data)
2087 {
2088         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2089                                                data, false);
2090 }
2091
2092 /**
2093  *  ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2094  *  @hw: pointer to hardware structure
2095  *  @byte_offset: byte offset to write
2096  *  @dev_addr: address to write to
2097  *  @data: value to write
2098  *  @lock: true if to take and release semaphore
2099  *
2100  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2101  *  a specified device address.
2102  **/
2103 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2104                                             u8 dev_addr, u8 data, bool lock)
2105 {
2106         s32 status;
2107         u32 max_retry = 1;
2108         u32 retry = 0;
2109         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2110
2111         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2112
2113         if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2114             IXGBE_SUCCESS)
2115                 return IXGBE_ERR_SWFW_SYNC;
2116
2117         do {
2118                 ixgbe_i2c_start(hw);
2119
2120                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2121                 if (status != IXGBE_SUCCESS)
2122                         goto fail;
2123
2124                 status = ixgbe_get_i2c_ack(hw);
2125                 if (status != IXGBE_SUCCESS)
2126                         goto fail;
2127
2128                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2129                 if (status != IXGBE_SUCCESS)
2130                         goto fail;
2131
2132                 status = ixgbe_get_i2c_ack(hw);
2133                 if (status != IXGBE_SUCCESS)
2134                         goto fail;
2135
2136                 status = ixgbe_clock_out_i2c_byte(hw, data);
2137                 if (status != IXGBE_SUCCESS)
2138                         goto fail;
2139
2140                 status = ixgbe_get_i2c_ack(hw);
2141                 if (status != IXGBE_SUCCESS)
2142                         goto fail;
2143
2144                 ixgbe_i2c_stop(hw);
2145                 if (lock)
2146                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2147                 return IXGBE_SUCCESS;
2148
2149 fail:
2150                 ixgbe_i2c_bus_clear(hw);
2151                 retry++;
2152                 if (retry < max_retry)
2153                         DEBUGOUT("I2C byte write error - Retrying.\n");
2154                 else
2155                         DEBUGOUT("I2C byte write error.\n");
2156         } while (retry < max_retry);
2157
2158         if (lock)
2159                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2160
2161         return status;
2162 }
2163
2164 /**
2165  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2166  *  @hw: pointer to hardware structure
2167  *  @byte_offset: byte offset to write
2168  *  @dev_addr: address to write to
2169  *  @data: value to write
2170  *
2171  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2172  *  a specified device address.
2173  **/
2174 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2175                                  u8 dev_addr, u8 data)
2176 {
2177         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2178                                                 data, true);
2179 }
2180
2181 /**
2182  *  ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2183  *  @hw: pointer to hardware structure
2184  *  @byte_offset: byte offset to write
2185  *  @dev_addr: address to write to
2186  *  @data: value to write
2187  *
2188  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2189  *  a specified device address.
2190  **/
2191 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2192                                           u8 dev_addr, u8 data)
2193 {
2194         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2195                                                 data, false);
2196 }
2197
2198 /**
2199  *  ixgbe_i2c_start - Sets I2C start condition
2200  *  @hw: pointer to hardware structure
2201  *
2202  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
2203  *  Set bit-bang mode on X550 hardware.
2204  **/
2205 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2206 {
2207         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2208
2209         DEBUGFUNC("ixgbe_i2c_start");
2210
2211         i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2212
2213         /* Start condition must begin with data and clock high */
2214         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2215         ixgbe_raise_i2c_clk(hw, &i2cctl);
2216
2217         /* Setup time for start condition (4.7us) */
2218         usec_delay(IXGBE_I2C_T_SU_STA);
2219
2220         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2221
2222         /* Hold time for start condition (4us) */
2223         usec_delay(IXGBE_I2C_T_HD_STA);
2224
2225         ixgbe_lower_i2c_clk(hw, &i2cctl);
2226
2227         /* Minimum low period of clock is 4.7 us */
2228         usec_delay(IXGBE_I2C_T_LOW);
2229
2230 }
2231
2232 /**
2233  *  ixgbe_i2c_stop - Sets I2C stop condition
2234  *  @hw: pointer to hardware structure
2235  *
2236  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
2237  *  Disables bit-bang mode and negates data output enable on X550
2238  *  hardware.
2239  **/
2240 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2241 {
2242         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2243         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2244         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2245         u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2246
2247         DEBUGFUNC("ixgbe_i2c_stop");
2248
2249         /* Stop condition must begin with data low and clock high */
2250         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2251         ixgbe_raise_i2c_clk(hw, &i2cctl);
2252
2253         /* Setup time for stop condition (4us) */
2254         usec_delay(IXGBE_I2C_T_SU_STO);
2255
2256         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2257
2258         /* bus free time between stop and start (4.7us)*/
2259         usec_delay(IXGBE_I2C_T_BUF);
2260
2261         if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2262                 i2cctl &= ~bb_en_bit;
2263                 i2cctl |= data_oe_bit | clk_oe_bit;
2264                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2265                 IXGBE_WRITE_FLUSH(hw);
2266         }
2267 }
2268
2269 /**
2270  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2271  *  @hw: pointer to hardware structure
2272  *  @data: data byte to clock in
2273  *
2274  *  Clocks in one byte data via I2C data/clock
2275  **/
2276 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2277 {
2278         s32 i;
2279         bool bit = 0;
2280
2281         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2282
2283         *data = 0;
2284         for (i = 7; i >= 0; i--) {
2285                 ixgbe_clock_in_i2c_bit(hw, &bit);
2286                 *data |= bit << i;
2287         }
2288
2289         return IXGBE_SUCCESS;
2290 }
2291
2292 /**
2293  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2294  *  @hw: pointer to hardware structure
2295  *  @data: data byte clocked out
2296  *
2297  *  Clocks out one byte data via I2C data/clock
2298  **/
2299 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2300 {
2301         s32 status = IXGBE_SUCCESS;
2302         s32 i;
2303         u32 i2cctl;
2304         bool bit;
2305
2306         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2307
2308         for (i = 7; i >= 0; i--) {
2309                 bit = (data >> i) & 0x1;
2310                 status = ixgbe_clock_out_i2c_bit(hw, bit);
2311
2312                 if (status != IXGBE_SUCCESS)
2313                         break;
2314         }
2315
2316         /* Release SDA line (set high) */
2317         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2318         i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2319         i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2320         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2321         IXGBE_WRITE_FLUSH(hw);
2322
2323         return status;
2324 }
2325
2326 /**
2327  *  ixgbe_get_i2c_ack - Polls for I2C ACK
2328  *  @hw: pointer to hardware structure
2329  *
2330  *  Clocks in/out one bit via I2C data/clock
2331  **/
2332 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2333 {
2334         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2335         s32 status = IXGBE_SUCCESS;
2336         u32 i = 0;
2337         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2338         u32 timeout = 10;
2339         bool ack = 1;
2340
2341         DEBUGFUNC("ixgbe_get_i2c_ack");
2342
2343         if (data_oe_bit) {
2344                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2345                 i2cctl |= data_oe_bit;
2346                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2347                 IXGBE_WRITE_FLUSH(hw);
2348         }
2349         ixgbe_raise_i2c_clk(hw, &i2cctl);
2350
2351         /* Minimum high period of clock is 4us */
2352         usec_delay(IXGBE_I2C_T_HIGH);
2353
2354         /* Poll for ACK.  Note that ACK in I2C spec is
2355          * transition from 1 to 0 */
2356         for (i = 0; i < timeout; i++) {
2357                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2358                 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2359
2360                 usec_delay(1);
2361                 if (!ack)
2362                         break;
2363         }
2364
2365         if (ack) {
2366                 DEBUGOUT("I2C ack was not received.\n");
2367                 status = IXGBE_ERR_I2C;
2368         }
2369
2370         ixgbe_lower_i2c_clk(hw, &i2cctl);
2371
2372         /* Minimum low period of clock is 4.7 us */
2373         usec_delay(IXGBE_I2C_T_LOW);
2374
2375         return status;
2376 }
2377
2378 /**
2379  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2380  *  @hw: pointer to hardware structure
2381  *  @data: read data value
2382  *
2383  *  Clocks in one bit via I2C data/clock
2384  **/
2385 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2386 {
2387         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2388         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2389
2390         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2391
2392         if (data_oe_bit) {
2393                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2394                 i2cctl |= data_oe_bit;
2395                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2396                 IXGBE_WRITE_FLUSH(hw);
2397         }
2398         ixgbe_raise_i2c_clk(hw, &i2cctl);
2399
2400         /* Minimum high period of clock is 4us */
2401         usec_delay(IXGBE_I2C_T_HIGH);
2402
2403         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2404         *data = ixgbe_get_i2c_data(hw, &i2cctl);
2405
2406         ixgbe_lower_i2c_clk(hw, &i2cctl);
2407
2408         /* Minimum low period of clock is 4.7 us */
2409         usec_delay(IXGBE_I2C_T_LOW);
2410
2411         return IXGBE_SUCCESS;
2412 }
2413
2414 /**
2415  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2416  *  @hw: pointer to hardware structure
2417  *  @data: data value to write
2418  *
2419  *  Clocks out one bit via I2C data/clock
2420  **/
2421 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2422 {
2423         s32 status;
2424         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2425
2426         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2427
2428         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2429         if (status == IXGBE_SUCCESS) {
2430                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2431
2432                 /* Minimum high period of clock is 4us */
2433                 usec_delay(IXGBE_I2C_T_HIGH);
2434
2435                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2436
2437                 /* Minimum low period of clock is 4.7 us.
2438                  * This also takes care of the data hold time.
2439                  */
2440                 usec_delay(IXGBE_I2C_T_LOW);
2441         } else {
2442                 status = IXGBE_ERR_I2C;
2443                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2444                              "I2C data was not set to %X\n", data);
2445         }
2446
2447         return status;
2448 }
2449
2450 /**
2451  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2452  *  @hw: pointer to hardware structure
2453  *  @i2cctl: Current value of I2CCTL register
2454  *
2455  *  Raises the I2C clock line '0'->'1'
2456  *  Negates the I2C clock output enable on X550 hardware.
2457  **/
2458 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2459 {
2460         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2461         u32 i = 0;
2462         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2463         u32 i2cctl_r = 0;
2464
2465         DEBUGFUNC("ixgbe_raise_i2c_clk");
2466
2467         if (clk_oe_bit) {
2468                 *i2cctl |= clk_oe_bit;
2469                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2470         }
2471
2472         for (i = 0; i < timeout; i++) {
2473                 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2474
2475                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2476                 IXGBE_WRITE_FLUSH(hw);
2477                 /* SCL rise time (1000ns) */
2478                 usec_delay(IXGBE_I2C_T_RISE);
2479
2480                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2481                 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2482                         break;
2483         }
2484 }
2485
2486 /**
2487  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2488  *  @hw: pointer to hardware structure
2489  *  @i2cctl: Current value of I2CCTL register
2490  *
2491  *  Lowers the I2C clock line '1'->'0'
2492  *  Asserts the I2C clock output enable on X550 hardware.
2493  **/
2494 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2495 {
2496         DEBUGFUNC("ixgbe_lower_i2c_clk");
2497
2498         *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2499         *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2500
2501         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2502         IXGBE_WRITE_FLUSH(hw);
2503
2504         /* SCL fall time (300ns) */
2505         usec_delay(IXGBE_I2C_T_FALL);
2506 }
2507
2508 /**
2509  *  ixgbe_set_i2c_data - Sets the I2C data bit
2510  *  @hw: pointer to hardware structure
2511  *  @i2cctl: Current value of I2CCTL register
2512  *  @data: I2C data value (0 or 1) to set
2513  *
2514  *  Sets the I2C data bit
2515  *  Asserts the I2C data output enable on X550 hardware.
2516  **/
2517 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2518 {
2519         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2520         s32 status = IXGBE_SUCCESS;
2521
2522         DEBUGFUNC("ixgbe_set_i2c_data");
2523
2524         if (data)
2525                 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2526         else
2527                 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2528         *i2cctl &= ~data_oe_bit;
2529
2530         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2531         IXGBE_WRITE_FLUSH(hw);
2532
2533         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2534         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2535
2536         if (!data)      /* Can't verify data in this case */
2537                 return IXGBE_SUCCESS;
2538         if (data_oe_bit) {
2539                 *i2cctl |= data_oe_bit;
2540                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2541                 IXGBE_WRITE_FLUSH(hw);
2542         }
2543
2544         /* Verify data was set correctly */
2545         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2546         if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2547                 status = IXGBE_ERR_I2C;
2548                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2549                              "Error - I2C data was not set to %X.\n",
2550                              data);
2551         }
2552
2553         return status;
2554 }
2555
2556 /**
2557  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2558  *  @hw: pointer to hardware structure
2559  *  @i2cctl: Current value of I2CCTL register
2560  *
2561  *  Returns the I2C data bit value
2562  *  Negates the I2C data output enable on X550 hardware.
2563  **/
2564 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2565 {
2566         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2567         bool data;
2568
2569         DEBUGFUNC("ixgbe_get_i2c_data");
2570
2571         if (data_oe_bit) {
2572                 *i2cctl |= data_oe_bit;
2573                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2574                 IXGBE_WRITE_FLUSH(hw);
2575                 usec_delay(IXGBE_I2C_T_FALL);
2576         }
2577
2578         if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2579                 data = 1;
2580         else
2581                 data = 0;
2582
2583         return data;
2584 }
2585
2586 /**
2587  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2588  *  @hw: pointer to hardware structure
2589  *
2590  *  Clears the I2C bus by sending nine clock pulses.
2591  *  Used when data line is stuck low.
2592  **/
2593 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2594 {
2595         u32 i2cctl;
2596         u32 i;
2597
2598         DEBUGFUNC("ixgbe_i2c_bus_clear");
2599
2600         ixgbe_i2c_start(hw);
2601         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2602
2603         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2604
2605         for (i = 0; i < 9; i++) {
2606                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2607
2608                 /* Min high period of clock is 4us */
2609                 usec_delay(IXGBE_I2C_T_HIGH);
2610
2611                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2612
2613                 /* Min low period of clock is 4.7us*/
2614                 usec_delay(IXGBE_I2C_T_LOW);
2615         }
2616
2617         ixgbe_i2c_start(hw);
2618
2619         /* Put the i2c bus back to default state */
2620         ixgbe_i2c_stop(hw);
2621 }
2622
2623 /**
2624  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2625  *  @hw: pointer to hardware structure
2626  *
2627  *  Checks if the LASI temp alarm status was triggered due to overtemp
2628  **/
2629 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2630 {
2631         s32 status = IXGBE_SUCCESS;
2632         u16 phy_data = 0;
2633
2634         DEBUGFUNC("ixgbe_tn_check_overtemp");
2635
2636         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2637                 goto out;
2638
2639         /* Check that the LASI temp alarm status was triggered */
2640         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2641                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2642
2643         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2644                 goto out;
2645
2646         status = IXGBE_ERR_OVERTEMP;
2647         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2648 out:
2649         return status;
2650 }
2651
2652 /**
2653  * ixgbe_set_copper_phy_power - Control power for copper phy
2654  * @hw: pointer to hardware structure
2655  * @on: true for on, false for off
2656  */
2657 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2658 {
2659         u32 status;
2660         u16 reg;
2661
2662         if (!on && ixgbe_mng_present(hw))
2663                 return 0;
2664
2665         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2666                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2667                                       &reg);
2668         if (status)
2669                 return status;
2670
2671         if (on) {
2672                 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2673         } else {
2674                 if (ixgbe_check_reset_blocked(hw))
2675                         return 0;
2676                 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2677         }
2678
2679         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2680                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2681                                        reg);
2682         return status;
2683 }