1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
6 #include "ixgbe_common.h"
9 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
10 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
11 STATIC void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
12 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
13 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
14 STATIC void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
15 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
16 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
17 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
18 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
19 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
20 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
24 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
25 * @hw: pointer to the hardware structure
28 * Returns an error code on error.
30 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
34 status = ixgbe_clock_out_i2c_byte(hw, byte);
37 return ixgbe_get_i2c_ack(hw);
41 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
42 * @hw: pointer to the hardware structure
43 * @byte: pointer to a u8 to receive the byte
45 * Returns an error code on error.
47 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
49 ixgbe_clock_in_i2c_byte(hw, byte);
51 return ixgbe_clock_out_i2c_bit(hw, false);
55 * ixgbe_ones_comp_byte_add - Perform one's complement addition
59 * Returns one's complement 8-bit sum.
61 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
63 u16 sum = add1 + add2;
65 sum = (sum & 0xFF) + (sum >> 8);
70 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
71 * @hw: pointer to the hardware structure
72 * @addr: I2C bus address to read from
73 * @reg: I2C device register to read from
74 * @val: pointer to location to receive read value
75 * @lock: true if to take and release semaphore
77 * Returns an error code on error.
79 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
82 u32 swfw_mask = hw->phy.phy_semaphore_mask;
91 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
92 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
95 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
96 return IXGBE_ERR_SWFW_SYNC;
98 /* Device Address and write indication */
99 if (ixgbe_out_i2c_byte_ack(hw, addr))
101 /* Write bits 14:8 */
102 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
105 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
108 if (ixgbe_out_i2c_byte_ack(hw, csum))
110 /* Re-start condition */
112 /* Device Address and read indication */
113 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
116 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
119 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
122 ixgbe_clock_in_i2c_byte(hw, &csum_byte);
124 if (ixgbe_clock_out_i2c_bit(hw, false))
128 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
129 *val = (high_bits << 8) | low_bits;
133 ixgbe_i2c_bus_clear(hw);
135 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
136 if (retry < max_retry)
137 DEBUGOUT("I2C byte read combined error - Retrying.\n");
139 DEBUGOUT("I2C byte read combined error.\n");
141 } while (retry <= max_retry);
143 return IXGBE_ERR_I2C;
147 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
148 * @hw: pointer to the hardware structure
149 * @addr: I2C bus address to write to
150 * @reg: I2C device register to write to
151 * @val: value to write
152 * @lock: true if to take and release semaphore
154 * Returns an error code on error.
156 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
159 u32 swfw_mask = hw->phy.phy_semaphore_mask;
165 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
166 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
167 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
168 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
171 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
172 return IXGBE_ERR_SWFW_SYNC;
174 /* Device Address and write indication */
175 if (ixgbe_out_i2c_byte_ack(hw, addr))
177 /* Write bits 14:8 */
178 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
181 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
183 /* Write data 15:8 */
184 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
187 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
190 if (ixgbe_out_i2c_byte_ack(hw, csum))
194 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
198 ixgbe_i2c_bus_clear(hw);
200 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
201 if (retry < max_retry)
202 DEBUGOUT("I2C byte write combined error - Retrying.\n");
204 DEBUGOUT("I2C byte write combined error.\n");
206 } while (retry <= max_retry);
208 return IXGBE_ERR_I2C;
212 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
213 * @hw: pointer to the hardware structure
215 * Initialize the function pointers.
217 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
219 struct ixgbe_phy_info *phy = &hw->phy;
221 DEBUGFUNC("ixgbe_init_phy_ops_generic");
224 phy->ops.identify = ixgbe_identify_phy_generic;
225 phy->ops.reset = ixgbe_reset_phy_generic;
226 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
227 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
228 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
229 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
230 phy->ops.setup_link = ixgbe_setup_phy_link_generic;
231 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
232 phy->ops.check_link = NULL;
233 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
234 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
235 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
236 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
237 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
238 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
239 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
240 phy->ops.identify_sfp = ixgbe_identify_module_generic;
241 phy->sfp_type = ixgbe_sfp_type_unknown;
242 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
243 phy->ops.write_i2c_byte_unlocked =
244 ixgbe_write_i2c_byte_generic_unlocked;
245 phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
246 return IXGBE_SUCCESS;
250 * ixgbe_probe_phy - Probe a single address for a PHY
251 * @hw: pointer to hardware structure
252 * @phy_addr: PHY address to probe
254 * Returns true if PHY found
256 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
260 if (!ixgbe_validate_phy_addr(hw, phy_addr)) {
261 DEBUGOUT1("Unable to validate PHY address 0x%04X\n",
266 if (ixgbe_get_phy_id(hw))
269 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
271 if (hw->phy.type == ixgbe_phy_unknown) {
272 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
273 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
275 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
276 IXGBE_MDIO_PHY_1000BASET_ABILITY))
277 hw->phy.type = ixgbe_phy_cu_unknown;
279 hw->phy.type = ixgbe_phy_generic;
286 * ixgbe_identify_phy_generic - Get physical layer module
287 * @hw: pointer to hardware structure
289 * Determines the physical layer module found on the current adapter.
291 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
293 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
296 DEBUGFUNC("ixgbe_identify_phy_generic");
298 if (!hw->phy.phy_semaphore_mask) {
300 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
302 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
305 if (hw->phy.type != ixgbe_phy_unknown)
306 return IXGBE_SUCCESS;
308 if (hw->phy.nw_mng_if_sel) {
309 phy_addr = (hw->phy.nw_mng_if_sel &
310 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
311 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
312 if (ixgbe_probe_phy(hw, phy_addr))
313 return IXGBE_SUCCESS;
315 return IXGBE_ERR_PHY_ADDR_INVALID;
318 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
319 if (ixgbe_probe_phy(hw, phy_addr)) {
320 status = IXGBE_SUCCESS;
325 /* Certain media types do not have a phy so an address will not
326 * be found and the code will take this path. Caller has to
327 * decide if it is an error or not.
329 if (status != IXGBE_SUCCESS)
336 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
337 * @hw: pointer to the hardware structure
339 * This function checks the MMNGC.MNG_VETO bit to see if there are
340 * any constraints on link from manageability. For MAC's that don't
341 * have this bit just return faluse since the link can not be blocked
344 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
348 DEBUGFUNC("ixgbe_check_reset_blocked");
350 /* If we don't have this bit, it can't be blocking */
351 if (hw->mac.type == ixgbe_mac_82598EB)
354 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
355 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
356 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
357 "MNG_VETO bit detected.\n");
365 * ixgbe_validate_phy_addr - Determines phy address is valid
366 * @hw: pointer to hardware structure
367 * @phy_addr: PHY address
370 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
375 DEBUGFUNC("ixgbe_validate_phy_addr");
377 hw->phy.addr = phy_addr;
378 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
379 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
381 if (phy_id != 0xFFFF && phy_id != 0x0)
384 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id);
390 * ixgbe_get_phy_id - Get the phy type
391 * @hw: pointer to hardware structure
394 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
400 DEBUGFUNC("ixgbe_get_phy_id");
402 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
403 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
406 if (status == IXGBE_SUCCESS) {
407 hw->phy.id = (u32)(phy_id_high << 16);
408 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
409 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
411 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
412 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
414 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
415 phy_id_high, phy_id_low);
421 * ixgbe_get_phy_type_from_id - Get the phy type
422 * @phy_id: PHY ID information
425 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
427 enum ixgbe_phy_type phy_type;
429 DEBUGFUNC("ixgbe_get_phy_type_from_id");
433 phy_type = ixgbe_phy_tn;
438 phy_type = ixgbe_phy_aq;
441 phy_type = ixgbe_phy_qt;
444 phy_type = ixgbe_phy_nl;
448 phy_type = ixgbe_phy_x550em_ext_t;
450 case IXGBE_M88E1500_E_PHY_ID:
451 case IXGBE_M88E1543_E_PHY_ID:
452 phy_type = ixgbe_phy_ext_1g_t;
455 phy_type = ixgbe_phy_unknown;
462 * ixgbe_reset_phy_generic - Performs a PHY reset
463 * @hw: pointer to hardware structure
465 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
469 s32 status = IXGBE_SUCCESS;
471 DEBUGFUNC("ixgbe_reset_phy_generic");
473 if (hw->phy.type == ixgbe_phy_unknown)
474 status = ixgbe_identify_phy_generic(hw);
476 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
479 /* Don't reset PHY if it's shut down due to overtemp. */
480 if (!hw->phy.reset_if_overtemp &&
481 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
484 /* Blocked by MNG FW so bail */
485 if (ixgbe_check_reset_blocked(hw))
489 * Perform soft PHY reset to the PHY_XS.
490 * This will cause a soft reset to the PHY
492 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
493 IXGBE_MDIO_PHY_XS_DEV_TYPE,
494 IXGBE_MDIO_PHY_XS_RESET);
497 * Poll for reset bit to self-clear indicating reset is complete.
498 * Some PHYs could take up to 3 seconds to complete and need about
499 * 1.7 usec delay after the reset is complete.
501 for (i = 0; i < 30; i++) {
503 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
504 status = hw->phy.ops.read_reg(hw,
505 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
506 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
508 if (status != IXGBE_SUCCESS)
511 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
516 status = hw->phy.ops.read_reg(hw,
517 IXGBE_MDIO_PHY_XS_CONTROL,
518 IXGBE_MDIO_PHY_XS_DEV_TYPE,
520 if (status != IXGBE_SUCCESS)
523 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
530 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
531 status = IXGBE_ERR_RESET_FAILED;
532 ERROR_REPORT1(IXGBE_ERROR_POLLING,
533 "PHY reset polling failed to complete.\n");
541 * ixgbe_restart_auto_neg - Restart auto negotiation on the PHY
542 * @hw: pointer to hardware structure
544 void ixgbe_restart_auto_neg(struct ixgbe_hw *hw)
548 /* Check if PHY reset is blocked by MNG FW */
549 if (ixgbe_check_reset_blocked(hw))
552 /* Restart PHY auto-negotiation. */
553 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
554 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
555 autoneg_reg |= IXGBE_MII_RESTART;
556 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
557 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
561 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
563 * @hw: pointer to hardware structure
564 * @reg_addr: 32 bit address of PHY register to read
565 * @device_type: 5 bit device type
566 * @phy_data: Pointer to read data from PHY register
568 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
571 u32 i, data, command;
573 /* Setup and write the address cycle command */
574 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
575 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
576 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
577 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
579 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
582 * Check every 10 usec to see if the address cycle completed.
583 * The MDI Command bit will clear when the operation is
586 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
589 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
590 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
595 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
596 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
597 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n");
598 return IXGBE_ERR_PHY;
602 * Address cycle complete, setup and write the read
605 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
606 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
607 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
608 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
610 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
613 * Check every 10 usec to see if the address cycle
614 * completed. The MDI Command bit will clear when the
615 * operation is complete
617 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
620 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
621 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
625 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
626 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
627 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n");
628 return IXGBE_ERR_PHY;
632 * Read operation is complete. Get the data
635 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
636 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
637 *phy_data = (u16)(data);
639 return IXGBE_SUCCESS;
643 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
644 * using the SWFW lock - this function is needed in most cases
645 * @hw: pointer to hardware structure
646 * @reg_addr: 32 bit address of PHY register to read
647 * @device_type: 5 bit device type
648 * @phy_data: Pointer to read data from PHY register
650 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
651 u32 device_type, u16 *phy_data)
654 u32 gssr = hw->phy.phy_semaphore_mask;
656 DEBUGFUNC("ixgbe_read_phy_reg_generic");
658 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
659 return IXGBE_ERR_SWFW_SYNC;
661 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
663 hw->mac.ops.release_swfw_sync(hw, gssr);
669 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
671 * @hw: pointer to hardware structure
672 * @reg_addr: 32 bit PHY register to write
673 * @device_type: 5 bit device type
674 * @phy_data: Data to write to the PHY register
676 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
677 u32 device_type, u16 phy_data)
681 /* Put the data in the MDI single read and write data register*/
682 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
684 /* Setup and write the address cycle command */
685 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
686 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
687 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
688 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
690 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
693 * Check every 10 usec to see if the address cycle completed.
694 * The MDI Command bit will clear when the operation is
697 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
700 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
701 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
705 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
706 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
707 return IXGBE_ERR_PHY;
711 * Address cycle complete, setup and write the write
714 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
715 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
716 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
717 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
719 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
722 * Check every 10 usec to see if the address cycle
723 * completed. The MDI Command bit will clear when the
724 * operation is complete
726 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
729 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
730 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
734 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
735 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
736 return IXGBE_ERR_PHY;
739 return IXGBE_SUCCESS;
743 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
744 * using SWFW lock- this function is needed in most cases
745 * @hw: pointer to hardware structure
746 * @reg_addr: 32 bit PHY register to write
747 * @device_type: 5 bit device type
748 * @phy_data: Data to write to the PHY register
750 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
751 u32 device_type, u16 phy_data)
754 u32 gssr = hw->phy.phy_semaphore_mask;
756 DEBUGFUNC("ixgbe_write_phy_reg_generic");
758 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
759 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
761 hw->mac.ops.release_swfw_sync(hw, gssr);
763 status = IXGBE_ERR_SWFW_SYNC;
770 * ixgbe_setup_phy_link_generic - Set and restart auto-neg
771 * @hw: pointer to hardware structure
773 * Restart auto-negotiation and PHY and waits for completion.
775 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
777 s32 status = IXGBE_SUCCESS;
778 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
779 bool autoneg = false;
780 ixgbe_link_speed speed;
782 DEBUGFUNC("ixgbe_setup_phy_link_generic");
784 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
786 /* Set or unset auto-negotiation 10G advertisement */
787 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
788 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
791 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
792 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
793 (speed & IXGBE_LINK_SPEED_10GB_FULL))
794 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
796 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
797 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
800 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
801 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
804 if (hw->mac.type == ixgbe_mac_X550) {
805 /* Set or unset auto-negotiation 5G advertisement */
806 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
807 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
808 (speed & IXGBE_LINK_SPEED_5GB_FULL))
809 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
811 /* Set or unset auto-negotiation 2.5G advertisement */
812 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
813 if ((hw->phy.autoneg_advertised &
814 IXGBE_LINK_SPEED_2_5GB_FULL) &&
815 (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
816 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
819 /* Set or unset auto-negotiation 1G advertisement */
820 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
821 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
822 (speed & IXGBE_LINK_SPEED_1GB_FULL))
823 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
825 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
826 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
829 /* Set or unset auto-negotiation 100M advertisement */
830 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
831 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
834 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
835 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
836 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
837 (speed & IXGBE_LINK_SPEED_100_FULL))
838 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
840 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
841 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
844 ixgbe_restart_auto_neg(hw);
849 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
850 * @hw: pointer to hardware structure
851 * @speed: new link speed
852 * @autoneg_wait_to_complete: unused
854 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
855 ixgbe_link_speed speed,
856 bool autoneg_wait_to_complete)
858 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
860 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
863 * Clear autoneg_advertised and set new values based on input link
866 hw->phy.autoneg_advertised = 0;
868 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
869 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
871 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
872 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
874 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
875 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
877 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
878 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
880 if (speed & IXGBE_LINK_SPEED_100_FULL)
881 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
883 if (speed & IXGBE_LINK_SPEED_10_FULL)
884 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
886 /* Setup link based on the new speed settings */
887 ixgbe_setup_phy_link(hw);
889 return IXGBE_SUCCESS;
893 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
894 * @hw: pointer to hardware structure
896 * Determines the supported link capabilities by reading the PHY auto
897 * negotiation register.
899 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
904 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
905 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
910 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
911 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
912 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
913 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
914 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
915 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
917 switch (hw->mac.type) {
918 case ixgbe_mac_X550EM_x:
919 case ixgbe_mac_X550EM_a:
920 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
930 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
931 * @hw: pointer to hardware structure
932 * @speed: pointer to link speed
933 * @autoneg: boolean auto-negotiation value
935 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
936 ixgbe_link_speed *speed,
939 s32 status = IXGBE_SUCCESS;
941 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
944 if (!hw->phy.speeds_supported)
945 status = ixgbe_get_copper_speeds_supported(hw);
947 *speed = hw->phy.speeds_supported;
952 * ixgbe_check_phy_link_tnx - Determine link and speed status
953 * @hw: pointer to hardware structure
954 * @speed: current link speed
955 * @link_up: true is link is up, false otherwise
957 * Reads the VS1 register to determine if link is up and the current speed for
960 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
963 s32 status = IXGBE_SUCCESS;
965 u32 max_time_out = 10;
970 DEBUGFUNC("ixgbe_check_phy_link_tnx");
972 /* Initialize speed and link to default case */
974 *speed = IXGBE_LINK_SPEED_10GB_FULL;
977 * Check current speed and link status of the PHY register.
978 * This is a vendor specific register and may have to
979 * be changed for other copper PHYs.
981 for (time_out = 0; time_out < max_time_out; time_out++) {
983 status = hw->phy.ops.read_reg(hw,
984 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
985 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
987 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
988 phy_speed = phy_data &
989 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
990 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
993 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
994 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1003 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1004 * @hw: pointer to hardware structure
1006 * Restart auto-negotiation and PHY and waits for completion.
1008 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1010 s32 status = IXGBE_SUCCESS;
1011 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1012 bool autoneg = false;
1013 ixgbe_link_speed speed;
1015 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1017 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1019 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1020 /* Set or unset auto-negotiation 10G advertisement */
1021 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1022 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1025 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1026 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1027 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1029 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1030 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1034 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1035 /* Set or unset auto-negotiation 1G advertisement */
1036 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1037 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1040 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1041 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1042 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1044 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1045 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1049 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1050 /* Set or unset auto-negotiation 100M advertisement */
1051 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1052 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1055 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1056 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1057 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1059 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1060 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1064 ixgbe_restart_auto_neg(hw);
1069 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1070 * @hw: pointer to hardware structure
1071 * @firmware_version: pointer to the PHY Firmware Version
1073 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1074 u16 *firmware_version)
1078 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1080 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1081 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1088 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1089 * @hw: pointer to hardware structure
1090 * @firmware_version: pointer to the PHY Firmware Version
1092 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1093 u16 *firmware_version)
1097 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1099 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1100 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1107 * ixgbe_reset_phy_nl - Performs a PHY reset
1108 * @hw: pointer to hardware structure
1110 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1112 u16 phy_offset, control, eword, edata, block_crc;
1113 bool end_data = false;
1114 u16 list_offset, data_offset;
1116 s32 ret_val = IXGBE_SUCCESS;
1119 DEBUGFUNC("ixgbe_reset_phy_nl");
1121 /* Blocked by MNG FW so bail */
1122 if (ixgbe_check_reset_blocked(hw))
1125 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1126 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1128 /* reset the PHY and poll for completion */
1129 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1130 IXGBE_MDIO_PHY_XS_DEV_TYPE,
1131 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1133 for (i = 0; i < 100; i++) {
1134 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1135 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1136 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1141 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1142 DEBUGOUT("PHY reset did not complete.\n");
1143 ret_val = IXGBE_ERR_PHY;
1147 /* Get init offsets */
1148 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1150 if (ret_val != IXGBE_SUCCESS)
1153 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1157 * Read control word from PHY init contents offset
1159 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1162 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1163 IXGBE_CONTROL_SHIFT_NL;
1164 edata = eword & IXGBE_DATA_MASK_NL;
1166 case IXGBE_DELAY_NL:
1168 DEBUGOUT1("DELAY: %d MS\n", edata);
1172 DEBUGOUT("DATA:\n");
1174 ret_val = hw->eeprom.ops.read(hw, data_offset,
1179 for (i = 0; i < edata; i++) {
1180 ret_val = hw->eeprom.ops.read(hw, data_offset,
1184 hw->phy.ops.write_reg(hw, phy_offset,
1185 IXGBE_TWINAX_DEV, eword);
1186 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1192 case IXGBE_CONTROL_NL:
1194 DEBUGOUT("CONTROL:\n");
1195 if (edata == IXGBE_CONTROL_EOL_NL) {
1198 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1201 DEBUGOUT("Bad control value\n");
1202 ret_val = IXGBE_ERR_PHY;
1207 DEBUGOUT("Bad control type\n");
1208 ret_val = IXGBE_ERR_PHY;
1217 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1218 "eeprom read at offset %d failed", data_offset);
1219 return IXGBE_ERR_PHY;
1223 * ixgbe_identify_module_generic - Identifies module type
1224 * @hw: pointer to hardware structure
1226 * Determines HW type and calls appropriate function.
1228 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1230 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1232 DEBUGFUNC("ixgbe_identify_module_generic");
1234 switch (hw->mac.ops.get_media_type(hw)) {
1235 case ixgbe_media_type_fiber:
1236 status = ixgbe_identify_sfp_module_generic(hw);
1239 case ixgbe_media_type_fiber_qsfp:
1240 status = ixgbe_identify_qsfp_module_generic(hw);
1244 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1245 status = IXGBE_ERR_SFP_NOT_PRESENT;
1253 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1254 * @hw: pointer to hardware structure
1256 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1258 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1260 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1262 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1264 u8 comp_codes_1g = 0;
1265 u8 comp_codes_10g = 0;
1266 u8 oui_bytes[3] = {0, 0, 0};
1269 u16 enforce_sfp = 0;
1272 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1274 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1275 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1276 status = IXGBE_ERR_SFP_NOT_PRESENT;
1280 /* LAN ID is needed for I2C access */
1281 hw->mac.ops.set_lan_id(hw);
1283 /* Need to check this a couple of times for a sane value.
1285 * SFPs that have a uC slaved to the I2C bus (vs. a dumb EEPROM) can be
1286 * poorly designed such that they will ACK I2C reads and return
1287 * whatever bogus data is in the SRAM (or whatever is backing the target
1288 * device) before things are truly initialized.
1290 * In a perfect world devices would NAK I2C requests until they were
1291 * sane, but here we are.
1293 * Give such devices a couple tries to get their act together before
1294 * marking the device as unsupported.
1296 for (retries = 0; retries < 5; retries++) {
1297 status = hw->phy.ops.read_i2c_eeprom(hw,
1298 IXGBE_SFF_IDENTIFIER,
1301 DEBUGOUT("status %d, SFF identifier 0x%x\n", status, identifier);
1302 if (status == IXGBE_SUCCESS &&
1303 identifier == IXGBE_SFF_IDENTIFIER_SFP)
1307 if (status != IXGBE_SUCCESS)
1308 goto err_read_i2c_eeprom;
1310 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1311 hw->phy.type = ixgbe_phy_sfp_unsupported;
1312 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1314 status = hw->phy.ops.read_i2c_eeprom(hw,
1315 IXGBE_SFF_1GBE_COMP_CODES,
1318 if (status != IXGBE_SUCCESS)
1319 goto err_read_i2c_eeprom;
1321 status = hw->phy.ops.read_i2c_eeprom(hw,
1322 IXGBE_SFF_10GBE_COMP_CODES,
1325 if (status != IXGBE_SUCCESS)
1326 goto err_read_i2c_eeprom;
1327 status = hw->phy.ops.read_i2c_eeprom(hw,
1328 IXGBE_SFF_CABLE_TECHNOLOGY,
1331 if (status != IXGBE_SUCCESS)
1332 goto err_read_i2c_eeprom;
1339 * 3 SFP_DA_CORE0 - 82599-specific
1340 * 4 SFP_DA_CORE1 - 82599-specific
1341 * 5 SFP_SR/LR_CORE0 - 82599-specific
1342 * 6 SFP_SR/LR_CORE1 - 82599-specific
1343 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1344 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1345 * 9 SFP_1g_cu_CORE0 - 82599-specific
1346 * 10 SFP_1g_cu_CORE1 - 82599-specific
1347 * 11 SFP_1g_sx_CORE0 - 82599-specific
1348 * 12 SFP_1g_sx_CORE1 - 82599-specific
1350 if (hw->mac.type == ixgbe_mac_82598EB) {
1351 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1352 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1353 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1354 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1355 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1356 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1358 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1360 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1361 if (hw->bus.lan_id == 0)
1363 ixgbe_sfp_type_da_cu_core0;
1366 ixgbe_sfp_type_da_cu_core1;
1367 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1368 hw->phy.ops.read_i2c_eeprom(
1369 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1372 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1373 if (hw->bus.lan_id == 0)
1375 ixgbe_sfp_type_da_act_lmt_core0;
1378 ixgbe_sfp_type_da_act_lmt_core1;
1381 ixgbe_sfp_type_unknown;
1383 } else if (comp_codes_10g &
1384 (IXGBE_SFF_10GBASESR_CAPABLE |
1385 IXGBE_SFF_10GBASELR_CAPABLE)) {
1386 if (hw->bus.lan_id == 0)
1388 ixgbe_sfp_type_srlr_core0;
1391 ixgbe_sfp_type_srlr_core1;
1392 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1393 if (hw->bus.lan_id == 0)
1395 ixgbe_sfp_type_1g_cu_core0;
1398 ixgbe_sfp_type_1g_cu_core1;
1399 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1400 if (hw->bus.lan_id == 0)
1402 ixgbe_sfp_type_1g_sx_core0;
1405 ixgbe_sfp_type_1g_sx_core1;
1406 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1407 if (hw->bus.lan_id == 0)
1409 ixgbe_sfp_type_1g_lx_core0;
1412 ixgbe_sfp_type_1g_lx_core1;
1413 } else if (comp_codes_1g & IXGBE_SFF_1GBASELHA_CAPABLE) {
1414 if (hw->bus.lan_id == 0)
1416 ixgbe_sfp_type_1g_lha_core0;
1419 ixgbe_sfp_type_1g_lha_core1;
1421 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1425 if (hw->phy.sfp_type != stored_sfp_type)
1426 hw->phy.sfp_setup_needed = true;
1428 /* Determine if the SFP+ PHY is dual speed or not. */
1429 hw->phy.multispeed_fiber = false;
1430 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1431 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1432 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1433 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1434 hw->phy.multispeed_fiber = true;
1436 /* Determine PHY vendor */
1437 if (hw->phy.type != ixgbe_phy_nl) {
1438 hw->phy.id = identifier;
1439 status = hw->phy.ops.read_i2c_eeprom(hw,
1440 IXGBE_SFF_VENDOR_OUI_BYTE0,
1443 if (status != IXGBE_SUCCESS)
1444 goto err_read_i2c_eeprom;
1446 status = hw->phy.ops.read_i2c_eeprom(hw,
1447 IXGBE_SFF_VENDOR_OUI_BYTE1,
1450 if (status != IXGBE_SUCCESS)
1451 goto err_read_i2c_eeprom;
1453 status = hw->phy.ops.read_i2c_eeprom(hw,
1454 IXGBE_SFF_VENDOR_OUI_BYTE2,
1457 if (status != IXGBE_SUCCESS)
1458 goto err_read_i2c_eeprom;
1461 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1462 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1463 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1465 switch (vendor_oui) {
1466 case IXGBE_SFF_VENDOR_OUI_TYCO:
1467 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1469 ixgbe_phy_sfp_passive_tyco;
1471 case IXGBE_SFF_VENDOR_OUI_FTL:
1472 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1473 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1475 hw->phy.type = ixgbe_phy_sfp_ftl;
1477 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1478 hw->phy.type = ixgbe_phy_sfp_avago;
1480 case IXGBE_SFF_VENDOR_OUI_INTEL:
1481 hw->phy.type = ixgbe_phy_sfp_intel;
1484 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1486 ixgbe_phy_sfp_passive_unknown;
1487 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1489 ixgbe_phy_sfp_active_unknown;
1491 hw->phy.type = ixgbe_phy_sfp_unknown;
1496 /* Allow any DA cable vendor */
1497 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1498 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1499 status = IXGBE_SUCCESS;
1503 /* Verify supported 1G SFP modules */
1504 if (comp_codes_10g == 0 &&
1505 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1506 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1507 hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core0 ||
1508 hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core1 ||
1509 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1510 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1511 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1512 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1513 hw->phy.type = ixgbe_phy_sfp_unsupported;
1514 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1518 /* Anything else 82598-based is supported */
1519 if (hw->mac.type == ixgbe_mac_82598EB) {
1520 status = IXGBE_SUCCESS;
1524 ixgbe_get_device_caps(hw, &enforce_sfp);
1525 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1526 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1527 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1528 hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core0 ||
1529 hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core1 ||
1530 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1531 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1532 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1533 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1534 /* Make sure we're a supported PHY type */
1535 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1536 status = IXGBE_SUCCESS;
1538 if (hw->allow_unsupported_sfp == true) {
1540 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. "
1541 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1542 "Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1543 status = IXGBE_SUCCESS;
1545 DEBUGOUT("SFP+ module not supported\n");
1547 ixgbe_phy_sfp_unsupported;
1548 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1552 status = IXGBE_SUCCESS;
1559 err_read_i2c_eeprom:
1560 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1561 if (hw->phy.type != ixgbe_phy_nl) {
1563 hw->phy.type = ixgbe_phy_unknown;
1565 return IXGBE_ERR_SFP_NOT_PRESENT;
1569 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1570 * @hw: pointer to hardware structure
1572 * Determines physical layer capabilities of the current SFP.
1574 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1576 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1577 u8 comp_codes_10g = 0;
1578 u8 comp_codes_1g = 0;
1580 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1582 hw->phy.ops.identify_sfp(hw);
1583 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1584 return physical_layer;
1586 switch (hw->phy.type) {
1587 case ixgbe_phy_sfp_passive_tyco:
1588 case ixgbe_phy_sfp_passive_unknown:
1589 case ixgbe_phy_qsfp_passive_unknown:
1590 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1592 case ixgbe_phy_sfp_ftl_active:
1593 case ixgbe_phy_sfp_active_unknown:
1594 case ixgbe_phy_qsfp_active_unknown:
1595 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1597 case ixgbe_phy_sfp_avago:
1598 case ixgbe_phy_sfp_ftl:
1599 case ixgbe_phy_sfp_intel:
1600 case ixgbe_phy_sfp_unknown:
1601 hw->phy.ops.read_i2c_eeprom(hw,
1602 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1603 hw->phy.ops.read_i2c_eeprom(hw,
1604 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1605 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1606 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1607 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1608 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1609 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1610 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1611 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1612 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1614 case ixgbe_phy_qsfp_intel:
1615 case ixgbe_phy_qsfp_unknown:
1616 hw->phy.ops.read_i2c_eeprom(hw,
1617 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1618 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1619 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1620 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1621 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1627 return physical_layer;
1631 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1632 * @hw: pointer to hardware structure
1634 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1636 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1638 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1640 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1642 u8 comp_codes_1g = 0;
1643 u8 comp_codes_10g = 0;
1644 u8 oui_bytes[3] = {0, 0, 0};
1645 u16 enforce_sfp = 0;
1647 u8 cable_length = 0;
1649 bool active_cable = false;
1651 DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1653 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1654 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1655 status = IXGBE_ERR_SFP_NOT_PRESENT;
1659 /* LAN ID is needed for I2C access */
1660 hw->mac.ops.set_lan_id(hw);
1662 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1665 if (status != IXGBE_SUCCESS)
1666 goto err_read_i2c_eeprom;
1668 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1669 hw->phy.type = ixgbe_phy_sfp_unsupported;
1670 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1674 hw->phy.id = identifier;
1676 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1679 if (status != IXGBE_SUCCESS)
1680 goto err_read_i2c_eeprom;
1682 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1685 if (status != IXGBE_SUCCESS)
1686 goto err_read_i2c_eeprom;
1688 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1689 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1690 if (hw->bus.lan_id == 0)
1691 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1693 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1694 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1695 IXGBE_SFF_10GBASELR_CAPABLE)) {
1696 if (hw->bus.lan_id == 0)
1697 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1699 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1701 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1702 active_cable = true;
1704 if (!active_cable) {
1705 /* check for active DA cables that pre-date
1707 hw->phy.ops.read_i2c_eeprom(hw,
1708 IXGBE_SFF_QSFP_CONNECTOR,
1711 hw->phy.ops.read_i2c_eeprom(hw,
1712 IXGBE_SFF_QSFP_CABLE_LENGTH,
1715 hw->phy.ops.read_i2c_eeprom(hw,
1716 IXGBE_SFF_QSFP_DEVICE_TECH,
1720 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1721 (cable_length > 0) &&
1722 ((device_tech >> 4) ==
1723 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1724 active_cable = true;
1728 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1729 if (hw->bus.lan_id == 0)
1731 ixgbe_sfp_type_da_act_lmt_core0;
1734 ixgbe_sfp_type_da_act_lmt_core1;
1736 /* unsupported module type */
1737 hw->phy.type = ixgbe_phy_sfp_unsupported;
1738 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1743 if (hw->phy.sfp_type != stored_sfp_type)
1744 hw->phy.sfp_setup_needed = true;
1746 /* Determine if the QSFP+ PHY is dual speed or not. */
1747 hw->phy.multispeed_fiber = false;
1748 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1749 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1750 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1751 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1752 hw->phy.multispeed_fiber = true;
1754 /* Determine PHY vendor for optical modules */
1755 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1756 IXGBE_SFF_10GBASELR_CAPABLE)) {
1757 status = hw->phy.ops.read_i2c_eeprom(hw,
1758 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1761 if (status != IXGBE_SUCCESS)
1762 goto err_read_i2c_eeprom;
1764 status = hw->phy.ops.read_i2c_eeprom(hw,
1765 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1768 if (status != IXGBE_SUCCESS)
1769 goto err_read_i2c_eeprom;
1771 status = hw->phy.ops.read_i2c_eeprom(hw,
1772 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1775 if (status != IXGBE_SUCCESS)
1776 goto err_read_i2c_eeprom;
1779 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1780 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1781 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1783 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1784 hw->phy.type = ixgbe_phy_qsfp_intel;
1786 hw->phy.type = ixgbe_phy_qsfp_unknown;
1788 ixgbe_get_device_caps(hw, &enforce_sfp);
1789 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1790 /* Make sure we're a supported PHY type */
1791 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1792 status = IXGBE_SUCCESS;
1794 if (hw->allow_unsupported_sfp == true) {
1796 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. "
1797 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1798 "Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1799 status = IXGBE_SUCCESS;
1801 DEBUGOUT("QSFP module not supported\n");
1803 ixgbe_phy_sfp_unsupported;
1804 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1808 status = IXGBE_SUCCESS;
1815 err_read_i2c_eeprom:
1816 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1818 hw->phy.type = ixgbe_phy_unknown;
1820 return IXGBE_ERR_SFP_NOT_PRESENT;
1824 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1825 * @hw: pointer to hardware structure
1826 * @list_offset: offset to the SFP ID list
1827 * @data_offset: offset to the SFP data block
1829 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1830 * so it returns the offsets to the phy init sequence block.
1832 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1837 u16 sfp_type = hw->phy.sfp_type;
1839 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1841 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1842 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1844 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1845 return IXGBE_ERR_SFP_NOT_PRESENT;
1847 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1848 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1849 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1852 * Limiting active cables and 1G Phys must be initialized as
1855 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1856 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1857 sfp_type == ixgbe_sfp_type_1g_lha_core0 ||
1858 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1859 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1860 sfp_type = ixgbe_sfp_type_srlr_core0;
1861 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1862 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1863 sfp_type == ixgbe_sfp_type_1g_lha_core1 ||
1864 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1865 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1866 sfp_type = ixgbe_sfp_type_srlr_core1;
1868 /* Read offset to PHY init contents */
1869 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1870 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1871 "eeprom read at offset %d failed",
1872 IXGBE_PHY_INIT_OFFSET_NL);
1873 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1876 if ((!*list_offset) || (*list_offset == 0xFFFF))
1877 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1879 /* Shift offset to first ID word */
1883 * Find the matching SFP ID in the EEPROM
1884 * and program the init sequence
1886 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1889 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1890 if (sfp_id == sfp_type) {
1892 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1894 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1895 DEBUGOUT("SFP+ module not supported\n");
1896 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1901 (*list_offset) += 2;
1902 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1907 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1908 DEBUGOUT("No matching SFP+ module found\n");
1909 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1912 return IXGBE_SUCCESS;
1915 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1916 "eeprom read at offset %d failed", *list_offset);
1917 return IXGBE_ERR_PHY;
1921 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1922 * @hw: pointer to hardware structure
1923 * @byte_offset: EEPROM byte offset to read
1924 * @eeprom_data: value read
1926 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1928 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1931 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1933 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1934 IXGBE_I2C_EEPROM_DEV_ADDR,
1939 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1940 * @hw: pointer to hardware structure
1941 * @byte_offset: byte offset at address 0xA2
1942 * @sff8472_data: value read
1944 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1946 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1949 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1950 IXGBE_I2C_EEPROM_DEV_ADDR2,
1955 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1956 * @hw: pointer to hardware structure
1957 * @byte_offset: EEPROM byte offset to write
1958 * @eeprom_data: value to write
1960 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1962 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1965 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1967 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1968 IXGBE_I2C_EEPROM_DEV_ADDR,
1973 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1974 * @hw: pointer to hardware structure
1975 * @offset: eeprom offset to be read
1976 * @addr: I2C address to be read
1978 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1980 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1981 offset == IXGBE_SFF_IDENTIFIER &&
1982 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1988 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1989 * @hw: pointer to hardware structure
1990 * @byte_offset: byte offset to read
1991 * @dev_addr: address to read from
1993 * @lock: true if to take and release semaphore
1995 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1996 * a specified device address.
1998 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1999 u8 dev_addr, u8 *data, bool lock)
2004 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2008 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2010 if (hw->mac.type >= ixgbe_mac_X550)
2012 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2013 max_retry = IXGBE_SFP_DETECT_RETRIES;
2016 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2017 return IXGBE_ERR_SWFW_SYNC;
2019 ixgbe_i2c_start(hw);
2021 /* Device Address and write indication */
2022 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2023 if (status != IXGBE_SUCCESS)
2026 status = ixgbe_get_i2c_ack(hw);
2027 if (status != IXGBE_SUCCESS)
2030 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2031 if (status != IXGBE_SUCCESS)
2034 status = ixgbe_get_i2c_ack(hw);
2035 if (status != IXGBE_SUCCESS)
2038 ixgbe_i2c_start(hw);
2040 /* Device Address and read indication */
2041 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2042 if (status != IXGBE_SUCCESS)
2045 status = ixgbe_get_i2c_ack(hw);
2046 if (status != IXGBE_SUCCESS)
2049 ixgbe_clock_in_i2c_byte(hw, data);
2051 status = ixgbe_clock_out_i2c_bit(hw, nack);
2052 if (status != IXGBE_SUCCESS)
2057 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2058 return IXGBE_SUCCESS;
2061 ixgbe_i2c_bus_clear(hw);
2063 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2066 if (retry < max_retry)
2067 DEBUGOUT("I2C byte read error - Retrying.\n");
2069 DEBUGOUT("I2C byte read error.\n");
2071 } while (retry <= max_retry);
2077 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2078 * @hw: pointer to hardware structure
2079 * @byte_offset: byte offset to read
2080 * @dev_addr: address to read from
2083 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2084 * a specified device address.
2086 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2087 u8 dev_addr, u8 *data)
2089 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2094 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2095 * @hw: pointer to hardware structure
2096 * @byte_offset: byte offset to read
2097 * @dev_addr: address to read from
2100 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2101 * a specified device address.
2103 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2104 u8 dev_addr, u8 *data)
2106 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2111 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2112 * @hw: pointer to hardware structure
2113 * @byte_offset: byte offset to write
2114 * @dev_addr: address to write to
2115 * @data: value to write
2116 * @lock: true if to take and release semaphore
2118 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2119 * a specified device address.
2121 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2122 u8 dev_addr, u8 data, bool lock)
2127 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2129 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2131 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2133 return IXGBE_ERR_SWFW_SYNC;
2136 ixgbe_i2c_start(hw);
2138 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2139 if (status != IXGBE_SUCCESS)
2142 status = ixgbe_get_i2c_ack(hw);
2143 if (status != IXGBE_SUCCESS)
2146 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2147 if (status != IXGBE_SUCCESS)
2150 status = ixgbe_get_i2c_ack(hw);
2151 if (status != IXGBE_SUCCESS)
2154 status = ixgbe_clock_out_i2c_byte(hw, data);
2155 if (status != IXGBE_SUCCESS)
2158 status = ixgbe_get_i2c_ack(hw);
2159 if (status != IXGBE_SUCCESS)
2164 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2165 return IXGBE_SUCCESS;
2168 ixgbe_i2c_bus_clear(hw);
2169 if (retry < max_retry)
2170 DEBUGOUT("I2C byte write error - Retrying.\n");
2172 DEBUGOUT("I2C byte write error.\n");
2174 } while (retry <= max_retry);
2177 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2183 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2184 * @hw: pointer to hardware structure
2185 * @byte_offset: byte offset to write
2186 * @dev_addr: address to write to
2187 * @data: value to write
2189 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2190 * a specified device address.
2192 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2193 u8 dev_addr, u8 data)
2195 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2200 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2201 * @hw: pointer to hardware structure
2202 * @byte_offset: byte offset to write
2203 * @dev_addr: address to write to
2204 * @data: value to write
2206 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2207 * a specified device address.
2209 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2210 u8 dev_addr, u8 data)
2212 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2217 * ixgbe_i2c_start - Sets I2C start condition
2218 * @hw: pointer to hardware structure
2220 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2221 * Set bit-bang mode on X550 hardware.
2223 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2225 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2227 DEBUGFUNC("ixgbe_i2c_start");
2229 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2231 /* Start condition must begin with data and clock high */
2232 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2233 ixgbe_raise_i2c_clk(hw, &i2cctl);
2235 /* Setup time for start condition (4.7us) */
2236 usec_delay(IXGBE_I2C_T_SU_STA);
2238 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2240 /* Hold time for start condition (4us) */
2241 usec_delay(IXGBE_I2C_T_HD_STA);
2243 ixgbe_lower_i2c_clk(hw, &i2cctl);
2245 /* Minimum low period of clock is 4.7 us */
2246 usec_delay(IXGBE_I2C_T_LOW);
2251 * ixgbe_i2c_stop - Sets I2C stop condition
2252 * @hw: pointer to hardware structure
2254 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2255 * Disables bit-bang mode and negates data output enable on X550
2258 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2260 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2261 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2262 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2263 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2265 DEBUGFUNC("ixgbe_i2c_stop");
2267 /* Stop condition must begin with data low and clock high */
2268 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2269 ixgbe_raise_i2c_clk(hw, &i2cctl);
2271 /* Setup time for stop condition (4us) */
2272 usec_delay(IXGBE_I2C_T_SU_STO);
2274 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2276 /* bus free time between stop and start (4.7us)*/
2277 usec_delay(IXGBE_I2C_T_BUF);
2279 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2280 i2cctl &= ~bb_en_bit;
2281 i2cctl |= data_oe_bit | clk_oe_bit;
2282 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2283 IXGBE_WRITE_FLUSH(hw);
2288 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2289 * @hw: pointer to hardware structure
2290 * @data: data byte to clock in
2292 * Clocks in one byte data via I2C data/clock
2294 STATIC void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2299 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2302 for (i = 7; i >= 0; i--) {
2303 ixgbe_clock_in_i2c_bit(hw, &bit);
2309 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2310 * @hw: pointer to hardware structure
2311 * @data: data byte clocked out
2313 * Clocks out one byte data via I2C data/clock
2315 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2317 s32 status = IXGBE_SUCCESS;
2322 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2324 for (i = 7; i >= 0; i--) {
2325 bit = (data >> i) & 0x1;
2326 status = ixgbe_clock_out_i2c_bit(hw, bit);
2328 if (status != IXGBE_SUCCESS)
2332 /* Release SDA line (set high) */
2333 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2334 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2335 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2336 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2337 IXGBE_WRITE_FLUSH(hw);
2343 * ixgbe_get_i2c_ack - Polls for I2C ACK
2344 * @hw: pointer to hardware structure
2346 * Clocks in/out one bit via I2C data/clock
2348 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2350 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2351 s32 status = IXGBE_SUCCESS;
2353 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2357 DEBUGFUNC("ixgbe_get_i2c_ack");
2360 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2361 i2cctl |= data_oe_bit;
2362 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2363 IXGBE_WRITE_FLUSH(hw);
2365 ixgbe_raise_i2c_clk(hw, &i2cctl);
2367 /* Minimum high period of clock is 4us */
2368 usec_delay(IXGBE_I2C_T_HIGH);
2370 /* Poll for ACK. Note that ACK in I2C spec is
2371 * transition from 1 to 0 */
2372 for (i = 0; i < timeout; i++) {
2373 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2374 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2382 DEBUGOUT("I2C ack was not received.\n");
2383 status = IXGBE_ERR_I2C;
2386 ixgbe_lower_i2c_clk(hw, &i2cctl);
2388 /* Minimum low period of clock is 4.7 us */
2389 usec_delay(IXGBE_I2C_T_LOW);
2395 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2396 * @hw: pointer to hardware structure
2397 * @data: read data value
2399 * Clocks in one bit via I2C data/clock
2401 STATIC void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2403 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2404 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2406 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2409 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2410 i2cctl |= data_oe_bit;
2411 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2412 IXGBE_WRITE_FLUSH(hw);
2414 ixgbe_raise_i2c_clk(hw, &i2cctl);
2416 /* Minimum high period of clock is 4us */
2417 usec_delay(IXGBE_I2C_T_HIGH);
2419 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2420 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2422 ixgbe_lower_i2c_clk(hw, &i2cctl);
2424 /* Minimum low period of clock is 4.7 us */
2425 usec_delay(IXGBE_I2C_T_LOW);
2429 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2430 * @hw: pointer to hardware structure
2431 * @data: data value to write
2433 * Clocks out one bit via I2C data/clock
2435 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2438 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2440 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2442 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2443 if (status == IXGBE_SUCCESS) {
2444 ixgbe_raise_i2c_clk(hw, &i2cctl);
2446 /* Minimum high period of clock is 4us */
2447 usec_delay(IXGBE_I2C_T_HIGH);
2449 ixgbe_lower_i2c_clk(hw, &i2cctl);
2451 /* Minimum low period of clock is 4.7 us.
2452 * This also takes care of the data hold time.
2454 usec_delay(IXGBE_I2C_T_LOW);
2456 status = IXGBE_ERR_I2C;
2457 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2458 "I2C data was not set to %X\n", data);
2465 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2466 * @hw: pointer to hardware structure
2467 * @i2cctl: Current value of I2CCTL register
2469 * Raises the I2C clock line '0'->'1'
2470 * Negates the I2C clock output enable on X550 hardware.
2472 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2474 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2476 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2479 DEBUGFUNC("ixgbe_raise_i2c_clk");
2482 *i2cctl |= clk_oe_bit;
2483 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2486 for (i = 0; i < timeout; i++) {
2487 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2489 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2490 IXGBE_WRITE_FLUSH(hw);
2491 /* SCL rise time (1000ns) */
2492 usec_delay(IXGBE_I2C_T_RISE);
2494 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2495 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2501 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2502 * @hw: pointer to hardware structure
2503 * @i2cctl: Current value of I2CCTL register
2505 * Lowers the I2C clock line '1'->'0'
2506 * Asserts the I2C clock output enable on X550 hardware.
2508 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2510 DEBUGFUNC("ixgbe_lower_i2c_clk");
2512 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2513 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2515 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2516 IXGBE_WRITE_FLUSH(hw);
2518 /* SCL fall time (300ns) */
2519 usec_delay(IXGBE_I2C_T_FALL);
2523 * ixgbe_set_i2c_data - Sets the I2C data bit
2524 * @hw: pointer to hardware structure
2525 * @i2cctl: Current value of I2CCTL register
2526 * @data: I2C data value (0 or 1) to set
2528 * Sets the I2C data bit
2529 * Asserts the I2C data output enable on X550 hardware.
2531 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2533 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2534 s32 status = IXGBE_SUCCESS;
2536 DEBUGFUNC("ixgbe_set_i2c_data");
2539 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2541 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2542 *i2cctl &= ~data_oe_bit;
2544 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2545 IXGBE_WRITE_FLUSH(hw);
2547 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2548 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2550 if (!data) /* Can't verify data in this case */
2551 return IXGBE_SUCCESS;
2553 *i2cctl |= data_oe_bit;
2554 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2555 IXGBE_WRITE_FLUSH(hw);
2558 /* Verify data was set correctly */
2559 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2560 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2561 status = IXGBE_ERR_I2C;
2562 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2563 "Error - I2C data was not set to %X.\n",
2571 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2572 * @hw: pointer to hardware structure
2573 * @i2cctl: Current value of I2CCTL register
2575 * Returns the I2C data bit value
2576 * Negates the I2C data output enable on X550 hardware.
2578 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2580 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2583 DEBUGFUNC("ixgbe_get_i2c_data");
2586 *i2cctl |= data_oe_bit;
2587 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2588 IXGBE_WRITE_FLUSH(hw);
2589 usec_delay(IXGBE_I2C_T_FALL);
2592 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2601 * ixgbe_i2c_bus_clear - Clears the I2C bus
2602 * @hw: pointer to hardware structure
2604 * Clears the I2C bus by sending nine clock pulses.
2605 * Used when data line is stuck low.
2607 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2612 DEBUGFUNC("ixgbe_i2c_bus_clear");
2614 ixgbe_i2c_start(hw);
2615 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2617 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2619 for (i = 0; i < 9; i++) {
2620 ixgbe_raise_i2c_clk(hw, &i2cctl);
2622 /* Min high period of clock is 4us */
2623 usec_delay(IXGBE_I2C_T_HIGH);
2625 ixgbe_lower_i2c_clk(hw, &i2cctl);
2627 /* Min low period of clock is 4.7us*/
2628 usec_delay(IXGBE_I2C_T_LOW);
2631 ixgbe_i2c_start(hw);
2633 /* Put the i2c bus back to default state */
2638 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2639 * @hw: pointer to hardware structure
2641 * Checks if the LASI temp alarm status was triggered due to overtemp
2643 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2645 s32 status = IXGBE_SUCCESS;
2648 DEBUGFUNC("ixgbe_tn_check_overtemp");
2650 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2653 /* Check that the LASI temp alarm status was triggered */
2654 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2655 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2657 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2660 status = IXGBE_ERR_OVERTEMP;
2661 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2667 * ixgbe_set_copper_phy_power - Control power for copper phy
2668 * @hw: pointer to hardware structure
2669 * @on: true for on, false for off
2671 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2676 if (!on && ixgbe_mng_present(hw))
2679 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2680 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2686 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2688 if (ixgbe_check_reset_blocked(hw))
2690 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2693 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2694 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,