drivers/net/ixgbe/base/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_api.h"
  35 #include "ixgbe_common.h"
  36 #include "ixgbe_phy.h"
  37
  38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
  39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  50                                           u8 *sff8472_data);
  51
  52 /**
  53  * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
  54  * @hw: pointer to the hardware structure
  55  * @byte: byte to send
  56  *
  57  * Returns an error code on error.
  58  */
  59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
  60 {
  61         s32 status;
  62
  63         status = ixgbe_clock_out_i2c_byte(hw, byte);
  64         if (status)
  65                 return status;
  66         return ixgbe_get_i2c_ack(hw);
  67 }
  68
  69 /**
  70  * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
  71  * @hw: pointer to the hardware structure
  72  * @byte: pointer to a u8 to receive the byte
  73  *
  74  * Returns an error code on error.
  75  */
  76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
  77 {
  78         s32 status;
  79
  80         status = ixgbe_clock_in_i2c_byte(hw, byte);
  81         if (status)
  82                 return status;
  83         /* ACK */
  84         return ixgbe_clock_out_i2c_bit(hw, false);
  85 }
  86
  87 /**
  88  * ixgbe_ones_comp_byte_add - Perform one's complement addition
  89  * @add1 - addend 1
  90  * @add2 - addend 2
  91  *
  92  * Returns one's complement 8-bit sum.
  93  */
  94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
  95 {
  96         u16 sum = add1 + add2;
  97
  98         sum = (sum & 0xFF) + (sum >> 8);
  99         return sum & 0xFF;
 100 }
 101
 102 /**
 103  * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
 104  * @hw: pointer to the hardware structure
 105  * @addr: I2C bus address to read from
 106  * @reg: I2C device register to read from
 107  * @val: pointer to location to receive read value
 108  * @lock: true if to take and release semaphore
 109  *
 110  * Returns an error code on error.
 111  */
 112 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 113                                         u16 *val, bool lock)
 114 {
 115         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 116         int max_retry = 10;
 117         int retry = 0;
 118         u8 csum_byte;
 119         u8 high_bits;
 120         u8 low_bits;
 121         u8 reg_high;
 122         u8 csum;
 123
 124         if (hw->mac.type >= ixgbe_mac_X550)
 125                 max_retry = 3;
 126         reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
 127         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 128         csum = ~csum;
 129         do {
 130                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 131                         return IXGBE_ERR_SWFW_SYNC;
 132                 ixgbe_i2c_start(hw);
 133                 /* Device Address and write indication */
 134                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 135                         goto fail;
 136                 /* Write bits 14:8 */
 137                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 138                         goto fail;
 139                 /* Write bits 7:0 */
 140                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 141                         goto fail;
 142                 /* Write csum */
 143                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 144                         goto fail;
 145                 /* Re-start condition */
 146                 ixgbe_i2c_start(hw);
 147                 /* Device Address and read indication */
 148                 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
 149                         goto fail;
 150                 /* Get upper bits */
 151                 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
 152                         goto fail;
 153                 /* Get low bits */
 154                 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
 155                         goto fail;
 156                 /* Get csum */
 157                 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
 158                         goto fail;
 159                 /* NACK */
 160                 if (ixgbe_clock_out_i2c_bit(hw, false))
 161                         goto fail;
 162                 ixgbe_i2c_stop(hw);
 163                 if (lock)
 164                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 165                 *val = (high_bits << 8) | low_bits;
 166                 return 0;
 167
 168 fail:
 169                 ixgbe_i2c_bus_clear(hw);
 170                 if (lock)
 171                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 172                 retry++;
 173                 if (retry < max_retry)
 174                         DEBUGOUT("I2C byte read combined error - Retrying.\n");
 175                 else
 176                         DEBUGOUT("I2C byte read combined error.\n");
 177         } while (retry < max_retry);
 178
 179         return IXGBE_ERR_I2C;
 180 }
 181
 182 /**
 183  * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
 184  * @hw: pointer to the hardware structure
 185  * @addr: I2C bus address to write to
 186  * @reg: I2C device register to write to
 187  * @val: value to write
 188  * @lock: true if to take and release semaphore
 189  *
 190  * Returns an error code on error.
 191  */
 192 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 193                                          u16 val, bool lock)
 194 {
 195         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 196         int max_retry = 1;
 197         int retry = 0;
 198         u8 reg_high;
 199         u8 csum;
 200
 201         reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
 202         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 203         csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
 204         csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
 205         csum = ~csum;
 206         do {
 207                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 208                         return IXGBE_ERR_SWFW_SYNC;
 209                 ixgbe_i2c_start(hw);
 210                 /* Device Address and write indication */
 211                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 212                         goto fail;
 213                 /* Write bits 14:8 */
 214                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 215                         goto fail;
 216                 /* Write bits 7:0 */
 217                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 218                         goto fail;
 219                 /* Write data 15:8 */
 220                 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
 221                         goto fail;
 222                 /* Write data 7:0 */
 223                 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
 224                         goto fail;
 225                 /* Write csum */
 226                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 227                         goto fail;
 228                 ixgbe_i2c_stop(hw);
 229                 if (lock)
 230                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 231                 return 0;
 232
 233 fail:
 234                 ixgbe_i2c_bus_clear(hw);
 235                 if (lock)
 236                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 237                 retry++;
 238                 if (retry < max_retry)
 239                         DEBUGOUT("I2C byte write combined error - Retrying.\n");
 240                 else
 241                         DEBUGOUT("I2C byte write combined error.\n");
 242         } while (retry < max_retry);
 243
 244         return IXGBE_ERR_I2C;
 245 }
 246
 247 /**
 248  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
 249  *  @hw: pointer to the hardware structure
 250  *
 251  *  Initialize the function pointers.
 252  **/
 253 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
 254 {
 255         struct ixgbe_phy_info *phy = &hw->phy;
 256
 257         DEBUGFUNC("ixgbe_init_phy_ops_generic");
 258
 259         /* PHY */
 260         phy->ops.identify = ixgbe_identify_phy_generic;
 261         phy->ops.reset = ixgbe_reset_phy_generic;
 262         phy->ops.read_reg = ixgbe_read_phy_reg_generic;
 263         phy->ops.write_reg = ixgbe_write_phy_reg_generic;
 264         phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
 265         phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
 266         phy->ops.setup_link = ixgbe_setup_phy_link_generic;
 267         phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
 268         phy->ops.check_link = NULL;
 269         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
 270         phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
 271         phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
 272         phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
 273         phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
 274         phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
 275         phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
 276         phy->ops.identify_sfp = ixgbe_identify_module_generic;
 277         phy->sfp_type = ixgbe_sfp_type_unknown;
 278         phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
 279         phy->ops.write_i2c_byte_unlocked =
 280                                 ixgbe_write_i2c_byte_generic_unlocked;
 281         phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
 282         return IXGBE_SUCCESS;
 283 }
 284
 285 /**
 286  * ixgbe_probe_phy - Probe a single address for a PHY
 287  * @hw: pointer to hardware structure
 288  * @phy_addr: PHY address to probe
 289  *
 290  * Returns true if PHY found
 291  */
 292 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
 293 {
 294         u16 ext_ability = 0;
 295
 296         if (!ixgbe_validate_phy_addr(hw, phy_addr))
 297                 return false;
 298
 299         if (ixgbe_get_phy_id(hw))
 300                 return false;
 301
 302         hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
 303
 304         if (hw->phy.type == ixgbe_phy_unknown) {
 305                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
 306                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
 307                 if (ext_ability &
 308                     (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 309                      IXGBE_MDIO_PHY_1000BASET_ABILITY))
 310                         hw->phy.type = ixgbe_phy_cu_unknown;
 311                 else
 312                         hw->phy.type = ixgbe_phy_generic;
 313         }
 314
 315         return true;
 316 }
 317
 318 /**
 319  *  ixgbe_identify_phy_generic - Get physical layer module
 320  *  @hw: pointer to hardware structure
 321  *
 322  *  Determines the physical layer module found on the current adapter.
 323  **/
 324 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 325 {
 326         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 327         u16 phy_addr;
 328
 329         DEBUGFUNC("ixgbe_identify_phy_generic");
 330
 331         if (!hw->phy.phy_semaphore_mask) {
 332                 if (hw->bus.lan_id)
 333                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 334                 else
 335                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 336         }
 337
 338         if (hw->phy.type != ixgbe_phy_unknown)
 339                 return IXGBE_SUCCESS;
 340
 341         if (hw->phy.nw_mng_if_sel) {
 342                 phy_addr = (hw->phy.nw_mng_if_sel &
 343                             IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
 344                            IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
 345                 if (ixgbe_probe_phy(hw, phy_addr))
 346                         return IXGBE_SUCCESS;
 347                 else
 348                         return IXGBE_ERR_PHY_ADDR_INVALID;
 349         }
 350
 351         for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 352                 if (ixgbe_probe_phy(hw, phy_addr)) {
 353                         status = IXGBE_SUCCESS;
 354                         break;
 355                 }
 356         }
 357
 358         /* Certain media types do not have a phy so an address will not
 359          * be found and the code will take this path.  Caller has to
 360          * decide if it is an error or not.
 361          */
 362         if (status != IXGBE_SUCCESS)
 363                 hw->phy.addr = 0;
 364
 365         return status;
 366 }
 367
 368 /**
 369  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 370  * @hw: pointer to the hardware structure
 371  *
 372  * This function checks the MMNGC.MNG_VETO bit to see if there are
 373  * any constraints on link from manageability.  For MAC's that don't
 374  * have this bit just return faluse since the link can not be blocked
 375  * via this method.
 376  **/
 377 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 378 {
 379         u32 mmngc;
 380
 381         DEBUGFUNC("ixgbe_check_reset_blocked");
 382
 383         /* If we don't have this bit, it can't be blocking */
 384         if (hw->mac.type == ixgbe_mac_82598EB)
 385                 return false;
 386
 387         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 388         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 389                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 390                               "MNG_VETO bit detected.\n");
 391                 return true;
 392         }
 393
 394         return false;
 395 }
 396
 397 /**
 398  *  ixgbe_validate_phy_addr - Determines phy address is valid
 399  *  @hw: pointer to hardware structure
 400  *
 401  **/
 402 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 403 {
 404         u16 phy_id = 0;
 405         bool valid = false;
 406
 407         DEBUGFUNC("ixgbe_validate_phy_addr");
 408
 409         hw->phy.addr = phy_addr;
 410         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 411                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 412
 413         if (phy_id != 0xFFFF && phy_id != 0x0)
 414                 valid = true;
 415
 416         return valid;
 417 }
 418
 419 /**
 420  *  ixgbe_get_phy_id - Get the phy type
 421  *  @hw: pointer to hardware structure
 422  *
 423  **/
 424 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 425 {
 426         u32 status;
 427         u16 phy_id_high = 0;
 428         u16 phy_id_low = 0;
 429
 430         DEBUGFUNC("ixgbe_get_phy_id");
 431
 432         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 433                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 434                                       &phy_id_high);
 435
 436         if (status == IXGBE_SUCCESS) {
 437                 hw->phy.id = (u32)(phy_id_high << 16);
 438                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 439                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 440                                               &phy_id_low);
 441                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 442                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 443         }
 444         return status;
 445 }
 446
 447 /**
 448  *  ixgbe_get_phy_type_from_id - Get the phy type
 449  *  @phy_id: PHY ID information
 450  *
 451  **/
 452 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 453 {
 454         enum ixgbe_phy_type phy_type;
 455
 456         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 457
 458         switch (phy_id) {
 459         case TN1010_PHY_ID:
 460                 phy_type = ixgbe_phy_tn;
 461                 break;
 462         case X550_PHY_ID1:
 463         case X550_PHY_ID2:
 464         case X550_PHY_ID3:
 465         case X540_PHY_ID:
 466                 phy_type = ixgbe_phy_aq;
 467                 break;
 468         case QT2022_PHY_ID:
 469                 phy_type = ixgbe_phy_qt;
 470                 break;
 471         case ATH_PHY_ID:
 472                 phy_type = ixgbe_phy_nl;
 473                 break;
 474         case X557_PHY_ID:
 475         case X557_PHY_ID2:
 476                 phy_type = ixgbe_phy_x550em_ext_t;
 477                 break;
 478         default:
 479                 phy_type = ixgbe_phy_unknown;
 480                 break;
 481         }
 482         return phy_type;
 483 }
 484
 485 /**
 486  *  ixgbe_reset_phy_generic - Performs a PHY reset
 487  *  @hw: pointer to hardware structure
 488  **/
 489 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 490 {
 491         u32 i;
 492         u16 ctrl = 0;
 493         s32 status = IXGBE_SUCCESS;
 494
 495         DEBUGFUNC("ixgbe_reset_phy_generic");
 496
 497         if (hw->phy.type == ixgbe_phy_unknown)
 498                 status = ixgbe_identify_phy_generic(hw);
 499
 500         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 501                 goto out;
 502
 503         /* Don't reset PHY if it's shut down due to overtemp. */
 504         if (!hw->phy.reset_if_overtemp &&
 505             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 506                 goto out;
 507
 508         /* Blocked by MNG FW so bail */
 509         if (ixgbe_check_reset_blocked(hw))
 510                 goto out;
 511
 512         /*
 513          * Perform soft PHY reset to the PHY_XS.
 514          * This will cause a soft reset to the PHY
 515          */
 516         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 517                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 518                               IXGBE_MDIO_PHY_XS_RESET);
 519
 520         /*
 521          * Poll for reset bit to self-clear indicating reset is complete.
 522          * Some PHYs could take up to 3 seconds to complete and need about
 523          * 1.7 usec delay after the reset is complete.
 524          */
 525         for (i = 0; i < 30; i++) {
 526                 msec_delay(100);
 527                 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
 528                         status = hw->phy.ops.read_reg(hw,
 529                                                   IXGBE_MDIO_TX_VENDOR_ALARMS_3,
 530                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 531                                                   &ctrl);
 532                         if (status != IXGBE_SUCCESS)
 533                                 return status;
 534
 535                         if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
 536                                 usec_delay(2);
 537                                 break;
 538                         }
 539                 } else {
 540                         status = hw->phy.ops.read_reg(hw,
 541                                                      IXGBE_MDIO_PHY_XS_CONTROL,
 542                                                      IXGBE_MDIO_PHY_XS_DEV_TYPE,
 543                                                      &ctrl);
 544                         if (status != IXGBE_SUCCESS)
 545                                 return status;
 546
 547                         if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 548                                 usec_delay(2);
 549                                 break;
 550                         }
 551                 }
 552         }
 553
 554         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 555                 status = IXGBE_ERR_RESET_FAILED;
 556                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 557                              "PHY reset polling failed to complete.\n");
 558         }
 559
 560 out:
 561         return status;
 562 }
 563
 564 /**
 565  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 566  *  the SWFW lock
 567  *  @hw: pointer to hardware structure
 568  *  @reg_addr: 32 bit address of PHY register to read
 569  *  @phy_data: Pointer to read data from PHY register
 570  **/
 571 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 572                        u16 *phy_data)
 573 {
 574         u32 i, data, command;
 575
 576         /* Setup and write the address cycle command */
 577         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 578                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 579                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 580                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 581
 582         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 583
 584         /*
 585          * Check every 10 usec to see if the address cycle completed.
 586          * The MDI Command bit will clear when the operation is
 587          * complete
 588          */
 589         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 590                 usec_delay(10);
 591
 592                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 593                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 594                                 break;
 595         }
 596
 597
 598         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 599                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 600                 return IXGBE_ERR_PHY;
 601         }
 602
 603         /*
 604          * Address cycle complete, setup and write the read
 605          * command
 606          */
 607         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 608                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 609                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 610                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 611
 612         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 613
 614         /*
 615          * Check every 10 usec to see if the address cycle
 616          * completed. The MDI Command bit will clear when the
 617          * operation is complete
 618          */
 619         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 620                 usec_delay(10);
 621
 622                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 623                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 624                         break;
 625         }
 626
 627         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 628                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 629                 return IXGBE_ERR_PHY;
 630         }
 631
 632         /*
 633          * Read operation is complete.  Get the data
 634          * from MSRWD
 635          */
 636         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 637         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 638         *phy_data = (u16)(data);
 639
 640         return IXGBE_SUCCESS;
 641 }
 642
 643 /**
 644  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 645  *  using the SWFW lock - this function is needed in most cases
 646  *  @hw: pointer to hardware structure
 647  *  @reg_addr: 32 bit address of PHY register to read
 648  *  @phy_data: Pointer to read data from PHY register
 649  **/
 650 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 651                                u32 device_type, u16 *phy_data)
 652 {
 653         s32 status;
 654         u32 gssr = hw->phy.phy_semaphore_mask;
 655
 656         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 657
 658         if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
 659                 return IXGBE_ERR_SWFW_SYNC;
 660
 661         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
 662
 663         hw->mac.ops.release_swfw_sync(hw, gssr);
 664
 665         return status;
 666 }
 667
 668 /**
 669  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 670  *  without SWFW lock
 671  *  @hw: pointer to hardware structure
 672  *  @reg_addr: 32 bit PHY register to write
 673  *  @device_type: 5 bit device type
 674  *  @phy_data: Data to write to the PHY register
 675  **/
 676 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 677                                 u32 device_type, u16 phy_data)
 678 {
 679         u32 i, command;
 680
 681         /* Put the data in the MDI single read and write data register*/
 682         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 683
 684         /* Setup and write the address cycle command */
 685         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 686                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 687                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 688                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 689
 690         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 691
 692         /*
 693          * Check every 10 usec to see if the address cycle completed.
 694          * The MDI Command bit will clear when the operation is
 695          * complete
 696          */
 697         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 698                 usec_delay(10);
 699
 700                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 701                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 702                         break;
 703         }
 704
 705         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 706                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 707                 return IXGBE_ERR_PHY;
 708         }
 709
 710         /*
 711          * Address cycle complete, setup and write the write
 712          * command
 713          */
 714         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 715                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 716                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 717                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 718
 719         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 720
 721         /*
 722          * Check every 10 usec to see if the address cycle
 723          * completed. The MDI Command bit will clear when the
 724          * operation is complete
 725          */
 726         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 727                 usec_delay(10);
 728
 729                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 730                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 731                         break;
 732         }
 733
 734         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 735                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 736                 return IXGBE_ERR_PHY;
 737         }
 738
 739         return IXGBE_SUCCESS;
 740 }
 741
 742 /**
 743  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 744  *  using SWFW lock- this function is needed in most cases
 745  *  @hw: pointer to hardware structure
 746  *  @reg_addr: 32 bit PHY register to write
 747  *  @device_type: 5 bit device type
 748  *  @phy_data: Data to write to the PHY register
 749  **/
 750 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 751                                 u32 device_type, u16 phy_data)
 752 {
 753         s32 status;
 754         u32 gssr = hw->phy.phy_semaphore_mask;
 755
 756         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 757
 758         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 759                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
 760                                                  phy_data);
 761                 hw->mac.ops.release_swfw_sync(hw, gssr);
 762         } else {
 763                 status = IXGBE_ERR_SWFW_SYNC;
 764         }
 765
 766         return status;
 767 }
 768
 769 /**
 770  *  ixgbe_setup_phy_link_generic - Set and restart auto-neg
 771  *  @hw: pointer to hardware structure
 772  *
 773  *  Restart auto-negotiation and PHY and waits for completion.
 774  **/
 775 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 776 {
 777         s32 status = IXGBE_SUCCESS;
 778         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 779         bool autoneg = false;
 780         ixgbe_link_speed speed;
 781
 782         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 783
 784         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 785
 786         /* Set or unset auto-negotiation 10G advertisement */
 787         hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 788                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 789                              &autoneg_reg);
 790
 791         autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 792         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
 793             (speed & IXGBE_LINK_SPEED_10GB_FULL))
 794                 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 795
 796         hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 797                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 798                               autoneg_reg);
 799
 800         hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 801                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 802                              &autoneg_reg);
 803
 804         if (hw->mac.type == ixgbe_mac_X550) {
 805                 /* Set or unset auto-negotiation 5G advertisement */
 806                 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
 807                 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
 808                     (speed & IXGBE_LINK_SPEED_5GB_FULL))
 809                         autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
 810
 811                 /* Set or unset auto-negotiation 2.5G advertisement */
 812                 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
 813                 if ((hw->phy.autoneg_advertised &
 814                      IXGBE_LINK_SPEED_2_5GB_FULL) &&
 815                     (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
 816                         autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
 817         }
 818
 819         /* Set or unset auto-negotiation 1G advertisement */
 820         autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 821         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
 822             (speed & IXGBE_LINK_SPEED_1GB_FULL))
 823                 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 824
 825         hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 826                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 827                               autoneg_reg);
 828
 829         /* Set or unset auto-negotiation 100M advertisement */
 830         hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 831                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 832                              &autoneg_reg);
 833
 834         autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 835                          IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 836         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
 837             (speed & IXGBE_LINK_SPEED_100_FULL))
 838                 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 839
 840         hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 841                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 842                               autoneg_reg);
 843
 844         /* Blocked by MNG FW so don't reset PHY */
 845         if (ixgbe_check_reset_blocked(hw))
 846                 return status;
 847
 848         /* Restart PHY auto-negotiation. */
 849         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 850                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 851
 852         autoneg_reg |= IXGBE_MII_RESTART;
 853
 854         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 855                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 856
 857         return status;
 858 }
 859
 860 /**
 861  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 862  *  @hw: pointer to hardware structure
 863  *  @speed: new link speed
 864  **/
 865 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 866                                        ixgbe_link_speed speed,
 867                                        bool autoneg_wait_to_complete)
 868 {
 869         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 870
 871         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 872
 873         /*
 874          * Clear autoneg_advertised and set new values based on input link
 875          * speed.
 876          */
 877         hw->phy.autoneg_advertised = 0;
 878
 879         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 880                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 881
 882         if (speed & IXGBE_LINK_SPEED_5GB_FULL)
 883                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
 884
 885         if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
 886                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
 887
 888         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 889                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 890
 891         if (speed & IXGBE_LINK_SPEED_100_FULL)
 892                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 893
 894         if (speed & IXGBE_LINK_SPEED_10_FULL)
 895                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
 896
 897         /* Setup link based on the new speed settings */
 898         ixgbe_setup_phy_link(hw);
 899
 900         return IXGBE_SUCCESS;
 901 }
 902
 903 /**
 904  * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
 905  * @hw: pointer to hardware structure
 906  *
 907  * Determines the supported link capabilities by reading the PHY auto
 908  * negotiation register.
 909  **/
 910 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
 911 {
 912         s32 status;
 913         u16 speed_ability;
 914
 915         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 916                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 917                                       &speed_ability);
 918         if (status)
 919                 return status;
 920
 921         if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 922                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
 923         if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 924                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
 925         if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 926                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
 927
 928         switch (hw->mac.type) {
 929         case ixgbe_mac_X550:
 930                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
 931                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
 932                 break;
 933         case ixgbe_mac_X550EM_x:
 934         case ixgbe_mac_X550EM_a:
 935                 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
 936                 break;
 937         default:
 938                 break;
 939         }
 940
 941         return status;
 942 }
 943
 944 /**
 945  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 946  *  @hw: pointer to hardware structure
 947  *  @speed: pointer to link speed
 948  *  @autoneg: boolean auto-negotiation value
 949  **/
 950 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 951                                                ixgbe_link_speed *speed,
 952                                                bool *autoneg)
 953 {
 954         s32 status = IXGBE_SUCCESS;
 955
 956         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 957
 958         *autoneg = true;
 959         if (!hw->phy.speeds_supported)
 960                 status = ixgbe_get_copper_speeds_supported(hw);
 961
 962         *speed = hw->phy.speeds_supported;
 963         return status;
 964 }
 965
 966 /**
 967  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 968  *  @hw: pointer to hardware structure
 969  *
 970  *  Reads the VS1 register to determine if link is up and the current speed for
 971  *  the PHY.
 972  **/
 973 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 974                              bool *link_up)
 975 {
 976         s32 status = IXGBE_SUCCESS;
 977         u32 time_out;
 978         u32 max_time_out = 10;
 979         u16 phy_link = 0;
 980         u16 phy_speed = 0;
 981         u16 phy_data = 0;
 982
 983         DEBUGFUNC("ixgbe_check_phy_link_tnx");
 984
 985         /* Initialize speed and link to default case */
 986         *link_up = false;
 987         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 988
 989         /*
 990          * Check current speed and link status of the PHY register.
 991          * This is a vendor specific register and may have to
 992          * be changed for other copper PHYs.
 993          */
 994         for (time_out = 0; time_out < max_time_out; time_out++) {
 995                 usec_delay(10);
 996                 status = hw->phy.ops.read_reg(hw,
 997                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
 998                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 999                                         &phy_data);
1000                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1001                 phy_speed = phy_data &
1002                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1003                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1004                         *link_up = true;
1005                         if (phy_speed ==
1006                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1007                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1008                         break;
1009                 }
1010         }
1011
1012         return status;
1013 }
1014
1015 /**
1016  *      ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1017  *      @hw: pointer to hardware structure
1018  *
1019  *      Restart auto-negotiation and PHY and waits for completion.
1020  **/
1021 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1022 {
1023         s32 status = IXGBE_SUCCESS;
1024         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1025         bool autoneg = false;
1026         ixgbe_link_speed speed;
1027
1028         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1029
1030         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1031
1032         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1033                 /* Set or unset auto-negotiation 10G advertisement */
1034                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1035                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1036                                      &autoneg_reg);
1037
1038                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1039                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1040                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1041
1042                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1043                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1044                                       autoneg_reg);
1045         }
1046
1047         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1048                 /* Set or unset auto-negotiation 1G advertisement */
1049                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1050                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1051                                      &autoneg_reg);
1052
1053                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1054                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1055                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1056
1057                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1058                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1059                                       autoneg_reg);
1060         }
1061
1062         if (speed & IXGBE_LINK_SPEED_100_FULL) {
1063                 /* Set or unset auto-negotiation 100M advertisement */
1064                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1065                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1066                                      &autoneg_reg);
1067
1068                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1069                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1070                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1071
1072                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1073                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1074                                       autoneg_reg);
1075         }
1076
1077         /* Blocked by MNG FW so don't reset PHY */
1078         if (ixgbe_check_reset_blocked(hw))
1079                 return status;
1080
1081         /* Restart PHY auto-negotiation. */
1082         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1083                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1084
1085         autoneg_reg |= IXGBE_MII_RESTART;
1086
1087         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1088                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1089
1090         return status;
1091 }
1092
1093 /**
1094  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1095  *  @hw: pointer to hardware structure
1096  *  @firmware_version: pointer to the PHY Firmware Version
1097  **/
1098 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1099                                        u16 *firmware_version)
1100 {
1101         s32 status;
1102
1103         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1104
1105         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1106                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1107                                       firmware_version);
1108
1109         return status;
1110 }
1111
1112 /**
1113  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1114  *  @hw: pointer to hardware structure
1115  *  @firmware_version: pointer to the PHY Firmware Version
1116  **/
1117 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1118                                            u16 *firmware_version)
1119 {
1120         s32 status;
1121
1122         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1123
1124         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1125                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1126                                       firmware_version);
1127
1128         return status;
1129 }
1130
1131 /**
1132  *  ixgbe_reset_phy_nl - Performs a PHY reset
1133  *  @hw: pointer to hardware structure
1134  **/
1135 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1136 {
1137         u16 phy_offset, control, eword, edata, block_crc;
1138         bool end_data = false;
1139         u16 list_offset, data_offset;
1140         u16 phy_data = 0;
1141         s32 ret_val = IXGBE_SUCCESS;
1142         u32 i;
1143
1144         DEBUGFUNC("ixgbe_reset_phy_nl");
1145
1146         /* Blocked by MNG FW so bail */
1147         if (ixgbe_check_reset_blocked(hw))
1148                 goto out;
1149
1150         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1151                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1152
1153         /* reset the PHY and poll for completion */
1154         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1155                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
1156                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1157
1158         for (i = 0; i < 100; i++) {
1159                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1160                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1161                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1162                         break;
1163                 msec_delay(10);
1164         }
1165
1166         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1167                 DEBUGOUT("PHY reset did not complete.\n");
1168                 ret_val = IXGBE_ERR_PHY;
1169                 goto out;
1170         }
1171
1172         /* Get init offsets */
1173         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1174                                                       &data_offset);
1175         if (ret_val != IXGBE_SUCCESS)
1176                 goto out;
1177
1178         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1179         data_offset++;
1180         while (!end_data) {
1181                 /*
1182                  * Read control word from PHY init contents offset
1183                  */
1184                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1185                 if (ret_val)
1186                         goto err_eeprom;
1187                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1188                            IXGBE_CONTROL_SHIFT_NL;
1189                 edata = eword & IXGBE_DATA_MASK_NL;
1190                 switch (control) {
1191                 case IXGBE_DELAY_NL:
1192                         data_offset++;
1193                         DEBUGOUT1("DELAY: %d MS\n", edata);
1194                         msec_delay(edata);
1195                         break;
1196                 case IXGBE_DATA_NL:
1197                         DEBUGOUT("DATA:\n");
1198                         data_offset++;
1199                         ret_val = hw->eeprom.ops.read(hw, data_offset,
1200                                                       &phy_offset);
1201                         if (ret_val)
1202                                 goto err_eeprom;
1203                         data_offset++;
1204                         for (i = 0; i < edata; i++) {
1205                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
1206                                                               &eword);
1207                                 if (ret_val)
1208                                         goto err_eeprom;
1209                                 hw->phy.ops.write_reg(hw, phy_offset,
1210                                                       IXGBE_TWINAX_DEV, eword);
1211                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1212                                           phy_offset);
1213                                 data_offset++;
1214                                 phy_offset++;
1215                         }
1216                         break;
1217                 case IXGBE_CONTROL_NL:
1218                         data_offset++;
1219                         DEBUGOUT("CONTROL:\n");
1220                         if (edata == IXGBE_CONTROL_EOL_NL) {
1221                                 DEBUGOUT("EOL\n");
1222                                 end_data = true;
1223                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
1224                                 DEBUGOUT("SOL\n");
1225                         } else {
1226                                 DEBUGOUT("Bad control value\n");
1227                                 ret_val = IXGBE_ERR_PHY;
1228                                 goto out;
1229                         }
1230                         break;
1231                 default:
1232                         DEBUGOUT("Bad control type\n");
1233                         ret_val = IXGBE_ERR_PHY;
1234                         goto out;
1235                 }
1236         }
1237
1238 out:
1239         return ret_val;
1240
1241 err_eeprom:
1242         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1243                       "eeprom read at offset %d failed", data_offset);
1244         return IXGBE_ERR_PHY;
1245 }
1246
1247 /**
1248  *  ixgbe_identify_module_generic - Identifies module type
1249  *  @hw: pointer to hardware structure
1250  *
1251  *  Determines HW type and calls appropriate function.
1252  **/
1253 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1254 {
1255         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1256
1257         DEBUGFUNC("ixgbe_identify_module_generic");
1258
1259         switch (hw->mac.ops.get_media_type(hw)) {
1260         case ixgbe_media_type_fiber:
1261                 status = ixgbe_identify_sfp_module_generic(hw);
1262                 break;
1263
1264         case ixgbe_media_type_fiber_qsfp:
1265                 status = ixgbe_identify_qsfp_module_generic(hw);
1266                 break;
1267
1268         default:
1269                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1270                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1271                 break;
1272         }
1273
1274         return status;
1275 }
1276
1277 /**
1278  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1279  *  @hw: pointer to hardware structure
1280  *
1281  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1282  **/
1283 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1284 {
1285         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1286         u32 vendor_oui = 0;
1287         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1288         u8 identifier = 0;
1289         u8 comp_codes_1g = 0;
1290         u8 comp_codes_10g = 0;
1291         u8 oui_bytes[3] = {0, 0, 0};
1292         u8 cable_tech = 0;
1293         u8 cable_spec = 0;
1294         u16 enforce_sfp = 0;
1295
1296         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1297
1298         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1299                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1300                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1301                 goto out;
1302         }
1303
1304         /* LAN ID is needed for I2C access */
1305         hw->mac.ops.set_lan_id(hw);
1306
1307         status = hw->phy.ops.read_i2c_eeprom(hw,
1308                                              IXGBE_SFF_IDENTIFIER,
1309                                              &identifier);
1310
1311         if (status != IXGBE_SUCCESS)
1312                 goto err_read_i2c_eeprom;
1313
1314         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1315                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1316                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1317         } else {
1318                 status = hw->phy.ops.read_i2c_eeprom(hw,
1319                                                      IXGBE_SFF_1GBE_COMP_CODES,
1320                                                      &comp_codes_1g);
1321
1322                 if (status != IXGBE_SUCCESS)
1323                         goto err_read_i2c_eeprom;
1324
1325                 status = hw->phy.ops.read_i2c_eeprom(hw,
1326                                                      IXGBE_SFF_10GBE_COMP_CODES,
1327                                                      &comp_codes_10g);
1328
1329                 if (status != IXGBE_SUCCESS)
1330                         goto err_read_i2c_eeprom;
1331                 status = hw->phy.ops.read_i2c_eeprom(hw,
1332                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1333                                                      &cable_tech);
1334
1335                 if (status != IXGBE_SUCCESS)
1336                         goto err_read_i2c_eeprom;
1337
1338                  /* ID Module
1339                   * =========
1340                   * 0   SFP_DA_CU
1341                   * 1   SFP_SR
1342                   * 2   SFP_LR
1343                   * 3   SFP_DA_CORE0 - 82599-specific
1344                   * 4   SFP_DA_CORE1 - 82599-specific
1345                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1346                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1347                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1348                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1349                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1350                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1351                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1352                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1353                   */
1354                 if (hw->mac.type == ixgbe_mac_82598EB) {
1355                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1356                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1357                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1358                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1359                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1360                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1361                         else
1362                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1363                 } else {
1364                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1365                                 if (hw->bus.lan_id == 0)
1366                                         hw->phy.sfp_type =
1367                                                      ixgbe_sfp_type_da_cu_core0;
1368                                 else
1369                                         hw->phy.sfp_type =
1370                                                      ixgbe_sfp_type_da_cu_core1;
1371                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1372                                 hw->phy.ops.read_i2c_eeprom(
1373                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1374                                                 &cable_spec);
1375                                 if (cable_spec &
1376                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1377                                         if (hw->bus.lan_id == 0)
1378                                                 hw->phy.sfp_type =
1379                                                 ixgbe_sfp_type_da_act_lmt_core0;
1380                                         else
1381                                                 hw->phy.sfp_type =
1382                                                 ixgbe_sfp_type_da_act_lmt_core1;
1383                                 } else {
1384                                         hw->phy.sfp_type =
1385                                                         ixgbe_sfp_type_unknown;
1386                                 }
1387                         } else if (comp_codes_10g &
1388                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1389                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1390                                 if (hw->bus.lan_id == 0)
1391                                         hw->phy.sfp_type =
1392                                                       ixgbe_sfp_type_srlr_core0;
1393                                 else
1394                                         hw->phy.sfp_type =
1395                                                       ixgbe_sfp_type_srlr_core1;
1396                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1397                                 if (hw->bus.lan_id == 0)
1398                                         hw->phy.sfp_type =
1399                                                 ixgbe_sfp_type_1g_cu_core0;
1400                                 else
1401                                         hw->phy.sfp_type =
1402                                                 ixgbe_sfp_type_1g_cu_core1;
1403                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1404                                 if (hw->bus.lan_id == 0)
1405                                         hw->phy.sfp_type =
1406                                                 ixgbe_sfp_type_1g_sx_core0;
1407                                 else
1408                                         hw->phy.sfp_type =
1409                                                 ixgbe_sfp_type_1g_sx_core1;
1410                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1411                                 if (hw->bus.lan_id == 0)
1412                                         hw->phy.sfp_type =
1413                                                 ixgbe_sfp_type_1g_lx_core0;
1414                                 else
1415                                         hw->phy.sfp_type =
1416                                                 ixgbe_sfp_type_1g_lx_core1;
1417                         } else {
1418                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1419                         }
1420                 }
1421
1422                 if (hw->phy.sfp_type != stored_sfp_type)
1423                         hw->phy.sfp_setup_needed = true;
1424
1425                 /* Determine if the SFP+ PHY is dual speed or not. */
1426                 hw->phy.multispeed_fiber = false;
1427                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1428                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1429                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1430                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1431                         hw->phy.multispeed_fiber = true;
1432
1433                 /* Determine PHY vendor */
1434                 if (hw->phy.type != ixgbe_phy_nl) {
1435                         hw->phy.id = identifier;
1436                         status = hw->phy.ops.read_i2c_eeprom(hw,
1437                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1438                                                     &oui_bytes[0]);
1439
1440                         if (status != IXGBE_SUCCESS)
1441                                 goto err_read_i2c_eeprom;
1442
1443                         status = hw->phy.ops.read_i2c_eeprom(hw,
1444                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1445                                                     &oui_bytes[1]);
1446
1447                         if (status != IXGBE_SUCCESS)
1448                                 goto err_read_i2c_eeprom;
1449
1450                         status = hw->phy.ops.read_i2c_eeprom(hw,
1451                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1452                                                     &oui_bytes[2]);
1453
1454                         if (status != IXGBE_SUCCESS)
1455                                 goto err_read_i2c_eeprom;
1456
1457                         vendor_oui =
1458                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1459                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1460                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1461
1462                         switch (vendor_oui) {
1463                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1464                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1465                                         hw->phy.type =
1466                                                     ixgbe_phy_sfp_passive_tyco;
1467                                 break;
1468                         case IXGBE_SFF_VENDOR_OUI_FTL:
1469                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1470                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1471                                 else
1472                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1473                                 break;
1474                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1475                                 hw->phy.type = ixgbe_phy_sfp_avago;
1476                                 break;
1477                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1478                                 hw->phy.type = ixgbe_phy_sfp_intel;
1479                                 break;
1480                         default:
1481                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1482                                         hw->phy.type =
1483                                                  ixgbe_phy_sfp_passive_unknown;
1484                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1485                                         hw->phy.type =
1486                                                 ixgbe_phy_sfp_active_unknown;
1487                                 else
1488                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1489                                 break;
1490                         }
1491                 }
1492
1493                 /* Allow any DA cable vendor */
1494                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1495                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1496                         status = IXGBE_SUCCESS;
1497                         goto out;
1498                 }
1499
1500                 /* Verify supported 1G SFP modules */
1501                 if (comp_codes_10g == 0 &&
1502                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1503                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1504                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1505                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1506                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1507                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1508                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1509                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1510                         goto out;
1511                 }
1512
1513                 /* Anything else 82598-based is supported */
1514                 if (hw->mac.type == ixgbe_mac_82598EB) {
1515                         status = IXGBE_SUCCESS;
1516                         goto out;
1517                 }
1518
1519                 ixgbe_get_device_caps(hw, &enforce_sfp);
1520                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1521                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1522                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1523                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1524                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1525                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1526                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1527                         /* Make sure we're a supported PHY type */
1528                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1529                                 status = IXGBE_SUCCESS;
1530                         } else {
1531                                 if (hw->allow_unsupported_sfp == true) {
1532                                         EWARN(hw, "WARNING: Intel (R) Network "
1533                                               "Connections are quality tested "
1534                                               "using Intel (R) Ethernet Optics."
1535                                               " Using untested modules is not "
1536                                               "supported and may cause unstable"
1537                                               " operation or damage to the "
1538                                               "module or the adapter. Intel "
1539                                               "Corporation is not responsible "
1540                                               "for any harm caused by using "
1541                                               "untested modules.\n", status);
1542                                         status = IXGBE_SUCCESS;
1543                                 } else {
1544                                         DEBUGOUT("SFP+ module not supported\n");
1545                                         hw->phy.type =
1546                                                 ixgbe_phy_sfp_unsupported;
1547                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1548                                 }
1549                         }
1550                 } else {
1551                         status = IXGBE_SUCCESS;
1552                 }
1553         }
1554
1555 out:
1556         return status;
1557
1558 err_read_i2c_eeprom:
1559         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1560         if (hw->phy.type != ixgbe_phy_nl) {
1561                 hw->phy.id = 0;
1562                 hw->phy.type = ixgbe_phy_unknown;
1563         }
1564         return IXGBE_ERR_SFP_NOT_PRESENT;
1565 }
1566
1567 /**
1568  *  ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1569  *  @hw: pointer to hardware structure
1570  *
1571  *  Determines physical layer capabilities of the current SFP.
1572  */
1573 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1574 {
1575         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1576         u8 comp_codes_10g = 0;
1577         u8 comp_codes_1g = 0;
1578
1579         DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1580
1581         hw->phy.ops.identify_sfp(hw);
1582         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1583                 return physical_layer;
1584
1585         switch (hw->phy.type) {
1586         case ixgbe_phy_sfp_passive_tyco:
1587         case ixgbe_phy_sfp_passive_unknown:
1588         case ixgbe_phy_qsfp_passive_unknown:
1589                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1590                 break;
1591         case ixgbe_phy_sfp_ftl_active:
1592         case ixgbe_phy_sfp_active_unknown:
1593         case ixgbe_phy_qsfp_active_unknown:
1594                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1595                 break;
1596         case ixgbe_phy_sfp_avago:
1597         case ixgbe_phy_sfp_ftl:
1598         case ixgbe_phy_sfp_intel:
1599         case ixgbe_phy_sfp_unknown:
1600                 hw->phy.ops.read_i2c_eeprom(hw,
1601                       IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1602                 hw->phy.ops.read_i2c_eeprom(hw,
1603                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1604                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1605                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1606                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1607                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1608                 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1609                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1610                 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1611                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1612                 break;
1613         case ixgbe_phy_qsfp_intel:
1614         case ixgbe_phy_qsfp_unknown:
1615                 hw->phy.ops.read_i2c_eeprom(hw,
1616                       IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1617                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1618                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1619                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1620                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1621                 break;
1622         default:
1623                 break;
1624         }
1625
1626         return physical_layer;
1627 }
1628
1629 /**
1630  *  ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1631  *  @hw: pointer to hardware structure
1632  *
1633  *  Searches for and identifies the QSFP module and assigns appropriate PHY type
1634  **/
1635 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1636 {
1637         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1638         u32 vendor_oui = 0;
1639         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1640         u8 identifier = 0;
1641         u8 comp_codes_1g = 0;
1642         u8 comp_codes_10g = 0;
1643         u8 oui_bytes[3] = {0, 0, 0};
1644         u16 enforce_sfp = 0;
1645         u8 connector = 0;
1646         u8 cable_length = 0;
1647         u8 device_tech = 0;
1648         bool active_cable = false;
1649
1650         DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1651
1652         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1653                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1654                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1655                 goto out;
1656         }
1657
1658         /* LAN ID is needed for I2C access */
1659         hw->mac.ops.set_lan_id(hw);
1660
1661         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1662                                              &identifier);
1663
1664         if (status != IXGBE_SUCCESS)
1665                 goto err_read_i2c_eeprom;
1666
1667         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1668                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1669                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1670                 goto out;
1671         }
1672
1673         hw->phy.id = identifier;
1674
1675         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1676                                              &comp_codes_10g);
1677
1678         if (status != IXGBE_SUCCESS)
1679                 goto err_read_i2c_eeprom;
1680
1681         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1682                                              &comp_codes_1g);
1683
1684         if (status != IXGBE_SUCCESS)
1685                 goto err_read_i2c_eeprom;
1686
1687         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1688                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1689                 if (hw->bus.lan_id == 0)
1690                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1691                 else
1692                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1693         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1694                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1695                 if (hw->bus.lan_id == 0)
1696                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1697                 else
1698                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1699         } else {
1700                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1701                         active_cable = true;
1702
1703                 if (!active_cable) {
1704                         /* check for active DA cables that pre-date
1705                          * SFF-8436 v3.6 */
1706                         hw->phy.ops.read_i2c_eeprom(hw,
1707                                         IXGBE_SFF_QSFP_CONNECTOR,
1708                                         &connector);
1709
1710                         hw->phy.ops.read_i2c_eeprom(hw,
1711                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1712                                         &cable_length);
1713
1714                         hw->phy.ops.read_i2c_eeprom(hw,
1715                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1716                                         &device_tech);
1717
1718                         if ((connector ==
1719                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1720                             (cable_length > 0) &&
1721                             ((device_tech >> 4) ==
1722                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1723                                 active_cable = true;
1724                 }
1725
1726                 if (active_cable) {
1727                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1728                         if (hw->bus.lan_id == 0)
1729                                 hw->phy.sfp_type =
1730                                                 ixgbe_sfp_type_da_act_lmt_core0;
1731                         else
1732                                 hw->phy.sfp_type =
1733                                                 ixgbe_sfp_type_da_act_lmt_core1;
1734                 } else {
1735                         /* unsupported module type */
1736                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1737                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1738                         goto out;
1739                 }
1740         }
1741
1742         if (hw->phy.sfp_type != stored_sfp_type)
1743                 hw->phy.sfp_setup_needed = true;
1744
1745         /* Determine if the QSFP+ PHY is dual speed or not. */
1746         hw->phy.multispeed_fiber = false;
1747         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1748            (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1749            ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1750            (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1751                 hw->phy.multispeed_fiber = true;
1752
1753         /* Determine PHY vendor for optical modules */
1754         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1755                               IXGBE_SFF_10GBASELR_CAPABLE))  {
1756                 status = hw->phy.ops.read_i2c_eeprom(hw,
1757                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1758                                             &oui_bytes[0]);
1759
1760                 if (status != IXGBE_SUCCESS)
1761                         goto err_read_i2c_eeprom;
1762
1763                 status = hw->phy.ops.read_i2c_eeprom(hw,
1764                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1765                                             &oui_bytes[1]);
1766
1767                 if (status != IXGBE_SUCCESS)
1768                         goto err_read_i2c_eeprom;
1769
1770                 status = hw->phy.ops.read_i2c_eeprom(hw,
1771                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1772                                             &oui_bytes[2]);
1773
1774                 if (status != IXGBE_SUCCESS)
1775                         goto err_read_i2c_eeprom;
1776
1777                 vendor_oui =
1778                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1779                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1780                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1781
1782                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1783                         hw->phy.type = ixgbe_phy_qsfp_intel;
1784                 else
1785                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1786
1787                 ixgbe_get_device_caps(hw, &enforce_sfp);
1788                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1789                         /* Make sure we're a supported PHY type */
1790                         if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1791                                 status = IXGBE_SUCCESS;
1792                         } else {
1793                                 if (hw->allow_unsupported_sfp == true) {
1794                                         EWARN(hw, "WARNING: Intel (R) Network "
1795                                               "Connections are quality tested "
1796                                               "using Intel (R) Ethernet Optics."
1797                                               " Using untested modules is not "
1798                                               "supported and may cause unstable"
1799                                               " operation or damage to the "
1800                                               "module or the adapter. Intel "
1801                                               "Corporation is not responsible "
1802                                               "for any harm caused by using "
1803                                               "untested modules.\n", status);
1804                                         status = IXGBE_SUCCESS;
1805                                 } else {
1806                                         DEBUGOUT("QSFP module not supported\n");
1807                                         hw->phy.type =
1808                                                 ixgbe_phy_sfp_unsupported;
1809                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1810                                 }
1811                         }
1812                 } else {
1813                         status = IXGBE_SUCCESS;
1814                 }
1815         }
1816
1817 out:
1818         return status;
1819
1820 err_read_i2c_eeprom:
1821         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1822         hw->phy.id = 0;
1823         hw->phy.type = ixgbe_phy_unknown;
1824
1825         return IXGBE_ERR_SFP_NOT_PRESENT;
1826 }
1827
1828
1829 /**
1830  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1831  *  @hw: pointer to hardware structure
1832  *  @list_offset: offset to the SFP ID list
1833  *  @data_offset: offset to the SFP data block
1834  *
1835  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1836  *  so it returns the offsets to the phy init sequence block.
1837  **/
1838 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1839                                         u16 *list_offset,
1840                                         u16 *data_offset)
1841 {
1842         u16 sfp_id;
1843         u16 sfp_type = hw->phy.sfp_type;
1844
1845         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1846
1847         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1848                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1849
1850         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1851                 return IXGBE_ERR_SFP_NOT_PRESENT;
1852
1853         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1854             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1855                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1856
1857         /*
1858          * Limiting active cables and 1G Phys must be initialized as
1859          * SR modules
1860          */
1861         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1862             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1863             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1864             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1865                 sfp_type = ixgbe_sfp_type_srlr_core0;
1866         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1867                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1868                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1869                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1870                 sfp_type = ixgbe_sfp_type_srlr_core1;
1871
1872         /* Read offset to PHY init contents */
1873         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1874                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1875                               "eeprom read at offset %d failed",
1876                               IXGBE_PHY_INIT_OFFSET_NL);
1877                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1878         }
1879
1880         if ((!*list_offset) || (*list_offset == 0xFFFF))
1881                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1882
1883         /* Shift offset to first ID word */
1884         (*list_offset)++;
1885
1886         /*
1887          * Find the matching SFP ID in the EEPROM
1888          * and program the init sequence
1889          */
1890         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1891                 goto err_phy;
1892
1893         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1894                 if (sfp_id == sfp_type) {
1895                         (*list_offset)++;
1896                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1897                                 goto err_phy;
1898                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1899                                 DEBUGOUT("SFP+ module not supported\n");
1900                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1901                         } else {
1902                                 break;
1903                         }
1904                 } else {
1905                         (*list_offset) += 2;
1906                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1907                                 goto err_phy;
1908                 }
1909         }
1910
1911         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1912                 DEBUGOUT("No matching SFP+ module found\n");
1913                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1914         }
1915
1916         return IXGBE_SUCCESS;
1917
1918 err_phy:
1919         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1920                       "eeprom read at offset %d failed", *list_offset);
1921         return IXGBE_ERR_PHY;
1922 }
1923
1924 /**
1925  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1926  *  @hw: pointer to hardware structure
1927  *  @byte_offset: EEPROM byte offset to read
1928  *  @eeprom_data: value read
1929  *
1930  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1931  **/
1932 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1933                                   u8 *eeprom_data)
1934 {
1935         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1936
1937         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1938                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1939                                          eeprom_data);
1940 }
1941
1942 /**
1943  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1944  *  @hw: pointer to hardware structure
1945  *  @byte_offset: byte offset at address 0xA2
1946  *  @eeprom_data: value read
1947  *
1948  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1949  **/
1950 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1951                                           u8 *sff8472_data)
1952 {
1953         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1954                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1955                                          sff8472_data);
1956 }
1957
1958 /**
1959  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1960  *  @hw: pointer to hardware structure
1961  *  @byte_offset: EEPROM byte offset to write
1962  *  @eeprom_data: value to write
1963  *
1964  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1965  **/
1966 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1967                                    u8 eeprom_data)
1968 {
1969         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1970
1971         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1972                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1973                                           eeprom_data);
1974 }
1975
1976 /**
1977  * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1978  * @hw: pointer to hardware structure
1979  * @offset: eeprom offset to be read
1980  * @addr: I2C address to be read
1981  */
1982 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1983 {
1984         if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1985             offset == IXGBE_SFF_IDENTIFIER &&
1986             hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1987                 return true;
1988         return false;
1989 }
1990
1991 /**
1992  *  ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1993  *  @hw: pointer to hardware structure
1994  *  @byte_offset: byte offset to read
1995  *  @data: value read
1996  *  @lock: true if to take and release semaphore
1997  *
1998  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1999  *  a specified device address.
2000  **/
2001 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2002                                            u8 dev_addr, u8 *data, bool lock)
2003 {
2004         s32 status;
2005         u32 max_retry = 10;
2006         u32 retry = 0;
2007         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2008         bool nack = 1;
2009         *data = 0;
2010
2011         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2012
2013         if (hw->mac.type >= ixgbe_mac_X550)
2014                 max_retry = 3;
2015         if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2016                 max_retry = IXGBE_SFP_DETECT_RETRIES;
2017
2018         do {
2019                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2020                         return IXGBE_ERR_SWFW_SYNC;
2021
2022                 ixgbe_i2c_start(hw);
2023
2024                 /* Device Address and write indication */
2025                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2026                 if (status != IXGBE_SUCCESS)
2027                         goto fail;
2028
2029                 status = ixgbe_get_i2c_ack(hw);
2030                 if (status != IXGBE_SUCCESS)
2031                         goto fail;
2032
2033                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2034                 if (status != IXGBE_SUCCESS)
2035                         goto fail;
2036
2037                 status = ixgbe_get_i2c_ack(hw);
2038                 if (status != IXGBE_SUCCESS)
2039                         goto fail;
2040
2041                 ixgbe_i2c_start(hw);
2042
2043                 /* Device Address and read indication */
2044                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2045                 if (status != IXGBE_SUCCESS)
2046                         goto fail;
2047
2048                 status = ixgbe_get_i2c_ack(hw);
2049                 if (status != IXGBE_SUCCESS)
2050                         goto fail;
2051
2052                 status = ixgbe_clock_in_i2c_byte(hw, data);
2053                 if (status != IXGBE_SUCCESS)
2054                         goto fail;
2055
2056                 status = ixgbe_clock_out_i2c_bit(hw, nack);
2057                 if (status != IXGBE_SUCCESS)
2058                         goto fail;
2059
2060                 ixgbe_i2c_stop(hw);
2061                 if (lock)
2062                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2063                 return IXGBE_SUCCESS;
2064
2065 fail:
2066                 ixgbe_i2c_bus_clear(hw);
2067                 if (lock) {
2068                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2069                         msec_delay(100);
2070                 }
2071                 retry++;
2072                 if (retry < max_retry)
2073                         DEBUGOUT("I2C byte read error - Retrying.\n");
2074                 else
2075                         DEBUGOUT("I2C byte read error.\n");
2076
2077         } while (retry < max_retry);
2078
2079         return status;
2080 }
2081
2082 /**
2083  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2084  *  @hw: pointer to hardware structure
2085  *  @byte_offset: byte offset to read
2086  *  @data: value read
2087  *
2088  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2089  *  a specified device address.
2090  **/
2091 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2092                                 u8 dev_addr, u8 *data)
2093 {
2094         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2095                                                data, true);
2096 }
2097
2098 /**
2099  *  ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2100  *  @hw: pointer to hardware structure
2101  *  @byte_offset: byte offset to read
2102  *  @data: value read
2103  *
2104  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2105  *  a specified device address.
2106  **/
2107 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2108                                          u8 dev_addr, u8 *data)
2109 {
2110         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2111                                                data, false);
2112 }
2113
2114 /**
2115  *  ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2116  *  @hw: pointer to hardware structure
2117  *  @byte_offset: byte offset to write
2118  *  @data: value to write
2119  *  @lock: true if to take and release semaphore
2120  *
2121  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2122  *  a specified device address.
2123  **/
2124 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2125                                             u8 dev_addr, u8 data, bool lock)
2126 {
2127         s32 status;
2128         u32 max_retry = 1;
2129         u32 retry = 0;
2130         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2131
2132         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2133
2134         if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2135             IXGBE_SUCCESS)
2136                 return IXGBE_ERR_SWFW_SYNC;
2137
2138         do {
2139                 ixgbe_i2c_start(hw);
2140
2141                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2142                 if (status != IXGBE_SUCCESS)
2143                         goto fail;
2144
2145                 status = ixgbe_get_i2c_ack(hw);
2146                 if (status != IXGBE_SUCCESS)
2147                         goto fail;
2148
2149                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2150                 if (status != IXGBE_SUCCESS)
2151                         goto fail;
2152
2153                 status = ixgbe_get_i2c_ack(hw);
2154                 if (status != IXGBE_SUCCESS)
2155                         goto fail;
2156
2157                 status = ixgbe_clock_out_i2c_byte(hw, data);
2158                 if (status != IXGBE_SUCCESS)
2159                         goto fail;
2160
2161                 status = ixgbe_get_i2c_ack(hw);
2162                 if (status != IXGBE_SUCCESS)
2163                         goto fail;
2164
2165                 ixgbe_i2c_stop(hw);
2166                 if (lock)
2167                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2168                 return IXGBE_SUCCESS;
2169
2170 fail:
2171                 ixgbe_i2c_bus_clear(hw);
2172                 retry++;
2173                 if (retry < max_retry)
2174                         DEBUGOUT("I2C byte write error - Retrying.\n");
2175                 else
2176                         DEBUGOUT("I2C byte write error.\n");
2177         } while (retry < max_retry);
2178
2179         if (lock)
2180                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2181
2182         return status;
2183 }
2184
2185 /**
2186  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2187  *  @hw: pointer to hardware structure
2188  *  @byte_offset: byte offset to write
2189  *  @data: value to write
2190  *
2191  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2192  *  a specified device address.
2193  **/
2194 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2195                                  u8 dev_addr, u8 data)
2196 {
2197         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2198                                                 data, true);
2199 }
2200
2201 /**
2202  *  ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2203  *  @hw: pointer to hardware structure
2204  *  @byte_offset: byte offset to write
2205  *  @data: value to write
2206  *
2207  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2208  *  a specified device address.
2209  **/
2210 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2211                                           u8 dev_addr, u8 data)
2212 {
2213         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2214                                                 data, false);
2215 }
2216
2217 /**
2218  *  ixgbe_i2c_start - Sets I2C start condition
2219  *  @hw: pointer to hardware structure
2220  *
2221  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
2222  *  Set bit-bang mode on X550 hardware.
2223  **/
2224 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2225 {
2226         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2227
2228         DEBUGFUNC("ixgbe_i2c_start");
2229
2230         i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2231
2232         /* Start condition must begin with data and clock high */
2233         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2234         ixgbe_raise_i2c_clk(hw, &i2cctl);
2235
2236         /* Setup time for start condition (4.7us) */
2237         usec_delay(IXGBE_I2C_T_SU_STA);
2238
2239         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2240
2241         /* Hold time for start condition (4us) */
2242         usec_delay(IXGBE_I2C_T_HD_STA);
2243
2244         ixgbe_lower_i2c_clk(hw, &i2cctl);
2245
2246         /* Minimum low period of clock is 4.7 us */
2247         usec_delay(IXGBE_I2C_T_LOW);
2248
2249 }
2250
2251 /**
2252  *  ixgbe_i2c_stop - Sets I2C stop condition
2253  *  @hw: pointer to hardware structure
2254  *
2255  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
2256  *  Disables bit-bang mode and negates data output enable on X550
2257  *  hardware.
2258  **/
2259 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2260 {
2261         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2262         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2263         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2264         u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2265
2266         DEBUGFUNC("ixgbe_i2c_stop");
2267
2268         /* Stop condition must begin with data low and clock high */
2269         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2270         ixgbe_raise_i2c_clk(hw, &i2cctl);
2271
2272         /* Setup time for stop condition (4us) */
2273         usec_delay(IXGBE_I2C_T_SU_STO);
2274
2275         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2276
2277         /* bus free time between stop and start (4.7us)*/
2278         usec_delay(IXGBE_I2C_T_BUF);
2279
2280         if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2281                 i2cctl &= ~bb_en_bit;
2282                 i2cctl |= data_oe_bit | clk_oe_bit;
2283                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2284                 IXGBE_WRITE_FLUSH(hw);
2285         }
2286 }
2287
2288 /**
2289  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2290  *  @hw: pointer to hardware structure
2291  *  @data: data byte to clock in
2292  *
2293  *  Clocks in one byte data via I2C data/clock
2294  **/
2295 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2296 {
2297         s32 i;
2298         bool bit = 0;
2299
2300         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2301
2302         *data = 0;
2303         for (i = 7; i >= 0; i--) {
2304                 ixgbe_clock_in_i2c_bit(hw, &bit);
2305                 *data |= bit << i;
2306         }
2307
2308         return IXGBE_SUCCESS;
2309 }
2310
2311 /**
2312  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2313  *  @hw: pointer to hardware structure
2314  *  @data: data byte clocked out
2315  *
2316  *  Clocks out one byte data via I2C data/clock
2317  **/
2318 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2319 {
2320         s32 status = IXGBE_SUCCESS;
2321         s32 i;
2322         u32 i2cctl;
2323         bool bit;
2324
2325         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2326
2327         for (i = 7; i >= 0; i--) {
2328                 bit = (data >> i) & 0x1;
2329                 status = ixgbe_clock_out_i2c_bit(hw, bit);
2330
2331                 if (status != IXGBE_SUCCESS)
2332                         break;
2333         }
2334
2335         /* Release SDA line (set high) */
2336         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2337         i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2338         i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2339         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2340         IXGBE_WRITE_FLUSH(hw);
2341
2342         return status;
2343 }
2344
2345 /**
2346  *  ixgbe_get_i2c_ack - Polls for I2C ACK
2347  *  @hw: pointer to hardware structure
2348  *
2349  *  Clocks in/out one bit via I2C data/clock
2350  **/
2351 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2352 {
2353         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2354         s32 status = IXGBE_SUCCESS;
2355         u32 i = 0;
2356         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2357         u32 timeout = 10;
2358         bool ack = 1;
2359
2360         DEBUGFUNC("ixgbe_get_i2c_ack");
2361
2362         if (data_oe_bit) {
2363                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2364                 i2cctl |= data_oe_bit;
2365                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2366                 IXGBE_WRITE_FLUSH(hw);
2367         }
2368         ixgbe_raise_i2c_clk(hw, &i2cctl);
2369
2370         /* Minimum high period of clock is 4us */
2371         usec_delay(IXGBE_I2C_T_HIGH);
2372
2373         /* Poll for ACK.  Note that ACK in I2C spec is
2374          * transition from 1 to 0 */
2375         for (i = 0; i < timeout; i++) {
2376                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2377                 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2378
2379                 usec_delay(1);
2380                 if (!ack)
2381                         break;
2382         }
2383
2384         if (ack) {
2385                 DEBUGOUT("I2C ack was not received.\n");
2386                 status = IXGBE_ERR_I2C;
2387         }
2388
2389         ixgbe_lower_i2c_clk(hw, &i2cctl);
2390
2391         /* Minimum low period of clock is 4.7 us */
2392         usec_delay(IXGBE_I2C_T_LOW);
2393
2394         return status;
2395 }
2396
2397 /**
2398  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2399  *  @hw: pointer to hardware structure
2400  *  @data: read data value
2401  *
2402  *  Clocks in one bit via I2C data/clock
2403  **/
2404 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2405 {
2406         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2407         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2408
2409         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2410
2411         if (data_oe_bit) {
2412                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2413                 i2cctl |= data_oe_bit;
2414                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2415                 IXGBE_WRITE_FLUSH(hw);
2416         }
2417         ixgbe_raise_i2c_clk(hw, &i2cctl);
2418
2419         /* Minimum high period of clock is 4us */
2420         usec_delay(IXGBE_I2C_T_HIGH);
2421
2422         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2423         *data = ixgbe_get_i2c_data(hw, &i2cctl);
2424
2425         ixgbe_lower_i2c_clk(hw, &i2cctl);
2426
2427         /* Minimum low period of clock is 4.7 us */
2428         usec_delay(IXGBE_I2C_T_LOW);
2429
2430         return IXGBE_SUCCESS;
2431 }
2432
2433 /**
2434  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2435  *  @hw: pointer to hardware structure
2436  *  @data: data value to write
2437  *
2438  *  Clocks out one bit via I2C data/clock
2439  **/
2440 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2441 {
2442         s32 status;
2443         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2444
2445         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2446
2447         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2448         if (status == IXGBE_SUCCESS) {
2449                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2450
2451                 /* Minimum high period of clock is 4us */
2452                 usec_delay(IXGBE_I2C_T_HIGH);
2453
2454                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2455
2456                 /* Minimum low period of clock is 4.7 us.
2457                  * This also takes care of the data hold time.
2458                  */
2459                 usec_delay(IXGBE_I2C_T_LOW);
2460         } else {
2461                 status = IXGBE_ERR_I2C;
2462                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2463                              "I2C data was not set to %X\n", data);
2464         }
2465
2466         return status;
2467 }
2468
2469 /**
2470  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2471  *  @hw: pointer to hardware structure
2472  *  @i2cctl: Current value of I2CCTL register
2473  *
2474  *  Raises the I2C clock line '0'->'1'
2475  *  Negates the I2C clock output enable on X550 hardware.
2476  **/
2477 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2478 {
2479         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2480         u32 i = 0;
2481         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2482         u32 i2cctl_r = 0;
2483
2484         DEBUGFUNC("ixgbe_raise_i2c_clk");
2485
2486         if (clk_oe_bit) {
2487                 *i2cctl |= clk_oe_bit;
2488                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2489         }
2490
2491         for (i = 0; i < timeout; i++) {
2492                 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2493
2494                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2495                 IXGBE_WRITE_FLUSH(hw);
2496                 /* SCL rise time (1000ns) */
2497                 usec_delay(IXGBE_I2C_T_RISE);
2498
2499                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2500                 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2501                         break;
2502         }
2503 }
2504
2505 /**
2506  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2507  *  @hw: pointer to hardware structure
2508  *  @i2cctl: Current value of I2CCTL register
2509  *
2510  *  Lowers the I2C clock line '1'->'0'
2511  *  Asserts the I2C clock output enable on X550 hardware.
2512  **/
2513 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2514 {
2515         DEBUGFUNC("ixgbe_lower_i2c_clk");
2516
2517         *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2518         *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2519
2520         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2521         IXGBE_WRITE_FLUSH(hw);
2522
2523         /* SCL fall time (300ns) */
2524         usec_delay(IXGBE_I2C_T_FALL);
2525 }
2526
2527 /**
2528  *  ixgbe_set_i2c_data - Sets the I2C data bit
2529  *  @hw: pointer to hardware structure
2530  *  @i2cctl: Current value of I2CCTL register
2531  *  @data: I2C data value (0 or 1) to set
2532  *
2533  *  Sets the I2C data bit
2534  *  Asserts the I2C data output enable on X550 hardware.
2535  **/
2536 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2537 {
2538         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2539         s32 status = IXGBE_SUCCESS;
2540
2541         DEBUGFUNC("ixgbe_set_i2c_data");
2542
2543         if (data)
2544                 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2545         else
2546                 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2547         *i2cctl &= ~data_oe_bit;
2548
2549         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2550         IXGBE_WRITE_FLUSH(hw);
2551
2552         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2553         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2554
2555         if (!data)      /* Can't verify data in this case */
2556                 return IXGBE_SUCCESS;
2557         if (data_oe_bit) {
2558                 *i2cctl |= data_oe_bit;
2559                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2560                 IXGBE_WRITE_FLUSH(hw);
2561         }
2562
2563         /* Verify data was set correctly */
2564         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2565         if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2566                 status = IXGBE_ERR_I2C;
2567                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2568                              "Error - I2C data was not set to %X.\n",
2569                              data);
2570         }
2571
2572         return status;
2573 }
2574
2575 /**
2576  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2577  *  @hw: pointer to hardware structure
2578  *  @i2cctl: Current value of I2CCTL register
2579  *
2580  *  Returns the I2C data bit value
2581  *  Negates the I2C data output enable on X550 hardware.
2582  **/
2583 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2584 {
2585         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2586         bool data;
2587
2588         DEBUGFUNC("ixgbe_get_i2c_data");
2589
2590         if (data_oe_bit) {
2591                 *i2cctl |= data_oe_bit;
2592                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2593                 IXGBE_WRITE_FLUSH(hw);
2594                 usec_delay(IXGBE_I2C_T_FALL);
2595         }
2596
2597         if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2598                 data = 1;
2599         else
2600                 data = 0;
2601
2602         return data;
2603 }
2604
2605 /**
2606  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2607  *  @hw: pointer to hardware structure
2608  *
2609  *  Clears the I2C bus by sending nine clock pulses.
2610  *  Used when data line is stuck low.
2611  **/
2612 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2613 {
2614         u32 i2cctl;
2615         u32 i;
2616
2617         DEBUGFUNC("ixgbe_i2c_bus_clear");
2618
2619         ixgbe_i2c_start(hw);
2620         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2621
2622         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2623
2624         for (i = 0; i < 9; i++) {
2625                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2626
2627                 /* Min high period of clock is 4us */
2628                 usec_delay(IXGBE_I2C_T_HIGH);
2629
2630                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2631
2632                 /* Min low period of clock is 4.7us*/
2633                 usec_delay(IXGBE_I2C_T_LOW);
2634         }
2635
2636         ixgbe_i2c_start(hw);
2637
2638         /* Put the i2c bus back to default state */
2639         ixgbe_i2c_stop(hw);
2640 }
2641
2642 /**
2643  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2644  *  @hw: pointer to hardware structure
2645  *
2646  *  Checks if the LASI temp alarm status was triggered due to overtemp
2647  **/
2648 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2649 {
2650         s32 status = IXGBE_SUCCESS;
2651         u16 phy_data = 0;
2652
2653         DEBUGFUNC("ixgbe_tn_check_overtemp");
2654
2655         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2656                 goto out;
2657
2658         /* Check that the LASI temp alarm status was triggered */
2659         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2660                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2661
2662         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2663                 goto out;
2664
2665         status = IXGBE_ERR_OVERTEMP;
2666         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2667 out:
2668         return status;
2669 }
2670
2671 /**
2672  * ixgbe_set_copper_phy_power - Control power for copper phy
2673  * @hw: pointer to hardware structure
2674  * @on: true for on, false for off
2675  */
2676 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2677 {
2678         u32 status;
2679         u16 reg;
2680
2681         if (!on && ixgbe_mng_present(hw))
2682                 return 0;
2683
2684         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2685                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2686                                       &reg);
2687         if (status)
2688                 return status;
2689
2690         if (on) {
2691                 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2692         } else {
2693                 if (ixgbe_check_reset_blocked(hw))
2694                         return 0;
2695                 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2696         }
2697
2698         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2699                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2700                                        reg);
2701         return status;
2702 }