1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
6 #include "ixgbe_common.h"
9 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
10 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
11 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
12 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
13 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
14 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
15 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
16 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
17 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
18 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
19 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
20 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
24 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
25 * @hw: pointer to the hardware structure
28 * Returns an error code on error.
30 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
34 status = ixgbe_clock_out_i2c_byte(hw, byte);
37 return ixgbe_get_i2c_ack(hw);
41 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
42 * @hw: pointer to the hardware structure
43 * @byte: pointer to a u8 to receive the byte
45 * Returns an error code on error.
47 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
51 status = ixgbe_clock_in_i2c_byte(hw, byte);
55 return ixgbe_clock_out_i2c_bit(hw, false);
59 * ixgbe_ones_comp_byte_add - Perform one's complement addition
63 * Returns one's complement 8-bit sum.
65 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
67 u16 sum = add1 + add2;
69 sum = (sum & 0xFF) + (sum >> 8);
74 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
75 * @hw: pointer to the hardware structure
76 * @addr: I2C bus address to read from
77 * @reg: I2C device register to read from
78 * @val: pointer to location to receive read value
79 * @lock: true if to take and release semaphore
81 * Returns an error code on error.
83 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
86 u32 swfw_mask = hw->phy.phy_semaphore_mask;
95 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
96 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
99 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
100 return IXGBE_ERR_SWFW_SYNC;
102 /* Device Address and write indication */
103 if (ixgbe_out_i2c_byte_ack(hw, addr))
105 /* Write bits 14:8 */
106 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
109 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
112 if (ixgbe_out_i2c_byte_ack(hw, csum))
114 /* Re-start condition */
116 /* Device Address and read indication */
117 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
120 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
123 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
126 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
129 if (ixgbe_clock_out_i2c_bit(hw, false))
133 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
134 *val = (high_bits << 8) | low_bits;
138 ixgbe_i2c_bus_clear(hw);
140 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
142 if (retry < max_retry)
143 DEBUGOUT("I2C byte read combined error - Retrying.\n");
145 DEBUGOUT("I2C byte read combined error.\n");
146 } while (retry < max_retry);
148 return IXGBE_ERR_I2C;
152 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
153 * @hw: pointer to the hardware structure
154 * @addr: I2C bus address to write to
155 * @reg: I2C device register to write to
156 * @val: value to write
157 * @lock: true if to take and release semaphore
159 * Returns an error code on error.
161 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
164 u32 swfw_mask = hw->phy.phy_semaphore_mask;
170 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
171 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
172 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
173 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
176 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
177 return IXGBE_ERR_SWFW_SYNC;
179 /* Device Address and write indication */
180 if (ixgbe_out_i2c_byte_ack(hw, addr))
182 /* Write bits 14:8 */
183 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
186 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
188 /* Write data 15:8 */
189 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
192 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
195 if (ixgbe_out_i2c_byte_ack(hw, csum))
199 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
203 ixgbe_i2c_bus_clear(hw);
205 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
207 if (retry < max_retry)
208 DEBUGOUT("I2C byte write combined error - Retrying.\n");
210 DEBUGOUT("I2C byte write combined error.\n");
211 } while (retry < max_retry);
213 return IXGBE_ERR_I2C;
217 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
218 * @hw: pointer to the hardware structure
220 * Initialize the function pointers.
222 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
224 struct ixgbe_phy_info *phy = &hw->phy;
226 DEBUGFUNC("ixgbe_init_phy_ops_generic");
229 phy->ops.identify = ixgbe_identify_phy_generic;
230 phy->ops.reset = ixgbe_reset_phy_generic;
231 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
232 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
233 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
234 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
235 phy->ops.setup_link = ixgbe_setup_phy_link_generic;
236 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
237 phy->ops.check_link = NULL;
238 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
239 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
240 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
241 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
242 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
243 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
244 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
245 phy->ops.identify_sfp = ixgbe_identify_module_generic;
246 phy->sfp_type = ixgbe_sfp_type_unknown;
247 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
248 phy->ops.write_i2c_byte_unlocked =
249 ixgbe_write_i2c_byte_generic_unlocked;
250 phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
251 return IXGBE_SUCCESS;
255 * ixgbe_probe_phy - Probe a single address for a PHY
256 * @hw: pointer to hardware structure
257 * @phy_addr: PHY address to probe
259 * Returns true if PHY found
261 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
265 if (!ixgbe_validate_phy_addr(hw, phy_addr)) {
266 DEBUGOUT1("Unable to validate PHY address 0x%04X\n",
271 if (ixgbe_get_phy_id(hw))
274 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
276 if (hw->phy.type == ixgbe_phy_unknown) {
277 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
278 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
280 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
281 IXGBE_MDIO_PHY_1000BASET_ABILITY))
282 hw->phy.type = ixgbe_phy_cu_unknown;
284 hw->phy.type = ixgbe_phy_generic;
291 * ixgbe_identify_phy_generic - Get physical layer module
292 * @hw: pointer to hardware structure
294 * Determines the physical layer module found on the current adapter.
296 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
298 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
301 DEBUGFUNC("ixgbe_identify_phy_generic");
303 if (!hw->phy.phy_semaphore_mask) {
305 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
307 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
310 if (hw->phy.type != ixgbe_phy_unknown)
311 return IXGBE_SUCCESS;
313 if (hw->phy.nw_mng_if_sel) {
314 phy_addr = (hw->phy.nw_mng_if_sel &
315 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
316 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
317 if (ixgbe_probe_phy(hw, phy_addr))
318 return IXGBE_SUCCESS;
320 return IXGBE_ERR_PHY_ADDR_INVALID;
323 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
324 if (ixgbe_probe_phy(hw, phy_addr)) {
325 status = IXGBE_SUCCESS;
330 /* Certain media types do not have a phy so an address will not
331 * be found and the code will take this path. Caller has to
332 * decide if it is an error or not.
334 if (status != IXGBE_SUCCESS)
341 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
342 * @hw: pointer to the hardware structure
344 * This function checks the MMNGC.MNG_VETO bit to see if there are
345 * any constraints on link from manageability. For MAC's that don't
346 * have this bit just return faluse since the link can not be blocked
349 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
353 DEBUGFUNC("ixgbe_check_reset_blocked");
355 /* If we don't have this bit, it can't be blocking */
356 if (hw->mac.type == ixgbe_mac_82598EB)
359 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
360 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
361 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
362 "MNG_VETO bit detected.\n");
370 * ixgbe_validate_phy_addr - Determines phy address is valid
371 * @hw: pointer to hardware structure
372 * @phy_addr: PHY address
375 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
380 DEBUGFUNC("ixgbe_validate_phy_addr");
382 hw->phy.addr = phy_addr;
383 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
384 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
386 if (phy_id != 0xFFFF && phy_id != 0x0)
389 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id);
395 * ixgbe_get_phy_id - Get the phy type
396 * @hw: pointer to hardware structure
399 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
405 DEBUGFUNC("ixgbe_get_phy_id");
407 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
408 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
411 if (status == IXGBE_SUCCESS) {
412 hw->phy.id = (u32)(phy_id_high << 16);
413 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
414 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
416 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
417 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
419 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
420 phy_id_high, phy_id_low);
426 * ixgbe_get_phy_type_from_id - Get the phy type
427 * @phy_id: PHY ID information
430 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
432 enum ixgbe_phy_type phy_type;
434 DEBUGFUNC("ixgbe_get_phy_type_from_id");
438 phy_type = ixgbe_phy_tn;
443 phy_type = ixgbe_phy_aq;
446 phy_type = ixgbe_phy_qt;
449 phy_type = ixgbe_phy_nl;
453 phy_type = ixgbe_phy_x550em_ext_t;
455 case IXGBE_M88E1500_E_PHY_ID:
456 case IXGBE_M88E1543_E_PHY_ID:
457 phy_type = ixgbe_phy_ext_1g_t;
460 phy_type = ixgbe_phy_unknown;
467 * ixgbe_reset_phy_generic - Performs a PHY reset
468 * @hw: pointer to hardware structure
470 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
474 s32 status = IXGBE_SUCCESS;
476 DEBUGFUNC("ixgbe_reset_phy_generic");
478 if (hw->phy.type == ixgbe_phy_unknown)
479 status = ixgbe_identify_phy_generic(hw);
481 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
484 /* Don't reset PHY if it's shut down due to overtemp. */
485 if (!hw->phy.reset_if_overtemp &&
486 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
489 /* Blocked by MNG FW so bail */
490 if (ixgbe_check_reset_blocked(hw))
494 * Perform soft PHY reset to the PHY_XS.
495 * This will cause a soft reset to the PHY
497 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
498 IXGBE_MDIO_PHY_XS_DEV_TYPE,
499 IXGBE_MDIO_PHY_XS_RESET);
502 * Poll for reset bit to self-clear indicating reset is complete.
503 * Some PHYs could take up to 3 seconds to complete and need about
504 * 1.7 usec delay after the reset is complete.
506 for (i = 0; i < 30; i++) {
508 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
509 status = hw->phy.ops.read_reg(hw,
510 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
511 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
513 if (status != IXGBE_SUCCESS)
516 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
521 status = hw->phy.ops.read_reg(hw,
522 IXGBE_MDIO_PHY_XS_CONTROL,
523 IXGBE_MDIO_PHY_XS_DEV_TYPE,
525 if (status != IXGBE_SUCCESS)
528 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
535 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
536 status = IXGBE_ERR_RESET_FAILED;
537 ERROR_REPORT1(IXGBE_ERROR_POLLING,
538 "PHY reset polling failed to complete.\n");
546 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
548 * @hw: pointer to hardware structure
549 * @reg_addr: 32 bit address of PHY register to read
550 * @device_type: 5 bit device type
551 * @phy_data: Pointer to read data from PHY register
553 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
556 u32 i, data, command;
558 /* Setup and write the address cycle command */
559 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
560 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
561 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
562 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
564 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
567 * Check every 10 usec to see if the address cycle completed.
568 * The MDI Command bit will clear when the operation is
571 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
574 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
575 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
580 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
581 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
582 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n");
583 return IXGBE_ERR_PHY;
587 * Address cycle complete, setup and write the read
590 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
591 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
592 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
593 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
595 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
598 * Check every 10 usec to see if the address cycle
599 * completed. The MDI Command bit will clear when the
600 * operation is complete
602 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
605 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
606 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
610 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
611 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
612 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n");
613 return IXGBE_ERR_PHY;
617 * Read operation is complete. Get the data
620 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
621 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
622 *phy_data = (u16)(data);
624 return IXGBE_SUCCESS;
628 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
629 * using the SWFW lock - this function is needed in most cases
630 * @hw: pointer to hardware structure
631 * @reg_addr: 32 bit address of PHY register to read
632 * @device_type: 5 bit device type
633 * @phy_data: Pointer to read data from PHY register
635 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
636 u32 device_type, u16 *phy_data)
639 u32 gssr = hw->phy.phy_semaphore_mask;
641 DEBUGFUNC("ixgbe_read_phy_reg_generic");
643 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
644 return IXGBE_ERR_SWFW_SYNC;
646 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
648 hw->mac.ops.release_swfw_sync(hw, gssr);
654 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
656 * @hw: pointer to hardware structure
657 * @reg_addr: 32 bit PHY register to write
658 * @device_type: 5 bit device type
659 * @phy_data: Data to write to the PHY register
661 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
662 u32 device_type, u16 phy_data)
666 /* Put the data in the MDI single read and write data register*/
667 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
669 /* Setup and write the address cycle command */
670 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
671 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
672 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
673 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
675 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
678 * Check every 10 usec to see if the address cycle completed.
679 * The MDI Command bit will clear when the operation is
682 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
685 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
686 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
690 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
691 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
692 return IXGBE_ERR_PHY;
696 * Address cycle complete, setup and write the write
699 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
700 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
701 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
702 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
704 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
707 * Check every 10 usec to see if the address cycle
708 * completed. The MDI Command bit will clear when the
709 * operation is complete
711 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
714 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
715 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
719 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
720 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
721 return IXGBE_ERR_PHY;
724 return IXGBE_SUCCESS;
728 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
729 * using SWFW lock- this function is needed in most cases
730 * @hw: pointer to hardware structure
731 * @reg_addr: 32 bit PHY register to write
732 * @device_type: 5 bit device type
733 * @phy_data: Data to write to the PHY register
735 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
736 u32 device_type, u16 phy_data)
739 u32 gssr = hw->phy.phy_semaphore_mask;
741 DEBUGFUNC("ixgbe_write_phy_reg_generic");
743 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
744 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
746 hw->mac.ops.release_swfw_sync(hw, gssr);
748 status = IXGBE_ERR_SWFW_SYNC;
755 * ixgbe_setup_phy_link_generic - Set and restart auto-neg
756 * @hw: pointer to hardware structure
758 * Restart auto-negotiation and PHY and waits for completion.
760 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
762 s32 status = IXGBE_SUCCESS;
763 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
764 bool autoneg = false;
765 ixgbe_link_speed speed;
767 DEBUGFUNC("ixgbe_setup_phy_link_generic");
769 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
771 /* Set or unset auto-negotiation 10G advertisement */
772 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
773 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
776 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
777 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
778 (speed & IXGBE_LINK_SPEED_10GB_FULL))
779 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
781 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
782 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
785 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
786 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
789 if (hw->mac.type == ixgbe_mac_X550) {
790 /* Set or unset auto-negotiation 5G advertisement */
791 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
792 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
793 (speed & IXGBE_LINK_SPEED_5GB_FULL))
794 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
796 /* Set or unset auto-negotiation 2.5G advertisement */
797 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
798 if ((hw->phy.autoneg_advertised &
799 IXGBE_LINK_SPEED_2_5GB_FULL) &&
800 (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
801 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
804 /* Set or unset auto-negotiation 1G advertisement */
805 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
806 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
807 (speed & IXGBE_LINK_SPEED_1GB_FULL))
808 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
810 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
811 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
814 /* Set or unset auto-negotiation 100M advertisement */
815 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
816 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
819 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
820 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
821 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
822 (speed & IXGBE_LINK_SPEED_100_FULL))
823 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
825 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
826 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
829 /* Blocked by MNG FW so don't reset PHY */
830 if (ixgbe_check_reset_blocked(hw))
833 /* Restart PHY auto-negotiation. */
834 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
835 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
837 autoneg_reg |= IXGBE_MII_RESTART;
839 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
840 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
846 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
847 * @hw: pointer to hardware structure
848 * @speed: new link speed
849 * @autoneg_wait_to_complete: unused
851 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
852 ixgbe_link_speed speed,
853 bool autoneg_wait_to_complete)
855 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
857 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
860 * Clear autoneg_advertised and set new values based on input link
863 hw->phy.autoneg_advertised = 0;
865 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
866 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
868 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
869 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
871 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
872 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
874 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
875 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
877 if (speed & IXGBE_LINK_SPEED_100_FULL)
878 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
880 if (speed & IXGBE_LINK_SPEED_10_FULL)
881 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
883 /* Setup link based on the new speed settings */
884 ixgbe_setup_phy_link(hw);
886 return IXGBE_SUCCESS;
890 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
891 * @hw: pointer to hardware structure
893 * Determines the supported link capabilities by reading the PHY auto
894 * negotiation register.
896 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
901 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
902 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
907 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
908 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
909 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
910 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
911 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
912 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
914 switch (hw->mac.type) {
916 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
917 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
919 case ixgbe_mac_X550EM_x:
920 case ixgbe_mac_X550EM_a:
921 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
931 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
932 * @hw: pointer to hardware structure
933 * @speed: pointer to link speed
934 * @autoneg: boolean auto-negotiation value
936 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
937 ixgbe_link_speed *speed,
940 s32 status = IXGBE_SUCCESS;
942 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
945 if (!hw->phy.speeds_supported)
946 status = ixgbe_get_copper_speeds_supported(hw);
948 *speed = hw->phy.speeds_supported;
953 * ixgbe_check_phy_link_tnx - Determine link and speed status
954 * @hw: pointer to hardware structure
955 * @speed: current link speed
956 * @link_up: true is link is up, false otherwise
958 * Reads the VS1 register to determine if link is up and the current speed for
961 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
964 s32 status = IXGBE_SUCCESS;
966 u32 max_time_out = 10;
971 DEBUGFUNC("ixgbe_check_phy_link_tnx");
973 /* Initialize speed and link to default case */
975 *speed = IXGBE_LINK_SPEED_10GB_FULL;
978 * Check current speed and link status of the PHY register.
979 * This is a vendor specific register and may have to
980 * be changed for other copper PHYs.
982 for (time_out = 0; time_out < max_time_out; time_out++) {
984 status = hw->phy.ops.read_reg(hw,
985 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
986 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
988 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
989 phy_speed = phy_data &
990 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
991 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
994 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
995 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1004 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1005 * @hw: pointer to hardware structure
1007 * Restart auto-negotiation and PHY and waits for completion.
1009 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1011 s32 status = IXGBE_SUCCESS;
1012 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1013 bool autoneg = false;
1014 ixgbe_link_speed speed;
1016 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1018 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1020 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1021 /* Set or unset auto-negotiation 10G advertisement */
1022 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1023 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1026 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1027 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1028 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1030 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1031 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1035 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1036 /* Set or unset auto-negotiation 1G advertisement */
1037 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1038 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1041 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1042 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1043 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1045 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1046 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1050 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1051 /* Set or unset auto-negotiation 100M advertisement */
1052 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1053 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1056 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1057 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1058 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1060 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1061 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1065 /* Blocked by MNG FW so don't reset PHY */
1066 if (ixgbe_check_reset_blocked(hw))
1069 /* Restart PHY auto-negotiation. */
1070 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1071 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1073 autoneg_reg |= IXGBE_MII_RESTART;
1075 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1076 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1082 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1083 * @hw: pointer to hardware structure
1084 * @firmware_version: pointer to the PHY Firmware Version
1086 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1087 u16 *firmware_version)
1091 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1093 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1094 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1101 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1102 * @hw: pointer to hardware structure
1103 * @firmware_version: pointer to the PHY Firmware Version
1105 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1106 u16 *firmware_version)
1110 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1112 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1113 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1120 * ixgbe_reset_phy_nl - Performs a PHY reset
1121 * @hw: pointer to hardware structure
1123 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1125 u16 phy_offset, control, eword, edata, block_crc;
1126 bool end_data = false;
1127 u16 list_offset, data_offset;
1129 s32 ret_val = IXGBE_SUCCESS;
1132 DEBUGFUNC("ixgbe_reset_phy_nl");
1134 /* Blocked by MNG FW so bail */
1135 if (ixgbe_check_reset_blocked(hw))
1138 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1139 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1141 /* reset the PHY and poll for completion */
1142 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1143 IXGBE_MDIO_PHY_XS_DEV_TYPE,
1144 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1146 for (i = 0; i < 100; i++) {
1147 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1148 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1149 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1154 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1155 DEBUGOUT("PHY reset did not complete.\n");
1156 ret_val = IXGBE_ERR_PHY;
1160 /* Get init offsets */
1161 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1163 if (ret_val != IXGBE_SUCCESS)
1166 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1170 * Read control word from PHY init contents offset
1172 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1175 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1176 IXGBE_CONTROL_SHIFT_NL;
1177 edata = eword & IXGBE_DATA_MASK_NL;
1179 case IXGBE_DELAY_NL:
1181 DEBUGOUT1("DELAY: %d MS\n", edata);
1185 DEBUGOUT("DATA:\n");
1187 ret_val = hw->eeprom.ops.read(hw, data_offset,
1192 for (i = 0; i < edata; i++) {
1193 ret_val = hw->eeprom.ops.read(hw, data_offset,
1197 hw->phy.ops.write_reg(hw, phy_offset,
1198 IXGBE_TWINAX_DEV, eword);
1199 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1205 case IXGBE_CONTROL_NL:
1207 DEBUGOUT("CONTROL:\n");
1208 if (edata == IXGBE_CONTROL_EOL_NL) {
1211 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1214 DEBUGOUT("Bad control value\n");
1215 ret_val = IXGBE_ERR_PHY;
1220 DEBUGOUT("Bad control type\n");
1221 ret_val = IXGBE_ERR_PHY;
1230 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1231 "eeprom read at offset %d failed", data_offset);
1232 return IXGBE_ERR_PHY;
1236 * ixgbe_identify_module_generic - Identifies module type
1237 * @hw: pointer to hardware structure
1239 * Determines HW type and calls appropriate function.
1241 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1243 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1245 DEBUGFUNC("ixgbe_identify_module_generic");
1247 switch (hw->mac.ops.get_media_type(hw)) {
1248 case ixgbe_media_type_fiber:
1249 status = ixgbe_identify_sfp_module_generic(hw);
1252 case ixgbe_media_type_fiber_qsfp:
1253 status = ixgbe_identify_qsfp_module_generic(hw);
1257 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1258 status = IXGBE_ERR_SFP_NOT_PRESENT;
1266 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1267 * @hw: pointer to hardware structure
1269 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1271 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1273 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1275 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1277 u8 comp_codes_1g = 0;
1278 u8 comp_codes_10g = 0;
1279 u8 oui_bytes[3] = {0, 0, 0};
1282 u16 enforce_sfp = 0;
1284 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1286 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1287 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1288 status = IXGBE_ERR_SFP_NOT_PRESENT;
1292 /* LAN ID is needed for I2C access */
1293 hw->mac.ops.set_lan_id(hw);
1295 status = hw->phy.ops.read_i2c_eeprom(hw,
1296 IXGBE_SFF_IDENTIFIER,
1299 if (status != IXGBE_SUCCESS)
1300 goto err_read_i2c_eeprom;
1302 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1303 hw->phy.type = ixgbe_phy_sfp_unsupported;
1304 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1306 status = hw->phy.ops.read_i2c_eeprom(hw,
1307 IXGBE_SFF_1GBE_COMP_CODES,
1310 if (status != IXGBE_SUCCESS)
1311 goto err_read_i2c_eeprom;
1313 status = hw->phy.ops.read_i2c_eeprom(hw,
1314 IXGBE_SFF_10GBE_COMP_CODES,
1317 if (status != IXGBE_SUCCESS)
1318 goto err_read_i2c_eeprom;
1319 status = hw->phy.ops.read_i2c_eeprom(hw,
1320 IXGBE_SFF_CABLE_TECHNOLOGY,
1323 if (status != IXGBE_SUCCESS)
1324 goto err_read_i2c_eeprom;
1331 * 3 SFP_DA_CORE0 - 82599-specific
1332 * 4 SFP_DA_CORE1 - 82599-specific
1333 * 5 SFP_SR/LR_CORE0 - 82599-specific
1334 * 6 SFP_SR/LR_CORE1 - 82599-specific
1335 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1336 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1337 * 9 SFP_1g_cu_CORE0 - 82599-specific
1338 * 10 SFP_1g_cu_CORE1 - 82599-specific
1339 * 11 SFP_1g_sx_CORE0 - 82599-specific
1340 * 12 SFP_1g_sx_CORE1 - 82599-specific
1342 if (hw->mac.type == ixgbe_mac_82598EB) {
1343 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1344 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1345 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1346 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1347 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1348 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1350 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1352 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1353 if (hw->bus.lan_id == 0)
1355 ixgbe_sfp_type_da_cu_core0;
1358 ixgbe_sfp_type_da_cu_core1;
1359 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1360 hw->phy.ops.read_i2c_eeprom(
1361 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1364 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1365 if (hw->bus.lan_id == 0)
1367 ixgbe_sfp_type_da_act_lmt_core0;
1370 ixgbe_sfp_type_da_act_lmt_core1;
1373 ixgbe_sfp_type_unknown;
1375 } else if (comp_codes_10g &
1376 (IXGBE_SFF_10GBASESR_CAPABLE |
1377 IXGBE_SFF_10GBASELR_CAPABLE)) {
1378 if (hw->bus.lan_id == 0)
1380 ixgbe_sfp_type_srlr_core0;
1383 ixgbe_sfp_type_srlr_core1;
1384 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1385 if (hw->bus.lan_id == 0)
1387 ixgbe_sfp_type_1g_cu_core0;
1390 ixgbe_sfp_type_1g_cu_core1;
1391 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1392 if (hw->bus.lan_id == 0)
1394 ixgbe_sfp_type_1g_sx_core0;
1397 ixgbe_sfp_type_1g_sx_core1;
1398 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1399 if (hw->bus.lan_id == 0)
1401 ixgbe_sfp_type_1g_lx_core0;
1404 ixgbe_sfp_type_1g_lx_core1;
1405 } else if (comp_codes_1g & IXGBE_SFF_1GBASELHA_CAPABLE) {
1406 if (hw->bus.lan_id == 0)
1408 ixgbe_sfp_type_1g_lha_core0;
1411 ixgbe_sfp_type_1g_lha_core1;
1413 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1417 if (hw->phy.sfp_type != stored_sfp_type)
1418 hw->phy.sfp_setup_needed = true;
1420 /* Determine if the SFP+ PHY is dual speed or not. */
1421 hw->phy.multispeed_fiber = false;
1422 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1423 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1424 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1425 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1426 hw->phy.multispeed_fiber = true;
1428 /* Determine PHY vendor */
1429 if (hw->phy.type != ixgbe_phy_nl) {
1430 hw->phy.id = identifier;
1431 status = hw->phy.ops.read_i2c_eeprom(hw,
1432 IXGBE_SFF_VENDOR_OUI_BYTE0,
1435 if (status != IXGBE_SUCCESS)
1436 goto err_read_i2c_eeprom;
1438 status = hw->phy.ops.read_i2c_eeprom(hw,
1439 IXGBE_SFF_VENDOR_OUI_BYTE1,
1442 if (status != IXGBE_SUCCESS)
1443 goto err_read_i2c_eeprom;
1445 status = hw->phy.ops.read_i2c_eeprom(hw,
1446 IXGBE_SFF_VENDOR_OUI_BYTE2,
1449 if (status != IXGBE_SUCCESS)
1450 goto err_read_i2c_eeprom;
1453 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1454 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1455 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1457 switch (vendor_oui) {
1458 case IXGBE_SFF_VENDOR_OUI_TYCO:
1459 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1461 ixgbe_phy_sfp_passive_tyco;
1463 case IXGBE_SFF_VENDOR_OUI_FTL:
1464 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1465 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1467 hw->phy.type = ixgbe_phy_sfp_ftl;
1469 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1470 hw->phy.type = ixgbe_phy_sfp_avago;
1472 case IXGBE_SFF_VENDOR_OUI_INTEL:
1473 hw->phy.type = ixgbe_phy_sfp_intel;
1476 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1478 ixgbe_phy_sfp_passive_unknown;
1479 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1481 ixgbe_phy_sfp_active_unknown;
1483 hw->phy.type = ixgbe_phy_sfp_unknown;
1488 /* Allow any DA cable vendor */
1489 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1490 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1491 status = IXGBE_SUCCESS;
1495 /* Verify supported 1G SFP modules */
1496 if (comp_codes_10g == 0 &&
1497 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1498 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1499 hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core0 ||
1500 hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core1 ||
1501 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1502 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1503 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1504 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1505 hw->phy.type = ixgbe_phy_sfp_unsupported;
1506 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1510 /* Anything else 82598-based is supported */
1511 if (hw->mac.type == ixgbe_mac_82598EB) {
1512 status = IXGBE_SUCCESS;
1516 ixgbe_get_device_caps(hw, &enforce_sfp);
1517 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1518 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1519 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1520 hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core0 ||
1521 hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core1 ||
1522 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1523 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1524 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1525 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1526 /* Make sure we're a supported PHY type */
1527 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1528 status = IXGBE_SUCCESS;
1530 if (hw->allow_unsupported_sfp == true) {
1532 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. "
1533 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1534 "Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1535 status = IXGBE_SUCCESS;
1537 DEBUGOUT("SFP+ module not supported\n");
1539 ixgbe_phy_sfp_unsupported;
1540 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1544 status = IXGBE_SUCCESS;
1551 err_read_i2c_eeprom:
1552 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1553 if (hw->phy.type != ixgbe_phy_nl) {
1555 hw->phy.type = ixgbe_phy_unknown;
1557 return IXGBE_ERR_SFP_NOT_PRESENT;
1561 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1562 * @hw: pointer to hardware structure
1564 * Determines physical layer capabilities of the current SFP.
1566 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1568 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1569 u8 comp_codes_10g = 0;
1570 u8 comp_codes_1g = 0;
1572 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1574 hw->phy.ops.identify_sfp(hw);
1575 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1576 return physical_layer;
1578 switch (hw->phy.type) {
1579 case ixgbe_phy_sfp_passive_tyco:
1580 case ixgbe_phy_sfp_passive_unknown:
1581 case ixgbe_phy_qsfp_passive_unknown:
1582 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1584 case ixgbe_phy_sfp_ftl_active:
1585 case ixgbe_phy_sfp_active_unknown:
1586 case ixgbe_phy_qsfp_active_unknown:
1587 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1589 case ixgbe_phy_sfp_avago:
1590 case ixgbe_phy_sfp_ftl:
1591 case ixgbe_phy_sfp_intel:
1592 case ixgbe_phy_sfp_unknown:
1593 hw->phy.ops.read_i2c_eeprom(hw,
1594 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1595 hw->phy.ops.read_i2c_eeprom(hw,
1596 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1597 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1598 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1599 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1600 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1601 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1602 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1603 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1604 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1606 case ixgbe_phy_qsfp_intel:
1607 case ixgbe_phy_qsfp_unknown:
1608 hw->phy.ops.read_i2c_eeprom(hw,
1609 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1610 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1611 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1612 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1613 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1619 return physical_layer;
1623 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1624 * @hw: pointer to hardware structure
1626 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1628 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1630 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1632 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1634 u8 comp_codes_1g = 0;
1635 u8 comp_codes_10g = 0;
1636 u8 oui_bytes[3] = {0, 0, 0};
1637 u16 enforce_sfp = 0;
1639 u8 cable_length = 0;
1641 bool active_cable = false;
1643 DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1645 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1646 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1647 status = IXGBE_ERR_SFP_NOT_PRESENT;
1651 /* LAN ID is needed for I2C access */
1652 hw->mac.ops.set_lan_id(hw);
1654 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1657 if (status != IXGBE_SUCCESS)
1658 goto err_read_i2c_eeprom;
1660 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1661 hw->phy.type = ixgbe_phy_sfp_unsupported;
1662 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1666 hw->phy.id = identifier;
1668 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1671 if (status != IXGBE_SUCCESS)
1672 goto err_read_i2c_eeprom;
1674 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1677 if (status != IXGBE_SUCCESS)
1678 goto err_read_i2c_eeprom;
1680 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1681 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1682 if (hw->bus.lan_id == 0)
1683 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1685 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1686 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1687 IXGBE_SFF_10GBASELR_CAPABLE)) {
1688 if (hw->bus.lan_id == 0)
1689 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1691 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1693 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1694 active_cable = true;
1696 if (!active_cable) {
1697 /* check for active DA cables that pre-date
1699 hw->phy.ops.read_i2c_eeprom(hw,
1700 IXGBE_SFF_QSFP_CONNECTOR,
1703 hw->phy.ops.read_i2c_eeprom(hw,
1704 IXGBE_SFF_QSFP_CABLE_LENGTH,
1707 hw->phy.ops.read_i2c_eeprom(hw,
1708 IXGBE_SFF_QSFP_DEVICE_TECH,
1712 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1713 (cable_length > 0) &&
1714 ((device_tech >> 4) ==
1715 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1716 active_cable = true;
1720 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1721 if (hw->bus.lan_id == 0)
1723 ixgbe_sfp_type_da_act_lmt_core0;
1726 ixgbe_sfp_type_da_act_lmt_core1;
1728 /* unsupported module type */
1729 hw->phy.type = ixgbe_phy_sfp_unsupported;
1730 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1735 if (hw->phy.sfp_type != stored_sfp_type)
1736 hw->phy.sfp_setup_needed = true;
1738 /* Determine if the QSFP+ PHY is dual speed or not. */
1739 hw->phy.multispeed_fiber = false;
1740 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1741 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1742 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1743 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1744 hw->phy.multispeed_fiber = true;
1746 /* Determine PHY vendor for optical modules */
1747 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1748 IXGBE_SFF_10GBASELR_CAPABLE)) {
1749 status = hw->phy.ops.read_i2c_eeprom(hw,
1750 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1753 if (status != IXGBE_SUCCESS)
1754 goto err_read_i2c_eeprom;
1756 status = hw->phy.ops.read_i2c_eeprom(hw,
1757 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1760 if (status != IXGBE_SUCCESS)
1761 goto err_read_i2c_eeprom;
1763 status = hw->phy.ops.read_i2c_eeprom(hw,
1764 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1767 if (status != IXGBE_SUCCESS)
1768 goto err_read_i2c_eeprom;
1771 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1772 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1773 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1775 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1776 hw->phy.type = ixgbe_phy_qsfp_intel;
1778 hw->phy.type = ixgbe_phy_qsfp_unknown;
1780 ixgbe_get_device_caps(hw, &enforce_sfp);
1781 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1782 /* Make sure we're a supported PHY type */
1783 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1784 status = IXGBE_SUCCESS;
1786 if (hw->allow_unsupported_sfp == true) {
1788 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. "
1789 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1790 "Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1791 status = IXGBE_SUCCESS;
1793 DEBUGOUT("QSFP module not supported\n");
1795 ixgbe_phy_sfp_unsupported;
1796 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1800 status = IXGBE_SUCCESS;
1807 err_read_i2c_eeprom:
1808 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1810 hw->phy.type = ixgbe_phy_unknown;
1812 return IXGBE_ERR_SFP_NOT_PRESENT;
1816 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1817 * @hw: pointer to hardware structure
1818 * @list_offset: offset to the SFP ID list
1819 * @data_offset: offset to the SFP data block
1821 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1822 * so it returns the offsets to the phy init sequence block.
1824 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1829 u16 sfp_type = hw->phy.sfp_type;
1831 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1833 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1834 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1836 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1837 return IXGBE_ERR_SFP_NOT_PRESENT;
1839 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1840 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1841 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1844 * Limiting active cables and 1G Phys must be initialized as
1847 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1848 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1849 sfp_type == ixgbe_sfp_type_1g_lha_core0 ||
1850 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1851 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1852 sfp_type = ixgbe_sfp_type_srlr_core0;
1853 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1854 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1855 sfp_type == ixgbe_sfp_type_1g_lha_core1 ||
1856 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1857 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1858 sfp_type = ixgbe_sfp_type_srlr_core1;
1860 /* Read offset to PHY init contents */
1861 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1862 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1863 "eeprom read at offset %d failed",
1864 IXGBE_PHY_INIT_OFFSET_NL);
1865 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1868 if ((!*list_offset) || (*list_offset == 0xFFFF))
1869 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1871 /* Shift offset to first ID word */
1875 * Find the matching SFP ID in the EEPROM
1876 * and program the init sequence
1878 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1881 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1882 if (sfp_id == sfp_type) {
1884 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1886 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1887 DEBUGOUT("SFP+ module not supported\n");
1888 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1893 (*list_offset) += 2;
1894 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1899 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1900 DEBUGOUT("No matching SFP+ module found\n");
1901 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1904 return IXGBE_SUCCESS;
1907 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1908 "eeprom read at offset %d failed", *list_offset);
1909 return IXGBE_ERR_PHY;
1913 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1914 * @hw: pointer to hardware structure
1915 * @byte_offset: EEPROM byte offset to read
1916 * @eeprom_data: value read
1918 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1920 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1923 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1925 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1926 IXGBE_I2C_EEPROM_DEV_ADDR,
1931 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1932 * @hw: pointer to hardware structure
1933 * @byte_offset: byte offset at address 0xA2
1934 * @sff8472_data: value read
1936 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1938 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1941 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1942 IXGBE_I2C_EEPROM_DEV_ADDR2,
1947 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1948 * @hw: pointer to hardware structure
1949 * @byte_offset: EEPROM byte offset to write
1950 * @eeprom_data: value to write
1952 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1954 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1957 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1959 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1960 IXGBE_I2C_EEPROM_DEV_ADDR,
1965 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1966 * @hw: pointer to hardware structure
1967 * @offset: eeprom offset to be read
1968 * @addr: I2C address to be read
1970 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1972 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1973 offset == IXGBE_SFF_IDENTIFIER &&
1974 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1980 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1981 * @hw: pointer to hardware structure
1982 * @byte_offset: byte offset to read
1983 * @dev_addr: address to read from
1985 * @lock: true if to take and release semaphore
1987 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1988 * a specified device address.
1990 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1991 u8 dev_addr, u8 *data, bool lock)
1996 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2000 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2002 if (hw->mac.type >= ixgbe_mac_X550)
2004 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2005 max_retry = IXGBE_SFP_DETECT_RETRIES;
2008 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2009 return IXGBE_ERR_SWFW_SYNC;
2011 ixgbe_i2c_start(hw);
2013 /* Device Address and write indication */
2014 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2015 if (status != IXGBE_SUCCESS)
2018 status = ixgbe_get_i2c_ack(hw);
2019 if (status != IXGBE_SUCCESS)
2022 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2023 if (status != IXGBE_SUCCESS)
2026 status = ixgbe_get_i2c_ack(hw);
2027 if (status != IXGBE_SUCCESS)
2030 ixgbe_i2c_start(hw);
2032 /* Device Address and read indication */
2033 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2034 if (status != IXGBE_SUCCESS)
2037 status = ixgbe_get_i2c_ack(hw);
2038 if (status != IXGBE_SUCCESS)
2041 status = ixgbe_clock_in_i2c_byte(hw, data);
2042 if (status != IXGBE_SUCCESS)
2045 status = ixgbe_clock_out_i2c_bit(hw, nack);
2046 if (status != IXGBE_SUCCESS)
2051 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2052 return IXGBE_SUCCESS;
2055 ixgbe_i2c_bus_clear(hw);
2057 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2061 if (retry < max_retry)
2062 DEBUGOUT("I2C byte read error - Retrying.\n");
2064 DEBUGOUT("I2C byte read error.\n");
2066 } while (retry < max_retry);
2072 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2073 * @hw: pointer to hardware structure
2074 * @byte_offset: byte offset to read
2075 * @dev_addr: address to read from
2078 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2079 * a specified device address.
2081 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2082 u8 dev_addr, u8 *data)
2084 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2089 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2090 * @hw: pointer to hardware structure
2091 * @byte_offset: byte offset to read
2092 * @dev_addr: address to read from
2095 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2096 * a specified device address.
2098 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2099 u8 dev_addr, u8 *data)
2101 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2106 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2107 * @hw: pointer to hardware structure
2108 * @byte_offset: byte offset to write
2109 * @dev_addr: address to write to
2110 * @data: value to write
2111 * @lock: true if to take and release semaphore
2113 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2114 * a specified device address.
2116 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2117 u8 dev_addr, u8 data, bool lock)
2122 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2124 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2126 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2128 return IXGBE_ERR_SWFW_SYNC;
2131 ixgbe_i2c_start(hw);
2133 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2134 if (status != IXGBE_SUCCESS)
2137 status = ixgbe_get_i2c_ack(hw);
2138 if (status != IXGBE_SUCCESS)
2141 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2142 if (status != IXGBE_SUCCESS)
2145 status = ixgbe_get_i2c_ack(hw);
2146 if (status != IXGBE_SUCCESS)
2149 status = ixgbe_clock_out_i2c_byte(hw, data);
2150 if (status != IXGBE_SUCCESS)
2153 status = ixgbe_get_i2c_ack(hw);
2154 if (status != IXGBE_SUCCESS)
2159 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2160 return IXGBE_SUCCESS;
2163 ixgbe_i2c_bus_clear(hw);
2165 if (retry < max_retry)
2166 DEBUGOUT("I2C byte write error - Retrying.\n");
2168 DEBUGOUT("I2C byte write error.\n");
2169 } while (retry < max_retry);
2172 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2178 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2179 * @hw: pointer to hardware structure
2180 * @byte_offset: byte offset to write
2181 * @dev_addr: address to write to
2182 * @data: value to write
2184 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2185 * a specified device address.
2187 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2188 u8 dev_addr, u8 data)
2190 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2195 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2196 * @hw: pointer to hardware structure
2197 * @byte_offset: byte offset to write
2198 * @dev_addr: address to write to
2199 * @data: value to write
2201 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2202 * a specified device address.
2204 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2205 u8 dev_addr, u8 data)
2207 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2212 * ixgbe_i2c_start - Sets I2C start condition
2213 * @hw: pointer to hardware structure
2215 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2216 * Set bit-bang mode on X550 hardware.
2218 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2220 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2222 DEBUGFUNC("ixgbe_i2c_start");
2224 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2226 /* Start condition must begin with data and clock high */
2227 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2228 ixgbe_raise_i2c_clk(hw, &i2cctl);
2230 /* Setup time for start condition (4.7us) */
2231 usec_delay(IXGBE_I2C_T_SU_STA);
2233 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2235 /* Hold time for start condition (4us) */
2236 usec_delay(IXGBE_I2C_T_HD_STA);
2238 ixgbe_lower_i2c_clk(hw, &i2cctl);
2240 /* Minimum low period of clock is 4.7 us */
2241 usec_delay(IXGBE_I2C_T_LOW);
2246 * ixgbe_i2c_stop - Sets I2C stop condition
2247 * @hw: pointer to hardware structure
2249 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2250 * Disables bit-bang mode and negates data output enable on X550
2253 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2255 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2256 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2257 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2258 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2260 DEBUGFUNC("ixgbe_i2c_stop");
2262 /* Stop condition must begin with data low and clock high */
2263 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2264 ixgbe_raise_i2c_clk(hw, &i2cctl);
2266 /* Setup time for stop condition (4us) */
2267 usec_delay(IXGBE_I2C_T_SU_STO);
2269 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2271 /* bus free time between stop and start (4.7us)*/
2272 usec_delay(IXGBE_I2C_T_BUF);
2274 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2275 i2cctl &= ~bb_en_bit;
2276 i2cctl |= data_oe_bit | clk_oe_bit;
2277 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2278 IXGBE_WRITE_FLUSH(hw);
2283 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2284 * @hw: pointer to hardware structure
2285 * @data: data byte to clock in
2287 * Clocks in one byte data via I2C data/clock
2289 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2294 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2297 for (i = 7; i >= 0; i--) {
2298 ixgbe_clock_in_i2c_bit(hw, &bit);
2302 return IXGBE_SUCCESS;
2306 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2307 * @hw: pointer to hardware structure
2308 * @data: data byte clocked out
2310 * Clocks out one byte data via I2C data/clock
2312 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2314 s32 status = IXGBE_SUCCESS;
2319 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2321 for (i = 7; i >= 0; i--) {
2322 bit = (data >> i) & 0x1;
2323 status = ixgbe_clock_out_i2c_bit(hw, bit);
2325 if (status != IXGBE_SUCCESS)
2329 /* Release SDA line (set high) */
2330 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2331 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2332 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2333 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2334 IXGBE_WRITE_FLUSH(hw);
2340 * ixgbe_get_i2c_ack - Polls for I2C ACK
2341 * @hw: pointer to hardware structure
2343 * Clocks in/out one bit via I2C data/clock
2345 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2347 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2348 s32 status = IXGBE_SUCCESS;
2350 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2354 DEBUGFUNC("ixgbe_get_i2c_ack");
2357 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2358 i2cctl |= data_oe_bit;
2359 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2360 IXGBE_WRITE_FLUSH(hw);
2362 ixgbe_raise_i2c_clk(hw, &i2cctl);
2364 /* Minimum high period of clock is 4us */
2365 usec_delay(IXGBE_I2C_T_HIGH);
2367 /* Poll for ACK. Note that ACK in I2C spec is
2368 * transition from 1 to 0 */
2369 for (i = 0; i < timeout; i++) {
2370 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2371 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2379 DEBUGOUT("I2C ack was not received.\n");
2380 status = IXGBE_ERR_I2C;
2383 ixgbe_lower_i2c_clk(hw, &i2cctl);
2385 /* Minimum low period of clock is 4.7 us */
2386 usec_delay(IXGBE_I2C_T_LOW);
2392 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2393 * @hw: pointer to hardware structure
2394 * @data: read data value
2396 * Clocks in one bit via I2C data/clock
2398 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2400 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2401 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2403 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2406 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2407 i2cctl |= data_oe_bit;
2408 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2409 IXGBE_WRITE_FLUSH(hw);
2411 ixgbe_raise_i2c_clk(hw, &i2cctl);
2413 /* Minimum high period of clock is 4us */
2414 usec_delay(IXGBE_I2C_T_HIGH);
2416 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2417 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2419 ixgbe_lower_i2c_clk(hw, &i2cctl);
2421 /* Minimum low period of clock is 4.7 us */
2422 usec_delay(IXGBE_I2C_T_LOW);
2424 return IXGBE_SUCCESS;
2428 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2429 * @hw: pointer to hardware structure
2430 * @data: data value to write
2432 * Clocks out one bit via I2C data/clock
2434 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2437 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2439 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2441 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2442 if (status == IXGBE_SUCCESS) {
2443 ixgbe_raise_i2c_clk(hw, &i2cctl);
2445 /* Minimum high period of clock is 4us */
2446 usec_delay(IXGBE_I2C_T_HIGH);
2448 ixgbe_lower_i2c_clk(hw, &i2cctl);
2450 /* Minimum low period of clock is 4.7 us.
2451 * This also takes care of the data hold time.
2453 usec_delay(IXGBE_I2C_T_LOW);
2455 status = IXGBE_ERR_I2C;
2456 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2457 "I2C data was not set to %X\n", data);
2464 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2465 * @hw: pointer to hardware structure
2466 * @i2cctl: Current value of I2CCTL register
2468 * Raises the I2C clock line '0'->'1'
2469 * Negates the I2C clock output enable on X550 hardware.
2471 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2473 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2475 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2478 DEBUGFUNC("ixgbe_raise_i2c_clk");
2481 *i2cctl |= clk_oe_bit;
2482 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2485 for (i = 0; i < timeout; i++) {
2486 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2488 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2489 IXGBE_WRITE_FLUSH(hw);
2490 /* SCL rise time (1000ns) */
2491 usec_delay(IXGBE_I2C_T_RISE);
2493 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2494 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2500 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2501 * @hw: pointer to hardware structure
2502 * @i2cctl: Current value of I2CCTL register
2504 * Lowers the I2C clock line '1'->'0'
2505 * Asserts the I2C clock output enable on X550 hardware.
2507 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2509 DEBUGFUNC("ixgbe_lower_i2c_clk");
2511 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2512 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2514 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2515 IXGBE_WRITE_FLUSH(hw);
2517 /* SCL fall time (300ns) */
2518 usec_delay(IXGBE_I2C_T_FALL);
2522 * ixgbe_set_i2c_data - Sets the I2C data bit
2523 * @hw: pointer to hardware structure
2524 * @i2cctl: Current value of I2CCTL register
2525 * @data: I2C data value (0 or 1) to set
2527 * Sets the I2C data bit
2528 * Asserts the I2C data output enable on X550 hardware.
2530 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2532 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2533 s32 status = IXGBE_SUCCESS;
2535 DEBUGFUNC("ixgbe_set_i2c_data");
2538 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2540 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2541 *i2cctl &= ~data_oe_bit;
2543 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2544 IXGBE_WRITE_FLUSH(hw);
2546 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2547 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2549 if (!data) /* Can't verify data in this case */
2550 return IXGBE_SUCCESS;
2552 *i2cctl |= data_oe_bit;
2553 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2554 IXGBE_WRITE_FLUSH(hw);
2557 /* Verify data was set correctly */
2558 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2559 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2560 status = IXGBE_ERR_I2C;
2561 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2562 "Error - I2C data was not set to %X.\n",
2570 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2571 * @hw: pointer to hardware structure
2572 * @i2cctl: Current value of I2CCTL register
2574 * Returns the I2C data bit value
2575 * Negates the I2C data output enable on X550 hardware.
2577 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2579 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2582 DEBUGFUNC("ixgbe_get_i2c_data");
2585 *i2cctl |= data_oe_bit;
2586 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2587 IXGBE_WRITE_FLUSH(hw);
2588 usec_delay(IXGBE_I2C_T_FALL);
2591 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2600 * ixgbe_i2c_bus_clear - Clears the I2C bus
2601 * @hw: pointer to hardware structure
2603 * Clears the I2C bus by sending nine clock pulses.
2604 * Used when data line is stuck low.
2606 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2611 DEBUGFUNC("ixgbe_i2c_bus_clear");
2613 ixgbe_i2c_start(hw);
2614 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2616 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2618 for (i = 0; i < 9; i++) {
2619 ixgbe_raise_i2c_clk(hw, &i2cctl);
2621 /* Min high period of clock is 4us */
2622 usec_delay(IXGBE_I2C_T_HIGH);
2624 ixgbe_lower_i2c_clk(hw, &i2cctl);
2626 /* Min low period of clock is 4.7us*/
2627 usec_delay(IXGBE_I2C_T_LOW);
2630 ixgbe_i2c_start(hw);
2632 /* Put the i2c bus back to default state */
2637 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2638 * @hw: pointer to hardware structure
2640 * Checks if the LASI temp alarm status was triggered due to overtemp
2642 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2644 s32 status = IXGBE_SUCCESS;
2647 DEBUGFUNC("ixgbe_tn_check_overtemp");
2649 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2652 /* Check that the LASI temp alarm status was triggered */
2653 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2654 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2656 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2659 status = IXGBE_ERR_OVERTEMP;
2660 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2666 * ixgbe_set_copper_phy_power - Control power for copper phy
2667 * @hw: pointer to hardware structure
2668 * @on: true for on, false for off
2670 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2675 if (!on && ixgbe_mng_present(hw))
2678 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2679 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2685 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2687 if (ixgbe_check_reset_blocked(hw))
2689 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2692 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2693 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,