1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_api.h"
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
53 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
54 * @hw: pointer to the hardware structure
57 * Returns an error code on error.
59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
63 status = ixgbe_clock_out_i2c_byte(hw, byte);
66 return ixgbe_get_i2c_ack(hw);
70 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
71 * @hw: pointer to the hardware structure
72 * @byte: pointer to a u8 to receive the byte
74 * Returns an error code on error.
76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
80 status = ixgbe_clock_in_i2c_byte(hw, byte);
84 return ixgbe_clock_out_i2c_bit(hw, false);
88 * ixgbe_ones_comp_byte_add - Perform one's complement addition
92 * Returns one's complement 8-bit sum.
94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
96 u16 sum = add1 + add2;
98 sum = (sum & 0xFF) + (sum >> 8);
103 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
104 * @hw: pointer to the hardware structure
105 * @addr: I2C bus address to read from
106 * @reg: I2C device register to read from
107 * @val: pointer to location to receive read value
108 * @lock: true if to take and release semaphore
110 * Returns an error code on error.
112 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
115 u32 swfw_mask = hw->phy.phy_semaphore_mask;
124 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
125 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
128 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
129 return IXGBE_ERR_SWFW_SYNC;
131 /* Device Address and write indication */
132 if (ixgbe_out_i2c_byte_ack(hw, addr))
134 /* Write bits 14:8 */
135 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
138 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
141 if (ixgbe_out_i2c_byte_ack(hw, csum))
143 /* Re-start condition */
145 /* Device Address and read indication */
146 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
149 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
152 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
155 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
158 if (ixgbe_clock_out_i2c_bit(hw, false))
162 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
163 *val = (high_bits << 8) | low_bits;
167 ixgbe_i2c_bus_clear(hw);
169 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
171 if (retry < max_retry)
172 DEBUGOUT("I2C byte read combined error - Retrying.\n");
174 DEBUGOUT("I2C byte read combined error.\n");
175 } while (retry < max_retry);
177 return IXGBE_ERR_I2C;
181 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
182 * @hw: pointer to the hardware structure
183 * @addr: I2C bus address to write to
184 * @reg: I2C device register to write to
185 * @val: value to write
186 * @lock: true if to take and release semaphore
188 * Returns an error code on error.
190 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
193 u32 swfw_mask = hw->phy.phy_semaphore_mask;
199 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
200 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
201 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
202 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
205 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
206 return IXGBE_ERR_SWFW_SYNC;
208 /* Device Address and write indication */
209 if (ixgbe_out_i2c_byte_ack(hw, addr))
211 /* Write bits 14:8 */
212 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
215 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
217 /* Write data 15:8 */
218 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
221 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
224 if (ixgbe_out_i2c_byte_ack(hw, csum))
228 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
232 ixgbe_i2c_bus_clear(hw);
234 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
236 if (retry < max_retry)
237 DEBUGOUT("I2C byte write combined error - Retrying.\n");
239 DEBUGOUT("I2C byte write combined error.\n");
240 } while (retry < max_retry);
242 return IXGBE_ERR_I2C;
246 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
247 * @hw: pointer to the hardware structure
249 * Initialize the function pointers.
251 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
253 struct ixgbe_phy_info *phy = &hw->phy;
255 DEBUGFUNC("ixgbe_init_phy_ops_generic");
258 phy->ops.identify = ixgbe_identify_phy_generic;
259 phy->ops.reset = ixgbe_reset_phy_generic;
260 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
261 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
262 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
263 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
264 phy->ops.setup_link = ixgbe_setup_phy_link_generic;
265 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
266 phy->ops.check_link = NULL;
267 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
268 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
269 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
270 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
271 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
272 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
273 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
274 phy->ops.identify_sfp = ixgbe_identify_module_generic;
275 phy->sfp_type = ixgbe_sfp_type_unknown;
276 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
277 phy->ops.write_i2c_byte_unlocked =
278 ixgbe_write_i2c_byte_generic_unlocked;
279 phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
280 return IXGBE_SUCCESS;
284 * ixgbe_probe_phy - Probe a single address for a PHY
285 * @hw: pointer to hardware structure
286 * @phy_addr: PHY address to probe
288 * Returns true if PHY found
290 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
294 if (!ixgbe_validate_phy_addr(hw, phy_addr)) {
295 DEBUGOUT1("Unable to validate PHY address 0x%04X\n",
300 if (ixgbe_get_phy_id(hw))
303 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
305 if (hw->phy.type == ixgbe_phy_unknown) {
306 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
307 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
309 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
310 IXGBE_MDIO_PHY_1000BASET_ABILITY))
311 hw->phy.type = ixgbe_phy_cu_unknown;
313 hw->phy.type = ixgbe_phy_generic;
320 * ixgbe_identify_phy_generic - Get physical layer module
321 * @hw: pointer to hardware structure
323 * Determines the physical layer module found on the current adapter.
325 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
327 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
330 DEBUGFUNC("ixgbe_identify_phy_generic");
332 if (!hw->phy.phy_semaphore_mask) {
334 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
336 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
339 if (hw->phy.type != ixgbe_phy_unknown)
340 return IXGBE_SUCCESS;
342 if (hw->phy.nw_mng_if_sel) {
343 phy_addr = (hw->phy.nw_mng_if_sel &
344 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
345 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
346 if (ixgbe_probe_phy(hw, phy_addr))
347 return IXGBE_SUCCESS;
349 return IXGBE_ERR_PHY_ADDR_INVALID;
352 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
353 if (ixgbe_probe_phy(hw, phy_addr)) {
354 status = IXGBE_SUCCESS;
359 /* Certain media types do not have a phy so an address will not
360 * be found and the code will take this path. Caller has to
361 * decide if it is an error or not.
363 if (status != IXGBE_SUCCESS)
370 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
371 * @hw: pointer to the hardware structure
373 * This function checks the MMNGC.MNG_VETO bit to see if there are
374 * any constraints on link from manageability. For MAC's that don't
375 * have this bit just return faluse since the link can not be blocked
378 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
382 DEBUGFUNC("ixgbe_check_reset_blocked");
384 /* If we don't have this bit, it can't be blocking */
385 if (hw->mac.type == ixgbe_mac_82598EB)
388 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
389 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
390 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
391 "MNG_VETO bit detected.\n");
399 * ixgbe_validate_phy_addr - Determines phy address is valid
400 * @hw: pointer to hardware structure
403 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
408 DEBUGFUNC("ixgbe_validate_phy_addr");
410 hw->phy.addr = phy_addr;
411 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
412 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
414 if (phy_id != 0xFFFF && phy_id != 0x0)
417 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id);
423 * ixgbe_get_phy_id - Get the phy type
424 * @hw: pointer to hardware structure
427 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
433 DEBUGFUNC("ixgbe_get_phy_id");
435 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
436 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
439 if (status == IXGBE_SUCCESS) {
440 hw->phy.id = (u32)(phy_id_high << 16);
441 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
442 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
444 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
445 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
447 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
448 phy_id_high, phy_id_low);
454 * ixgbe_get_phy_type_from_id - Get the phy type
455 * @phy_id: PHY ID information
458 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
460 enum ixgbe_phy_type phy_type;
462 DEBUGFUNC("ixgbe_get_phy_type_from_id");
466 phy_type = ixgbe_phy_tn;
471 phy_type = ixgbe_phy_aq;
474 phy_type = ixgbe_phy_qt;
477 phy_type = ixgbe_phy_nl;
481 phy_type = ixgbe_phy_x550em_ext_t;
483 case IXGBE_M88E1500_E_PHY_ID:
484 case IXGBE_M88E1543_E_PHY_ID:
485 phy_type = ixgbe_phy_ext_1g_t;
488 phy_type = ixgbe_phy_unknown;
495 * ixgbe_reset_phy_generic - Performs a PHY reset
496 * @hw: pointer to hardware structure
498 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
502 s32 status = IXGBE_SUCCESS;
504 DEBUGFUNC("ixgbe_reset_phy_generic");
506 if (hw->phy.type == ixgbe_phy_unknown)
507 status = ixgbe_identify_phy_generic(hw);
509 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
512 /* Don't reset PHY if it's shut down due to overtemp. */
513 if (!hw->phy.reset_if_overtemp &&
514 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
517 /* Blocked by MNG FW so bail */
518 if (ixgbe_check_reset_blocked(hw))
522 * Perform soft PHY reset to the PHY_XS.
523 * This will cause a soft reset to the PHY
525 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
526 IXGBE_MDIO_PHY_XS_DEV_TYPE,
527 IXGBE_MDIO_PHY_XS_RESET);
530 * Poll for reset bit to self-clear indicating reset is complete.
531 * Some PHYs could take up to 3 seconds to complete and need about
532 * 1.7 usec delay after the reset is complete.
534 for (i = 0; i < 30; i++) {
536 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
537 status = hw->phy.ops.read_reg(hw,
538 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
539 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
541 if (status != IXGBE_SUCCESS)
544 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
549 status = hw->phy.ops.read_reg(hw,
550 IXGBE_MDIO_PHY_XS_CONTROL,
551 IXGBE_MDIO_PHY_XS_DEV_TYPE,
553 if (status != IXGBE_SUCCESS)
556 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
563 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
564 status = IXGBE_ERR_RESET_FAILED;
565 ERROR_REPORT1(IXGBE_ERROR_POLLING,
566 "PHY reset polling failed to complete.\n");
574 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
576 * @hw: pointer to hardware structure
577 * @reg_addr: 32 bit address of PHY register to read
578 * @phy_data: Pointer to read data from PHY register
580 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
583 u32 i, data, command;
585 /* Setup and write the address cycle command */
586 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
587 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
588 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
589 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
591 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
594 * Check every 10 usec to see if the address cycle completed.
595 * The MDI Command bit will clear when the operation is
598 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
601 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
602 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
607 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
608 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
609 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n");
610 return IXGBE_ERR_PHY;
614 * Address cycle complete, setup and write the read
617 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
618 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
619 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
620 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
622 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
625 * Check every 10 usec to see if the address cycle
626 * completed. The MDI Command bit will clear when the
627 * operation is complete
629 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
632 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
633 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
637 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
638 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
639 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n");
640 return IXGBE_ERR_PHY;
644 * Read operation is complete. Get the data
647 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
648 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
649 *phy_data = (u16)(data);
651 return IXGBE_SUCCESS;
655 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
656 * using the SWFW lock - this function is needed in most cases
657 * @hw: pointer to hardware structure
658 * @reg_addr: 32 bit address of PHY register to read
659 * @phy_data: Pointer to read data from PHY register
661 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
662 u32 device_type, u16 *phy_data)
665 u32 gssr = hw->phy.phy_semaphore_mask;
667 DEBUGFUNC("ixgbe_read_phy_reg_generic");
669 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
670 return IXGBE_ERR_SWFW_SYNC;
672 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
674 hw->mac.ops.release_swfw_sync(hw, gssr);
680 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
682 * @hw: pointer to hardware structure
683 * @reg_addr: 32 bit PHY register to write
684 * @device_type: 5 bit device type
685 * @phy_data: Data to write to the PHY register
687 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
688 u32 device_type, u16 phy_data)
692 /* Put the data in the MDI single read and write data register*/
693 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
695 /* Setup and write the address cycle command */
696 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
697 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
698 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
699 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
701 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
704 * Check every 10 usec to see if the address cycle completed.
705 * The MDI Command bit will clear when the operation is
708 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
711 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
712 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
716 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
717 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
718 return IXGBE_ERR_PHY;
722 * Address cycle complete, setup and write the write
725 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
726 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
727 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
728 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
730 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
733 * Check every 10 usec to see if the address cycle
734 * completed. The MDI Command bit will clear when the
735 * operation is complete
737 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
740 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
741 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
745 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
746 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
747 return IXGBE_ERR_PHY;
750 return IXGBE_SUCCESS;
754 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
755 * using SWFW lock- this function is needed in most cases
756 * @hw: pointer to hardware structure
757 * @reg_addr: 32 bit PHY register to write
758 * @device_type: 5 bit device type
759 * @phy_data: Data to write to the PHY register
761 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
762 u32 device_type, u16 phy_data)
765 u32 gssr = hw->phy.phy_semaphore_mask;
767 DEBUGFUNC("ixgbe_write_phy_reg_generic");
769 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
770 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
772 hw->mac.ops.release_swfw_sync(hw, gssr);
774 status = IXGBE_ERR_SWFW_SYNC;
781 * ixgbe_setup_phy_link_generic - Set and restart auto-neg
782 * @hw: pointer to hardware structure
784 * Restart auto-negotiation and PHY and waits for completion.
786 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
788 s32 status = IXGBE_SUCCESS;
789 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
790 bool autoneg = false;
791 ixgbe_link_speed speed;
793 DEBUGFUNC("ixgbe_setup_phy_link_generic");
795 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
797 /* Set or unset auto-negotiation 10G advertisement */
798 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
799 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
802 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
803 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
804 (speed & IXGBE_LINK_SPEED_10GB_FULL))
805 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
807 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
808 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
811 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
812 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
815 if (hw->mac.type == ixgbe_mac_X550) {
816 /* Set or unset auto-negotiation 5G advertisement */
817 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
818 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
819 (speed & IXGBE_LINK_SPEED_5GB_FULL))
820 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
822 /* Set or unset auto-negotiation 2.5G advertisement */
823 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
824 if ((hw->phy.autoneg_advertised &
825 IXGBE_LINK_SPEED_2_5GB_FULL) &&
826 (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
827 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
830 /* Set or unset auto-negotiation 1G advertisement */
831 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
832 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
833 (speed & IXGBE_LINK_SPEED_1GB_FULL))
834 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
836 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
837 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
840 /* Set or unset auto-negotiation 100M advertisement */
841 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
842 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
845 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
846 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
847 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
848 (speed & IXGBE_LINK_SPEED_100_FULL))
849 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
851 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
852 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
855 /* Blocked by MNG FW so don't reset PHY */
856 if (ixgbe_check_reset_blocked(hw))
859 /* Restart PHY auto-negotiation. */
860 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
861 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
863 autoneg_reg |= IXGBE_MII_RESTART;
865 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
866 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
872 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
873 * @hw: pointer to hardware structure
874 * @speed: new link speed
876 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
877 ixgbe_link_speed speed,
878 bool autoneg_wait_to_complete)
880 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
882 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
885 * Clear autoneg_advertised and set new values based on input link
888 hw->phy.autoneg_advertised = 0;
890 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
891 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
893 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
894 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
896 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
897 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
899 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
900 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
902 if (speed & IXGBE_LINK_SPEED_100_FULL)
903 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
905 if (speed & IXGBE_LINK_SPEED_10_FULL)
906 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
908 /* Setup link based on the new speed settings */
909 ixgbe_setup_phy_link(hw);
911 return IXGBE_SUCCESS;
915 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
916 * @hw: pointer to hardware structure
918 * Determines the supported link capabilities by reading the PHY auto
919 * negotiation register.
921 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
926 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
927 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
932 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
933 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
934 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
935 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
936 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
937 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
939 switch (hw->mac.type) {
941 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
942 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
944 case ixgbe_mac_X550EM_x:
945 case ixgbe_mac_X550EM_a:
946 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
956 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
957 * @hw: pointer to hardware structure
958 * @speed: pointer to link speed
959 * @autoneg: boolean auto-negotiation value
961 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
962 ixgbe_link_speed *speed,
965 s32 status = IXGBE_SUCCESS;
967 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
970 if (!hw->phy.speeds_supported)
971 status = ixgbe_get_copper_speeds_supported(hw);
973 *speed = hw->phy.speeds_supported;
978 * ixgbe_check_phy_link_tnx - Determine link and speed status
979 * @hw: pointer to hardware structure
981 * Reads the VS1 register to determine if link is up and the current speed for
984 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
987 s32 status = IXGBE_SUCCESS;
989 u32 max_time_out = 10;
994 DEBUGFUNC("ixgbe_check_phy_link_tnx");
996 /* Initialize speed and link to default case */
998 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1001 * Check current speed and link status of the PHY register.
1002 * This is a vendor specific register and may have to
1003 * be changed for other copper PHYs.
1005 for (time_out = 0; time_out < max_time_out; time_out++) {
1007 status = hw->phy.ops.read_reg(hw,
1008 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1009 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1011 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1012 phy_speed = phy_data &
1013 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1014 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1017 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1018 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1027 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1028 * @hw: pointer to hardware structure
1030 * Restart auto-negotiation and PHY and waits for completion.
1032 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1034 s32 status = IXGBE_SUCCESS;
1035 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1036 bool autoneg = false;
1037 ixgbe_link_speed speed;
1039 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1041 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1043 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1044 /* Set or unset auto-negotiation 10G advertisement */
1045 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1046 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1049 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1050 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1051 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1053 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1054 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1058 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1059 /* Set or unset auto-negotiation 1G advertisement */
1060 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1061 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1064 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1065 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1066 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1068 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1069 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1073 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1074 /* Set or unset auto-negotiation 100M advertisement */
1075 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1076 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1079 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1080 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1081 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1083 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1084 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1088 /* Blocked by MNG FW so don't reset PHY */
1089 if (ixgbe_check_reset_blocked(hw))
1092 /* Restart PHY auto-negotiation. */
1093 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1094 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1096 autoneg_reg |= IXGBE_MII_RESTART;
1098 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1099 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1105 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1106 * @hw: pointer to hardware structure
1107 * @firmware_version: pointer to the PHY Firmware Version
1109 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1110 u16 *firmware_version)
1114 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1116 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1117 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1124 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1125 * @hw: pointer to hardware structure
1126 * @firmware_version: pointer to the PHY Firmware Version
1128 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1129 u16 *firmware_version)
1133 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1135 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1136 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1143 * ixgbe_reset_phy_nl - Performs a PHY reset
1144 * @hw: pointer to hardware structure
1146 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1148 u16 phy_offset, control, eword, edata, block_crc;
1149 bool end_data = false;
1150 u16 list_offset, data_offset;
1152 s32 ret_val = IXGBE_SUCCESS;
1155 DEBUGFUNC("ixgbe_reset_phy_nl");
1157 /* Blocked by MNG FW so bail */
1158 if (ixgbe_check_reset_blocked(hw))
1161 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1162 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1164 /* reset the PHY and poll for completion */
1165 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1166 IXGBE_MDIO_PHY_XS_DEV_TYPE,
1167 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1169 for (i = 0; i < 100; i++) {
1170 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1171 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1172 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1177 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1178 DEBUGOUT("PHY reset did not complete.\n");
1179 ret_val = IXGBE_ERR_PHY;
1183 /* Get init offsets */
1184 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1186 if (ret_val != IXGBE_SUCCESS)
1189 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1193 * Read control word from PHY init contents offset
1195 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1198 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1199 IXGBE_CONTROL_SHIFT_NL;
1200 edata = eword & IXGBE_DATA_MASK_NL;
1202 case IXGBE_DELAY_NL:
1204 DEBUGOUT1("DELAY: %d MS\n", edata);
1208 DEBUGOUT("DATA:\n");
1210 ret_val = hw->eeprom.ops.read(hw, data_offset,
1215 for (i = 0; i < edata; i++) {
1216 ret_val = hw->eeprom.ops.read(hw, data_offset,
1220 hw->phy.ops.write_reg(hw, phy_offset,
1221 IXGBE_TWINAX_DEV, eword);
1222 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1228 case IXGBE_CONTROL_NL:
1230 DEBUGOUT("CONTROL:\n");
1231 if (edata == IXGBE_CONTROL_EOL_NL) {
1234 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1237 DEBUGOUT("Bad control value\n");
1238 ret_val = IXGBE_ERR_PHY;
1243 DEBUGOUT("Bad control type\n");
1244 ret_val = IXGBE_ERR_PHY;
1253 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1254 "eeprom read at offset %d failed", data_offset);
1255 return IXGBE_ERR_PHY;
1259 * ixgbe_identify_module_generic - Identifies module type
1260 * @hw: pointer to hardware structure
1262 * Determines HW type and calls appropriate function.
1264 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1266 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1268 DEBUGFUNC("ixgbe_identify_module_generic");
1270 switch (hw->mac.ops.get_media_type(hw)) {
1271 case ixgbe_media_type_fiber:
1272 status = ixgbe_identify_sfp_module_generic(hw);
1275 case ixgbe_media_type_fiber_qsfp:
1276 status = ixgbe_identify_qsfp_module_generic(hw);
1280 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1281 status = IXGBE_ERR_SFP_NOT_PRESENT;
1289 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1290 * @hw: pointer to hardware structure
1292 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1294 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1296 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1298 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1300 u8 comp_codes_1g = 0;
1301 u8 comp_codes_10g = 0;
1302 u8 oui_bytes[3] = {0, 0, 0};
1305 u16 enforce_sfp = 0;
1307 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1309 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1310 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1311 status = IXGBE_ERR_SFP_NOT_PRESENT;
1315 /* LAN ID is needed for I2C access */
1316 hw->mac.ops.set_lan_id(hw);
1318 status = hw->phy.ops.read_i2c_eeprom(hw,
1319 IXGBE_SFF_IDENTIFIER,
1322 if (status != IXGBE_SUCCESS)
1323 goto err_read_i2c_eeprom;
1325 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1326 hw->phy.type = ixgbe_phy_sfp_unsupported;
1327 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1329 status = hw->phy.ops.read_i2c_eeprom(hw,
1330 IXGBE_SFF_1GBE_COMP_CODES,
1333 if (status != IXGBE_SUCCESS)
1334 goto err_read_i2c_eeprom;
1336 status = hw->phy.ops.read_i2c_eeprom(hw,
1337 IXGBE_SFF_10GBE_COMP_CODES,
1340 if (status != IXGBE_SUCCESS)
1341 goto err_read_i2c_eeprom;
1342 status = hw->phy.ops.read_i2c_eeprom(hw,
1343 IXGBE_SFF_CABLE_TECHNOLOGY,
1346 if (status != IXGBE_SUCCESS)
1347 goto err_read_i2c_eeprom;
1354 * 3 SFP_DA_CORE0 - 82599-specific
1355 * 4 SFP_DA_CORE1 - 82599-specific
1356 * 5 SFP_SR/LR_CORE0 - 82599-specific
1357 * 6 SFP_SR/LR_CORE1 - 82599-specific
1358 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1359 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1360 * 9 SFP_1g_cu_CORE0 - 82599-specific
1361 * 10 SFP_1g_cu_CORE1 - 82599-specific
1362 * 11 SFP_1g_sx_CORE0 - 82599-specific
1363 * 12 SFP_1g_sx_CORE1 - 82599-specific
1365 if (hw->mac.type == ixgbe_mac_82598EB) {
1366 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1367 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1368 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1369 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1370 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1371 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1373 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1375 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1376 if (hw->bus.lan_id == 0)
1378 ixgbe_sfp_type_da_cu_core0;
1381 ixgbe_sfp_type_da_cu_core1;
1382 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1383 hw->phy.ops.read_i2c_eeprom(
1384 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1387 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1388 if (hw->bus.lan_id == 0)
1390 ixgbe_sfp_type_da_act_lmt_core0;
1393 ixgbe_sfp_type_da_act_lmt_core1;
1396 ixgbe_sfp_type_unknown;
1398 } else if (comp_codes_10g &
1399 (IXGBE_SFF_10GBASESR_CAPABLE |
1400 IXGBE_SFF_10GBASELR_CAPABLE)) {
1401 if (hw->bus.lan_id == 0)
1403 ixgbe_sfp_type_srlr_core0;
1406 ixgbe_sfp_type_srlr_core1;
1407 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1408 if (hw->bus.lan_id == 0)
1410 ixgbe_sfp_type_1g_cu_core0;
1413 ixgbe_sfp_type_1g_cu_core1;
1414 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1415 if (hw->bus.lan_id == 0)
1417 ixgbe_sfp_type_1g_sx_core0;
1420 ixgbe_sfp_type_1g_sx_core1;
1421 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1422 if (hw->bus.lan_id == 0)
1424 ixgbe_sfp_type_1g_lx_core0;
1427 ixgbe_sfp_type_1g_lx_core1;
1429 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1433 if (hw->phy.sfp_type != stored_sfp_type)
1434 hw->phy.sfp_setup_needed = true;
1436 /* Determine if the SFP+ PHY is dual speed or not. */
1437 hw->phy.multispeed_fiber = false;
1438 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1439 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1440 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1441 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1442 hw->phy.multispeed_fiber = true;
1444 /* Determine PHY vendor */
1445 if (hw->phy.type != ixgbe_phy_nl) {
1446 hw->phy.id = identifier;
1447 status = hw->phy.ops.read_i2c_eeprom(hw,
1448 IXGBE_SFF_VENDOR_OUI_BYTE0,
1451 if (status != IXGBE_SUCCESS)
1452 goto err_read_i2c_eeprom;
1454 status = hw->phy.ops.read_i2c_eeprom(hw,
1455 IXGBE_SFF_VENDOR_OUI_BYTE1,
1458 if (status != IXGBE_SUCCESS)
1459 goto err_read_i2c_eeprom;
1461 status = hw->phy.ops.read_i2c_eeprom(hw,
1462 IXGBE_SFF_VENDOR_OUI_BYTE2,
1465 if (status != IXGBE_SUCCESS)
1466 goto err_read_i2c_eeprom;
1469 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1470 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1471 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1473 switch (vendor_oui) {
1474 case IXGBE_SFF_VENDOR_OUI_TYCO:
1475 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1477 ixgbe_phy_sfp_passive_tyco;
1479 case IXGBE_SFF_VENDOR_OUI_FTL:
1480 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1481 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1483 hw->phy.type = ixgbe_phy_sfp_ftl;
1485 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1486 hw->phy.type = ixgbe_phy_sfp_avago;
1488 case IXGBE_SFF_VENDOR_OUI_INTEL:
1489 hw->phy.type = ixgbe_phy_sfp_intel;
1492 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1494 ixgbe_phy_sfp_passive_unknown;
1495 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1497 ixgbe_phy_sfp_active_unknown;
1499 hw->phy.type = ixgbe_phy_sfp_unknown;
1504 /* Allow any DA cable vendor */
1505 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1506 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1507 status = IXGBE_SUCCESS;
1511 /* Verify supported 1G SFP modules */
1512 if (comp_codes_10g == 0 &&
1513 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1514 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1515 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1516 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1517 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1518 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1519 hw->phy.type = ixgbe_phy_sfp_unsupported;
1520 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1524 /* Anything else 82598-based is supported */
1525 if (hw->mac.type == ixgbe_mac_82598EB) {
1526 status = IXGBE_SUCCESS;
1530 ixgbe_get_device_caps(hw, &enforce_sfp);
1531 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1532 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1533 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1534 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1535 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1536 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1537 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1538 /* Make sure we're a supported PHY type */
1539 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1540 status = IXGBE_SUCCESS;
1542 if (hw->allow_unsupported_sfp == true) {
1543 EWARN(hw, "WARNING: Intel (R) Network "
1544 "Connections are quality tested "
1545 "using Intel (R) Ethernet Optics."
1546 " Using untested modules is not "
1547 "supported and may cause unstable"
1548 " operation or damage to the "
1549 "module or the adapter. Intel "
1550 "Corporation is not responsible "
1551 "for any harm caused by using "
1552 "untested modules.\n", status);
1553 status = IXGBE_SUCCESS;
1555 DEBUGOUT("SFP+ module not supported\n");
1557 ixgbe_phy_sfp_unsupported;
1558 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1562 status = IXGBE_SUCCESS;
1569 err_read_i2c_eeprom:
1570 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1571 if (hw->phy.type != ixgbe_phy_nl) {
1573 hw->phy.type = ixgbe_phy_unknown;
1575 return IXGBE_ERR_SFP_NOT_PRESENT;
1579 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1580 * @hw: pointer to hardware structure
1582 * Determines physical layer capabilities of the current SFP.
1584 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1586 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1587 u8 comp_codes_10g = 0;
1588 u8 comp_codes_1g = 0;
1590 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1592 hw->phy.ops.identify_sfp(hw);
1593 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1594 return physical_layer;
1596 switch (hw->phy.type) {
1597 case ixgbe_phy_sfp_passive_tyco:
1598 case ixgbe_phy_sfp_passive_unknown:
1599 case ixgbe_phy_qsfp_passive_unknown:
1600 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1602 case ixgbe_phy_sfp_ftl_active:
1603 case ixgbe_phy_sfp_active_unknown:
1604 case ixgbe_phy_qsfp_active_unknown:
1605 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1607 case ixgbe_phy_sfp_avago:
1608 case ixgbe_phy_sfp_ftl:
1609 case ixgbe_phy_sfp_intel:
1610 case ixgbe_phy_sfp_unknown:
1611 hw->phy.ops.read_i2c_eeprom(hw,
1612 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1613 hw->phy.ops.read_i2c_eeprom(hw,
1614 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1615 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1616 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1617 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1618 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1619 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1620 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1621 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1622 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1624 case ixgbe_phy_qsfp_intel:
1625 case ixgbe_phy_qsfp_unknown:
1626 hw->phy.ops.read_i2c_eeprom(hw,
1627 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1628 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1629 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1630 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1631 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1637 return physical_layer;
1641 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1642 * @hw: pointer to hardware structure
1644 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1646 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1648 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1650 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1652 u8 comp_codes_1g = 0;
1653 u8 comp_codes_10g = 0;
1654 u8 oui_bytes[3] = {0, 0, 0};
1655 u16 enforce_sfp = 0;
1657 u8 cable_length = 0;
1659 bool active_cable = false;
1661 DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1663 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1664 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1665 status = IXGBE_ERR_SFP_NOT_PRESENT;
1669 /* LAN ID is needed for I2C access */
1670 hw->mac.ops.set_lan_id(hw);
1672 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1675 if (status != IXGBE_SUCCESS)
1676 goto err_read_i2c_eeprom;
1678 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1679 hw->phy.type = ixgbe_phy_sfp_unsupported;
1680 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1684 hw->phy.id = identifier;
1686 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1689 if (status != IXGBE_SUCCESS)
1690 goto err_read_i2c_eeprom;
1692 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1695 if (status != IXGBE_SUCCESS)
1696 goto err_read_i2c_eeprom;
1698 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1699 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1700 if (hw->bus.lan_id == 0)
1701 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1703 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1704 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1705 IXGBE_SFF_10GBASELR_CAPABLE)) {
1706 if (hw->bus.lan_id == 0)
1707 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1709 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1711 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1712 active_cable = true;
1714 if (!active_cable) {
1715 /* check for active DA cables that pre-date
1717 hw->phy.ops.read_i2c_eeprom(hw,
1718 IXGBE_SFF_QSFP_CONNECTOR,
1721 hw->phy.ops.read_i2c_eeprom(hw,
1722 IXGBE_SFF_QSFP_CABLE_LENGTH,
1725 hw->phy.ops.read_i2c_eeprom(hw,
1726 IXGBE_SFF_QSFP_DEVICE_TECH,
1730 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1731 (cable_length > 0) &&
1732 ((device_tech >> 4) ==
1733 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1734 active_cable = true;
1738 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1739 if (hw->bus.lan_id == 0)
1741 ixgbe_sfp_type_da_act_lmt_core0;
1744 ixgbe_sfp_type_da_act_lmt_core1;
1746 /* unsupported module type */
1747 hw->phy.type = ixgbe_phy_sfp_unsupported;
1748 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1753 if (hw->phy.sfp_type != stored_sfp_type)
1754 hw->phy.sfp_setup_needed = true;
1756 /* Determine if the QSFP+ PHY is dual speed or not. */
1757 hw->phy.multispeed_fiber = false;
1758 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1759 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1760 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1761 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1762 hw->phy.multispeed_fiber = true;
1764 /* Determine PHY vendor for optical modules */
1765 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1766 IXGBE_SFF_10GBASELR_CAPABLE)) {
1767 status = hw->phy.ops.read_i2c_eeprom(hw,
1768 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1771 if (status != IXGBE_SUCCESS)
1772 goto err_read_i2c_eeprom;
1774 status = hw->phy.ops.read_i2c_eeprom(hw,
1775 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1778 if (status != IXGBE_SUCCESS)
1779 goto err_read_i2c_eeprom;
1781 status = hw->phy.ops.read_i2c_eeprom(hw,
1782 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1785 if (status != IXGBE_SUCCESS)
1786 goto err_read_i2c_eeprom;
1789 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1790 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1791 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1793 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1794 hw->phy.type = ixgbe_phy_qsfp_intel;
1796 hw->phy.type = ixgbe_phy_qsfp_unknown;
1798 ixgbe_get_device_caps(hw, &enforce_sfp);
1799 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1800 /* Make sure we're a supported PHY type */
1801 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1802 status = IXGBE_SUCCESS;
1804 if (hw->allow_unsupported_sfp == true) {
1805 EWARN(hw, "WARNING: Intel (R) Network "
1806 "Connections are quality tested "
1807 "using Intel (R) Ethernet Optics."
1808 " Using untested modules is not "
1809 "supported and may cause unstable"
1810 " operation or damage to the "
1811 "module or the adapter. Intel "
1812 "Corporation is not responsible "
1813 "for any harm caused by using "
1814 "untested modules.\n", status);
1815 status = IXGBE_SUCCESS;
1817 DEBUGOUT("QSFP module not supported\n");
1819 ixgbe_phy_sfp_unsupported;
1820 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1824 status = IXGBE_SUCCESS;
1831 err_read_i2c_eeprom:
1832 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1834 hw->phy.type = ixgbe_phy_unknown;
1836 return IXGBE_ERR_SFP_NOT_PRESENT;
1841 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1842 * @hw: pointer to hardware structure
1843 * @list_offset: offset to the SFP ID list
1844 * @data_offset: offset to the SFP data block
1846 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1847 * so it returns the offsets to the phy init sequence block.
1849 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1854 u16 sfp_type = hw->phy.sfp_type;
1856 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1858 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1859 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1861 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1862 return IXGBE_ERR_SFP_NOT_PRESENT;
1864 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1865 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1866 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1869 * Limiting active cables and 1G Phys must be initialized as
1872 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1873 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1874 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1875 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1876 sfp_type = ixgbe_sfp_type_srlr_core0;
1877 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1878 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1879 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1880 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1881 sfp_type = ixgbe_sfp_type_srlr_core1;
1883 /* Read offset to PHY init contents */
1884 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1885 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1886 "eeprom read at offset %d failed",
1887 IXGBE_PHY_INIT_OFFSET_NL);
1888 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1891 if ((!*list_offset) || (*list_offset == 0xFFFF))
1892 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1894 /* Shift offset to first ID word */
1898 * Find the matching SFP ID in the EEPROM
1899 * and program the init sequence
1901 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1904 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1905 if (sfp_id == sfp_type) {
1907 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1909 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1910 DEBUGOUT("SFP+ module not supported\n");
1911 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1916 (*list_offset) += 2;
1917 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1922 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1923 DEBUGOUT("No matching SFP+ module found\n");
1924 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1927 return IXGBE_SUCCESS;
1930 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1931 "eeprom read at offset %d failed", *list_offset);
1932 return IXGBE_ERR_PHY;
1936 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1937 * @hw: pointer to hardware structure
1938 * @byte_offset: EEPROM byte offset to read
1939 * @eeprom_data: value read
1941 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1943 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1946 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1948 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1949 IXGBE_I2C_EEPROM_DEV_ADDR,
1954 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1955 * @hw: pointer to hardware structure
1956 * @byte_offset: byte offset at address 0xA2
1957 * @eeprom_data: value read
1959 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1961 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1964 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1965 IXGBE_I2C_EEPROM_DEV_ADDR2,
1970 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1971 * @hw: pointer to hardware structure
1972 * @byte_offset: EEPROM byte offset to write
1973 * @eeprom_data: value to write
1975 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1977 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1980 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1982 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1983 IXGBE_I2C_EEPROM_DEV_ADDR,
1988 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1989 * @hw: pointer to hardware structure
1990 * @offset: eeprom offset to be read
1991 * @addr: I2C address to be read
1993 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1995 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1996 offset == IXGBE_SFF_IDENTIFIER &&
1997 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2003 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
2004 * @hw: pointer to hardware structure
2005 * @byte_offset: byte offset to read
2007 * @lock: true if to take and release semaphore
2009 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2010 * a specified device address.
2012 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2013 u8 dev_addr, u8 *data, bool lock)
2018 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2022 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2024 if (hw->mac.type >= ixgbe_mac_X550)
2026 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2027 max_retry = IXGBE_SFP_DETECT_RETRIES;
2030 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2031 return IXGBE_ERR_SWFW_SYNC;
2033 ixgbe_i2c_start(hw);
2035 /* Device Address and write indication */
2036 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2037 if (status != IXGBE_SUCCESS)
2040 status = ixgbe_get_i2c_ack(hw);
2041 if (status != IXGBE_SUCCESS)
2044 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2045 if (status != IXGBE_SUCCESS)
2048 status = ixgbe_get_i2c_ack(hw);
2049 if (status != IXGBE_SUCCESS)
2052 ixgbe_i2c_start(hw);
2054 /* Device Address and read indication */
2055 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2056 if (status != IXGBE_SUCCESS)
2059 status = ixgbe_get_i2c_ack(hw);
2060 if (status != IXGBE_SUCCESS)
2063 status = ixgbe_clock_in_i2c_byte(hw, data);
2064 if (status != IXGBE_SUCCESS)
2067 status = ixgbe_clock_out_i2c_bit(hw, nack);
2068 if (status != IXGBE_SUCCESS)
2073 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2074 return IXGBE_SUCCESS;
2077 ixgbe_i2c_bus_clear(hw);
2079 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2083 if (retry < max_retry)
2084 DEBUGOUT("I2C byte read error - Retrying.\n");
2086 DEBUGOUT("I2C byte read error.\n");
2088 } while (retry < max_retry);
2094 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2095 * @hw: pointer to hardware structure
2096 * @byte_offset: byte offset to read
2099 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2100 * a specified device address.
2102 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2103 u8 dev_addr, u8 *data)
2105 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2110 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2111 * @hw: pointer to hardware structure
2112 * @byte_offset: byte offset to read
2115 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2116 * a specified device address.
2118 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2119 u8 dev_addr, u8 *data)
2121 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2126 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2127 * @hw: pointer to hardware structure
2128 * @byte_offset: byte offset to write
2129 * @data: value to write
2130 * @lock: true if to take and release semaphore
2132 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2133 * a specified device address.
2135 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2136 u8 dev_addr, u8 data, bool lock)
2141 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2143 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2145 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2147 return IXGBE_ERR_SWFW_SYNC;
2150 ixgbe_i2c_start(hw);
2152 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2153 if (status != IXGBE_SUCCESS)
2156 status = ixgbe_get_i2c_ack(hw);
2157 if (status != IXGBE_SUCCESS)
2160 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2161 if (status != IXGBE_SUCCESS)
2164 status = ixgbe_get_i2c_ack(hw);
2165 if (status != IXGBE_SUCCESS)
2168 status = ixgbe_clock_out_i2c_byte(hw, data);
2169 if (status != IXGBE_SUCCESS)
2172 status = ixgbe_get_i2c_ack(hw);
2173 if (status != IXGBE_SUCCESS)
2178 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2179 return IXGBE_SUCCESS;
2182 ixgbe_i2c_bus_clear(hw);
2184 if (retry < max_retry)
2185 DEBUGOUT("I2C byte write error - Retrying.\n");
2187 DEBUGOUT("I2C byte write error.\n");
2188 } while (retry < max_retry);
2191 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2197 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2198 * @hw: pointer to hardware structure
2199 * @byte_offset: byte offset to write
2200 * @data: value to write
2202 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2203 * a specified device address.
2205 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2206 u8 dev_addr, u8 data)
2208 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2213 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2214 * @hw: pointer to hardware structure
2215 * @byte_offset: byte offset to write
2216 * @data: value to write
2218 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2219 * a specified device address.
2221 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2222 u8 dev_addr, u8 data)
2224 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2229 * ixgbe_i2c_start - Sets I2C start condition
2230 * @hw: pointer to hardware structure
2232 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2233 * Set bit-bang mode on X550 hardware.
2235 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2237 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2239 DEBUGFUNC("ixgbe_i2c_start");
2241 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2243 /* Start condition must begin with data and clock high */
2244 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2245 ixgbe_raise_i2c_clk(hw, &i2cctl);
2247 /* Setup time for start condition (4.7us) */
2248 usec_delay(IXGBE_I2C_T_SU_STA);
2250 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2252 /* Hold time for start condition (4us) */
2253 usec_delay(IXGBE_I2C_T_HD_STA);
2255 ixgbe_lower_i2c_clk(hw, &i2cctl);
2257 /* Minimum low period of clock is 4.7 us */
2258 usec_delay(IXGBE_I2C_T_LOW);
2263 * ixgbe_i2c_stop - Sets I2C stop condition
2264 * @hw: pointer to hardware structure
2266 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2267 * Disables bit-bang mode and negates data output enable on X550
2270 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2272 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2273 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2274 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2275 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2277 DEBUGFUNC("ixgbe_i2c_stop");
2279 /* Stop condition must begin with data low and clock high */
2280 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2281 ixgbe_raise_i2c_clk(hw, &i2cctl);
2283 /* Setup time for stop condition (4us) */
2284 usec_delay(IXGBE_I2C_T_SU_STO);
2286 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2288 /* bus free time between stop and start (4.7us)*/
2289 usec_delay(IXGBE_I2C_T_BUF);
2291 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2292 i2cctl &= ~bb_en_bit;
2293 i2cctl |= data_oe_bit | clk_oe_bit;
2294 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2295 IXGBE_WRITE_FLUSH(hw);
2300 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2301 * @hw: pointer to hardware structure
2302 * @data: data byte to clock in
2304 * Clocks in one byte data via I2C data/clock
2306 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2311 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2314 for (i = 7; i >= 0; i--) {
2315 ixgbe_clock_in_i2c_bit(hw, &bit);
2319 return IXGBE_SUCCESS;
2323 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2324 * @hw: pointer to hardware structure
2325 * @data: data byte clocked out
2327 * Clocks out one byte data via I2C data/clock
2329 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2331 s32 status = IXGBE_SUCCESS;
2336 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2338 for (i = 7; i >= 0; i--) {
2339 bit = (data >> i) & 0x1;
2340 status = ixgbe_clock_out_i2c_bit(hw, bit);
2342 if (status != IXGBE_SUCCESS)
2346 /* Release SDA line (set high) */
2347 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2348 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2349 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2350 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2351 IXGBE_WRITE_FLUSH(hw);
2357 * ixgbe_get_i2c_ack - Polls for I2C ACK
2358 * @hw: pointer to hardware structure
2360 * Clocks in/out one bit via I2C data/clock
2362 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2364 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2365 s32 status = IXGBE_SUCCESS;
2367 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2371 DEBUGFUNC("ixgbe_get_i2c_ack");
2374 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2375 i2cctl |= data_oe_bit;
2376 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2377 IXGBE_WRITE_FLUSH(hw);
2379 ixgbe_raise_i2c_clk(hw, &i2cctl);
2381 /* Minimum high period of clock is 4us */
2382 usec_delay(IXGBE_I2C_T_HIGH);
2384 /* Poll for ACK. Note that ACK in I2C spec is
2385 * transition from 1 to 0 */
2386 for (i = 0; i < timeout; i++) {
2387 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2388 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2396 DEBUGOUT("I2C ack was not received.\n");
2397 status = IXGBE_ERR_I2C;
2400 ixgbe_lower_i2c_clk(hw, &i2cctl);
2402 /* Minimum low period of clock is 4.7 us */
2403 usec_delay(IXGBE_I2C_T_LOW);
2409 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2410 * @hw: pointer to hardware structure
2411 * @data: read data value
2413 * Clocks in one bit via I2C data/clock
2415 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2417 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2418 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2420 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2423 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2424 i2cctl |= data_oe_bit;
2425 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2426 IXGBE_WRITE_FLUSH(hw);
2428 ixgbe_raise_i2c_clk(hw, &i2cctl);
2430 /* Minimum high period of clock is 4us */
2431 usec_delay(IXGBE_I2C_T_HIGH);
2433 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2434 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2436 ixgbe_lower_i2c_clk(hw, &i2cctl);
2438 /* Minimum low period of clock is 4.7 us */
2439 usec_delay(IXGBE_I2C_T_LOW);
2441 return IXGBE_SUCCESS;
2445 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2446 * @hw: pointer to hardware structure
2447 * @data: data value to write
2449 * Clocks out one bit via I2C data/clock
2451 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2454 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2456 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2458 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2459 if (status == IXGBE_SUCCESS) {
2460 ixgbe_raise_i2c_clk(hw, &i2cctl);
2462 /* Minimum high period of clock is 4us */
2463 usec_delay(IXGBE_I2C_T_HIGH);
2465 ixgbe_lower_i2c_clk(hw, &i2cctl);
2467 /* Minimum low period of clock is 4.7 us.
2468 * This also takes care of the data hold time.
2470 usec_delay(IXGBE_I2C_T_LOW);
2472 status = IXGBE_ERR_I2C;
2473 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2474 "I2C data was not set to %X\n", data);
2481 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2482 * @hw: pointer to hardware structure
2483 * @i2cctl: Current value of I2CCTL register
2485 * Raises the I2C clock line '0'->'1'
2486 * Negates the I2C clock output enable on X550 hardware.
2488 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2490 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2492 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2495 DEBUGFUNC("ixgbe_raise_i2c_clk");
2498 *i2cctl |= clk_oe_bit;
2499 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2502 for (i = 0; i < timeout; i++) {
2503 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2505 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2506 IXGBE_WRITE_FLUSH(hw);
2507 /* SCL rise time (1000ns) */
2508 usec_delay(IXGBE_I2C_T_RISE);
2510 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2511 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2517 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2518 * @hw: pointer to hardware structure
2519 * @i2cctl: Current value of I2CCTL register
2521 * Lowers the I2C clock line '1'->'0'
2522 * Asserts the I2C clock output enable on X550 hardware.
2524 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2526 DEBUGFUNC("ixgbe_lower_i2c_clk");
2528 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2529 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2531 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2532 IXGBE_WRITE_FLUSH(hw);
2534 /* SCL fall time (300ns) */
2535 usec_delay(IXGBE_I2C_T_FALL);
2539 * ixgbe_set_i2c_data - Sets the I2C data bit
2540 * @hw: pointer to hardware structure
2541 * @i2cctl: Current value of I2CCTL register
2542 * @data: I2C data value (0 or 1) to set
2544 * Sets the I2C data bit
2545 * Asserts the I2C data output enable on X550 hardware.
2547 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2549 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2550 s32 status = IXGBE_SUCCESS;
2552 DEBUGFUNC("ixgbe_set_i2c_data");
2555 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2557 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2558 *i2cctl &= ~data_oe_bit;
2560 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2561 IXGBE_WRITE_FLUSH(hw);
2563 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2564 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2566 if (!data) /* Can't verify data in this case */
2567 return IXGBE_SUCCESS;
2569 *i2cctl |= data_oe_bit;
2570 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2571 IXGBE_WRITE_FLUSH(hw);
2574 /* Verify data was set correctly */
2575 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2576 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2577 status = IXGBE_ERR_I2C;
2578 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2579 "Error - I2C data was not set to %X.\n",
2587 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2588 * @hw: pointer to hardware structure
2589 * @i2cctl: Current value of I2CCTL register
2591 * Returns the I2C data bit value
2592 * Negates the I2C data output enable on X550 hardware.
2594 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2596 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2599 DEBUGFUNC("ixgbe_get_i2c_data");
2602 *i2cctl |= data_oe_bit;
2603 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2604 IXGBE_WRITE_FLUSH(hw);
2605 usec_delay(IXGBE_I2C_T_FALL);
2608 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2617 * ixgbe_i2c_bus_clear - Clears the I2C bus
2618 * @hw: pointer to hardware structure
2620 * Clears the I2C bus by sending nine clock pulses.
2621 * Used when data line is stuck low.
2623 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2628 DEBUGFUNC("ixgbe_i2c_bus_clear");
2630 ixgbe_i2c_start(hw);
2631 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2633 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2635 for (i = 0; i < 9; i++) {
2636 ixgbe_raise_i2c_clk(hw, &i2cctl);
2638 /* Min high period of clock is 4us */
2639 usec_delay(IXGBE_I2C_T_HIGH);
2641 ixgbe_lower_i2c_clk(hw, &i2cctl);
2643 /* Min low period of clock is 4.7us*/
2644 usec_delay(IXGBE_I2C_T_LOW);
2647 ixgbe_i2c_start(hw);
2649 /* Put the i2c bus back to default state */
2654 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2655 * @hw: pointer to hardware structure
2657 * Checks if the LASI temp alarm status was triggered due to overtemp
2659 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2661 s32 status = IXGBE_SUCCESS;
2664 DEBUGFUNC("ixgbe_tn_check_overtemp");
2666 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2669 /* Check that the LASI temp alarm status was triggered */
2670 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2671 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2673 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2676 status = IXGBE_ERR_OVERTEMP;
2677 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2683 * ixgbe_set_copper_phy_power - Control power for copper phy
2684 * @hw: pointer to hardware structure
2685 * @on: true for on, false for off
2687 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2692 if (!on && ixgbe_mng_present(hw))
2695 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2696 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2702 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2704 if (ixgbe_check_reset_blocked(hw))
2706 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2709 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2710 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,